| Jean-Christophe PLAGNIOL-VILLARD | 14f991a | 2011-11-18 01:41:28 +0800 | [diff] [blame] | 1 | /* |
| 2 | * reset AT91SAM9G45 as per errata |
| 3 | * |
| 4 | * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcosoft.com> |
| 5 | * |
| 6 | * unless the SDRAM is cleanly shutdown before we hit the |
| 7 | * reset register it can be left driving the data bus and |
| 8 | * killing the chance of a subsequent boot from NAND |
| 9 | * |
| 10 | * GPLv2 Only |
| 11 | */ |
| 12 | |
| 13 | #include <linux/linkage.h> |
| 14 | #include <mach/hardware.h> |
| Jean-Christophe PLAGNIOL-VILLARD | f363c40 | 2012-02-13 12:58:53 +0800 | [diff] [blame^] | 15 | #include <mach/at91_ramc.h> |
| Jean-Christophe PLAGNIOL-VILLARD | 14f991a | 2011-11-18 01:41:28 +0800 | [diff] [blame] | 16 | #include <mach/at91_rstc.h> |
| 17 | |
| 18 | .arm |
| 19 | |
| 20 | .globl at91sam9g45_restart |
| 21 | |
| 22 | at91sam9g45_restart: |
| Jean-Christophe PLAGNIOL-VILLARD | f363c40 | 2012-02-13 12:58:53 +0800 | [diff] [blame^] | 23 | ldr r5, =at91_ramc_base @ preload constants |
| 24 | ldr r0, [r5] |
| 25 | ldr r4, =at91_rstc_base |
| 26 | ldr r1, [r4] |
| Jean-Christophe PLAGNIOL-VILLARD | 14f991a | 2011-11-18 01:41:28 +0800 | [diff] [blame] | 27 | |
| 28 | mov r2, #1 |
| 29 | mov r3, #AT91_DDRSDRC_LPCB_POWER_DOWN |
| 30 | ldr r4, =AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST |
| 31 | |
| 32 | .balign 32 @ align to cache line |
| 33 | |
| 34 | str r2, [r0, #AT91_DDRSDRC_RTR] @ disable DDR0 access |
| 35 | str r3, [r0, #AT91_DDRSDRC_LPR] @ power down DDR0 |
| 36 | str r4, [r1, #AT91_RSTC_CR] @ reset processor |
| 37 | |
| 38 | b . |