Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Christian König. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Christian König |
| 25 | */ |
| 26 | #include "drmP.h" |
| 27 | #include "radeon_drm.h" |
| 28 | #include "radeon.h" |
| 29 | #include "atom.h" |
| 30 | |
| 31 | /* |
| 32 | * HDMI color format |
| 33 | */ |
| 34 | enum r600_hdmi_color_format { |
| 35 | RGB = 0, |
| 36 | YCC_422 = 1, |
| 37 | YCC_444 = 2 |
| 38 | }; |
| 39 | |
| 40 | /* |
| 41 | * IEC60958 status bits |
| 42 | */ |
| 43 | enum r600_hdmi_iec_status_bits { |
| 44 | AUDIO_STATUS_DIG_ENABLE = 0x01, |
Rafał Miłecki | 3fe373d | 2010-03-06 13:03:38 +0000 | [diff] [blame] | 45 | AUDIO_STATUS_V = 0x02, |
| 46 | AUDIO_STATUS_VCFG = 0x04, |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 47 | AUDIO_STATUS_EMPHASIS = 0x08, |
| 48 | AUDIO_STATUS_COPYRIGHT = 0x10, |
| 49 | AUDIO_STATUS_NONAUDIO = 0x20, |
| 50 | AUDIO_STATUS_PROFESSIONAL = 0x40, |
Rafał Miłecki | 3fe373d | 2010-03-06 13:03:38 +0000 | [diff] [blame] | 51 | AUDIO_STATUS_LEVEL = 0x80 |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 52 | }; |
| 53 | |
| 54 | struct { |
| 55 | uint32_t Clock; |
| 56 | |
| 57 | int N_32kHz; |
| 58 | int CTS_32kHz; |
| 59 | |
| 60 | int N_44_1kHz; |
| 61 | int CTS_44_1kHz; |
| 62 | |
| 63 | int N_48kHz; |
| 64 | int CTS_48kHz; |
| 65 | |
| 66 | } r600_hdmi_ACR[] = { |
| 67 | /* 32kHz 44.1kHz 48kHz */ |
| 68 | /* Clock N CTS N CTS N CTS */ |
| 69 | { 25174, 4576, 28125, 7007, 31250, 6864, 28125 }, /* 25,20/1.001 MHz */ |
| 70 | { 25200, 4096, 25200, 6272, 28000, 6144, 25200 }, /* 25.20 MHz */ |
| 71 | { 27000, 4096, 27000, 6272, 30000, 6144, 27000 }, /* 27.00 MHz */ |
| 72 | { 27027, 4096, 27027, 6272, 30030, 6144, 27027 }, /* 27.00*1.001 MHz */ |
| 73 | { 54000, 4096, 54000, 6272, 60000, 6144, 54000 }, /* 54.00 MHz */ |
| 74 | { 54054, 4096, 54054, 6272, 60060, 6144, 54054 }, /* 54.00*1.001 MHz */ |
| 75 | { 74175, 11648, 210937, 17836, 234375, 11648, 140625 }, /* 74.25/1.001 MHz */ |
| 76 | { 74250, 4096, 74250, 6272, 82500, 6144, 74250 }, /* 74.25 MHz */ |
| 77 | { 148351, 11648, 421875, 8918, 234375, 5824, 140625 }, /* 148.50/1.001 MHz */ |
| 78 | { 148500, 4096, 148500, 6272, 165000, 6144, 148500 }, /* 148.50 MHz */ |
| 79 | { 0, 4096, 0, 6272, 0, 6144, 0 } /* Other */ |
| 80 | }; |
| 81 | |
| 82 | /* |
| 83 | * calculate CTS value if it's not found in the table |
| 84 | */ |
| 85 | static void r600_hdmi_calc_CTS(uint32_t clock, int *CTS, int N, int freq) |
| 86 | { |
| 87 | if (*CTS == 0) |
Rafał Miłecki | 3fe373d | 2010-03-06 13:03:38 +0000 | [diff] [blame] | 88 | *CTS = clock * N / (128 * freq) * 1000; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 89 | DRM_DEBUG("Using ACR timing N=%d CTS=%d for frequency %d\n", |
| 90 | N, *CTS, freq); |
| 91 | } |
| 92 | |
| 93 | /* |
| 94 | * update the N and CTS parameters for a given pixel clock rate |
| 95 | */ |
| 96 | static void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock) |
| 97 | { |
| 98 | struct drm_device *dev = encoder->dev; |
| 99 | struct radeon_device *rdev = dev->dev_private; |
| 100 | uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset; |
| 101 | int CTS; |
| 102 | int N; |
| 103 | int i; |
| 104 | |
| 105 | for (i = 0; r600_hdmi_ACR[i].Clock != clock && r600_hdmi_ACR[i].Clock != 0; i++); |
| 106 | |
| 107 | CTS = r600_hdmi_ACR[i].CTS_32kHz; |
| 108 | N = r600_hdmi_ACR[i].N_32kHz; |
| 109 | r600_hdmi_calc_CTS(clock, &CTS, N, 32000); |
| 110 | WREG32(offset+R600_HDMI_32kHz_CTS, CTS << 12); |
| 111 | WREG32(offset+R600_HDMI_32kHz_N, N); |
| 112 | |
| 113 | CTS = r600_hdmi_ACR[i].CTS_44_1kHz; |
| 114 | N = r600_hdmi_ACR[i].N_44_1kHz; |
| 115 | r600_hdmi_calc_CTS(clock, &CTS, N, 44100); |
| 116 | WREG32(offset+R600_HDMI_44_1kHz_CTS, CTS << 12); |
| 117 | WREG32(offset+R600_HDMI_44_1kHz_N, N); |
| 118 | |
| 119 | CTS = r600_hdmi_ACR[i].CTS_48kHz; |
| 120 | N = r600_hdmi_ACR[i].N_48kHz; |
| 121 | r600_hdmi_calc_CTS(clock, &CTS, N, 48000); |
| 122 | WREG32(offset+R600_HDMI_48kHz_CTS, CTS << 12); |
| 123 | WREG32(offset+R600_HDMI_48kHz_N, N); |
| 124 | } |
| 125 | |
| 126 | /* |
| 127 | * calculate the crc for a given info frame |
| 128 | */ |
| 129 | static void r600_hdmi_infoframe_checksum(uint8_t packetType, |
| 130 | uint8_t versionNumber, |
| 131 | uint8_t length, |
| 132 | uint8_t *frame) |
| 133 | { |
Rafał Miłecki | 3fe373d | 2010-03-06 13:03:38 +0000 | [diff] [blame] | 134 | int i; |
| 135 | frame[0] = packetType + versionNumber + length; |
| 136 | for (i = 1; i <= length; i++) |
| 137 | frame[0] += frame[i]; |
| 138 | frame[0] = 0x100 - frame[0]; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 139 | } |
| 140 | |
| 141 | /* |
| 142 | * build a HDMI Video Info Frame |
| 143 | */ |
| 144 | static void r600_hdmi_videoinfoframe( |
| 145 | struct drm_encoder *encoder, |
| 146 | enum r600_hdmi_color_format color_format, |
| 147 | int active_information_present, |
| 148 | uint8_t active_format_aspect_ratio, |
| 149 | uint8_t scan_information, |
| 150 | uint8_t colorimetry, |
| 151 | uint8_t ex_colorimetry, |
| 152 | uint8_t quantization, |
| 153 | int ITC, |
| 154 | uint8_t picture_aspect_ratio, |
| 155 | uint8_t video_format_identification, |
| 156 | uint8_t pixel_repetition, |
| 157 | uint8_t non_uniform_picture_scaling, |
| 158 | uint8_t bar_info_data_valid, |
| 159 | uint16_t top_bar, |
| 160 | uint16_t bottom_bar, |
| 161 | uint16_t left_bar, |
| 162 | uint16_t right_bar |
| 163 | ) |
| 164 | { |
| 165 | struct drm_device *dev = encoder->dev; |
| 166 | struct radeon_device *rdev = dev->dev_private; |
| 167 | uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset; |
| 168 | |
| 169 | uint8_t frame[14]; |
| 170 | |
| 171 | frame[0x0] = 0; |
| 172 | frame[0x1] = |
| 173 | (scan_information & 0x3) | |
| 174 | ((bar_info_data_valid & 0x3) << 2) | |
| 175 | ((active_information_present & 0x1) << 4) | |
| 176 | ((color_format & 0x3) << 5); |
| 177 | frame[0x2] = |
| 178 | (active_format_aspect_ratio & 0xF) | |
| 179 | ((picture_aspect_ratio & 0x3) << 4) | |
| 180 | ((colorimetry & 0x3) << 6); |
| 181 | frame[0x3] = |
| 182 | (non_uniform_picture_scaling & 0x3) | |
| 183 | ((quantization & 0x3) << 2) | |
| 184 | ((ex_colorimetry & 0x7) << 4) | |
| 185 | ((ITC & 0x1) << 7); |
| 186 | frame[0x4] = (video_format_identification & 0x7F); |
| 187 | frame[0x5] = (pixel_repetition & 0xF); |
| 188 | frame[0x6] = (top_bar & 0xFF); |
| 189 | frame[0x7] = (top_bar >> 8); |
| 190 | frame[0x8] = (bottom_bar & 0xFF); |
| 191 | frame[0x9] = (bottom_bar >> 8); |
| 192 | frame[0xA] = (left_bar & 0xFF); |
| 193 | frame[0xB] = (left_bar >> 8); |
| 194 | frame[0xC] = (right_bar & 0xFF); |
| 195 | frame[0xD] = (right_bar >> 8); |
| 196 | |
| 197 | r600_hdmi_infoframe_checksum(0x82, 0x02, 0x0D, frame); |
| 198 | |
| 199 | WREG32(offset+R600_HDMI_VIDEOINFOFRAME_0, |
| 200 | frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); |
| 201 | WREG32(offset+R600_HDMI_VIDEOINFOFRAME_1, |
| 202 | frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); |
| 203 | WREG32(offset+R600_HDMI_VIDEOINFOFRAME_2, |
| 204 | frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); |
| 205 | WREG32(offset+R600_HDMI_VIDEOINFOFRAME_3, |
| 206 | frame[0xC] | (frame[0xD] << 8)); |
| 207 | } |
| 208 | |
| 209 | /* |
| 210 | * build a Audio Info Frame |
| 211 | */ |
| 212 | static void r600_hdmi_audioinfoframe( |
| 213 | struct drm_encoder *encoder, |
| 214 | uint8_t channel_count, |
| 215 | uint8_t coding_type, |
| 216 | uint8_t sample_size, |
| 217 | uint8_t sample_frequency, |
| 218 | uint8_t format, |
| 219 | uint8_t channel_allocation, |
| 220 | uint8_t level_shift, |
| 221 | int downmix_inhibit |
| 222 | ) |
| 223 | { |
| 224 | struct drm_device *dev = encoder->dev; |
| 225 | struct radeon_device *rdev = dev->dev_private; |
| 226 | uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset; |
| 227 | |
| 228 | uint8_t frame[11]; |
| 229 | |
| 230 | frame[0x0] = 0; |
| 231 | frame[0x1] = (channel_count & 0x7) | ((coding_type & 0xF) << 4); |
| 232 | frame[0x2] = (sample_size & 0x3) | ((sample_frequency & 0x7) << 2); |
| 233 | frame[0x3] = format; |
| 234 | frame[0x4] = channel_allocation; |
| 235 | frame[0x5] = ((level_shift & 0xF) << 3) | ((downmix_inhibit & 0x1) << 7); |
| 236 | frame[0x6] = 0; |
| 237 | frame[0x7] = 0; |
| 238 | frame[0x8] = 0; |
| 239 | frame[0x9] = 0; |
| 240 | frame[0xA] = 0; |
| 241 | |
| 242 | r600_hdmi_infoframe_checksum(0x84, 0x01, 0x0A, frame); |
| 243 | |
| 244 | WREG32(offset+R600_HDMI_AUDIOINFOFRAME_0, |
| 245 | frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); |
| 246 | WREG32(offset+R600_HDMI_AUDIOINFOFRAME_1, |
| 247 | frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24)); |
| 248 | } |
| 249 | |
| 250 | /* |
| 251 | * test if audio buffer is filled enough to start playing |
| 252 | */ |
| 253 | static int r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder) |
| 254 | { |
| 255 | struct drm_device *dev = encoder->dev; |
| 256 | struct radeon_device *rdev = dev->dev_private; |
| 257 | uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset; |
| 258 | |
| 259 | return (RREG32(offset+R600_HDMI_STATUS) & 0x10) != 0; |
| 260 | } |
| 261 | |
| 262 | /* |
| 263 | * have buffer status changed since last call? |
| 264 | */ |
| 265 | int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder) |
| 266 | { |
| 267 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 268 | int status, result; |
| 269 | |
| 270 | if (!radeon_encoder->hdmi_offset) |
| 271 | return 0; |
| 272 | |
| 273 | status = r600_hdmi_is_audio_buffer_filled(encoder); |
| 274 | result = radeon_encoder->hdmi_buffer_status != status; |
| 275 | radeon_encoder->hdmi_buffer_status = status; |
| 276 | |
| 277 | return result; |
| 278 | } |
| 279 | |
| 280 | /* |
| 281 | * write the audio workaround status to the hardware |
| 282 | */ |
| 283 | void r600_hdmi_audio_workaround(struct drm_encoder *encoder) |
| 284 | { |
| 285 | struct drm_device *dev = encoder->dev; |
| 286 | struct radeon_device *rdev = dev->dev_private; |
| 287 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 288 | uint32_t offset = radeon_encoder->hdmi_offset; |
| 289 | |
| 290 | if (!offset) |
| 291 | return; |
| 292 | |
Christian Koenig | f259493 | 2010-04-10 03:13:16 +0200 | [diff] [blame] | 293 | if (!radeon_encoder->hdmi_audio_workaround || |
| 294 | r600_hdmi_is_audio_buffer_filled(encoder)) { |
| 295 | |
| 296 | /* disable audio workaround */ |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 297 | WREG32_P(offset+R600_HDMI_CNTL, 0x00000001, ~0x00001001); |
| 298 | |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 299 | } else { |
Christian Koenig | f259493 | 2010-04-10 03:13:16 +0200 | [diff] [blame] | 300 | /* enable audio workaround */ |
| 301 | WREG32_P(offset+R600_HDMI_CNTL, 0x00001001, ~0x00001001); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 302 | } |
| 303 | } |
| 304 | |
| 305 | |
| 306 | /* |
| 307 | * update the info frames with the data from the current display mode |
| 308 | */ |
| 309 | void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode) |
| 310 | { |
| 311 | struct drm_device *dev = encoder->dev; |
| 312 | struct radeon_device *rdev = dev->dev_private; |
| 313 | uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset; |
| 314 | |
Alex Deucher | 16823d1 | 2010-04-16 11:35:30 -0400 | [diff] [blame] | 315 | if (ASIC_IS_DCE4(rdev)) |
| 316 | return; |
| 317 | |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 318 | if (!offset) |
| 319 | return; |
| 320 | |
| 321 | r600_audio_set_clock(encoder, mode->clock); |
| 322 | |
| 323 | WREG32(offset+R600_HDMI_UNKNOWN_0, 0x1000); |
| 324 | WREG32(offset+R600_HDMI_UNKNOWN_1, 0x0); |
| 325 | WREG32(offset+R600_HDMI_UNKNOWN_2, 0x1000); |
| 326 | |
| 327 | r600_hdmi_update_ACR(encoder, mode->clock); |
| 328 | |
| 329 | WREG32(offset+R600_HDMI_VIDEOCNTL, 0x13); |
| 330 | |
| 331 | WREG32(offset+R600_HDMI_VERSION, 0x202); |
| 332 | |
| 333 | r600_hdmi_videoinfoframe(encoder, RGB, 0, 0, 0, 0, |
| 334 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); |
| 335 | |
| 336 | /* it's unknown what these bits do excatly, but it's indeed quite usefull for debugging */ |
| 337 | WREG32(offset+R600_HDMI_AUDIO_DEBUG_0, 0x00FFFFFF); |
| 338 | WREG32(offset+R600_HDMI_AUDIO_DEBUG_1, 0x007FFFFF); |
| 339 | WREG32(offset+R600_HDMI_AUDIO_DEBUG_2, 0x00000001); |
| 340 | WREG32(offset+R600_HDMI_AUDIO_DEBUG_3, 0x00000001); |
| 341 | |
| 342 | r600_hdmi_audio_workaround(encoder); |
| 343 | |
| 344 | /* audio packets per line, does anyone know how to calc this ? */ |
| 345 | WREG32_P(offset+R600_HDMI_CNTL, 0x00040000, ~0x001F0000); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 346 | } |
| 347 | |
| 348 | /* |
| 349 | * update settings with current parameters from audio engine |
| 350 | */ |
Christian König | 58bd086 | 2010-04-05 22:14:55 +0200 | [diff] [blame] | 351 | void r600_hdmi_update_audio_settings(struct drm_encoder *encoder) |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 352 | { |
| 353 | struct drm_device *dev = encoder->dev; |
| 354 | struct radeon_device *rdev = dev->dev_private; |
| 355 | uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset; |
| 356 | |
Christian König | 58bd086 | 2010-04-05 22:14:55 +0200 | [diff] [blame] | 357 | int channels = r600_audio_channels(rdev); |
| 358 | int rate = r600_audio_rate(rdev); |
| 359 | int bps = r600_audio_bits_per_sample(rdev); |
| 360 | uint8_t status_bits = r600_audio_status_bits(rdev); |
| 361 | uint8_t category_code = r600_audio_category_code(rdev); |
| 362 | |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 363 | uint32_t iec; |
| 364 | |
| 365 | if (!offset) |
| 366 | return; |
| 367 | |
| 368 | DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n", |
| 369 | r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped", |
| 370 | channels, rate, bps); |
| 371 | DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n", |
| 372 | (int)status_bits, (int)category_code); |
| 373 | |
| 374 | iec = 0; |
| 375 | if (status_bits & AUDIO_STATUS_PROFESSIONAL) |
| 376 | iec |= 1 << 0; |
| 377 | if (status_bits & AUDIO_STATUS_NONAUDIO) |
| 378 | iec |= 1 << 1; |
| 379 | if (status_bits & AUDIO_STATUS_COPYRIGHT) |
| 380 | iec |= 1 << 2; |
| 381 | if (status_bits & AUDIO_STATUS_EMPHASIS) |
| 382 | iec |= 1 << 3; |
| 383 | |
| 384 | iec |= category_code << 8; |
| 385 | |
| 386 | switch (rate) { |
| 387 | case 32000: iec |= 0x3 << 24; break; |
| 388 | case 44100: iec |= 0x0 << 24; break; |
| 389 | case 88200: iec |= 0x8 << 24; break; |
| 390 | case 176400: iec |= 0xc << 24; break; |
| 391 | case 48000: iec |= 0x2 << 24; break; |
| 392 | case 96000: iec |= 0xa << 24; break; |
| 393 | case 192000: iec |= 0xe << 24; break; |
| 394 | } |
| 395 | |
| 396 | WREG32(offset+R600_HDMI_IEC60958_1, iec); |
| 397 | |
| 398 | iec = 0; |
| 399 | switch (bps) { |
| 400 | case 16: iec |= 0x2; break; |
| 401 | case 20: iec |= 0x3; break; |
| 402 | case 24: iec |= 0xb; break; |
| 403 | } |
| 404 | if (status_bits & AUDIO_STATUS_V) |
| 405 | iec |= 0x5 << 16; |
| 406 | |
| 407 | WREG32_P(offset+R600_HDMI_IEC60958_2, iec, ~0x5000f); |
| 408 | |
| 409 | /* 0x021 or 0x031 sets the audio frame length */ |
| 410 | WREG32(offset+R600_HDMI_AUDIOCNTL, 0x31); |
| 411 | r600_hdmi_audioinfoframe(encoder, channels-1, 0, 0, 0, 0, 0, 0, 0); |
| 412 | |
| 413 | r600_hdmi_audio_workaround(encoder); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 414 | } |
| 415 | |
Rafał Miłecki | 5715f67 | 2010-03-06 13:03:35 +0000 | [diff] [blame] | 416 | static int r600_hdmi_find_free_block(struct drm_device *dev) |
| 417 | { |
| 418 | struct radeon_device *rdev = dev->dev_private; |
| 419 | struct drm_encoder *encoder; |
| 420 | struct radeon_encoder *radeon_encoder; |
| 421 | bool free_blocks[3] = { true, true, true }; |
| 422 | |
| 423 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 424 | radeon_encoder = to_radeon_encoder(encoder); |
| 425 | switch (radeon_encoder->hdmi_offset) { |
| 426 | case R600_HDMI_BLOCK1: |
| 427 | free_blocks[0] = false; |
| 428 | break; |
| 429 | case R600_HDMI_BLOCK2: |
| 430 | free_blocks[1] = false; |
| 431 | break; |
| 432 | case R600_HDMI_BLOCK3: |
| 433 | free_blocks[2] = false; |
| 434 | break; |
| 435 | } |
| 436 | } |
| 437 | |
Rafał Miłecki | fe50ac7 | 2010-06-19 12:24:57 +0200 | [diff] [blame] | 438 | if (rdev->family == CHIP_RS600 || rdev->family == CHIP_RS690 || |
| 439 | rdev->family == CHIP_RS740) { |
Rafał Miłecki | 5715f67 | 2010-03-06 13:03:35 +0000 | [diff] [blame] | 440 | return free_blocks[0] ? R600_HDMI_BLOCK1 : 0; |
| 441 | } else if (rdev->family >= CHIP_R600) { |
| 442 | if (free_blocks[0]) |
| 443 | return R600_HDMI_BLOCK1; |
| 444 | else if (free_blocks[1]) |
| 445 | return R600_HDMI_BLOCK2; |
| 446 | } |
| 447 | return 0; |
| 448 | } |
| 449 | |
Rafał Miłecki | 2cd6218c | 2010-03-08 22:14:01 +0000 | [diff] [blame] | 450 | static void r600_hdmi_assign_block(struct drm_encoder *encoder) |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 451 | { |
| 452 | struct drm_device *dev = encoder->dev; |
| 453 | struct radeon_device *rdev = dev->dev_private; |
| 454 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
Rafał Miłecki | 2cd6218c | 2010-03-08 22:14:01 +0000 | [diff] [blame] | 455 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 456 | |
Rafał Miłecki | 2cd6218c | 2010-03-08 22:14:01 +0000 | [diff] [blame] | 457 | if (!dig) { |
| 458 | dev_err(rdev->dev, "Enabling HDMI on non-dig encoder\n"); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 459 | return; |
Rafał Miłecki | 2cd6218c | 2010-03-08 22:14:01 +0000 | [diff] [blame] | 460 | } |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 461 | |
Rafał Miłecki | 2cd6218c | 2010-03-08 22:14:01 +0000 | [diff] [blame] | 462 | if (ASIC_IS_DCE4(rdev)) { |
| 463 | /* TODO */ |
| 464 | } else if (ASIC_IS_DCE3(rdev)) { |
| 465 | radeon_encoder->hdmi_offset = dig->dig_encoder ? |
| 466 | R600_HDMI_BLOCK3 : R600_HDMI_BLOCK1; |
| 467 | if (ASIC_IS_DCE32(rdev)) |
| 468 | radeon_encoder->hdmi_config_offset = dig->dig_encoder ? |
| 469 | R600_HDMI_CONFIG2 : R600_HDMI_CONFIG1; |
Rafał Miłecki | fe50ac7 | 2010-06-19 12:24:57 +0200 | [diff] [blame] | 470 | } else if (rdev->family >= CHIP_R600 || rdev->family == CHIP_RS600 || |
| 471 | rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { |
Rafał Miłecki | 5715f67 | 2010-03-06 13:03:35 +0000 | [diff] [blame] | 472 | radeon_encoder->hdmi_offset = r600_hdmi_find_free_block(dev); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 473 | } |
| 474 | } |
| 475 | |
| 476 | /* |
Rafał Miłecki | 2cd6218c | 2010-03-08 22:14:01 +0000 | [diff] [blame] | 477 | * enable the HDMI engine |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 478 | */ |
Rafał Miłecki | 2cd6218c | 2010-03-08 22:14:01 +0000 | [diff] [blame] | 479 | void r600_hdmi_enable(struct drm_encoder *encoder) |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 480 | { |
Rafał Miłecki | 2cd6218c | 2010-03-08 22:14:01 +0000 | [diff] [blame] | 481 | struct drm_device *dev = encoder->dev; |
| 482 | struct radeon_device *rdev = dev->dev_private; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 483 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
Christian Koenig | f259493 | 2010-04-10 03:13:16 +0200 | [diff] [blame] | 484 | uint32_t offset; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 485 | |
Alex Deucher | 16823d1 | 2010-04-16 11:35:30 -0400 | [diff] [blame] | 486 | if (ASIC_IS_DCE4(rdev)) |
| 487 | return; |
| 488 | |
Rafał Miłecki | 2cd6218c | 2010-03-08 22:14:01 +0000 | [diff] [blame] | 489 | if (!radeon_encoder->hdmi_offset) { |
| 490 | r600_hdmi_assign_block(encoder); |
| 491 | if (!radeon_encoder->hdmi_offset) { |
| 492 | dev_warn(rdev->dev, "Could not find HDMI block for " |
| 493 | "0x%x encoder\n", radeon_encoder->encoder_id); |
| 494 | return; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 495 | } |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 496 | } |
| 497 | |
Christian Koenig | f259493 | 2010-04-10 03:13:16 +0200 | [diff] [blame] | 498 | offset = radeon_encoder->hdmi_offset; |
Rafał Miłecki | 5715f67 | 2010-03-06 13:03:35 +0000 | [diff] [blame] | 499 | if (ASIC_IS_DCE32(rdev) && !ASIC_IS_DCE4(rdev)) { |
Rafał Miłecki | 2cd6218c | 2010-03-08 22:14:01 +0000 | [diff] [blame] | 500 | WREG32_P(radeon_encoder->hdmi_config_offset + 0x4, 0x1, ~0x1); |
Rafał Miłecki | 5715f67 | 2010-03-06 13:03:35 +0000 | [diff] [blame] | 501 | } else if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) { |
Rafał Miłecki | 5715f67 | 2010-03-06 13:03:35 +0000 | [diff] [blame] | 502 | switch (radeon_encoder->encoder_id) { |
| 503 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
| 504 | WREG32_P(AVIVO_TMDSA_CNTL, 0x4, ~0x4); |
| 505 | WREG32(offset + R600_HDMI_ENABLE, 0x101); |
| 506 | break; |
| 507 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
| 508 | WREG32_P(AVIVO_LVTMA_CNTL, 0x4, ~0x4); |
| 509 | WREG32(offset + R600_HDMI_ENABLE, 0x105); |
| 510 | break; |
| 511 | default: |
| 512 | dev_err(rdev->dev, "Unknown HDMI output type\n"); |
| 513 | break; |
| 514 | } |
| 515 | } |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 516 | |
Christian Koenig | f259493 | 2010-04-10 03:13:16 +0200 | [diff] [blame] | 517 | if (rdev->irq.installed |
| 518 | && rdev->family != CHIP_RS600 |
| 519 | && rdev->family != CHIP_RS690 |
| 520 | && rdev->family != CHIP_RS740) { |
| 521 | |
| 522 | /* if irq is available use it */ |
| 523 | rdev->irq.hdmi[offset == R600_HDMI_BLOCK1 ? 0 : 1] = true; |
| 524 | radeon_irq_set(rdev); |
| 525 | |
| 526 | r600_audio_disable_polling(encoder); |
| 527 | } else { |
| 528 | /* if not fallback to polling */ |
| 529 | r600_audio_enable_polling(encoder); |
| 530 | } |
Christian König | 58bd086 | 2010-04-05 22:14:55 +0200 | [diff] [blame] | 531 | |
Rafał Miłecki | 2cd6218c | 2010-03-08 22:14:01 +0000 | [diff] [blame] | 532 | DRM_DEBUG("Enabling HDMI interface @ 0x%04X for encoder 0x%x\n", |
| 533 | radeon_encoder->hdmi_offset, radeon_encoder->encoder_id); |
| 534 | } |
| 535 | |
| 536 | /* |
| 537 | * disable the HDMI engine |
| 538 | */ |
| 539 | void r600_hdmi_disable(struct drm_encoder *encoder) |
| 540 | { |
| 541 | struct drm_device *dev = encoder->dev; |
| 542 | struct radeon_device *rdev = dev->dev_private; |
| 543 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
Dave Airlie | 6698998 | 2010-05-19 10:35:02 +1000 | [diff] [blame] | 544 | uint32_t offset; |
Rafał Miłecki | 2cd6218c | 2010-03-08 22:14:01 +0000 | [diff] [blame] | 545 | |
Alex Deucher | 16823d1 | 2010-04-16 11:35:30 -0400 | [diff] [blame] | 546 | if (ASIC_IS_DCE4(rdev)) |
| 547 | return; |
| 548 | |
Christian Koenig | f259493 | 2010-04-10 03:13:16 +0200 | [diff] [blame] | 549 | offset = radeon_encoder->hdmi_offset; |
| 550 | if (!offset) { |
Rafał Miłecki | 2cd6218c | 2010-03-08 22:14:01 +0000 | [diff] [blame] | 551 | dev_err(rdev->dev, "Disabling not enabled HDMI\n"); |
| 552 | return; |
| 553 | } |
| 554 | |
| 555 | DRM_DEBUG("Disabling HDMI interface @ 0x%04X for encoder 0x%x\n", |
Christian Koenig | f259493 | 2010-04-10 03:13:16 +0200 | [diff] [blame] | 556 | offset, radeon_encoder->encoder_id); |
| 557 | |
| 558 | /* disable irq */ |
| 559 | rdev->irq.hdmi[offset == R600_HDMI_BLOCK1 ? 0 : 1] = false; |
| 560 | radeon_irq_set(rdev); |
| 561 | |
| 562 | /* disable polling */ |
| 563 | r600_audio_disable_polling(encoder); |
Rafał Miłecki | 2cd6218c | 2010-03-08 22:14:01 +0000 | [diff] [blame] | 564 | |
Rafał Miłecki | 5715f67 | 2010-03-06 13:03:35 +0000 | [diff] [blame] | 565 | if (ASIC_IS_DCE32(rdev) && !ASIC_IS_DCE4(rdev)) { |
Rafał Miłecki | 2cd6218c | 2010-03-08 22:14:01 +0000 | [diff] [blame] | 566 | WREG32_P(radeon_encoder->hdmi_config_offset + 0x4, 0, ~0x1); |
Rafał Miłecki | 5715f67 | 2010-03-06 13:03:35 +0000 | [diff] [blame] | 567 | } else if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) { |
Rafał Miłecki | 5715f67 | 2010-03-06 13:03:35 +0000 | [diff] [blame] | 568 | switch (radeon_encoder->encoder_id) { |
| 569 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: |
| 570 | WREG32_P(AVIVO_TMDSA_CNTL, 0, ~0x4); |
| 571 | WREG32(offset + R600_HDMI_ENABLE, 0); |
| 572 | break; |
| 573 | case ENCODER_OBJECT_ID_INTERNAL_LVTM1: |
| 574 | WREG32_P(AVIVO_LVTMA_CNTL, 0, ~0x4); |
| 575 | WREG32(offset + R600_HDMI_ENABLE, 0); |
| 576 | break; |
| 577 | default: |
| 578 | dev_err(rdev->dev, "Unknown HDMI output type\n"); |
| 579 | break; |
| 580 | } |
| 581 | } |
Rafał Miłecki | 2cd6218c | 2010-03-08 22:14:01 +0000 | [diff] [blame] | 582 | |
| 583 | radeon_encoder->hdmi_offset = 0; |
| 584 | radeon_encoder->hdmi_config_offset = 0; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 585 | } |