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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * ahci.c - AHCI SATA support
3 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04004 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04008 * Copyright 2004-2005 Red Hat, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070010 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040011 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
Linus Torvalds1da177e2005-04-16 15:20:36 -070030 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040031 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
Linus Torvalds1da177e2005-04-16 15:20:36 -070032 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
domen@coderock.org87507cf2005-04-08 09:53:06 +020042#include <linux/dma-mapping.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050043#include <linux/device.h>
Tejun Heoedc93052007-10-25 14:59:16 +090044#include <linux/dmi.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070045#include <scsi/scsi_host.h>
Jeff Garzik193515d2005-11-07 00:59:37 -050046#include <scsi/scsi_cmnd.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070047#include <linux/libata.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070048
49#define DRV_NAME "ahci"
Tejun Heo7d50b602007-09-23 13:19:54 +090050#define DRV_VERSION "3.0"
Linus Torvalds1da177e2005-04-16 15:20:36 -070051
David Milburn87943ac2008-10-13 14:38:36 -050052/* Enclosure Management Control */
53#define EM_CTRL_MSG_TYPE 0x000f0000
54
55/* Enclosure Management LED Message Type */
56#define EM_MSG_LED_HBA_PORT 0x0000000f
57#define EM_MSG_LED_PMP_SLOT 0x0000ff00
58#define EM_MSG_LED_VALUE 0xffff0000
59#define EM_MSG_LED_VALUE_ACTIVITY 0x00070000
60#define EM_MSG_LED_VALUE_OFF 0xfff80000
61#define EM_MSG_LED_VALUE_ON 0x00010000
62
Tejun Heoa22e6442008-03-10 10:25:25 +090063static int ahci_skip_host_reset;
Arjan van de Venf3d7f232009-01-26 02:05:44 -080064static int ahci_ignore_sss;
65
Tejun Heoa22e6442008-03-10 10:25:25 +090066module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
67MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
68
Arjan van de Venf3d7f232009-01-26 02:05:44 -080069module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
70MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
71
Kristen Carlson Accardi31556592007-10-25 01:33:26 -040072static int ahci_enable_alpm(struct ata_port *ap,
73 enum link_pm policy);
74static void ahci_disable_alpm(struct ata_port *ap);
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -070075static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
76static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
77 size_t size);
78static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
79 ssize_t size);
80#define MAX_SLOTS 8
Linus Torvalds1da177e2005-04-16 15:20:36 -070081
82enum {
83 AHCI_PCI_BAR = 5,
Tejun Heo648a88b2006-11-09 15:08:40 +090084 AHCI_MAX_PORTS = 32,
Linus Torvalds1da177e2005-04-16 15:20:36 -070085 AHCI_MAX_SG = 168, /* hardware max is 64K */
86 AHCI_DMA_BOUNDARY = 0xffffffff,
Tejun Heo12fad3f2006-05-15 21:03:55 +090087 AHCI_MAX_CMDS = 32,
Tejun Heodd410ff2006-05-15 21:03:50 +090088 AHCI_CMD_SZ = 32,
Tejun Heo12fad3f2006-05-15 21:03:55 +090089 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
Linus Torvalds1da177e2005-04-16 15:20:36 -070090 AHCI_RX_FIS_SZ = 256,
Jeff Garzika0ea7322005-06-04 01:13:15 -040091 AHCI_CMD_TBL_CDB = 0x40,
Tejun Heodd410ff2006-05-15 21:03:50 +090092 AHCI_CMD_TBL_HDR_SZ = 0x80,
93 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
94 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
95 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
Linus Torvalds1da177e2005-04-16 15:20:36 -070096 AHCI_RX_FIS_SZ,
97 AHCI_IRQ_ON_SG = (1 << 31),
98 AHCI_CMD_ATAPI = (1 << 5),
99 AHCI_CMD_WRITE = (1 << 6),
Tejun Heo4b10e552006-03-12 11:25:27 +0900100 AHCI_CMD_PREFETCH = (1 << 7),
Tejun Heo22b49982006-01-23 21:38:44 +0900101 AHCI_CMD_RESET = (1 << 8),
102 AHCI_CMD_CLR_BUSY = (1 << 10),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700103
104 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
Tejun Heo0291f952007-01-25 19:16:28 +0900105 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
Tejun Heo78cd52d2006-05-15 20:58:29 +0900106 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700107
108 board_ahci = 0,
Tejun Heo7a234af2007-09-03 12:44:57 +0900109 board_ahci_vt8251 = 1,
110 board_ahci_ign_iferr = 2,
111 board_ahci_sb600 = 3,
112 board_ahci_mv = 4,
Shane Huange427fe02008-12-30 10:53:41 +0800113 board_ahci_sb700 = 5, /* for SB700 and SB800 */
Tejun Heoe297d992008-06-10 00:13:04 +0900114 board_ahci_mcp65 = 6,
Tejun Heo9a3b1032008-06-18 20:56:58 -0400115 board_ahci_nopmp = 7,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700116
117 /* global controller registers */
118 HOST_CAP = 0x00, /* host capabilities */
119 HOST_CTL = 0x04, /* global host control */
120 HOST_IRQ_STAT = 0x08, /* interrupt status */
121 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
122 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700123 HOST_EM_LOC = 0x1c, /* Enclosure Management location */
124 HOST_EM_CTL = 0x20, /* Enclosure Management Control */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700125
126 /* HOST_CTL bits */
127 HOST_RESET = (1 << 0), /* reset controller; self-clear */
128 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
129 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
130
131 /* HOST_CAP bits */
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700132 HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */
Tejun Heo0be0aa92006-07-26 15:59:26 +0900133 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
Tejun Heo7d50b602007-09-23 13:19:54 +0900134 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
Tejun Heo22b49982006-01-23 21:38:44 +0900135 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400136 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
Tejun Heo0be0aa92006-07-26 15:59:26 +0900137 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
Tejun Heo203ef6c2007-07-16 14:29:40 +0900138 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
Tejun Heo979db802006-05-15 21:03:52 +0900139 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
Tejun Heodd410ff2006-05-15 21:03:50 +0900140 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700141
142 /* registers for each SATA port */
143 PORT_LST_ADDR = 0x00, /* command list DMA addr */
144 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
145 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
146 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
147 PORT_IRQ_STAT = 0x10, /* interrupt status */
148 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
149 PORT_CMD = 0x18, /* port command */
150 PORT_TFDATA = 0x20, /* taskfile data */
151 PORT_SIG = 0x24, /* device TF signature */
152 PORT_CMD_ISSUE = 0x38, /* command issue */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700153 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
154 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
155 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
156 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
Tejun Heo203ef6c2007-07-16 14:29:40 +0900157 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700158
159 /* PORT_IRQ_{STAT,MASK} bits */
160 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
161 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
162 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
163 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
164 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
165 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
166 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
167 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
168
169 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
170 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
171 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
172 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
173 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
174 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
175 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
176 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
177 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
178
Tejun Heo78cd52d2006-05-15 20:58:29 +0900179 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
180 PORT_IRQ_IF_ERR |
181 PORT_IRQ_CONNECT |
Tejun Heo42969712006-05-31 18:28:18 +0900182 PORT_IRQ_PHYRDY |
Tejun Heo7d50b602007-09-23 13:19:54 +0900183 PORT_IRQ_UNK_FIS |
184 PORT_IRQ_BAD_PMP,
Tejun Heo78cd52d2006-05-15 20:58:29 +0900185 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
186 PORT_IRQ_TF_ERR |
187 PORT_IRQ_HBUS_DATA_ERR,
188 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
189 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
190 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700191
192 /* PORT_CMD bits */
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400193 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
194 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
Jeff Garzik02eaa662005-11-12 01:32:19 -0500195 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
Tejun Heo7d50b602007-09-23 13:19:54 +0900196 PORT_CMD_PMP = (1 << 17), /* PMP attached */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700197 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
198 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
199 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
Tejun Heo22b49982006-01-23 21:38:44 +0900200 PORT_CMD_CLO = (1 << 3), /* Command list override */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700201 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
202 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
203 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
204
Tejun Heo0be0aa92006-07-26 15:59:26 +0900205 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700206 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
207 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
208 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
Jeff Garzik4b0060f2005-06-04 00:50:22 -0400209
Tejun Heo417a1a62007-09-23 13:19:55 +0900210 /* hpriv->flags bits */
211 AHCI_HFLAG_NO_NCQ = (1 << 0),
212 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
213 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
214 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
215 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
216 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
Tejun Heo6949b912007-09-23 13:19:55 +0900217 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400218 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
Jeff Garzika8785392008-02-28 15:43:48 -0500219 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
Tejun Heoe297d992008-06-10 00:13:04 +0900220 AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */
Tejun Heo417a1a62007-09-23 13:19:55 +0900221
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200222 /* ap->flags bits */
Tejun Heo1188c0d2007-04-23 02:41:05 +0900223
224 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
225 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400226 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
227 ATA_FLAG_IPM,
Tejun Heoc4f77922007-12-06 15:09:43 +0900228
229 ICH_MAP = 0x90, /* ICH MAP register */
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700230
231 /* em_ctl bits */
232 EM_CTL_RST = (1 << 9), /* Reset */
233 EM_CTL_TM = (1 << 8), /* Transmit Message */
234 EM_CTL_ALHD = (1 << 26), /* Activity LED */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700235};
236
237struct ahci_cmd_hdr {
Al Viro4ca4e432007-12-30 09:32:22 +0000238 __le32 opts;
239 __le32 status;
240 __le32 tbl_addr;
241 __le32 tbl_addr_hi;
242 __le32 reserved[4];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700243};
244
245struct ahci_sg {
Al Viro4ca4e432007-12-30 09:32:22 +0000246 __le32 addr;
247 __le32 addr_hi;
248 __le32 reserved;
249 __le32 flags_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700250};
251
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700252struct ahci_em_priv {
253 enum sw_activity blink_policy;
254 struct timer_list timer;
255 unsigned long saved_activity;
256 unsigned long activity;
257 unsigned long led_state;
258};
259
Linus Torvalds1da177e2005-04-16 15:20:36 -0700260struct ahci_host_priv {
Tejun Heo417a1a62007-09-23 13:19:55 +0900261 unsigned int flags; /* AHCI_HFLAG_* */
Tejun Heod447df12007-03-18 22:15:33 +0900262 u32 cap; /* cap to use */
263 u32 port_map; /* port map to use */
264 u32 saved_cap; /* saved initial cap */
265 u32 saved_port_map; /* saved initial port_map */
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700266 u32 em_loc; /* enclosure management location */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700267};
268
269struct ahci_port_priv {
Tejun Heo7d50b602007-09-23 13:19:54 +0900270 struct ata_link *active_link;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700271 struct ahci_cmd_hdr *cmd_slot;
272 dma_addr_t cmd_slot_dma;
273 void *cmd_tbl;
274 dma_addr_t cmd_tbl_dma;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700275 void *rx_fis;
276 dma_addr_t rx_fis_dma;
Tejun Heo0291f952007-01-25 19:16:28 +0900277 /* for NCQ spurious interrupt analysis */
Tejun Heo0291f952007-01-25 19:16:28 +0900278 unsigned int ncq_saw_d2h:1;
279 unsigned int ncq_saw_dmas:1;
Tejun Heoafb2d552007-02-27 13:24:19 +0900280 unsigned int ncq_saw_sdb:1;
Kristen Carlson Accardia7384922007-08-09 14:23:41 -0700281 u32 intr_mask; /* interrupts to enable */
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700282 struct ahci_em_priv em_priv[MAX_SLOTS];/* enclosure management info
283 * per PM slot */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700284};
285
Tejun Heo82ef04f2008-07-31 17:02:40 +0900286static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
287static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400288static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
Tejun Heo9a3d9eb2006-01-23 13:09:36 +0900289static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
Tejun Heo4c9bf4e2008-04-07 22:47:20 +0900290static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700291static int ahci_port_start(struct ata_port *ap);
292static void ahci_port_stop(struct ata_port *ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700293static void ahci_qc_prep(struct ata_queued_cmd *qc);
Tejun Heo78cd52d2006-05-15 20:58:29 +0900294static void ahci_freeze(struct ata_port *ap);
295static void ahci_thaw(struct ata_port *ap);
Tejun Heo7d50b602007-09-23 13:19:54 +0900296static void ahci_pmp_attach(struct ata_port *ap);
297static void ahci_pmp_detach(struct ata_port *ap);
Tejun Heoa1efdab2008-03-25 12:22:50 +0900298static int ahci_softreset(struct ata_link *link, unsigned int *class,
299 unsigned long deadline);
Shane Huangbd172432008-06-10 15:52:04 +0800300static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
301 unsigned long deadline);
Tejun Heoa1efdab2008-03-25 12:22:50 +0900302static int ahci_hardreset(struct ata_link *link, unsigned int *class,
303 unsigned long deadline);
304static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
305 unsigned long deadline);
306static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
307 unsigned long deadline);
308static void ahci_postreset(struct ata_link *link, unsigned int *class);
Tejun Heo78cd52d2006-05-15 20:58:29 +0900309static void ahci_error_handler(struct ata_port *ap);
310static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
Jeff Garzikdf69c9c2007-05-26 20:46:51 -0400311static int ahci_port_resume(struct ata_port *ap);
Jeff Garzika8785392008-02-28 15:43:48 -0500312static void ahci_dev_config(struct ata_device *dev);
Jeff Garzikdab632e2007-05-28 08:33:01 -0400313static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
314static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
315 u32 opts);
Tejun Heo438ac6d2007-03-02 17:31:26 +0900316#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900317static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
Tejun Heoc1332872006-07-26 15:59:26 +0900318static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
319static int ahci_pci_device_resume(struct pci_dev *pdev);
Tejun Heo438ac6d2007-03-02 17:31:26 +0900320#endif
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700321static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
322static ssize_t ahci_activity_store(struct ata_device *dev,
323 enum sw_activity val);
324static void ahci_init_sw_activity(struct ata_link *link);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700325
Tony Jonesee959b02008-02-22 00:13:36 +0100326static struct device_attribute *ahci_shost_attrs[] = {
327 &dev_attr_link_power_management_policy,
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700328 &dev_attr_em_message_type,
329 &dev_attr_em_message,
330 NULL
331};
332
333static struct device_attribute *ahci_sdev_attrs[] = {
334 &dev_attr_sw_activity,
Elias Oltmanns45fabbb2008-09-21 11:54:08 +0200335 &dev_attr_unload_heads,
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400336 NULL
337};
338
Jeff Garzik193515d2005-11-07 00:59:37 -0500339static struct scsi_host_template ahci_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900340 ATA_NCQ_SHT(DRV_NAME),
Tejun Heo12fad3f2006-05-15 21:03:55 +0900341 .can_queue = AHCI_MAX_CMDS - 1,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700342 .sg_tablesize = AHCI_MAX_SG,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700343 .dma_boundary = AHCI_DMA_BOUNDARY,
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400344 .shost_attrs = ahci_shost_attrs,
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700345 .sdev_attrs = ahci_sdev_attrs,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700346};
347
Tejun Heo029cfd62008-03-25 12:22:49 +0900348static struct ata_port_operations ahci_ops = {
349 .inherits = &sata_pmp_port_ops,
350
Tejun Heo7d50b602007-09-23 13:19:54 +0900351 .qc_defer = sata_pmp_qc_defer_cmd_switch,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700352 .qc_prep = ahci_qc_prep,
353 .qc_issue = ahci_qc_issue,
Tejun Heo4c9bf4e2008-04-07 22:47:20 +0900354 .qc_fill_rtf = ahci_qc_fill_rtf,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700355
Tejun Heo78cd52d2006-05-15 20:58:29 +0900356 .freeze = ahci_freeze,
357 .thaw = ahci_thaw,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900358 .softreset = ahci_softreset,
359 .hardreset = ahci_hardreset,
360 .postreset = ahci_postreset,
Tejun Heo071f44b2008-04-07 22:47:22 +0900361 .pmp_softreset = ahci_softreset,
Tejun Heo78cd52d2006-05-15 20:58:29 +0900362 .error_handler = ahci_error_handler,
363 .post_internal_cmd = ahci_post_internal_cmd,
Tejun Heo029cfd62008-03-25 12:22:49 +0900364 .dev_config = ahci_dev_config,
Tejun Heo78cd52d2006-05-15 20:58:29 +0900365
Tejun Heo029cfd62008-03-25 12:22:49 +0900366 .scr_read = ahci_scr_read,
367 .scr_write = ahci_scr_write,
Tejun Heo7d50b602007-09-23 13:19:54 +0900368 .pmp_attach = ahci_pmp_attach,
369 .pmp_detach = ahci_pmp_detach,
Tejun Heo7d50b602007-09-23 13:19:54 +0900370
Tejun Heo029cfd62008-03-25 12:22:49 +0900371 .enable_pm = ahci_enable_alpm,
372 .disable_pm = ahci_disable_alpm,
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700373 .em_show = ahci_led_show,
374 .em_store = ahci_led_store,
375 .sw_activity_show = ahci_activity_show,
376 .sw_activity_store = ahci_activity_store,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900377#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900378 .port_suspend = ahci_port_suspend,
379 .port_resume = ahci_port_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900380#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700381 .port_start = ahci_port_start,
382 .port_stop = ahci_port_stop,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700383};
384
Tejun Heo029cfd62008-03-25 12:22:49 +0900385static struct ata_port_operations ahci_vt8251_ops = {
386 .inherits = &ahci_ops,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900387 .hardreset = ahci_vt8251_hardreset,
Tejun Heoad616ff2006-11-01 18:00:24 +0900388};
389
Tejun Heo029cfd62008-03-25 12:22:49 +0900390static struct ata_port_operations ahci_p5wdh_ops = {
391 .inherits = &ahci_ops,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900392 .hardreset = ahci_p5wdh_hardreset,
Tejun Heoedc93052007-10-25 14:59:16 +0900393};
394
Shane Huangbd172432008-06-10 15:52:04 +0800395static struct ata_port_operations ahci_sb600_ops = {
396 .inherits = &ahci_ops,
397 .softreset = ahci_sb600_softreset,
398 .pmp_softreset = ahci_sb600_softreset,
399};
400
Tejun Heo417a1a62007-09-23 13:19:55 +0900401#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
402
Arjan van de Ven98ac62d2005-11-28 10:06:23 +0100403static const struct ata_port_info ahci_port_info[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700404 /* board_ahci */
405 {
Tejun Heo1188c0d2007-04-23 02:41:05 +0900406 .flags = AHCI_FLAG_COMMON,
Brett Russ7da79312005-09-01 21:53:34 -0400407 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzik469248a2007-07-08 01:13:16 -0400408 .udma_mask = ATA_UDMA6,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700409 .port_ops = &ahci_ops,
410 },
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200411 /* board_ahci_vt8251 */
412 {
Tejun Heo6949b912007-09-23 13:19:55 +0900413 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
Tejun Heo417a1a62007-09-23 13:19:55 +0900414 .flags = AHCI_FLAG_COMMON,
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200415 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzik469248a2007-07-08 01:13:16 -0400416 .udma_mask = ATA_UDMA6,
Tejun Heoad616ff2006-11-01 18:00:24 +0900417 .port_ops = &ahci_vt8251_ops,
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200418 },
Tejun Heo41669552006-11-29 11:33:14 +0900419 /* board_ahci_ign_iferr */
420 {
Tejun Heo417a1a62007-09-23 13:19:55 +0900421 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
422 .flags = AHCI_FLAG_COMMON,
Tejun Heo41669552006-11-29 11:33:14 +0900423 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzik469248a2007-07-08 01:13:16 -0400424 .udma_mask = ATA_UDMA6,
Tejun Heo41669552006-11-29 11:33:14 +0900425 .port_ops = &ahci_ops,
426 },
Conke Hu55a61602007-03-27 18:33:05 +0800427 /* board_ahci_sb600 */
428 {
Tejun Heo417a1a62007-09-23 13:19:55 +0900429 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
Tejun Heo22b5e7a2008-04-29 16:09:22 +0900430 AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI |
Shane Huangbd172432008-06-10 15:52:04 +0800431 AHCI_HFLAG_SECT255),
Tejun Heo417a1a62007-09-23 13:19:55 +0900432 .flags = AHCI_FLAG_COMMON,
Conke Hu55a61602007-03-27 18:33:05 +0800433 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzik469248a2007-07-08 01:13:16 -0400434 .udma_mask = ATA_UDMA6,
Shane Huangbd172432008-06-10 15:52:04 +0800435 .port_ops = &ahci_sb600_ops,
Conke Hu55a61602007-03-27 18:33:05 +0800436 },
Jeff Garzikcd70c262007-07-08 02:29:42 -0400437 /* board_ahci_mv */
438 {
Tejun Heo417a1a62007-09-23 13:19:55 +0900439 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
Tejun Heo17248462008-08-29 16:03:59 +0200440 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
Jeff Garzikcd70c262007-07-08 02:29:42 -0400441 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
Tejun Heo417a1a62007-09-23 13:19:55 +0900442 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
Jeff Garzikcd70c262007-07-08 02:29:42 -0400443 .pio_mask = 0x1f, /* pio0-4 */
444 .udma_mask = ATA_UDMA6,
445 .port_ops = &ahci_ops,
446 },
Shane Huange427fe02008-12-30 10:53:41 +0800447 /* board_ahci_sb700, for SB700 and SB800 */
Shane Huange39fc8c2008-02-22 05:00:31 -0800448 {
Shane Huangbd172432008-06-10 15:52:04 +0800449 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
Shane Huange39fc8c2008-02-22 05:00:31 -0800450 .flags = AHCI_FLAG_COMMON,
Shane Huange39fc8c2008-02-22 05:00:31 -0800451 .pio_mask = 0x1f, /* pio0-4 */
452 .udma_mask = ATA_UDMA6,
Shane Huangbd172432008-06-10 15:52:04 +0800453 .port_ops = &ahci_sb600_ops,
Shane Huange39fc8c2008-02-22 05:00:31 -0800454 },
Tejun Heoe297d992008-06-10 00:13:04 +0900455 /* board_ahci_mcp65 */
456 {
457 AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ),
458 .flags = AHCI_FLAG_COMMON,
459 .pio_mask = 0x1f, /* pio0-4 */
460 .udma_mask = ATA_UDMA6,
461 .port_ops = &ahci_ops,
462 },
Tejun Heo9a3b1032008-06-18 20:56:58 -0400463 /* board_ahci_nopmp */
464 {
465 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP),
466 .flags = AHCI_FLAG_COMMON,
467 .pio_mask = 0x1f, /* pio0-4 */
468 .udma_mask = ATA_UDMA6,
469 .port_ops = &ahci_ops,
470 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700471};
472
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500473static const struct pci_device_id ahci_pci_tbl[] = {
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400474 /* Intel */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400475 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
476 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
477 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
478 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
479 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
Tejun Heo82490c02007-01-23 15:13:39 +0900480 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400481 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
482 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
483 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
484 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
Tejun Heo7a234af2007-09-03 12:44:57 +0900485 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
486 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
487 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
488 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
489 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
490 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
491 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
492 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
493 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
494 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
495 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
496 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
497 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
498 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
499 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
500 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
501 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
Jason Gastond4155e62007-09-20 17:35:00 -0400502 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
503 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
Jason Gaston16ad1ad2008-01-28 17:34:14 -0800504 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
505 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
Seth Heasleyadcb5302008-08-11 17:03:09 -0700506 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
Seth Heasley8e48b6b2008-08-27 16:47:22 -0700507 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
Seth Heasleyadcb5302008-08-11 17:03:09 -0700508 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
Seth Heasley8e48b6b2008-08-27 16:47:22 -0700509 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400510
Tejun Heoe34bb372007-02-26 20:24:03 +0900511 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
512 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
513 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400514
515 /* ATI */
Conke Huc65ec1c2007-04-11 18:23:14 +0800516 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
Shane Huange39fc8c2008-02-22 05:00:31 -0800517 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
518 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
519 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
520 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
521 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
522 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400523
524 /* VIA */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400525 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
Tejun Heobf335542007-04-11 17:27:14 +0900526 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400527
528 /* NVIDIA */
Tejun Heoe297d992008-06-10 00:13:04 +0900529 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
530 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
531 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
532 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
533 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
534 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
535 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
536 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
Peer Chen6fbf5ba2006-12-20 14:18:00 -0500537 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
538 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
539 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
540 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
Peer Chen895663c2006-11-02 17:59:46 -0500541 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
542 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
543 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
544 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
545 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
546 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
547 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
548 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
Peer Chen0522b282007-06-07 18:05:12 +0800549 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
550 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
551 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
552 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
553 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
554 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
555 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
556 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
557 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
558 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
559 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
560 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
561 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
562 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
563 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
564 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
565 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
566 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
567 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
568 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
569 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
570 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
571 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
572 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
peerchen6ba86952007-12-03 22:20:37 +0800573 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
574 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
575 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
576 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
Peer Chen71008192007-09-24 10:16:25 +0800577 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
578 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
579 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
580 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
581 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
582 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
583 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
584 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
peerchen70d562c2008-03-06 21:22:41 +0800585 { PCI_VDEVICE(NVIDIA, 0x0bc8), board_ahci }, /* MCP7B */
586 { PCI_VDEVICE(NVIDIA, 0x0bc9), board_ahci }, /* MCP7B */
587 { PCI_VDEVICE(NVIDIA, 0x0bca), board_ahci }, /* MCP7B */
588 { PCI_VDEVICE(NVIDIA, 0x0bcb), board_ahci }, /* MCP7B */
589 { PCI_VDEVICE(NVIDIA, 0x0bcc), board_ahci }, /* MCP7B */
590 { PCI_VDEVICE(NVIDIA, 0x0bcd), board_ahci }, /* MCP7B */
591 { PCI_VDEVICE(NVIDIA, 0x0bce), board_ahci }, /* MCP7B */
592 { PCI_VDEVICE(NVIDIA, 0x0bcf), board_ahci }, /* MCP7B */
peerchen3072c372008-05-19 14:44:57 +0800593 { PCI_VDEVICE(NVIDIA, 0x0bc4), board_ahci }, /* MCP7B */
594 { PCI_VDEVICE(NVIDIA, 0x0bc5), board_ahci }, /* MCP7B */
595 { PCI_VDEVICE(NVIDIA, 0x0bc6), board_ahci }, /* MCP7B */
596 { PCI_VDEVICE(NVIDIA, 0x0bc7), board_ahci }, /* MCP7B */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400597
Jeff Garzik95916ed2006-07-29 04:10:14 -0400598 /* SiS */
Tejun Heo20e2de42008-08-01 12:51:43 +0900599 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
600 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
601 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
Jeff Garzik95916ed2006-07-29 04:10:14 -0400602
Jeff Garzikcd70c262007-07-08 02:29:42 -0400603 /* Marvell */
604 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100605 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
Jeff Garzikcd70c262007-07-08 02:29:42 -0400606
Mark Nelsonc77a0362008-10-23 14:08:16 +1100607 /* Promise */
608 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
609
Jeff Garzik415ae2b2006-11-01 05:10:42 -0500610 /* Generic, PCI class code for AHCI */
611 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
Conke Huc9f89472007-01-09 05:32:51 -0500612 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
Jeff Garzik415ae2b2006-11-01 05:10:42 -0500613
Linus Torvalds1da177e2005-04-16 15:20:36 -0700614 { } /* terminate list */
615};
616
617
618static struct pci_driver ahci_pci_driver = {
619 .name = DRV_NAME,
620 .id_table = ahci_pci_tbl,
621 .probe = ahci_init_one,
Tejun Heo24dc5f32007-01-20 16:00:28 +0900622 .remove = ata_pci_remove_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900623#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900624 .suspend = ahci_pci_device_suspend,
625 .resume = ahci_pci_device_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900626#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700627};
628
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700629static int ahci_em_messages = 1;
630module_param(ahci_em_messages, int, 0444);
631/* add other LED protocol types when they become supported */
632MODULE_PARM_DESC(ahci_em_messages,
633 "Set AHCI Enclosure Management Message type (0 = disabled, 1 = LED");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700634
Alan Cox5b66c822008-09-03 14:48:34 +0100635#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
636static int marvell_enable;
637#else
638static int marvell_enable = 1;
639#endif
640module_param(marvell_enable, int, 0644);
641MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
642
643
Tejun Heo98fa4b62006-11-02 12:17:23 +0900644static inline int ahci_nr_ports(u32 cap)
645{
646 return (cap & 0x1f) + 1;
647}
648
Jeff Garzikdab632e2007-05-28 08:33:01 -0400649static inline void __iomem *__ahci_port_base(struct ata_host *host,
650 unsigned int port_no)
651{
652 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
653
654 return mmio + 0x100 + (port_no * 0x80);
655}
656
Tejun Heo4447d352007-04-17 23:44:08 +0900657static inline void __iomem *ahci_port_base(struct ata_port *ap)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700658{
Jeff Garzikdab632e2007-05-28 08:33:01 -0400659 return __ahci_port_base(ap->host, ap->port_no);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700660}
661
Tejun Heob710a1f2008-01-05 23:11:57 +0900662static void ahci_enable_ahci(void __iomem *mmio)
663{
Tejun Heo15fe9822008-04-23 20:52:58 +0900664 int i;
Tejun Heob710a1f2008-01-05 23:11:57 +0900665 u32 tmp;
666
667 /* turn on AHCI_EN */
668 tmp = readl(mmio + HOST_CTL);
Tejun Heo15fe9822008-04-23 20:52:58 +0900669 if (tmp & HOST_AHCI_EN)
670 return;
671
672 /* Some controllers need AHCI_EN to be written multiple times.
673 * Try a few times before giving up.
674 */
675 for (i = 0; i < 5; i++) {
Tejun Heob710a1f2008-01-05 23:11:57 +0900676 tmp |= HOST_AHCI_EN;
677 writel(tmp, mmio + HOST_CTL);
678 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
Tejun Heo15fe9822008-04-23 20:52:58 +0900679 if (tmp & HOST_AHCI_EN)
680 return;
681 msleep(10);
Tejun Heob710a1f2008-01-05 23:11:57 +0900682 }
Tejun Heo15fe9822008-04-23 20:52:58 +0900683
684 WARN_ON(1);
Tejun Heob710a1f2008-01-05 23:11:57 +0900685}
686
Tejun Heod447df12007-03-18 22:15:33 +0900687/**
688 * ahci_save_initial_config - Save and fixup initial config values
Tejun Heo4447d352007-04-17 23:44:08 +0900689 * @pdev: target PCI device
Tejun Heo4447d352007-04-17 23:44:08 +0900690 * @hpriv: host private area to store config values
Tejun Heod447df12007-03-18 22:15:33 +0900691 *
692 * Some registers containing configuration info might be setup by
693 * BIOS and might be cleared on reset. This function saves the
694 * initial values of those registers into @hpriv such that they
695 * can be restored after controller reset.
696 *
697 * If inconsistent, config values are fixed up by this function.
698 *
699 * LOCKING:
700 * None.
701 */
Tejun Heo4447d352007-04-17 23:44:08 +0900702static void ahci_save_initial_config(struct pci_dev *pdev,
Tejun Heo4447d352007-04-17 23:44:08 +0900703 struct ahci_host_priv *hpriv)
Tejun Heod447df12007-03-18 22:15:33 +0900704{
Tejun Heo4447d352007-04-17 23:44:08 +0900705 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
Tejun Heod447df12007-03-18 22:15:33 +0900706 u32 cap, port_map;
Tejun Heo17199b12007-03-18 22:26:53 +0900707 int i;
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100708 int mv;
Tejun Heod447df12007-03-18 22:15:33 +0900709
Tejun Heob710a1f2008-01-05 23:11:57 +0900710 /* make sure AHCI mode is enabled before accessing CAP */
711 ahci_enable_ahci(mmio);
712
Tejun Heod447df12007-03-18 22:15:33 +0900713 /* Values prefixed with saved_ are written back to host after
714 * reset. Values without are used for driver operation.
715 */
716 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
717 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
718
Tejun Heo274c1fd2007-07-16 14:29:40 +0900719 /* some chips have errata preventing 64bit use */
Tejun Heo417a1a62007-09-23 13:19:55 +0900720 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
Tejun Heoc7a42152007-05-18 16:23:19 +0200721 dev_printk(KERN_INFO, &pdev->dev,
722 "controller can't do 64bit DMA, forcing 32bit\n");
723 cap &= ~HOST_CAP_64;
724 }
725
Tejun Heo417a1a62007-09-23 13:19:55 +0900726 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
Tejun Heo274c1fd2007-07-16 14:29:40 +0900727 dev_printk(KERN_INFO, &pdev->dev,
728 "controller can't do NCQ, turning off CAP_NCQ\n");
729 cap &= ~HOST_CAP_NCQ;
730 }
731
Tejun Heoe297d992008-06-10 00:13:04 +0900732 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
733 dev_printk(KERN_INFO, &pdev->dev,
734 "controller can do NCQ, turning on CAP_NCQ\n");
735 cap |= HOST_CAP_NCQ;
736 }
737
Roel Kluin258cd842008-03-09 21:42:40 +0100738 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
Tejun Heo6949b912007-09-23 13:19:55 +0900739 dev_printk(KERN_INFO, &pdev->dev,
740 "controller can't do PMP, turning off CAP_PMP\n");
741 cap &= ~HOST_CAP_PMP;
742 }
743
Tejun Heod799e082008-06-17 12:46:30 +0900744 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361 &&
745 port_map != 1) {
746 dev_printk(KERN_INFO, &pdev->dev,
747 "JMB361 has only one port, port_map 0x%x -> 0x%x\n",
748 port_map, 1);
749 port_map = 1;
750 }
751
Jeff Garzikcd70c262007-07-08 02:29:42 -0400752 /*
753 * Temporary Marvell 6145 hack: PATA port presence
754 * is asserted through the standard AHCI port
755 * presence register, as bit 4 (counting from 0)
756 */
Tejun Heo417a1a62007-09-23 13:19:55 +0900757 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100758 if (pdev->device == 0x6121)
759 mv = 0x3;
760 else
761 mv = 0xf;
Jeff Garzikcd70c262007-07-08 02:29:42 -0400762 dev_printk(KERN_ERR, &pdev->dev,
763 "MV_AHCI HACK: port_map %x -> %x\n",
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100764 port_map,
765 port_map & mv);
Alan Cox5b66c822008-09-03 14:48:34 +0100766 dev_printk(KERN_ERR, &pdev->dev,
767 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
Jeff Garzikcd70c262007-07-08 02:29:42 -0400768
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100769 port_map &= mv;
Jeff Garzikcd70c262007-07-08 02:29:42 -0400770 }
771
Tejun Heo17199b12007-03-18 22:26:53 +0900772 /* cross check port_map and cap.n_ports */
Tejun Heo7a234af2007-09-03 12:44:57 +0900773 if (port_map) {
Tejun Heo837f5f82008-02-06 15:13:51 +0900774 int map_ports = 0;
Tejun Heo17199b12007-03-18 22:26:53 +0900775
Tejun Heo837f5f82008-02-06 15:13:51 +0900776 for (i = 0; i < AHCI_MAX_PORTS; i++)
777 if (port_map & (1 << i))
778 map_ports++;
Tejun Heo17199b12007-03-18 22:26:53 +0900779
Tejun Heo837f5f82008-02-06 15:13:51 +0900780 /* If PI has more ports than n_ports, whine, clear
781 * port_map and let it be generated from n_ports.
Tejun Heo17199b12007-03-18 22:26:53 +0900782 */
Tejun Heo837f5f82008-02-06 15:13:51 +0900783 if (map_ports > ahci_nr_ports(cap)) {
Tejun Heo4447d352007-04-17 23:44:08 +0900784 dev_printk(KERN_WARNING, &pdev->dev,
Tejun Heo837f5f82008-02-06 15:13:51 +0900785 "implemented port map (0x%x) contains more "
786 "ports than nr_ports (%u), using nr_ports\n",
787 port_map, ahci_nr_ports(cap));
Tejun Heo7a234af2007-09-03 12:44:57 +0900788 port_map = 0;
789 }
790 }
791
792 /* fabricate port_map from cap.nr_ports */
793 if (!port_map) {
Tejun Heo17199b12007-03-18 22:26:53 +0900794 port_map = (1 << ahci_nr_ports(cap)) - 1;
Tejun Heo7a234af2007-09-03 12:44:57 +0900795 dev_printk(KERN_WARNING, &pdev->dev,
796 "forcing PORTS_IMPL to 0x%x\n", port_map);
797
798 /* write the fixed up value to the PI register */
799 hpriv->saved_port_map = port_map;
Tejun Heo17199b12007-03-18 22:26:53 +0900800 }
801
Tejun Heod447df12007-03-18 22:15:33 +0900802 /* record values to use during operation */
803 hpriv->cap = cap;
804 hpriv->port_map = port_map;
805}
806
807/**
808 * ahci_restore_initial_config - Restore initial config
Tejun Heo4447d352007-04-17 23:44:08 +0900809 * @host: target ATA host
Tejun Heod447df12007-03-18 22:15:33 +0900810 *
811 * Restore initial config stored by ahci_save_initial_config().
812 *
813 * LOCKING:
814 * None.
815 */
Tejun Heo4447d352007-04-17 23:44:08 +0900816static void ahci_restore_initial_config(struct ata_host *host)
Tejun Heod447df12007-03-18 22:15:33 +0900817{
Tejun Heo4447d352007-04-17 23:44:08 +0900818 struct ahci_host_priv *hpriv = host->private_data;
819 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
820
Tejun Heod447df12007-03-18 22:15:33 +0900821 writel(hpriv->saved_cap, mmio + HOST_CAP);
822 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
823 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
824}
825
Tejun Heo203ef6c2007-07-16 14:29:40 +0900826static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700827{
Tejun Heo203ef6c2007-07-16 14:29:40 +0900828 static const int offset[] = {
829 [SCR_STATUS] = PORT_SCR_STAT,
830 [SCR_CONTROL] = PORT_SCR_CTL,
831 [SCR_ERROR] = PORT_SCR_ERR,
832 [SCR_ACTIVE] = PORT_SCR_ACT,
833 [SCR_NOTIFICATION] = PORT_SCR_NTF,
834 };
835 struct ahci_host_priv *hpriv = ap->host->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700836
Tejun Heo203ef6c2007-07-16 14:29:40 +0900837 if (sc_reg < ARRAY_SIZE(offset) &&
838 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
839 return offset[sc_reg];
Tejun Heoda3dbb12007-07-16 14:29:40 +0900840 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700841}
842
Tejun Heo82ef04f2008-07-31 17:02:40 +0900843static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700844{
Tejun Heo82ef04f2008-07-31 17:02:40 +0900845 void __iomem *port_mmio = ahci_port_base(link->ap);
846 int offset = ahci_scr_offset(link->ap, sc_reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700847
Tejun Heo203ef6c2007-07-16 14:29:40 +0900848 if (offset) {
849 *val = readl(port_mmio + offset);
850 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700851 }
Tejun Heo203ef6c2007-07-16 14:29:40 +0900852 return -EINVAL;
853}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700854
Tejun Heo82ef04f2008-07-31 17:02:40 +0900855static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
Tejun Heo203ef6c2007-07-16 14:29:40 +0900856{
Tejun Heo82ef04f2008-07-31 17:02:40 +0900857 void __iomem *port_mmio = ahci_port_base(link->ap);
858 int offset = ahci_scr_offset(link->ap, sc_reg);
Tejun Heo203ef6c2007-07-16 14:29:40 +0900859
860 if (offset) {
861 writel(val, port_mmio + offset);
862 return 0;
863 }
864 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700865}
866
Tejun Heo4447d352007-04-17 23:44:08 +0900867static void ahci_start_engine(struct ata_port *ap)
Tejun Heo7c76d1e2005-12-19 22:36:34 +0900868{
Tejun Heo4447d352007-04-17 23:44:08 +0900869 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo7c76d1e2005-12-19 22:36:34 +0900870 u32 tmp;
871
Tejun Heod8fcd112006-07-26 15:59:25 +0900872 /* start DMA */
Tejun Heo9f592052006-07-26 15:59:26 +0900873 tmp = readl(port_mmio + PORT_CMD);
Tejun Heo7c76d1e2005-12-19 22:36:34 +0900874 tmp |= PORT_CMD_START;
875 writel(tmp, port_mmio + PORT_CMD);
876 readl(port_mmio + PORT_CMD); /* flush */
877}
878
Tejun Heo4447d352007-04-17 23:44:08 +0900879static int ahci_stop_engine(struct ata_port *ap)
Tejun Heo254950c2006-07-26 15:59:25 +0900880{
Tejun Heo4447d352007-04-17 23:44:08 +0900881 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo254950c2006-07-26 15:59:25 +0900882 u32 tmp;
883
884 tmp = readl(port_mmio + PORT_CMD);
885
Tejun Heod8fcd112006-07-26 15:59:25 +0900886 /* check if the HBA is idle */
Tejun Heo254950c2006-07-26 15:59:25 +0900887 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
888 return 0;
889
Tejun Heod8fcd112006-07-26 15:59:25 +0900890 /* setting HBA to idle */
Tejun Heo254950c2006-07-26 15:59:25 +0900891 tmp &= ~PORT_CMD_START;
892 writel(tmp, port_mmio + PORT_CMD);
893
Tejun Heod8fcd112006-07-26 15:59:25 +0900894 /* wait for engine to stop. This could be as long as 500 msec */
Tejun Heo254950c2006-07-26 15:59:25 +0900895 tmp = ata_wait_register(port_mmio + PORT_CMD,
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400896 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
Tejun Heod8fcd112006-07-26 15:59:25 +0900897 if (tmp & PORT_CMD_LIST_ON)
Tejun Heo254950c2006-07-26 15:59:25 +0900898 return -EIO;
899
900 return 0;
901}
902
Tejun Heo4447d352007-04-17 23:44:08 +0900903static void ahci_start_fis_rx(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +0900904{
Tejun Heo4447d352007-04-17 23:44:08 +0900905 void __iomem *port_mmio = ahci_port_base(ap);
906 struct ahci_host_priv *hpriv = ap->host->private_data;
907 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo0be0aa92006-07-26 15:59:26 +0900908 u32 tmp;
909
910 /* set FIS registers */
Tejun Heo4447d352007-04-17 23:44:08 +0900911 if (hpriv->cap & HOST_CAP_64)
912 writel((pp->cmd_slot_dma >> 16) >> 16,
913 port_mmio + PORT_LST_ADDR_HI);
914 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900915
Tejun Heo4447d352007-04-17 23:44:08 +0900916 if (hpriv->cap & HOST_CAP_64)
917 writel((pp->rx_fis_dma >> 16) >> 16,
918 port_mmio + PORT_FIS_ADDR_HI);
919 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900920
921 /* enable FIS reception */
922 tmp = readl(port_mmio + PORT_CMD);
923 tmp |= PORT_CMD_FIS_RX;
924 writel(tmp, port_mmio + PORT_CMD);
925
926 /* flush */
927 readl(port_mmio + PORT_CMD);
928}
929
Tejun Heo4447d352007-04-17 23:44:08 +0900930static int ahci_stop_fis_rx(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +0900931{
Tejun Heo4447d352007-04-17 23:44:08 +0900932 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900933 u32 tmp;
934
935 /* disable FIS reception */
936 tmp = readl(port_mmio + PORT_CMD);
937 tmp &= ~PORT_CMD_FIS_RX;
938 writel(tmp, port_mmio + PORT_CMD);
939
940 /* wait for completion, spec says 500ms, give it 1000 */
941 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
942 PORT_CMD_FIS_ON, 10, 1000);
943 if (tmp & PORT_CMD_FIS_ON)
944 return -EBUSY;
945
946 return 0;
947}
948
Tejun Heo4447d352007-04-17 23:44:08 +0900949static void ahci_power_up(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +0900950{
Tejun Heo4447d352007-04-17 23:44:08 +0900951 struct ahci_host_priv *hpriv = ap->host->private_data;
952 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900953 u32 cmd;
954
955 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
956
957 /* spin up device */
Tejun Heo4447d352007-04-17 23:44:08 +0900958 if (hpriv->cap & HOST_CAP_SSS) {
Tejun Heo0be0aa92006-07-26 15:59:26 +0900959 cmd |= PORT_CMD_SPIN_UP;
960 writel(cmd, port_mmio + PORT_CMD);
961 }
962
963 /* wake up link */
964 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
965}
966
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400967static void ahci_disable_alpm(struct ata_port *ap)
968{
969 struct ahci_host_priv *hpriv = ap->host->private_data;
970 void __iomem *port_mmio = ahci_port_base(ap);
971 u32 cmd;
972 struct ahci_port_priv *pp = ap->private_data;
973
974 /* IPM bits should be disabled by libata-core */
975 /* get the existing command bits */
976 cmd = readl(port_mmio + PORT_CMD);
977
978 /* disable ALPM and ASP */
979 cmd &= ~PORT_CMD_ASP;
980 cmd &= ~PORT_CMD_ALPE;
981
982 /* force the interface back to active */
983 cmd |= PORT_CMD_ICC_ACTIVE;
984
985 /* write out new cmd value */
986 writel(cmd, port_mmio + PORT_CMD);
987 cmd = readl(port_mmio + PORT_CMD);
988
989 /* wait 10ms to be sure we've come out of any low power state */
990 msleep(10);
991
992 /* clear out any PhyRdy stuff from interrupt status */
993 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
994
995 /* go ahead and clean out PhyRdy Change from Serror too */
Tejun Heo82ef04f2008-07-31 17:02:40 +0900996 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400997
998 /*
999 * Clear flag to indicate that we should ignore all PhyRdy
1000 * state changes
1001 */
1002 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
1003
1004 /*
1005 * Enable interrupts on Phy Ready.
1006 */
1007 pp->intr_mask |= PORT_IRQ_PHYRDY;
1008 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1009
1010 /*
1011 * don't change the link pm policy - we can be called
1012 * just to turn of link pm temporarily
1013 */
1014}
1015
1016static int ahci_enable_alpm(struct ata_port *ap,
1017 enum link_pm policy)
1018{
1019 struct ahci_host_priv *hpriv = ap->host->private_data;
1020 void __iomem *port_mmio = ahci_port_base(ap);
1021 u32 cmd;
1022 struct ahci_port_priv *pp = ap->private_data;
1023 u32 asp;
1024
1025 /* Make sure the host is capable of link power management */
1026 if (!(hpriv->cap & HOST_CAP_ALPM))
1027 return -EINVAL;
1028
1029 switch (policy) {
1030 case MAX_PERFORMANCE:
1031 case NOT_AVAILABLE:
1032 /*
1033 * if we came here with NOT_AVAILABLE,
1034 * it just means this is the first time we
1035 * have tried to enable - default to max performance,
1036 * and let the user go to lower power modes on request.
1037 */
1038 ahci_disable_alpm(ap);
1039 return 0;
1040 case MIN_POWER:
1041 /* configure HBA to enter SLUMBER */
1042 asp = PORT_CMD_ASP;
1043 break;
1044 case MEDIUM_POWER:
1045 /* configure HBA to enter PARTIAL */
1046 asp = 0;
1047 break;
1048 default:
1049 return -EINVAL;
1050 }
1051
1052 /*
1053 * Disable interrupts on Phy Ready. This keeps us from
1054 * getting woken up due to spurious phy ready interrupts
1055 * TBD - Hot plug should be done via polling now, is
1056 * that even supported?
1057 */
1058 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
1059 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1060
1061 /*
1062 * Set a flag to indicate that we should ignore all PhyRdy
1063 * state changes since these can happen now whenever we
1064 * change link state
1065 */
1066 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
1067
1068 /* get the existing command bits */
1069 cmd = readl(port_mmio + PORT_CMD);
1070
1071 /*
1072 * Set ASP based on Policy
1073 */
1074 cmd |= asp;
1075
1076 /*
1077 * Setting this bit will instruct the HBA to aggressively
1078 * enter a lower power link state when it's appropriate and
1079 * based on the value set above for ASP
1080 */
1081 cmd |= PORT_CMD_ALPE;
1082
1083 /* write out new cmd value */
1084 writel(cmd, port_mmio + PORT_CMD);
1085 cmd = readl(port_mmio + PORT_CMD);
1086
1087 /* IPM bits should be set by libata-core */
1088 return 0;
1089}
1090
Tejun Heo438ac6d2007-03-02 17:31:26 +09001091#ifdef CONFIG_PM
Tejun Heo4447d352007-04-17 23:44:08 +09001092static void ahci_power_down(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +09001093{
Tejun Heo4447d352007-04-17 23:44:08 +09001094 struct ahci_host_priv *hpriv = ap->host->private_data;
1095 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001096 u32 cmd, scontrol;
1097
Tejun Heo4447d352007-04-17 23:44:08 +09001098 if (!(hpriv->cap & HOST_CAP_SSS))
Tejun Heo07c53da2007-01-21 02:10:11 +09001099 return;
1100
1101 /* put device into listen mode, first set PxSCTL.DET to 0 */
1102 scontrol = readl(port_mmio + PORT_SCR_CTL);
1103 scontrol &= ~0xf;
1104 writel(scontrol, port_mmio + PORT_SCR_CTL);
1105
1106 /* then set PxCMD.SUD to 0 */
Tejun Heo0be0aa92006-07-26 15:59:26 +09001107 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
Tejun Heo07c53da2007-01-21 02:10:11 +09001108 cmd &= ~PORT_CMD_SPIN_UP;
1109 writel(cmd, port_mmio + PORT_CMD);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001110}
Tejun Heo438ac6d2007-03-02 17:31:26 +09001111#endif
Tejun Heo0be0aa92006-07-26 15:59:26 +09001112
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04001113static void ahci_start_port(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +09001114{
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001115 struct ahci_port_priv *pp = ap->private_data;
1116 struct ata_link *link;
1117 struct ahci_em_priv *emp;
1118
Tejun Heo0be0aa92006-07-26 15:59:26 +09001119 /* enable FIS reception */
Tejun Heo4447d352007-04-17 23:44:08 +09001120 ahci_start_fis_rx(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001121
1122 /* enable DMA */
Tejun Heo4447d352007-04-17 23:44:08 +09001123 ahci_start_engine(ap);
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001124
1125 /* turn on LEDs */
1126 if (ap->flags & ATA_FLAG_EM) {
Tejun Heo1eca4362008-11-03 20:03:17 +09001127 ata_for_each_link(link, ap, EDGE) {
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001128 emp = &pp->em_priv[link->pmp];
1129 ahci_transmit_led_message(ap, emp->led_state, 4);
1130 }
1131 }
1132
1133 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
Tejun Heo1eca4362008-11-03 20:03:17 +09001134 ata_for_each_link(link, ap, EDGE)
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001135 ahci_init_sw_activity(link);
1136
Tejun Heo0be0aa92006-07-26 15:59:26 +09001137}
1138
Tejun Heo4447d352007-04-17 23:44:08 +09001139static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
Tejun Heo0be0aa92006-07-26 15:59:26 +09001140{
1141 int rc;
1142
1143 /* disable DMA */
Tejun Heo4447d352007-04-17 23:44:08 +09001144 rc = ahci_stop_engine(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001145 if (rc) {
1146 *emsg = "failed to stop engine";
1147 return rc;
1148 }
1149
1150 /* disable FIS reception */
Tejun Heo4447d352007-04-17 23:44:08 +09001151 rc = ahci_stop_fis_rx(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001152 if (rc) {
1153 *emsg = "failed stop FIS RX";
1154 return rc;
1155 }
1156
Tejun Heo0be0aa92006-07-26 15:59:26 +09001157 return 0;
1158}
1159
Tejun Heo4447d352007-04-17 23:44:08 +09001160static int ahci_reset_controller(struct ata_host *host)
Tejun Heod91542c2006-07-26 15:59:26 +09001161{
Tejun Heo4447d352007-04-17 23:44:08 +09001162 struct pci_dev *pdev = to_pci_dev(host->dev);
Tejun Heo49f29092007-11-19 16:03:44 +09001163 struct ahci_host_priv *hpriv = host->private_data;
Tejun Heo4447d352007-04-17 23:44:08 +09001164 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Tejun Heod447df12007-03-18 22:15:33 +09001165 u32 tmp;
Tejun Heod91542c2006-07-26 15:59:26 +09001166
Jeff Garzik3cc3eb12007-09-26 00:02:41 -04001167 /* we must be in AHCI mode, before using anything
1168 * AHCI-specific, such as HOST_RESET.
1169 */
Tejun Heob710a1f2008-01-05 23:11:57 +09001170 ahci_enable_ahci(mmio);
Jeff Garzik3cc3eb12007-09-26 00:02:41 -04001171
1172 /* global controller reset */
Tejun Heoa22e6442008-03-10 10:25:25 +09001173 if (!ahci_skip_host_reset) {
1174 tmp = readl(mmio + HOST_CTL);
1175 if ((tmp & HOST_RESET) == 0) {
1176 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1177 readl(mmio + HOST_CTL); /* flush */
1178 }
Tejun Heod91542c2006-07-26 15:59:26 +09001179
Zhang Rui24920c82008-07-04 13:32:17 +08001180 /*
1181 * to perform host reset, OS should set HOST_RESET
1182 * and poll until this bit is read to be "0".
1183 * reset must complete within 1 second, or
Tejun Heoa22e6442008-03-10 10:25:25 +09001184 * the hardware should be considered fried.
1185 */
Zhang Rui24920c82008-07-04 13:32:17 +08001186 tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET,
1187 HOST_RESET, 10, 1000);
Tejun Heod91542c2006-07-26 15:59:26 +09001188
Tejun Heoa22e6442008-03-10 10:25:25 +09001189 if (tmp & HOST_RESET) {
1190 dev_printk(KERN_ERR, host->dev,
1191 "controller reset failed (0x%x)\n", tmp);
1192 return -EIO;
1193 }
Tejun Heod91542c2006-07-26 15:59:26 +09001194
Tejun Heoa22e6442008-03-10 10:25:25 +09001195 /* turn on AHCI mode */
1196 ahci_enable_ahci(mmio);
Tejun Heo98fa4b62006-11-02 12:17:23 +09001197
Tejun Heoa22e6442008-03-10 10:25:25 +09001198 /* Some registers might be cleared on reset. Restore
1199 * initial values.
1200 */
1201 ahci_restore_initial_config(host);
1202 } else
1203 dev_printk(KERN_INFO, host->dev,
1204 "skipping global host reset\n");
Tejun Heod91542c2006-07-26 15:59:26 +09001205
1206 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1207 u16 tmp16;
1208
1209 /* configure PCS */
1210 pci_read_config_word(pdev, 0x92, &tmp16);
Tejun Heo49f29092007-11-19 16:03:44 +09001211 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1212 tmp16 |= hpriv->port_map;
1213 pci_write_config_word(pdev, 0x92, tmp16);
1214 }
Tejun Heod91542c2006-07-26 15:59:26 +09001215 }
1216
1217 return 0;
1218}
1219
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001220static void ahci_sw_activity(struct ata_link *link)
1221{
1222 struct ata_port *ap = link->ap;
1223 struct ahci_port_priv *pp = ap->private_data;
1224 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1225
1226 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
1227 return;
1228
1229 emp->activity++;
1230 if (!timer_pending(&emp->timer))
1231 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
1232}
1233
1234static void ahci_sw_activity_blink(unsigned long arg)
1235{
1236 struct ata_link *link = (struct ata_link *)arg;
1237 struct ata_port *ap = link->ap;
1238 struct ahci_port_priv *pp = ap->private_data;
1239 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1240 unsigned long led_message = emp->led_state;
1241 u32 activity_led_state;
David Milburneb409632008-10-16 09:26:19 -05001242 unsigned long flags;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001243
David Milburn87943ac2008-10-13 14:38:36 -05001244 led_message &= EM_MSG_LED_VALUE;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001245 led_message |= ap->port_no | (link->pmp << 8);
1246
1247 /* check to see if we've had activity. If so,
1248 * toggle state of LED and reset timer. If not,
1249 * turn LED to desired idle state.
1250 */
David Milburneb409632008-10-16 09:26:19 -05001251 spin_lock_irqsave(ap->lock, flags);
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001252 if (emp->saved_activity != emp->activity) {
1253 emp->saved_activity = emp->activity;
1254 /* get the current LED state */
David Milburn87943ac2008-10-13 14:38:36 -05001255 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001256
1257 if (activity_led_state)
1258 activity_led_state = 0;
1259 else
1260 activity_led_state = 1;
1261
1262 /* clear old state */
David Milburn87943ac2008-10-13 14:38:36 -05001263 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001264
1265 /* toggle state */
1266 led_message |= (activity_led_state << 16);
1267 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
1268 } else {
1269 /* switch to idle */
David Milburn87943ac2008-10-13 14:38:36 -05001270 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001271 if (emp->blink_policy == BLINK_OFF)
1272 led_message |= (1 << 16);
1273 }
David Milburneb409632008-10-16 09:26:19 -05001274 spin_unlock_irqrestore(ap->lock, flags);
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001275 ahci_transmit_led_message(ap, led_message, 4);
1276}
1277
1278static void ahci_init_sw_activity(struct ata_link *link)
1279{
1280 struct ata_port *ap = link->ap;
1281 struct ahci_port_priv *pp = ap->private_data;
1282 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1283
1284 /* init activity stats, setup timer */
1285 emp->saved_activity = emp->activity = 0;
1286 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
1287
1288 /* check our blink policy and set flag for link if it's enabled */
1289 if (emp->blink_policy)
1290 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1291}
1292
1293static int ahci_reset_em(struct ata_host *host)
1294{
1295 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1296 u32 em_ctl;
1297
1298 em_ctl = readl(mmio + HOST_EM_CTL);
1299 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1300 return -EINVAL;
1301
1302 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1303 return 0;
1304}
1305
1306static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1307 ssize_t size)
1308{
1309 struct ahci_host_priv *hpriv = ap->host->private_data;
1310 struct ahci_port_priv *pp = ap->private_data;
1311 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1312 u32 em_ctl;
1313 u32 message[] = {0, 0};
Linus Torvalds93082f02008-07-25 10:56:36 -07001314 unsigned long flags;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001315 int pmp;
1316 struct ahci_em_priv *emp;
1317
1318 /* get the slot number from the message */
David Milburn87943ac2008-10-13 14:38:36 -05001319 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001320 if (pmp < MAX_SLOTS)
1321 emp = &pp->em_priv[pmp];
1322 else
1323 return -EINVAL;
1324
1325 spin_lock_irqsave(ap->lock, flags);
1326
1327 /*
1328 * if we are still busy transmitting a previous message,
1329 * do not allow
1330 */
1331 em_ctl = readl(mmio + HOST_EM_CTL);
1332 if (em_ctl & EM_CTL_TM) {
1333 spin_unlock_irqrestore(ap->lock, flags);
1334 return -EINVAL;
1335 }
1336
1337 /*
1338 * create message header - this is all zero except for
1339 * the message size, which is 4 bytes.
1340 */
1341 message[0] |= (4 << 8);
1342
1343 /* ignore 0:4 of byte zero, fill in port info yourself */
David Milburn87943ac2008-10-13 14:38:36 -05001344 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001345
1346 /* write message to EM_LOC */
1347 writel(message[0], mmio + hpriv->em_loc);
1348 writel(message[1], mmio + hpriv->em_loc+4);
1349
1350 /* save off new led state for port/slot */
1351 emp->led_state = message[1];
1352
1353 /*
1354 * tell hardware to transmit the message
1355 */
1356 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1357
1358 spin_unlock_irqrestore(ap->lock, flags);
1359 return size;
1360}
1361
1362static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1363{
1364 struct ahci_port_priv *pp = ap->private_data;
1365 struct ata_link *link;
1366 struct ahci_em_priv *emp;
1367 int rc = 0;
1368
Tejun Heo1eca4362008-11-03 20:03:17 +09001369 ata_for_each_link(link, ap, EDGE) {
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001370 emp = &pp->em_priv[link->pmp];
1371 rc += sprintf(buf, "%lx\n", emp->led_state);
1372 }
1373 return rc;
1374}
1375
1376static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1377 size_t size)
1378{
1379 int state;
1380 int pmp;
1381 struct ahci_port_priv *pp = ap->private_data;
1382 struct ahci_em_priv *emp;
1383
1384 state = simple_strtoul(buf, NULL, 0);
1385
1386 /* get the slot number from the message */
David Milburn87943ac2008-10-13 14:38:36 -05001387 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001388 if (pmp < MAX_SLOTS)
1389 emp = &pp->em_priv[pmp];
1390 else
1391 return -EINVAL;
1392
1393 /* mask off the activity bits if we are in sw_activity
1394 * mode, user should turn off sw_activity before setting
1395 * activity led through em_message
1396 */
1397 if (emp->blink_policy)
David Milburn87943ac2008-10-13 14:38:36 -05001398 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001399
1400 return ahci_transmit_led_message(ap, state, size);
1401}
1402
1403static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1404{
1405 struct ata_link *link = dev->link;
1406 struct ata_port *ap = link->ap;
1407 struct ahci_port_priv *pp = ap->private_data;
1408 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1409 u32 port_led_state = emp->led_state;
1410
1411 /* save the desired Activity LED behavior */
1412 if (val == OFF) {
1413 /* clear LFLAG */
1414 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1415
1416 /* set the LED to OFF */
David Milburn87943ac2008-10-13 14:38:36 -05001417 port_led_state &= EM_MSG_LED_VALUE_OFF;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001418 port_led_state |= (ap->port_no | (link->pmp << 8));
1419 ahci_transmit_led_message(ap, port_led_state, 4);
1420 } else {
1421 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1422 if (val == BLINK_OFF) {
1423 /* set LED to ON for idle */
David Milburn87943ac2008-10-13 14:38:36 -05001424 port_led_state &= EM_MSG_LED_VALUE_OFF;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001425 port_led_state |= (ap->port_no | (link->pmp << 8));
David Milburn87943ac2008-10-13 14:38:36 -05001426 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001427 ahci_transmit_led_message(ap, port_led_state, 4);
1428 }
1429 }
1430 emp->blink_policy = val;
1431 return 0;
1432}
1433
1434static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1435{
1436 struct ata_link *link = dev->link;
1437 struct ata_port *ap = link->ap;
1438 struct ahci_port_priv *pp = ap->private_data;
1439 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1440
1441 /* display the saved value of activity behavior for this
1442 * disk.
1443 */
1444 return sprintf(buf, "%d\n", emp->blink_policy);
1445}
1446
Jeff Garzik2bcd8662007-05-28 07:45:27 -04001447static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
1448 int port_no, void __iomem *mmio,
1449 void __iomem *port_mmio)
1450{
1451 const char *emsg = NULL;
1452 int rc;
1453 u32 tmp;
1454
1455 /* make sure port is not active */
1456 rc = ahci_deinit_port(ap, &emsg);
1457 if (rc)
1458 dev_printk(KERN_WARNING, &pdev->dev,
1459 "%s (%d)\n", emsg, rc);
1460
1461 /* clear SError */
1462 tmp = readl(port_mmio + PORT_SCR_ERR);
1463 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1464 writel(tmp, port_mmio + PORT_SCR_ERR);
1465
1466 /* clear port IRQ */
1467 tmp = readl(port_mmio + PORT_IRQ_STAT);
1468 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1469 if (tmp)
1470 writel(tmp, port_mmio + PORT_IRQ_STAT);
1471
1472 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1473}
1474
Tejun Heo4447d352007-04-17 23:44:08 +09001475static void ahci_init_controller(struct ata_host *host)
Tejun Heod91542c2006-07-26 15:59:26 +09001476{
Tejun Heo417a1a62007-09-23 13:19:55 +09001477 struct ahci_host_priv *hpriv = host->private_data;
Tejun Heo4447d352007-04-17 23:44:08 +09001478 struct pci_dev *pdev = to_pci_dev(host->dev);
1479 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Jeff Garzik2bcd8662007-05-28 07:45:27 -04001480 int i;
Jeff Garzikcd70c262007-07-08 02:29:42 -04001481 void __iomem *port_mmio;
Tejun Heod91542c2006-07-26 15:59:26 +09001482 u32 tmp;
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +01001483 int mv;
Tejun Heod91542c2006-07-26 15:59:26 +09001484
Tejun Heo417a1a62007-09-23 13:19:55 +09001485 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +01001486 if (pdev->device == 0x6121)
1487 mv = 2;
1488 else
1489 mv = 4;
1490 port_mmio = __ahci_port_base(host, mv);
Jeff Garzikcd70c262007-07-08 02:29:42 -04001491
1492 writel(0, port_mmio + PORT_IRQ_MASK);
1493
1494 /* clear port IRQ */
1495 tmp = readl(port_mmio + PORT_IRQ_STAT);
1496 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1497 if (tmp)
1498 writel(tmp, port_mmio + PORT_IRQ_STAT);
1499 }
1500
Tejun Heo4447d352007-04-17 23:44:08 +09001501 for (i = 0; i < host->n_ports; i++) {
1502 struct ata_port *ap = host->ports[i];
Tejun Heod91542c2006-07-26 15:59:26 +09001503
Jeff Garzikcd70c262007-07-08 02:29:42 -04001504 port_mmio = ahci_port_base(ap);
Tejun Heo4447d352007-04-17 23:44:08 +09001505 if (ata_port_is_dummy(ap))
Tejun Heod91542c2006-07-26 15:59:26 +09001506 continue;
Tejun Heod91542c2006-07-26 15:59:26 +09001507
Jeff Garzik2bcd8662007-05-28 07:45:27 -04001508 ahci_port_init(pdev, ap, i, mmio, port_mmio);
Tejun Heod91542c2006-07-26 15:59:26 +09001509 }
1510
1511 tmp = readl(mmio + HOST_CTL);
1512 VPRINTK("HOST_CTL 0x%x\n", tmp);
1513 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1514 tmp = readl(mmio + HOST_CTL);
1515 VPRINTK("HOST_CTL 0x%x\n", tmp);
1516}
1517
Jeff Garzika8785392008-02-28 15:43:48 -05001518static void ahci_dev_config(struct ata_device *dev)
1519{
1520 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1521
Jeff Garzik4cde32f2008-03-24 22:40:40 -04001522 if (hpriv->flags & AHCI_HFLAG_SECT255) {
Jeff Garzika8785392008-02-28 15:43:48 -05001523 dev->max_sectors = 255;
Jeff Garzik4cde32f2008-03-24 22:40:40 -04001524 ata_dev_printk(dev, KERN_INFO,
1525 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1526 }
Jeff Garzika8785392008-02-28 15:43:48 -05001527}
1528
Tejun Heo422b7592005-12-19 22:37:17 +09001529static unsigned int ahci_dev_classify(struct ata_port *ap)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001530{
Tejun Heo4447d352007-04-17 23:44:08 +09001531 void __iomem *port_mmio = ahci_port_base(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001532 struct ata_taskfile tf;
Tejun Heo422b7592005-12-19 22:37:17 +09001533 u32 tmp;
1534
1535 tmp = readl(port_mmio + PORT_SIG);
1536 tf.lbah = (tmp >> 24) & 0xff;
1537 tf.lbam = (tmp >> 16) & 0xff;
1538 tf.lbal = (tmp >> 8) & 0xff;
1539 tf.nsect = (tmp) & 0xff;
1540
1541 return ata_dev_classify(&tf);
1542}
1543
Tejun Heo12fad3f2006-05-15 21:03:55 +09001544static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1545 u32 opts)
Tejun Heocc9278e2006-02-10 17:25:47 +09001546{
Tejun Heo12fad3f2006-05-15 21:03:55 +09001547 dma_addr_t cmd_tbl_dma;
1548
1549 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1550
1551 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1552 pp->cmd_slot[tag].status = 0;
1553 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1554 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
Tejun Heocc9278e2006-02-10 17:25:47 +09001555}
1556
Tejun Heod2e75df2007-07-16 14:29:39 +09001557static int ahci_kick_engine(struct ata_port *ap, int force_restart)
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001558{
Tejun Heo350756f2008-04-07 22:47:21 +09001559 void __iomem *port_mmio = ahci_port_base(ap);
Jeff Garzikcca39742006-08-24 03:19:22 -04001560 struct ahci_host_priv *hpriv = ap->host->private_data;
Tejun Heo520d06f2008-04-07 22:47:21 +09001561 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001562 u32 tmp;
Tejun Heod2e75df2007-07-16 14:29:39 +09001563 int busy, rc;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001564
Tejun Heod2e75df2007-07-16 14:29:39 +09001565 /* do we need to kick the port? */
Tejun Heo520d06f2008-04-07 22:47:21 +09001566 busy = status & (ATA_BUSY | ATA_DRQ);
Tejun Heod2e75df2007-07-16 14:29:39 +09001567 if (!busy && !force_restart)
1568 return 0;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001569
Tejun Heod2e75df2007-07-16 14:29:39 +09001570 /* stop engine */
1571 rc = ahci_stop_engine(ap);
1572 if (rc)
1573 goto out_restart;
1574
1575 /* need to do CLO? */
1576 if (!busy) {
1577 rc = 0;
1578 goto out_restart;
1579 }
1580
1581 if (!(hpriv->cap & HOST_CAP_CLO)) {
1582 rc = -EOPNOTSUPP;
1583 goto out_restart;
1584 }
1585
1586 /* perform CLO */
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001587 tmp = readl(port_mmio + PORT_CMD);
1588 tmp |= PORT_CMD_CLO;
1589 writel(tmp, port_mmio + PORT_CMD);
1590
Tejun Heod2e75df2007-07-16 14:29:39 +09001591 rc = 0;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001592 tmp = ata_wait_register(port_mmio + PORT_CMD,
1593 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1594 if (tmp & PORT_CMD_CLO)
Tejun Heod2e75df2007-07-16 14:29:39 +09001595 rc = -EIO;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001596
Tejun Heod2e75df2007-07-16 14:29:39 +09001597 /* restart engine */
1598 out_restart:
1599 ahci_start_engine(ap);
1600 return rc;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001601}
1602
Tejun Heo91c4a2e2007-07-16 14:29:39 +09001603static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1604 struct ata_taskfile *tf, int is_cmd, u16 flags,
1605 unsigned long timeout_msec)
1606{
1607 const u32 cmd_fis_len = 5; /* five dwords */
1608 struct ahci_port_priv *pp = ap->private_data;
1609 void __iomem *port_mmio = ahci_port_base(ap);
1610 u8 *fis = pp->cmd_tbl;
1611 u32 tmp;
1612
1613 /* prep the command */
1614 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1615 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1616
1617 /* issue & wait */
1618 writel(1, port_mmio + PORT_CMD_ISSUE);
1619
1620 if (timeout_msec) {
1621 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1622 1, timeout_msec);
1623 if (tmp & 0x1) {
1624 ahci_kick_engine(ap, 1);
1625 return -EBUSY;
1626 }
1627 } else
1628 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1629
1630 return 0;
1631}
1632
Shane Huangbd172432008-06-10 15:52:04 +08001633static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1634 int pmp, unsigned long deadline,
1635 int (*check_ready)(struct ata_link *link))
Tejun Heo4658f792006-03-22 21:07:03 +09001636{
Tejun Heocc0680a2007-08-06 18:36:23 +09001637 struct ata_port *ap = link->ap;
Tejun Heo4658f792006-03-22 21:07:03 +09001638 const char *reason = NULL;
Tejun Heo2cbb79e2007-07-16 14:29:38 +09001639 unsigned long now, msecs;
Tejun Heo4658f792006-03-22 21:07:03 +09001640 struct ata_taskfile tf;
Tejun Heo4658f792006-03-22 21:07:03 +09001641 int rc;
1642
1643 DPRINTK("ENTER\n");
1644
1645 /* prepare for SRST (AHCI-1.1 10.4.1) */
Tejun Heod2e75df2007-07-16 14:29:39 +09001646 rc = ahci_kick_engine(ap, 1);
Tejun Heo994056d2007-12-06 15:02:48 +09001647 if (rc && rc != -EOPNOTSUPP)
Tejun Heocc0680a2007-08-06 18:36:23 +09001648 ata_link_printk(link, KERN_WARNING,
Tejun Heo994056d2007-12-06 15:02:48 +09001649 "failed to reset engine (errno=%d)\n", rc);
Tejun Heo4658f792006-03-22 21:07:03 +09001650
Tejun Heocc0680a2007-08-06 18:36:23 +09001651 ata_tf_init(link->device, &tf);
Tejun Heo4658f792006-03-22 21:07:03 +09001652
1653 /* issue the first D2H Register FIS */
Tejun Heo2cbb79e2007-07-16 14:29:38 +09001654 msecs = 0;
1655 now = jiffies;
1656 if (time_after(now, deadline))
1657 msecs = jiffies_to_msecs(deadline - now);
1658
Tejun Heo4658f792006-03-22 21:07:03 +09001659 tf.ctl |= ATA_SRST;
Tejun Heoa9cf5e82007-07-16 14:29:39 +09001660 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
Tejun Heo91c4a2e2007-07-16 14:29:39 +09001661 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
Tejun Heo4658f792006-03-22 21:07:03 +09001662 rc = -EIO;
1663 reason = "1st FIS failed";
1664 goto fail;
1665 }
1666
1667 /* spec says at least 5us, but be generous and sleep for 1ms */
1668 msleep(1);
1669
1670 /* issue the second D2H Register FIS */
Tejun Heo4658f792006-03-22 21:07:03 +09001671 tf.ctl &= ~ATA_SRST;
Tejun Heoa9cf5e82007-07-16 14:29:39 +09001672 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
Tejun Heo4658f792006-03-22 21:07:03 +09001673
Tejun Heo705e76b2008-04-07 22:47:19 +09001674 /* wait for link to become ready */
Shane Huangbd172432008-06-10 15:52:04 +08001675 rc = ata_wait_after_reset(link, deadline, check_ready);
Tejun Heo9b893912007-02-02 16:50:52 +09001676 /* link occupied, -ENODEV too is an error */
1677 if (rc) {
1678 reason = "device not ready";
1679 goto fail;
Tejun Heo4658f792006-03-22 21:07:03 +09001680 }
Tejun Heo9b893912007-02-02 16:50:52 +09001681 *class = ahci_dev_classify(ap);
Tejun Heo4658f792006-03-22 21:07:03 +09001682
1683 DPRINTK("EXIT, class=%u\n", *class);
1684 return 0;
1685
Tejun Heo4658f792006-03-22 21:07:03 +09001686 fail:
Tejun Heocc0680a2007-08-06 18:36:23 +09001687 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
Tejun Heo4658f792006-03-22 21:07:03 +09001688 return rc;
1689}
1690
Shane Huangbd172432008-06-10 15:52:04 +08001691static int ahci_check_ready(struct ata_link *link)
1692{
1693 void __iomem *port_mmio = ahci_port_base(link->ap);
1694 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1695
1696 return ata_check_ready(status);
1697}
1698
1699static int ahci_softreset(struct ata_link *link, unsigned int *class,
1700 unsigned long deadline)
1701{
1702 int pmp = sata_srst_pmp(link);
1703
1704 DPRINTK("ENTER\n");
1705
1706 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1707}
1708
1709static int ahci_sb600_check_ready(struct ata_link *link)
1710{
1711 void __iomem *port_mmio = ahci_port_base(link->ap);
1712 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1713 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1714
1715 /*
1716 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1717 * which can save timeout delay.
1718 */
1719 if (irq_status & PORT_IRQ_BAD_PMP)
1720 return -EIO;
1721
1722 return ata_check_ready(status);
1723}
1724
1725static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
1726 unsigned long deadline)
1727{
1728 struct ata_port *ap = link->ap;
1729 void __iomem *port_mmio = ahci_port_base(ap);
1730 int pmp = sata_srst_pmp(link);
1731 int rc;
1732 u32 irq_sts;
1733
1734 DPRINTK("ENTER\n");
1735
1736 rc = ahci_do_softreset(link, class, pmp, deadline,
1737 ahci_sb600_check_ready);
1738
1739 /*
1740 * Soft reset fails on some ATI chips with IPMS set when PMP
1741 * is enabled but SATA HDD/ODD is connected to SATA port,
1742 * do soft reset again to port 0.
1743 */
1744 if (rc == -EIO) {
1745 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1746 if (irq_sts & PORT_IRQ_BAD_PMP) {
1747 ata_link_printk(link, KERN_WARNING,
1748 "failed due to HW bug, retry pmp=0\n");
1749 rc = ahci_do_softreset(link, class, 0, deadline,
1750 ahci_check_ready);
1751 }
1752 }
1753
1754 return rc;
1755}
1756
Tejun Heocc0680a2007-08-06 18:36:23 +09001757static int ahci_hardreset(struct ata_link *link, unsigned int *class,
Tejun Heod4b2bab2007-02-02 16:50:52 +09001758 unsigned long deadline)
Tejun Heo422b7592005-12-19 22:37:17 +09001759{
Tejun Heo9dadd452008-04-07 22:47:19 +09001760 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
Tejun Heocc0680a2007-08-06 18:36:23 +09001761 struct ata_port *ap = link->ap;
Tejun Heo42969712006-05-31 18:28:18 +09001762 struct ahci_port_priv *pp = ap->private_data;
1763 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1764 struct ata_taskfile tf;
Tejun Heo9dadd452008-04-07 22:47:19 +09001765 bool online;
Tejun Heo4bd00f62006-02-11 16:26:02 +09001766 int rc;
1767
1768 DPRINTK("ENTER\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001769
Tejun Heo4447d352007-04-17 23:44:08 +09001770 ahci_stop_engine(ap);
Tejun Heo42969712006-05-31 18:28:18 +09001771
1772 /* clear D2H reception area to properly wait for D2H FIS */
Tejun Heocc0680a2007-08-06 18:36:23 +09001773 ata_tf_init(link->device, &tf);
Tejun Heodfd7a3d2007-01-26 15:37:20 +09001774 tf.command = 0x80;
Tejun Heo99771262007-07-16 14:29:38 +09001775 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
Tejun Heo42969712006-05-31 18:28:18 +09001776
Tejun Heo9dadd452008-04-07 22:47:19 +09001777 rc = sata_link_hardreset(link, timing, deadline, &online,
1778 ahci_check_ready);
Tejun Heo42969712006-05-31 18:28:18 +09001779
Tejun Heo4447d352007-04-17 23:44:08 +09001780 ahci_start_engine(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001781
Tejun Heo9dadd452008-04-07 22:47:19 +09001782 if (online)
Tejun Heo4bd00f62006-02-11 16:26:02 +09001783 *class = ahci_dev_classify(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001784
Tejun Heo4bd00f62006-02-11 16:26:02 +09001785 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1786 return rc;
1787}
1788
Tejun Heocc0680a2007-08-06 18:36:23 +09001789static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
Tejun Heod4b2bab2007-02-02 16:50:52 +09001790 unsigned long deadline)
Tejun Heoad616ff2006-11-01 18:00:24 +09001791{
Tejun Heocc0680a2007-08-06 18:36:23 +09001792 struct ata_port *ap = link->ap;
Tejun Heo9dadd452008-04-07 22:47:19 +09001793 bool online;
Tejun Heoad616ff2006-11-01 18:00:24 +09001794 int rc;
1795
1796 DPRINTK("ENTER\n");
1797
Tejun Heo4447d352007-04-17 23:44:08 +09001798 ahci_stop_engine(ap);
Tejun Heoad616ff2006-11-01 18:00:24 +09001799
Tejun Heocc0680a2007-08-06 18:36:23 +09001800 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
Tejun Heo9dadd452008-04-07 22:47:19 +09001801 deadline, &online, NULL);
Tejun Heoad616ff2006-11-01 18:00:24 +09001802
Tejun Heo4447d352007-04-17 23:44:08 +09001803 ahci_start_engine(ap);
Tejun Heoad616ff2006-11-01 18:00:24 +09001804
1805 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1806
1807 /* vt8251 doesn't clear BSY on signature FIS reception,
1808 * request follow-up softreset.
1809 */
Tejun Heo9dadd452008-04-07 22:47:19 +09001810 return online ? -EAGAIN : rc;
Tejun Heoad616ff2006-11-01 18:00:24 +09001811}
1812
Tejun Heoedc93052007-10-25 14:59:16 +09001813static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1814 unsigned long deadline)
1815{
1816 struct ata_port *ap = link->ap;
1817 struct ahci_port_priv *pp = ap->private_data;
1818 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1819 struct ata_taskfile tf;
Tejun Heo9dadd452008-04-07 22:47:19 +09001820 bool online;
Tejun Heoedc93052007-10-25 14:59:16 +09001821 int rc;
1822
1823 ahci_stop_engine(ap);
1824
1825 /* clear D2H reception area to properly wait for D2H FIS */
1826 ata_tf_init(link->device, &tf);
1827 tf.command = 0x80;
1828 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1829
1830 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
Tejun Heo9dadd452008-04-07 22:47:19 +09001831 deadline, &online, NULL);
Tejun Heoedc93052007-10-25 14:59:16 +09001832
1833 ahci_start_engine(ap);
1834
Tejun Heoedc93052007-10-25 14:59:16 +09001835 /* The pseudo configuration device on SIMG4726 attached to
1836 * ASUS P5W-DH Deluxe doesn't send signature FIS after
1837 * hardreset if no device is attached to the first downstream
1838 * port && the pseudo device locks up on SRST w/ PMP==0. To
1839 * work around this, wait for !BSY only briefly. If BSY isn't
1840 * cleared, perform CLO and proceed to IDENTIFY (achieved by
1841 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
1842 *
1843 * Wait for two seconds. Devices attached to downstream port
1844 * which can't process the following IDENTIFY after this will
1845 * have to be reset again. For most cases, this should
1846 * suffice while making probing snappish enough.
1847 */
Tejun Heo9dadd452008-04-07 22:47:19 +09001848 if (online) {
1849 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
1850 ahci_check_ready);
1851 if (rc)
1852 ahci_kick_engine(ap, 0);
1853 }
Tejun Heo9dadd452008-04-07 22:47:19 +09001854 return rc;
Tejun Heoedc93052007-10-25 14:59:16 +09001855}
1856
Tejun Heocc0680a2007-08-06 18:36:23 +09001857static void ahci_postreset(struct ata_link *link, unsigned int *class)
Tejun Heo4bd00f62006-02-11 16:26:02 +09001858{
Tejun Heocc0680a2007-08-06 18:36:23 +09001859 struct ata_port *ap = link->ap;
Tejun Heo4447d352007-04-17 23:44:08 +09001860 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo4bd00f62006-02-11 16:26:02 +09001861 u32 new_tmp, tmp;
1862
Tejun Heo203c75b2008-04-07 22:47:18 +09001863 ata_std_postreset(link, class);
Jeff Garzik02eaa662005-11-12 01:32:19 -05001864
1865 /* Make sure port's ATAPI bit is set appropriately */
1866 new_tmp = tmp = readl(port_mmio + PORT_CMD);
Tejun Heo4bd00f62006-02-11 16:26:02 +09001867 if (*class == ATA_DEV_ATAPI)
Jeff Garzik02eaa662005-11-12 01:32:19 -05001868 new_tmp |= PORT_CMD_ATAPI;
1869 else
1870 new_tmp &= ~PORT_CMD_ATAPI;
1871 if (new_tmp != tmp) {
1872 writel(new_tmp, port_mmio + PORT_CMD);
1873 readl(port_mmio + PORT_CMD); /* flush */
1874 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001875}
1876
Tejun Heo12fad3f2006-05-15 21:03:55 +09001877static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001878{
Jeff Garzikcedc9a42005-10-05 07:13:30 -04001879 struct scatterlist *sg;
Tejun Heoff2aeb12007-12-05 16:43:11 +09001880 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1881 unsigned int si;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001882
1883 VPRINTK("ENTER\n");
1884
1885 /*
1886 * Next, the S/G list.
1887 */
Tejun Heoff2aeb12007-12-05 16:43:11 +09001888 for_each_sg(qc->sg, sg, qc->n_elem, si) {
Jeff Garzikcedc9a42005-10-05 07:13:30 -04001889 dma_addr_t addr = sg_dma_address(sg);
1890 u32 sg_len = sg_dma_len(sg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001891
Tejun Heoff2aeb12007-12-05 16:43:11 +09001892 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1893 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1894 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001895 }
Jeff Garzik828d09d2005-11-12 01:27:07 -05001896
Tejun Heoff2aeb12007-12-05 16:43:11 +09001897 return si;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001898}
1899
1900static void ahci_qc_prep(struct ata_queued_cmd *qc)
1901{
Jeff Garzika0ea7322005-06-04 01:13:15 -04001902 struct ata_port *ap = qc->ap;
1903 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo405e66b2007-11-27 19:28:53 +09001904 int is_atapi = ata_is_atapi(qc->tf.protocol);
Tejun Heo12fad3f2006-05-15 21:03:55 +09001905 void *cmd_tbl;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001906 u32 opts;
1907 const u32 cmd_fis_len = 5; /* five dwords */
Jeff Garzik828d09d2005-11-12 01:27:07 -05001908 unsigned int n_elem;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001909
1910 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001911 * Fill in command table information. First, the header,
1912 * a SATA Register - Host to Device command FIS.
1913 */
Tejun Heo12fad3f2006-05-15 21:03:55 +09001914 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1915
Tejun Heo7d50b602007-09-23 13:19:54 +09001916 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
Tejun Heocc9278e2006-02-10 17:25:47 +09001917 if (is_atapi) {
Tejun Heo12fad3f2006-05-15 21:03:55 +09001918 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1919 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
Jeff Garzika0ea7322005-06-04 01:13:15 -04001920 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001921
Tejun Heocc9278e2006-02-10 17:25:47 +09001922 n_elem = 0;
1923 if (qc->flags & ATA_QCFLAG_DMAMAP)
Tejun Heo12fad3f2006-05-15 21:03:55 +09001924 n_elem = ahci_fill_sg(qc, cmd_tbl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001925
Tejun Heocc9278e2006-02-10 17:25:47 +09001926 /*
1927 * Fill in command slot information.
1928 */
Tejun Heo7d50b602007-09-23 13:19:54 +09001929 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
Tejun Heocc9278e2006-02-10 17:25:47 +09001930 if (qc->tf.flags & ATA_TFLAG_WRITE)
1931 opts |= AHCI_CMD_WRITE;
1932 if (is_atapi)
Tejun Heo4b10e552006-03-12 11:25:27 +09001933 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
Jeff Garzik828d09d2005-11-12 01:27:07 -05001934
Tejun Heo12fad3f2006-05-15 21:03:55 +09001935 ahci_fill_cmd_slot(pp, qc->tag, opts);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001936}
1937
Tejun Heo78cd52d2006-05-15 20:58:29 +09001938static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001939{
Tejun Heo417a1a62007-09-23 13:19:55 +09001940 struct ahci_host_priv *hpriv = ap->host->private_data;
Tejun Heo78cd52d2006-05-15 20:58:29 +09001941 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo7d50b602007-09-23 13:19:54 +09001942 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1943 struct ata_link *link = NULL;
1944 struct ata_queued_cmd *active_qc;
1945 struct ata_eh_info *active_ehi;
Tejun Heo78cd52d2006-05-15 20:58:29 +09001946 u32 serror;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001947
Tejun Heo7d50b602007-09-23 13:19:54 +09001948 /* determine active link */
Tejun Heo1eca4362008-11-03 20:03:17 +09001949 ata_for_each_link(link, ap, EDGE)
Tejun Heo7d50b602007-09-23 13:19:54 +09001950 if (ata_link_active(link))
1951 break;
1952 if (!link)
1953 link = &ap->link;
1954
1955 active_qc = ata_qc_from_tag(ap, link->active_tag);
1956 active_ehi = &link->eh_info;
1957
1958 /* record irq stat */
1959 ata_ehi_clear_desc(host_ehi);
1960 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
Jeff Garzik9f68a242005-11-15 14:03:47 -05001961
Tejun Heo78cd52d2006-05-15 20:58:29 +09001962 /* AHCI needs SError cleared; otherwise, it might lock up */
Tejun Heo82ef04f2008-07-31 17:02:40 +09001963 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1964 ahci_scr_write(&ap->link, SCR_ERROR, serror);
Tejun Heo7d50b602007-09-23 13:19:54 +09001965 host_ehi->serror |= serror;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001966
Tejun Heo41669552006-11-29 11:33:14 +09001967 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
Tejun Heo417a1a62007-09-23 13:19:55 +09001968 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
Tejun Heo41669552006-11-29 11:33:14 +09001969 irq_stat &= ~PORT_IRQ_IF_ERR;
1970
Conke Hu55a61602007-03-27 18:33:05 +08001971 if (irq_stat & PORT_IRQ_TF_ERR) {
Tejun Heo7d50b602007-09-23 13:19:54 +09001972 /* If qc is active, charge it; otherwise, the active
1973 * link. There's no active qc on NCQ errors. It will
1974 * be determined by EH by reading log page 10h.
1975 */
1976 if (active_qc)
1977 active_qc->err_mask |= AC_ERR_DEV;
1978 else
1979 active_ehi->err_mask |= AC_ERR_DEV;
1980
Tejun Heo417a1a62007-09-23 13:19:55 +09001981 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
Tejun Heo7d50b602007-09-23 13:19:54 +09001982 host_ehi->serror &= ~SERR_INTERNAL;
Tejun Heo78cd52d2006-05-15 20:58:29 +09001983 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001984
Tejun Heo78cd52d2006-05-15 20:58:29 +09001985 if (irq_stat & PORT_IRQ_UNK_FIS) {
1986 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001987
Tejun Heo7d50b602007-09-23 13:19:54 +09001988 active_ehi->err_mask |= AC_ERR_HSM;
Tejun Heocf480622008-01-24 00:05:14 +09001989 active_ehi->action |= ATA_EH_RESET;
Tejun Heo7d50b602007-09-23 13:19:54 +09001990 ata_ehi_push_desc(active_ehi,
1991 "unknown FIS %08x %08x %08x %08x" ,
Tejun Heo78cd52d2006-05-15 20:58:29 +09001992 unk[0], unk[1], unk[2], unk[3]);
1993 }
Jeff Garzikb8f61532005-08-25 22:01:20 -04001994
Tejun Heo071f44b2008-04-07 22:47:22 +09001995 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
Tejun Heo7d50b602007-09-23 13:19:54 +09001996 active_ehi->err_mask |= AC_ERR_HSM;
Tejun Heocf480622008-01-24 00:05:14 +09001997 active_ehi->action |= ATA_EH_RESET;
Tejun Heo7d50b602007-09-23 13:19:54 +09001998 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1999 }
Tejun Heo78cd52d2006-05-15 20:58:29 +09002000
Tejun Heo7d50b602007-09-23 13:19:54 +09002001 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
2002 host_ehi->err_mask |= AC_ERR_HOST_BUS;
Tejun Heocf480622008-01-24 00:05:14 +09002003 host_ehi->action |= ATA_EH_RESET;
Tejun Heo7d50b602007-09-23 13:19:54 +09002004 ata_ehi_push_desc(host_ehi, "host bus error");
2005 }
2006
2007 if (irq_stat & PORT_IRQ_IF_ERR) {
2008 host_ehi->err_mask |= AC_ERR_ATA_BUS;
Tejun Heocf480622008-01-24 00:05:14 +09002009 host_ehi->action |= ATA_EH_RESET;
Tejun Heo7d50b602007-09-23 13:19:54 +09002010 ata_ehi_push_desc(host_ehi, "interface fatal error");
2011 }
2012
2013 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
2014 ata_ehi_hotplugged(host_ehi);
2015 ata_ehi_push_desc(host_ehi, "%s",
2016 irq_stat & PORT_IRQ_CONNECT ?
2017 "connection status changed" : "PHY RDY changed");
2018 }
2019
2020 /* okay, let's hand over to EH */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002021
Tejun Heo78cd52d2006-05-15 20:58:29 +09002022 if (irq_stat & PORT_IRQ_FREEZE)
2023 ata_port_freeze(ap);
2024 else
2025 ata_port_abort(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002026}
2027
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04002028static void ahci_port_intr(struct ata_port *ap)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002029{
Tejun Heo350756f2008-04-07 22:47:21 +09002030 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo9af5c9c2007-08-06 18:36:22 +09002031 struct ata_eh_info *ehi = &ap->link.eh_info;
Tejun Heo0291f952007-01-25 19:16:28 +09002032 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo5f226c62007-10-09 15:02:23 +09002033 struct ahci_host_priv *hpriv = ap->host->private_data;
Tejun Heob06ce3e2007-10-09 15:06:48 +09002034 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
Tejun Heo12fad3f2006-05-15 21:03:55 +09002035 u32 status, qc_active;
Tejun Heo459ad682007-12-07 12:46:23 +09002036 int rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002037
2038 status = readl(port_mmio + PORT_IRQ_STAT);
2039 writel(status, port_mmio + PORT_IRQ_STAT);
2040
Tejun Heob06ce3e2007-10-09 15:06:48 +09002041 /* ignore BAD_PMP while resetting */
2042 if (unlikely(resetting))
2043 status &= ~PORT_IRQ_BAD_PMP;
2044
Kristen Carlson Accardi31556592007-10-25 01:33:26 -04002045 /* If we are getting PhyRdy, this is
2046 * just a power state change, we should
2047 * clear out this, plus the PhyRdy/Comm
2048 * Wake bits from Serror
2049 */
2050 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
2051 (status & PORT_IRQ_PHYRDY)) {
2052 status &= ~PORT_IRQ_PHYRDY;
Tejun Heo82ef04f2008-07-31 17:02:40 +09002053 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
Kristen Carlson Accardi31556592007-10-25 01:33:26 -04002054 }
2055
Tejun Heo78cd52d2006-05-15 20:58:29 +09002056 if (unlikely(status & PORT_IRQ_ERROR)) {
2057 ahci_error_intr(ap, status);
2058 return;
2059 }
2060
Kristen Carlson Accardi2f294962007-08-15 04:11:25 -04002061 if (status & PORT_IRQ_SDB_FIS) {
Tejun Heo5f226c62007-10-09 15:02:23 +09002062 /* If SNotification is available, leave notification
2063 * handling to sata_async_notification(). If not,
2064 * emulate it by snooping SDB FIS RX area.
2065 *
2066 * Snooping FIS RX area is probably cheaper than
2067 * poking SNotification but some constrollers which
2068 * implement SNotification, ICH9 for example, don't
2069 * store AN SDB FIS into receive area.
Kristen Carlson Accardi2f294962007-08-15 04:11:25 -04002070 */
Tejun Heo5f226c62007-10-09 15:02:23 +09002071 if (hpriv->cap & HOST_CAP_SNTF)
Tejun Heo7d77b242007-09-23 13:14:13 +09002072 sata_async_notification(ap);
Tejun Heo5f226c62007-10-09 15:02:23 +09002073 else {
2074 /* If the 'N' bit in word 0 of the FIS is set,
2075 * we just received asynchronous notification.
2076 * Tell libata about it.
2077 */
2078 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
2079 u32 f0 = le32_to_cpu(f[0]);
2080
2081 if (f0 & (1 << 15))
2082 sata_async_notification(ap);
2083 }
Kristen Carlson Accardi2f294962007-08-15 04:11:25 -04002084 }
2085
Tejun Heo7d50b602007-09-23 13:19:54 +09002086 /* pp->active_link is valid iff any command is in flight */
2087 if (ap->qc_active && pp->active_link->sactive)
Tejun Heo12fad3f2006-05-15 21:03:55 +09002088 qc_active = readl(port_mmio + PORT_SCR_ACT);
2089 else
2090 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
2091
Tejun Heo79f97da2008-04-07 22:47:20 +09002092 rc = ata_qc_complete_multiple(ap, qc_active);
Tejun Heob06ce3e2007-10-09 15:06:48 +09002093
Tejun Heo459ad682007-12-07 12:46:23 +09002094 /* while resetting, invalid completions are expected */
2095 if (unlikely(rc < 0 && !resetting)) {
Tejun Heo12fad3f2006-05-15 21:03:55 +09002096 ehi->err_mask |= AC_ERR_HSM;
Tejun Heocf480622008-01-24 00:05:14 +09002097 ehi->action |= ATA_EH_RESET;
Tejun Heo12fad3f2006-05-15 21:03:55 +09002098 ata_port_freeze(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002099 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002100}
2101
David Howells7d12e782006-10-05 14:55:46 +01002102static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002103{
Jeff Garzikcca39742006-08-24 03:19:22 -04002104 struct ata_host *host = dev_instance;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002105 struct ahci_host_priv *hpriv;
2106 unsigned int i, handled = 0;
Jeff Garzikea6ba102005-08-30 05:18:18 -04002107 void __iomem *mmio;
Tejun Heod28f87a2008-07-05 13:10:50 +09002108 u32 irq_stat, irq_masked;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002109
2110 VPRINTK("ENTER\n");
2111
Jeff Garzikcca39742006-08-24 03:19:22 -04002112 hpriv = host->private_data;
Tejun Heo0d5ff562007-02-01 15:06:36 +09002113 mmio = host->iomap[AHCI_PCI_BAR];
Linus Torvalds1da177e2005-04-16 15:20:36 -07002114
2115 /* sigh. 0xffffffff is a valid return from h/w */
2116 irq_stat = readl(mmio + HOST_IRQ_STAT);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002117 if (!irq_stat)
2118 return IRQ_NONE;
2119
Tejun Heod28f87a2008-07-05 13:10:50 +09002120 irq_masked = irq_stat & hpriv->port_map;
2121
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002122 spin_lock(&host->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002123
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002124 for (i = 0; i < host->n_ports; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002125 struct ata_port *ap;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002126
Tejun Heod28f87a2008-07-05 13:10:50 +09002127 if (!(irq_masked & (1 << i)))
Jeff Garzik67846b32005-10-05 02:58:32 -04002128 continue;
2129
Jeff Garzikcca39742006-08-24 03:19:22 -04002130 ap = host->ports[i];
Jeff Garzik67846b32005-10-05 02:58:32 -04002131 if (ap) {
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04002132 ahci_port_intr(ap);
Jeff Garzik67846b32005-10-05 02:58:32 -04002133 VPRINTK("port %u\n", i);
2134 } else {
2135 VPRINTK("port %u (no irq)\n", i);
Tejun Heo6971ed12006-03-11 12:47:54 +09002136 if (ata_ratelimit())
Jeff Garzikcca39742006-08-24 03:19:22 -04002137 dev_printk(KERN_WARNING, host->dev,
Jeff Garzika9524a72005-10-30 14:39:11 -05002138 "interrupt on disabled port %u\n", i);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002139 }
Jeff Garzik67846b32005-10-05 02:58:32 -04002140
Linus Torvalds1da177e2005-04-16 15:20:36 -07002141 handled = 1;
2142 }
2143
Tejun Heod28f87a2008-07-05 13:10:50 +09002144 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
2145 * it should be cleared after all the port events are cleared;
2146 * otherwise, it will raise a spurious interrupt after each
2147 * valid one. Please read section 10.6.2 of ahci 1.1 for more
2148 * information.
2149 *
2150 * Also, use the unmasked value to clear interrupt as spurious
2151 * pending event on a dummy port might cause screaming IRQ.
2152 */
Tejun Heoea0c62f2008-06-28 01:49:02 +09002153 writel(irq_stat, mmio + HOST_IRQ_STAT);
2154
Jeff Garzikcca39742006-08-24 03:19:22 -04002155 spin_unlock(&host->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002156
2157 VPRINTK("EXIT\n");
2158
2159 return IRQ_RETVAL(handled);
2160}
2161
Tejun Heo9a3d9eb2006-01-23 13:09:36 +09002162static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002163{
2164 struct ata_port *ap = qc->ap;
Tejun Heo4447d352007-04-17 23:44:08 +09002165 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo7d50b602007-09-23 13:19:54 +09002166 struct ahci_port_priv *pp = ap->private_data;
2167
2168 /* Keep track of the currently active link. It will be used
2169 * in completion path to determine whether NCQ phase is in
2170 * progress.
2171 */
2172 pp->active_link = qc->dev->link;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002173
Tejun Heo12fad3f2006-05-15 21:03:55 +09002174 if (qc->tf.protocol == ATA_PROT_NCQ)
2175 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
2176 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002177
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07002178 ahci_sw_activity(qc->dev->link);
2179
Linus Torvalds1da177e2005-04-16 15:20:36 -07002180 return 0;
2181}
2182
Tejun Heo4c9bf4e2008-04-07 22:47:20 +09002183static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2184{
2185 struct ahci_port_priv *pp = qc->ap->private_data;
2186 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
2187
2188 ata_tf_from_fis(d2h_fis, &qc->result_tf);
2189 return true;
2190}
2191
Tejun Heo78cd52d2006-05-15 20:58:29 +09002192static void ahci_freeze(struct ata_port *ap)
2193{
Tejun Heo4447d352007-04-17 23:44:08 +09002194 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +09002195
2196 /* turn IRQ off */
2197 writel(0, port_mmio + PORT_IRQ_MASK);
2198}
2199
2200static void ahci_thaw(struct ata_port *ap)
2201{
Tejun Heo0d5ff562007-02-01 15:06:36 +09002202 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
Tejun Heo4447d352007-04-17 23:44:08 +09002203 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +09002204 u32 tmp;
Kristen Carlson Accardia7384922007-08-09 14:23:41 -07002205 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo78cd52d2006-05-15 20:58:29 +09002206
2207 /* clear IRQ */
2208 tmp = readl(port_mmio + PORT_IRQ_STAT);
2209 writel(tmp, port_mmio + PORT_IRQ_STAT);
Tejun Heoa7187282007-01-27 11:04:26 +09002210 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
Tejun Heo78cd52d2006-05-15 20:58:29 +09002211
Tejun Heo1c954a42007-10-09 15:01:37 +09002212 /* turn IRQ back on */
2213 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
Tejun Heo78cd52d2006-05-15 20:58:29 +09002214}
2215
2216static void ahci_error_handler(struct ata_port *ap)
2217{
Tejun Heob51e9e52006-06-29 01:29:30 +09002218 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
Tejun Heo78cd52d2006-05-15 20:58:29 +09002219 /* restart engine */
Tejun Heo4447d352007-04-17 23:44:08 +09002220 ahci_stop_engine(ap);
2221 ahci_start_engine(ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +09002222 }
2223
Tejun Heoa1efdab2008-03-25 12:22:50 +09002224 sata_pmp_error_handler(ap);
Tejun Heoedc93052007-10-25 14:59:16 +09002225}
2226
Tejun Heo78cd52d2006-05-15 20:58:29 +09002227static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2228{
2229 struct ata_port *ap = qc->ap;
2230
Tejun Heod2e75df2007-07-16 14:29:39 +09002231 /* make DMA engine forget about the failed command */
2232 if (qc->flags & ATA_QCFLAG_FAILED)
2233 ahci_kick_engine(ap, 1);
Tejun Heo78cd52d2006-05-15 20:58:29 +09002234}
2235
Tejun Heo7d50b602007-09-23 13:19:54 +09002236static void ahci_pmp_attach(struct ata_port *ap)
2237{
2238 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo1c954a42007-10-09 15:01:37 +09002239 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo7d50b602007-09-23 13:19:54 +09002240 u32 cmd;
2241
2242 cmd = readl(port_mmio + PORT_CMD);
2243 cmd |= PORT_CMD_PMP;
2244 writel(cmd, port_mmio + PORT_CMD);
Tejun Heo1c954a42007-10-09 15:01:37 +09002245
2246 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2247 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
Tejun Heo7d50b602007-09-23 13:19:54 +09002248}
2249
2250static void ahci_pmp_detach(struct ata_port *ap)
2251{
2252 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo1c954a42007-10-09 15:01:37 +09002253 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo7d50b602007-09-23 13:19:54 +09002254 u32 cmd;
2255
2256 cmd = readl(port_mmio + PORT_CMD);
2257 cmd &= ~PORT_CMD_PMP;
2258 writel(cmd, port_mmio + PORT_CMD);
Tejun Heo1c954a42007-10-09 15:01:37 +09002259
2260 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2261 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
Tejun Heo7d50b602007-09-23 13:19:54 +09002262}
2263
Alexey Dobriyan028a2592007-07-17 23:48:48 +04002264static int ahci_port_resume(struct ata_port *ap)
2265{
2266 ahci_power_up(ap);
2267 ahci_start_port(ap);
2268
Tejun Heo071f44b2008-04-07 22:47:22 +09002269 if (sata_pmp_attached(ap))
Tejun Heo7d50b602007-09-23 13:19:54 +09002270 ahci_pmp_attach(ap);
2271 else
2272 ahci_pmp_detach(ap);
2273
Alexey Dobriyan028a2592007-07-17 23:48:48 +04002274 return 0;
2275}
2276
Tejun Heo438ac6d2007-03-02 17:31:26 +09002277#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +09002278static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2279{
Tejun Heoc1332872006-07-26 15:59:26 +09002280 const char *emsg = NULL;
2281 int rc;
2282
Tejun Heo4447d352007-04-17 23:44:08 +09002283 rc = ahci_deinit_port(ap, &emsg);
Tejun Heo8e16f942006-11-20 15:42:36 +09002284 if (rc == 0)
Tejun Heo4447d352007-04-17 23:44:08 +09002285 ahci_power_down(ap);
Tejun Heo8e16f942006-11-20 15:42:36 +09002286 else {
Tejun Heoc1332872006-07-26 15:59:26 +09002287 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04002288 ahci_start_port(ap);
Tejun Heoc1332872006-07-26 15:59:26 +09002289 }
2290
2291 return rc;
2292}
2293
Tejun Heoc1332872006-07-26 15:59:26 +09002294static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
2295{
Jeff Garzikcca39742006-08-24 03:19:22 -04002296 struct ata_host *host = dev_get_drvdata(&pdev->dev);
Tejun Heo0d5ff562007-02-01 15:06:36 +09002297 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Tejun Heoc1332872006-07-26 15:59:26 +09002298 u32 ctl;
2299
Rafael J. Wysocki3a2d5b72008-02-23 19:13:25 +01002300 if (mesg.event & PM_EVENT_SLEEP) {
Tejun Heoc1332872006-07-26 15:59:26 +09002301 /* AHCI spec rev1.1 section 8.3.3:
2302 * Software must disable interrupts prior to requesting a
2303 * transition of the HBA to D3 state.
2304 */
2305 ctl = readl(mmio + HOST_CTL);
2306 ctl &= ~HOST_IRQ_EN;
2307 writel(ctl, mmio + HOST_CTL);
2308 readl(mmio + HOST_CTL); /* flush */
2309 }
2310
2311 return ata_pci_device_suspend(pdev, mesg);
2312}
2313
2314static int ahci_pci_device_resume(struct pci_dev *pdev)
2315{
Jeff Garzikcca39742006-08-24 03:19:22 -04002316 struct ata_host *host = dev_get_drvdata(&pdev->dev);
Tejun Heoc1332872006-07-26 15:59:26 +09002317 int rc;
2318
Tejun Heo553c4aa2006-12-26 19:39:50 +09002319 rc = ata_pci_device_do_resume(pdev);
2320 if (rc)
2321 return rc;
Tejun Heoc1332872006-07-26 15:59:26 +09002322
2323 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
Tejun Heo4447d352007-04-17 23:44:08 +09002324 rc = ahci_reset_controller(host);
Tejun Heoc1332872006-07-26 15:59:26 +09002325 if (rc)
2326 return rc;
2327
Tejun Heo4447d352007-04-17 23:44:08 +09002328 ahci_init_controller(host);
Tejun Heoc1332872006-07-26 15:59:26 +09002329 }
2330
Jeff Garzikcca39742006-08-24 03:19:22 -04002331 ata_host_resume(host);
Tejun Heoc1332872006-07-26 15:59:26 +09002332
2333 return 0;
2334}
Tejun Heo438ac6d2007-03-02 17:31:26 +09002335#endif
Tejun Heoc1332872006-07-26 15:59:26 +09002336
Tejun Heo254950c2006-07-26 15:59:25 +09002337static int ahci_port_start(struct ata_port *ap)
2338{
Jeff Garzikcca39742006-08-24 03:19:22 -04002339 struct device *dev = ap->host->dev;
Tejun Heo254950c2006-07-26 15:59:25 +09002340 struct ahci_port_priv *pp;
Tejun Heo254950c2006-07-26 15:59:25 +09002341 void *mem;
2342 dma_addr_t mem_dma;
Tejun Heo254950c2006-07-26 15:59:25 +09002343
Tejun Heo24dc5f32007-01-20 16:00:28 +09002344 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
Tejun Heo254950c2006-07-26 15:59:25 +09002345 if (!pp)
2346 return -ENOMEM;
Tejun Heo254950c2006-07-26 15:59:25 +09002347
Tejun Heo24dc5f32007-01-20 16:00:28 +09002348 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
2349 GFP_KERNEL);
2350 if (!mem)
Tejun Heo254950c2006-07-26 15:59:25 +09002351 return -ENOMEM;
Tejun Heo254950c2006-07-26 15:59:25 +09002352 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
2353
2354 /*
2355 * First item in chunk of DMA memory: 32-slot command table,
2356 * 32 bytes each in size
2357 */
2358 pp->cmd_slot = mem;
2359 pp->cmd_slot_dma = mem_dma;
2360
2361 mem += AHCI_CMD_SLOT_SZ;
2362 mem_dma += AHCI_CMD_SLOT_SZ;
2363
2364 /*
2365 * Second item: Received-FIS area
2366 */
2367 pp->rx_fis = mem;
2368 pp->rx_fis_dma = mem_dma;
2369
2370 mem += AHCI_RX_FIS_SZ;
2371 mem_dma += AHCI_RX_FIS_SZ;
2372
2373 /*
2374 * Third item: data area for storing a single command
2375 * and its scatter-gather table
2376 */
2377 pp->cmd_tbl = mem;
2378 pp->cmd_tbl_dma = mem_dma;
2379
Kristen Carlson Accardia7384922007-08-09 14:23:41 -07002380 /*
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002381 * Save off initial list of interrupts to be enabled.
2382 * This could be changed later
2383 */
Kristen Carlson Accardia7384922007-08-09 14:23:41 -07002384 pp->intr_mask = DEF_PORT_IRQ;
2385
Tejun Heo254950c2006-07-26 15:59:25 +09002386 ap->private_data = pp;
2387
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04002388 /* engage engines, captain */
2389 return ahci_port_resume(ap);
Tejun Heo254950c2006-07-26 15:59:25 +09002390}
2391
2392static void ahci_port_stop(struct ata_port *ap)
2393{
Tejun Heo0be0aa92006-07-26 15:59:26 +09002394 const char *emsg = NULL;
2395 int rc;
Tejun Heo254950c2006-07-26 15:59:25 +09002396
Tejun Heo0be0aa92006-07-26 15:59:26 +09002397 /* de-initialize port */
Tejun Heo4447d352007-04-17 23:44:08 +09002398 rc = ahci_deinit_port(ap, &emsg);
Tejun Heo0be0aa92006-07-26 15:59:26 +09002399 if (rc)
2400 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
Tejun Heo254950c2006-07-26 15:59:25 +09002401}
2402
Tejun Heo4447d352007-04-17 23:44:08 +09002403static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002404{
Linus Torvalds1da177e2005-04-16 15:20:36 -07002405 int rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002406
Linus Torvalds1da177e2005-04-16 15:20:36 -07002407 if (using_dac &&
2408 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
2409 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
2410 if (rc) {
2411 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2412 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -05002413 dev_printk(KERN_ERR, &pdev->dev,
2414 "64-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002415 return rc;
2416 }
2417 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002418 } else {
2419 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2420 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -05002421 dev_printk(KERN_ERR, &pdev->dev,
2422 "32-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002423 return rc;
2424 }
2425 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2426 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -05002427 dev_printk(KERN_ERR, &pdev->dev,
2428 "32-bit consistent DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002429 return rc;
2430 }
2431 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002432 return 0;
2433}
2434
Tejun Heo4447d352007-04-17 23:44:08 +09002435static void ahci_print_info(struct ata_host *host)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002436{
Tejun Heo4447d352007-04-17 23:44:08 +09002437 struct ahci_host_priv *hpriv = host->private_data;
2438 struct pci_dev *pdev = to_pci_dev(host->dev);
2439 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Linus Torvalds1da177e2005-04-16 15:20:36 -07002440 u32 vers, cap, impl, speed;
2441 const char *speed_s;
2442 u16 cc;
2443 const char *scc_s;
2444
2445 vers = readl(mmio + HOST_VERSION);
2446 cap = hpriv->cap;
2447 impl = hpriv->port_map;
2448
2449 speed = (cap >> 20) & 0xf;
2450 if (speed == 1)
2451 speed_s = "1.5";
2452 else if (speed == 2)
2453 speed_s = "3";
Shane Huang8522ee22008-12-30 11:00:37 +08002454 else if (speed == 3)
2455 speed_s = "6";
Linus Torvalds1da177e2005-04-16 15:20:36 -07002456 else
2457 speed_s = "?";
2458
2459 pci_read_config_word(pdev, 0x0a, &cc);
Conke Huc9f89472007-01-09 05:32:51 -05002460 if (cc == PCI_CLASS_STORAGE_IDE)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002461 scc_s = "IDE";
Conke Huc9f89472007-01-09 05:32:51 -05002462 else if (cc == PCI_CLASS_STORAGE_SATA)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002463 scc_s = "SATA";
Conke Huc9f89472007-01-09 05:32:51 -05002464 else if (cc == PCI_CLASS_STORAGE_RAID)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002465 scc_s = "RAID";
2466 else
2467 scc_s = "unknown";
2468
Jeff Garzika9524a72005-10-30 14:39:11 -05002469 dev_printk(KERN_INFO, &pdev->dev,
2470 "AHCI %02x%02x.%02x%02x "
Linus Torvalds1da177e2005-04-16 15:20:36 -07002471 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002472 ,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002473
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002474 (vers >> 24) & 0xff,
2475 (vers >> 16) & 0xff,
2476 (vers >> 8) & 0xff,
2477 vers & 0xff,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002478
2479 ((cap >> 8) & 0x1f) + 1,
2480 (cap & 0x1f) + 1,
2481 speed_s,
2482 impl,
2483 scc_s);
2484
Jeff Garzika9524a72005-10-30 14:39:11 -05002485 dev_printk(KERN_INFO, &pdev->dev,
2486 "flags: "
Tejun Heo203ef6c2007-07-16 14:29:40 +09002487 "%s%s%s%s%s%s%s"
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07002488 "%s%s%s%s%s%s%s"
2489 "%s\n"
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002490 ,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002491
2492 cap & (1 << 31) ? "64bit " : "",
2493 cap & (1 << 30) ? "ncq " : "",
Tejun Heo203ef6c2007-07-16 14:29:40 +09002494 cap & (1 << 29) ? "sntf " : "",
Linus Torvalds1da177e2005-04-16 15:20:36 -07002495 cap & (1 << 28) ? "ilck " : "",
2496 cap & (1 << 27) ? "stag " : "",
2497 cap & (1 << 26) ? "pm " : "",
2498 cap & (1 << 25) ? "led " : "",
2499
2500 cap & (1 << 24) ? "clo " : "",
2501 cap & (1 << 19) ? "nz " : "",
2502 cap & (1 << 18) ? "only " : "",
2503 cap & (1 << 17) ? "pmp " : "",
2504 cap & (1 << 15) ? "pio " : "",
2505 cap & (1 << 14) ? "slum " : "",
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07002506 cap & (1 << 13) ? "part " : "",
2507 cap & (1 << 6) ? "ems ": ""
Linus Torvalds1da177e2005-04-16 15:20:36 -07002508 );
2509}
2510
Tejun Heoedc93052007-10-25 14:59:16 +09002511/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2512 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2513 * support PMP and the 4726 either directly exports the device
2514 * attached to the first downstream port or acts as a hardware storage
2515 * controller and emulate a single ATA device (can be RAID 0/1 or some
2516 * other configuration).
2517 *
2518 * When there's no device attached to the first downstream port of the
2519 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2520 * configure the 4726. However, ATA emulation of the device is very
2521 * lame. It doesn't send signature D2H Reg FIS after the initial
2522 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2523 *
2524 * The following function works around the problem by always using
2525 * hardreset on the port and not depending on receiving signature FIS
2526 * afterward. If signature FIS isn't received soon, ATA class is
2527 * assumed without follow-up softreset.
2528 */
2529static void ahci_p5wdh_workaround(struct ata_host *host)
2530{
2531 static struct dmi_system_id sysids[] = {
2532 {
2533 .ident = "P5W DH Deluxe",
2534 .matches = {
2535 DMI_MATCH(DMI_SYS_VENDOR,
2536 "ASUSTEK COMPUTER INC"),
2537 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2538 },
2539 },
2540 { }
2541 };
2542 struct pci_dev *pdev = to_pci_dev(host->dev);
2543
2544 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2545 dmi_check_system(sysids)) {
2546 struct ata_port *ap = host->ports[1];
2547
2548 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2549 "Deluxe on-board SIMG4726 workaround\n");
2550
2551 ap->ops = &ahci_p5wdh_ops;
2552 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2553 }
2554}
2555
Rafael J. Wysocki1fd68432009-01-19 20:57:36 +01002556static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
2557{
2558 static const struct dmi_system_id broken_systems[] = {
2559 {
2560 .ident = "HP Compaq nx6310",
2561 .matches = {
2562 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2563 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
2564 },
2565 /* PCI slot number of the controller */
2566 .driver_data = (void *)0x1FUL,
2567 },
2568
2569 { } /* terminate list */
2570 };
2571 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
2572
2573 if (dmi) {
2574 unsigned long slot = (unsigned long)dmi->driver_data;
2575 /* apply the quirk only to on-board controllers */
2576 return slot == PCI_SLOT(pdev->devfn);
2577 }
2578
2579 return false;
2580}
2581
Tejun Heo24dc5f32007-01-20 16:00:28 +09002582static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002583{
2584 static int printed_version;
Tejun Heoe297d992008-06-10 00:13:04 +09002585 unsigned int board_id = ent->driver_data;
2586 struct ata_port_info pi = ahci_port_info[board_id];
Tejun Heo4447d352007-04-17 23:44:08 +09002587 const struct ata_port_info *ppi[] = { &pi, NULL };
Tejun Heo24dc5f32007-01-20 16:00:28 +09002588 struct device *dev = &pdev->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002589 struct ahci_host_priv *hpriv;
Tejun Heo4447d352007-04-17 23:44:08 +09002590 struct ata_host *host;
Tejun Heo837f5f82008-02-06 15:13:51 +09002591 int n_ports, i, rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002592
2593 VPRINTK("ENTER\n");
2594
Tejun Heo12fad3f2006-05-15 21:03:55 +09002595 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
2596
Linus Torvalds1da177e2005-04-16 15:20:36 -07002597 if (!printed_version++)
Jeff Garzika9524a72005-10-30 14:39:11 -05002598 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002599
Alan Cox5b66c822008-09-03 14:48:34 +01002600 /* The AHCI driver can only drive the SATA ports, the PATA driver
2601 can drive them all so if both drivers are selected make sure
2602 AHCI stays out of the way */
2603 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
2604 return -ENODEV;
2605
Tejun Heo4447d352007-04-17 23:44:08 +09002606 /* acquire resources */
Tejun Heo24dc5f32007-01-20 16:00:28 +09002607 rc = pcim_enable_device(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002608 if (rc)
2609 return rc;
2610
Tejun Heodea55132008-03-11 19:52:31 +09002611 /* AHCI controllers often implement SFF compatible interface.
2612 * Grab all PCI BARs just in case.
2613 */
2614 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
Tejun Heo0d5ff562007-02-01 15:06:36 +09002615 if (rc == -EBUSY)
Tejun Heo24dc5f32007-01-20 16:00:28 +09002616 pcim_pin_device(pdev);
Tejun Heo0d5ff562007-02-01 15:06:36 +09002617 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09002618 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002619
Tejun Heoc4f77922007-12-06 15:09:43 +09002620 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
2621 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
2622 u8 map;
2623
2624 /* ICH6s share the same PCI ID for both piix and ahci
2625 * modes. Enabling ahci mode while MAP indicates
2626 * combined mode is a bad idea. Yield to ata_piix.
2627 */
2628 pci_read_config_byte(pdev, ICH_MAP, &map);
2629 if (map & 0x3) {
2630 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
2631 "combined mode, can't enable AHCI mode\n");
2632 return -ENODEV;
2633 }
2634 }
2635
Tejun Heo24dc5f32007-01-20 16:00:28 +09002636 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2637 if (!hpriv)
2638 return -ENOMEM;
Tejun Heo417a1a62007-09-23 13:19:55 +09002639 hpriv->flags |= (unsigned long)pi.private_data;
2640
Tejun Heoe297d992008-06-10 00:13:04 +09002641 /* MCP65 revision A1 and A2 can't do MSI */
2642 if (board_id == board_ahci_mcp65 &&
2643 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
2644 hpriv->flags |= AHCI_HFLAG_NO_MSI;
2645
Shane Huange427fe02008-12-30 10:53:41 +08002646 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
2647 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
2648 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
2649
Tejun Heo417a1a62007-09-23 13:19:55 +09002650 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
2651 pci_intx(pdev, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002652
Tejun Heo4447d352007-04-17 23:44:08 +09002653 /* save initial config */
Tejun Heo417a1a62007-09-23 13:19:55 +09002654 ahci_save_initial_config(pdev, hpriv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002655
Tejun Heo4447d352007-04-17 23:44:08 +09002656 /* prepare host */
Tejun Heo274c1fd2007-07-16 14:29:40 +09002657 if (hpriv->cap & HOST_CAP_NCQ)
Tejun Heo4447d352007-04-17 23:44:08 +09002658 pi.flags |= ATA_FLAG_NCQ;
2659
Tejun Heo7d50b602007-09-23 13:19:54 +09002660 if (hpriv->cap & HOST_CAP_PMP)
2661 pi.flags |= ATA_FLAG_PMP;
2662
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07002663 if (ahci_em_messages && (hpriv->cap & HOST_CAP_EMS)) {
2664 u8 messages;
2665 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
2666 u32 em_loc = readl(mmio + HOST_EM_LOC);
2667 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2668
David Milburn87943ac2008-10-13 14:38:36 -05002669 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07002670
2671 /* we only support LED message type right now */
2672 if ((messages & 0x01) && (ahci_em_messages == 1)) {
2673 /* store em_loc */
2674 hpriv->em_loc = ((em_loc >> 16) * 4);
2675 pi.flags |= ATA_FLAG_EM;
2676 if (!(em_ctl & EM_CTL_ALHD))
2677 pi.flags |= ATA_FLAG_SW_ACTIVITY;
2678 }
2679 }
2680
Rafael J. Wysocki1fd68432009-01-19 20:57:36 +01002681 if (ahci_broken_system_poweroff(pdev)) {
2682 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
2683 dev_info(&pdev->dev,
2684 "quirky BIOS, skipping spindown on poweroff\n");
2685 }
2686
Tejun Heo837f5f82008-02-06 15:13:51 +09002687 /* CAP.NP sometimes indicate the index of the last enabled
2688 * port, at other times, that of the last possible port, so
2689 * determining the maximum port number requires looking at
2690 * both CAP.NP and port_map.
2691 */
2692 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
2693
2694 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
Tejun Heo4447d352007-04-17 23:44:08 +09002695 if (!host)
2696 return -ENOMEM;
2697 host->iomap = pcim_iomap_table(pdev);
2698 host->private_data = hpriv;
2699
Arjan van de Venf3d7f232009-01-26 02:05:44 -08002700 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
Arjan van de Ven886ad092009-01-09 15:54:07 -08002701 host->flags |= ATA_HOST_PARALLEL_SCAN;
Arjan van de Venf3d7f232009-01-26 02:05:44 -08002702 else
2703 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
Arjan van de Ven886ad092009-01-09 15:54:07 -08002704
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07002705 if (pi.flags & ATA_FLAG_EM)
2706 ahci_reset_em(host);
2707
Tejun Heo4447d352007-04-17 23:44:08 +09002708 for (i = 0; i < host->n_ports; i++) {
Jeff Garzikdab632e2007-05-28 08:33:01 -04002709 struct ata_port *ap = host->ports[i];
Tejun Heo4447d352007-04-17 23:44:08 +09002710
Tejun Heocbcdd872007-08-18 13:14:55 +09002711 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2712 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2713 0x100 + ap->port_no * 0x80, "port");
2714
Kristen Carlson Accardi31556592007-10-25 01:33:26 -04002715 /* set initial link pm policy */
2716 ap->pm_policy = NOT_AVAILABLE;
2717
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07002718 /* set enclosure management message type */
2719 if (ap->flags & ATA_FLAG_EM)
2720 ap->em_message_type = ahci_em_messages;
2721
2722
Jeff Garzikdab632e2007-05-28 08:33:01 -04002723 /* disabled/not-implemented port */
Tejun Heo350756f2008-04-07 22:47:21 +09002724 if (!(hpriv->port_map & (1 << i)))
Jeff Garzikdab632e2007-05-28 08:33:01 -04002725 ap->ops = &ata_dummy_port_ops;
Tejun Heo4447d352007-04-17 23:44:08 +09002726 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002727
Tejun Heoedc93052007-10-25 14:59:16 +09002728 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2729 ahci_p5wdh_workaround(host);
2730
Linus Torvalds1da177e2005-04-16 15:20:36 -07002731 /* initialize adapter */
Tejun Heo4447d352007-04-17 23:44:08 +09002732 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002733 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09002734 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002735
Tejun Heo4447d352007-04-17 23:44:08 +09002736 rc = ahci_reset_controller(host);
2737 if (rc)
2738 return rc;
Tejun Heo12fad3f2006-05-15 21:03:55 +09002739
Tejun Heo4447d352007-04-17 23:44:08 +09002740 ahci_init_controller(host);
2741 ahci_print_info(host);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002742
Tejun Heo4447d352007-04-17 23:44:08 +09002743 pci_set_master(pdev);
2744 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
2745 &ahci_sht);
Jeff Garzik907f4672005-05-12 15:03:42 -04002746}
Linus Torvalds1da177e2005-04-16 15:20:36 -07002747
2748static int __init ahci_init(void)
2749{
Pavel Roskinb7887192006-08-10 18:13:18 +09002750 return pci_register_driver(&ahci_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002751}
2752
Linus Torvalds1da177e2005-04-16 15:20:36 -07002753static void __exit ahci_exit(void)
2754{
2755 pci_unregister_driver(&ahci_pci_driver);
2756}
2757
2758
2759MODULE_AUTHOR("Jeff Garzik");
2760MODULE_DESCRIPTION("AHCI SATA low-level driver");
2761MODULE_LICENSE("GPL");
2762MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
Jeff Garzik68854332005-08-23 02:53:51 -04002763MODULE_VERSION(DRV_VERSION);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002764
2765module_init(ahci_init);
2766module_exit(ahci_exit);