blob: 401e03c920bdf034c3849ea01c03d6a5adc8fabc [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * drivers/pci/setup-bus.c
3 *
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
7 * David Miller (davem@redhat.com)
8 *
9 * Support routines for initializing a PCI subsystem.
10 */
11
12/*
13 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
14 * PCI-PCI bridges cleanup, sorted resource allocation.
15 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
16 * Converted to allocation in 3 passes, which gives
17 * tighter packing. Prefetchable range support.
18 */
19
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/pci.h>
24#include <linux/errno.h>
25#include <linux/ioport.h>
26#include <linux/cache.h>
27#include <linux/slab.h>
28
29
30#define DEBUG_CONFIG 1
31#if DEBUG_CONFIG
32#define DBG(x...) printk(x)
33#else
34#define DBG(x...)
35#endif
36
Sam Ravnborg96bde062007-03-26 21:53:30 -080037static void pbus_assign_resources_sorted(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -070038{
39 struct pci_dev *dev;
40 struct resource *res;
41 struct resource_list head, *list, *tmp;
42 int idx;
43
Linus Torvalds1da177e2005-04-16 15:20:36 -070044 head.next = NULL;
45 list_for_each_entry(dev, &bus->devices, bus_list) {
46 u16 class = dev->class >> 8;
47
Kenji Kaneshige9bded002006-10-04 02:15:34 -070048 /* Don't touch classless devices or host bridges or ioapics. */
Linus Torvalds1da177e2005-04-16 15:20:36 -070049 if (class == PCI_CLASS_NOT_DEFINED ||
Satoru Takeuchi23186272006-09-12 10:21:44 -070050 class == PCI_CLASS_BRIDGE_HOST)
Linus Torvalds1da177e2005-04-16 15:20:36 -070051 continue;
52
Kenji Kaneshige9bded002006-10-04 02:15:34 -070053 /* Don't touch ioapic devices already enabled by firmware */
Satoru Takeuchi23186272006-09-12 10:21:44 -070054 if (class == PCI_CLASS_SYSTEM_PIC) {
Kenji Kaneshige9bded002006-10-04 02:15:34 -070055 u16 command;
56 pci_read_config_word(dev, PCI_COMMAND, &command);
57 if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
Satoru Takeuchi23186272006-09-12 10:21:44 -070058 continue;
59 }
60
Linus Torvalds1da177e2005-04-16 15:20:36 -070061 pdev_sort_resources(dev, &head);
62 }
63
64 for (list = head.next; list;) {
65 res = list->res;
66 idx = res - &list->dev->resource[0];
Rajesh Shah542df5d2005-04-28 00:25:50 -070067 if (pci_assign_resource(list->dev, idx)) {
68 res->start = 0;
Ivan Kokshaysky960b8462005-07-07 03:07:56 +040069 res->end = 0;
Rajesh Shah542df5d2005-04-28 00:25:50 -070070 res->flags = 0;
71 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070072 tmp = list;
73 list = list->next;
74 kfree(tmp);
75 }
76}
77
Dominik Brodowskib3743fa2005-09-09 13:03:23 -070078void pci_setup_cardbus(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -070079{
80 struct pci_dev *bridge = bus->self;
81 struct pci_bus_region region;
82
83 printk("PCI: Bus %d, cardbus bridge: %s\n",
84 bus->number, pci_name(bridge));
85
86 pcibios_resource_to_bus(bridge, &region, bus->resource[0]);
87 if (bus->resource[0]->flags & IORESOURCE_IO) {
88 /*
89 * The IO resource is allocated a range twice as large as it
90 * would normally need. This allows us to set both IO regs.
91 */
92 printk(" IO window: %08lx-%08lx\n",
93 region.start, region.end);
94 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
95 region.start);
96 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
97 region.end);
98 }
99
100 pcibios_resource_to_bus(bridge, &region, bus->resource[1]);
101 if (bus->resource[1]->flags & IORESOURCE_IO) {
102 printk(" IO window: %08lx-%08lx\n",
103 region.start, region.end);
104 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
105 region.start);
106 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
107 region.end);
108 }
109
110 pcibios_resource_to_bus(bridge, &region, bus->resource[2]);
111 if (bus->resource[2]->flags & IORESOURCE_MEM) {
112 printk(" PREFETCH window: %08lx-%08lx\n",
113 region.start, region.end);
114 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
115 region.start);
116 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
117 region.end);
118 }
119
120 pcibios_resource_to_bus(bridge, &region, bus->resource[3]);
121 if (bus->resource[3]->flags & IORESOURCE_MEM) {
122 printk(" MEM window: %08lx-%08lx\n",
123 region.start, region.end);
124 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
125 region.start);
126 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
127 region.end);
128 }
129}
Dominik Brodowskib3743fa2005-09-09 13:03:23 -0700130EXPORT_SYMBOL(pci_setup_cardbus);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700131
132/* Initialize bridges with base/limit values we have collected.
133 PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
134 requires that if there is no I/O ports or memory behind the
135 bridge, corresponding range must be turned off by writing base
136 value greater than limit to the bridge's base/limit registers.
137
138 Note: care must be taken when updating I/O base/limit registers
139 of bridges which support 32-bit I/O. This update requires two
140 config space writes, so it's quite possible that an I/O window of
141 the bridge will have some undesirable address (e.g. 0) after the
142 first write. Ditto 64-bit prefetchable MMIO. */
143static void __devinit
144pci_setup_bridge(struct pci_bus *bus)
145{
146 struct pci_dev *bridge = bus->self;
147 struct pci_bus_region region;
148 u32 l, io_upper16;
149
150 DBG(KERN_INFO "PCI: Bridge: %s\n", pci_name(bridge));
151
152 /* Set up the top and bottom of the PCI I/O segment for this bus. */
153 pcibios_resource_to_bus(bridge, &region, bus->resource[0]);
154 if (bus->resource[0]->flags & IORESOURCE_IO) {
155 pci_read_config_dword(bridge, PCI_IO_BASE, &l);
156 l &= 0xffff0000;
157 l |= (region.start >> 8) & 0x00f0;
158 l |= region.end & 0xf000;
159 /* Set up upper 16 bits of I/O base/limit. */
160 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
161 DBG(KERN_INFO " IO window: %04lx-%04lx\n",
162 region.start, region.end);
163 }
164 else {
165 /* Clear upper 16 bits of I/O base/limit. */
166 io_upper16 = 0;
167 l = 0x00f0;
168 DBG(KERN_INFO " IO window: disabled.\n");
169 }
170 /* Temporarily disable the I/O range before updating PCI_IO_BASE. */
171 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
172 /* Update lower 16 bits of I/O base/limit. */
173 pci_write_config_dword(bridge, PCI_IO_BASE, l);
174 /* Update upper 16 bits of I/O base/limit. */
175 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
176
177 /* Set up the top and bottom of the PCI Memory segment
178 for this bus. */
179 pcibios_resource_to_bus(bridge, &region, bus->resource[1]);
180 if (bus->resource[1]->flags & IORESOURCE_MEM) {
181 l = (region.start >> 16) & 0xfff0;
182 l |= region.end & 0xfff00000;
183 DBG(KERN_INFO " MEM window: %08lx-%08lx\n",
184 region.start, region.end);
185 }
186 else {
187 l = 0x0000fff0;
188 DBG(KERN_INFO " MEM window: disabled.\n");
189 }
190 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
191
192 /* Clear out the upper 32 bits of PREF limit.
193 If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
194 disables PREF range, which is ok. */
195 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
196
197 /* Set up PREF base/limit. */
198 pcibios_resource_to_bus(bridge, &region, bus->resource[2]);
199 if (bus->resource[2]->flags & IORESOURCE_PREFETCH) {
200 l = (region.start >> 16) & 0xfff0;
201 l |= region.end & 0xfff00000;
202 DBG(KERN_INFO " PREFETCH window: %08lx-%08lx\n",
203 region.start, region.end);
204 }
205 else {
206 l = 0x0000fff0;
207 DBG(KERN_INFO " PREFETCH window: disabled.\n");
208 }
209 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
210
211 /* Clear out the upper 32 bits of PREF base. */
212 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, 0);
213
214 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
215}
216
217/* Check whether the bridge supports optional I/O and
218 prefetchable memory ranges. If not, the respective
219 base/limit registers must be read-only and read as 0. */
Sam Ravnborg96bde062007-03-26 21:53:30 -0800220static void pci_bridge_check_ranges(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700221{
222 u16 io;
223 u32 pmem;
224 struct pci_dev *bridge = bus->self;
225 struct resource *b_res;
226
227 b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
228 b_res[1].flags |= IORESOURCE_MEM;
229
230 pci_read_config_word(bridge, PCI_IO_BASE, &io);
231 if (!io) {
232 pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0);
233 pci_read_config_word(bridge, PCI_IO_BASE, &io);
234 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
235 }
236 if (io)
237 b_res[0].flags |= IORESOURCE_IO;
238 /* DECchip 21050 pass 2 errata: the bridge may miss an address
239 disconnect boundary by one PCI data phase.
240 Workaround: do not use prefetching on this device. */
241 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
242 return;
243 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
244 if (!pmem) {
245 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
246 0xfff0fff0);
247 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
248 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
249 }
250 if (pmem)
251 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
252}
253
254/* Helper function for sizing routines: find first available
255 bus resource of a given type. Note: we intentionally skip
256 the bus resources which have already been assigned (that is,
257 have non-NULL parent resource). */
Sam Ravnborg96bde062007-03-26 21:53:30 -0800258static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700259{
260 int i;
261 struct resource *r;
262 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
263 IORESOURCE_PREFETCH;
264
265 for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
266 r = bus->resource[i];
Ivan Kokshaysky299de032005-06-15 18:59:27 +0400267 if (r == &ioport_resource || r == &iomem_resource)
268 continue;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700269 if (r && (r->flags & type_mask) == type && !r->parent)
270 return r;
271 }
272 return NULL;
273}
274
275/* Sizing the IO windows of the PCI-PCI bridge is trivial,
276 since these windows have 4K granularity and the IO ranges
277 of non-bridge PCI devices are limited to 256 bytes.
278 We must be careful with the ISA aliasing though. */
Sam Ravnborg96bde062007-03-26 21:53:30 -0800279static void pbus_size_io(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700280{
281 struct pci_dev *dev;
282 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO);
283 unsigned long size = 0, size1 = 0;
284
285 if (!b_res)
286 return;
287
288 list_for_each_entry(dev, &bus->devices, bus_list) {
289 int i;
290
291 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
292 struct resource *r = &dev->resource[i];
293 unsigned long r_size;
294
295 if (r->parent || !(r->flags & IORESOURCE_IO))
296 continue;
297 r_size = r->end - r->start + 1;
298
299 if (r_size < 0x400)
300 /* Might be re-aligned for ISA */
301 size += r_size;
302 else
303 size1 += r_size;
304 }
305 }
306/* To be fixed in 2.5: we should have sort of HAVE_ISA
307 flag in the struct pci_bus. */
308#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
309 size = (size & 0xff) + ((size & ~0xffUL) << 2);
310#endif
Milind Arun Choudhary6f6f8c22007-07-09 11:55:51 -0700311 size = ALIGN(size + size1, 4096);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700312 if (!size) {
313 b_res->flags = 0;
314 return;
315 }
316 /* Alignment of the IO window is always 4K */
317 b_res->start = 4096;
318 b_res->end = b_res->start + size - 1;
319}
320
321/* Calculate the size of the bus and minimal alignment which
322 guarantees that all child resources fit in this size. */
Sam Ravnborg96bde062007-03-26 21:53:30 -0800323static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long type)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700324{
325 struct pci_dev *dev;
326 unsigned long min_align, align, size;
327 unsigned long aligns[12]; /* Alignments from 1Mb to 2Gb */
328 int order, max_order;
329 struct resource *b_res = find_free_bus_resource(bus, type);
330
331 if (!b_res)
332 return 0;
333
334 memset(aligns, 0, sizeof(aligns));
335 max_order = 0;
336 size = 0;
337
338 list_for_each_entry(dev, &bus->devices, bus_list) {
339 int i;
340
341 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
342 struct resource *r = &dev->resource[i];
343 unsigned long r_size;
344
345 if (r->parent || (r->flags & mask) != type)
346 continue;
347 r_size = r->end - r->start + 1;
348 /* For bridges size != alignment */
349 align = (i < PCI_BRIDGE_RESOURCES) ? r_size : r->start;
350 order = __ffs(align) - 20;
351 if (order > 11) {
352 printk(KERN_WARNING "PCI: region %s/%d "
Greg Kroah-Hartman1396a8c2006-06-12 15:14:29 -0700353 "too large: %llx-%llx\n",
354 pci_name(dev), i,
355 (unsigned long long)r->start,
356 (unsigned long long)r->end);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700357 r->flags = 0;
358 continue;
359 }
360 size += r_size;
361 if (order < 0)
362 order = 0;
363 /* Exclude ranges with size > align from
364 calculation of the alignment. */
365 if (r_size == align)
366 aligns[order] += align;
367 if (order > max_order)
368 max_order = order;
369 }
370 }
371
372 align = 0;
373 min_align = 0;
374 for (order = 0; order <= max_order; order++) {
375 unsigned long align1 = 1UL << (order + 20);
376
377 if (!align)
378 min_align = align1;
Milind Arun Choudhary6f6f8c22007-07-09 11:55:51 -0700379 else if (ALIGN(align + min_align, min_align) < align1)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700380 min_align = align1 >> 1;
381 align += aligns[order];
382 }
Milind Arun Choudhary6f6f8c22007-07-09 11:55:51 -0700383 size = ALIGN(size, min_align);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700384 if (!size) {
385 b_res->flags = 0;
386 return 1;
387 }
388 b_res->start = min_align;
389 b_res->end = size + min_align - 1;
390 return 1;
391}
392
393static void __devinit
394pci_bus_size_cardbus(struct pci_bus *bus)
395{
396 struct pci_dev *bridge = bus->self;
397 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
398 u16 ctrl;
399
400 /*
401 * Reserve some resources for CardBus. We reserve
402 * a fixed amount of bus space for CardBus bridges.
403 */
Atsushi Nemoto4516a612007-02-05 16:36:06 -0800404 b_res[0].start = pci_cardbus_io_size;
405 b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700406 b_res[0].flags |= IORESOURCE_IO;
407
Atsushi Nemoto4516a612007-02-05 16:36:06 -0800408 b_res[1].start = pci_cardbus_io_size;
409 b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700410 b_res[1].flags |= IORESOURCE_IO;
411
412 /*
413 * Check whether prefetchable memory is supported
414 * by this bridge.
415 */
416 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
417 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
418 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
419 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
420 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
421 }
422
423 /*
424 * If we have prefetchable memory support, allocate
425 * two regions. Otherwise, allocate one region of
426 * twice the size.
427 */
428 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
Atsushi Nemoto4516a612007-02-05 16:36:06 -0800429 b_res[2].start = pci_cardbus_mem_size;
430 b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700431 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
432
Atsushi Nemoto4516a612007-02-05 16:36:06 -0800433 b_res[3].start = pci_cardbus_mem_size;
434 b_res[3].end = b_res[3].start + pci_cardbus_mem_size - 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700435 b_res[3].flags |= IORESOURCE_MEM;
436 } else {
Atsushi Nemoto4516a612007-02-05 16:36:06 -0800437 b_res[3].start = pci_cardbus_mem_size * 2;
438 b_res[3].end = b_res[3].start + pci_cardbus_mem_size * 2 - 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700439 b_res[3].flags |= IORESOURCE_MEM;
440 }
441}
442
Sam Ravnborg96bde062007-03-26 21:53:30 -0800443void pci_bus_size_bridges(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700444{
445 struct pci_dev *dev;
446 unsigned long mask, prefmask;
447
448 list_for_each_entry(dev, &bus->devices, bus_list) {
449 struct pci_bus *b = dev->subordinate;
450 if (!b)
451 continue;
452
453 switch (dev->class >> 8) {
454 case PCI_CLASS_BRIDGE_CARDBUS:
455 pci_bus_size_cardbus(b);
456 break;
457
458 case PCI_CLASS_BRIDGE_PCI:
459 default:
460 pci_bus_size_bridges(b);
461 break;
462 }
463 }
464
465 /* The root bus? */
466 if (!bus->self)
467 return;
468
469 switch (bus->self->class >> 8) {
470 case PCI_CLASS_BRIDGE_CARDBUS:
471 /* don't size cardbuses yet. */
472 break;
473
474 case PCI_CLASS_BRIDGE_PCI:
Gary Hade8fa59132007-10-03 15:55:51 -0700475 /* don't size subtractive decoding (transparent)
476 * PCI-to-PCI bridges */
477 if (bus->self->transparent)
478 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700479 pci_bridge_check_ranges(bus);
Gary Hade8fa59132007-10-03 15:55:51 -0700480 /* fall through */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700481 default:
482 pbus_size_io(bus);
483 /* If the bridge supports prefetchable range, size it
484 separately. If it doesn't, or its prefetchable window
485 has already been allocated by arch code, try
486 non-prefetchable range for both types of PCI memory
487 resources. */
488 mask = IORESOURCE_MEM;
489 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
490 if (pbus_size_mem(bus, prefmask, prefmask))
491 mask = prefmask; /* Success, size non-prefetch only. */
492 pbus_size_mem(bus, mask, IORESOURCE_MEM);
493 break;
494 }
495}
496EXPORT_SYMBOL(pci_bus_size_bridges);
497
Sam Ravnborg96bde062007-03-26 21:53:30 -0800498void pci_bus_assign_resources(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700499{
500 struct pci_bus *b;
501 struct pci_dev *dev;
502
503 pbus_assign_resources_sorted(bus);
504
Linus Torvalds1da177e2005-04-16 15:20:36 -0700505 list_for_each_entry(dev, &bus->devices, bus_list) {
506 b = dev->subordinate;
507 if (!b)
508 continue;
509
510 pci_bus_assign_resources(b);
511
512 switch (dev->class >> 8) {
513 case PCI_CLASS_BRIDGE_PCI:
514 pci_setup_bridge(b);
515 break;
516
517 case PCI_CLASS_BRIDGE_CARDBUS:
518 pci_setup_cardbus(b);
519 break;
520
521 default:
522 printk(KERN_INFO "PCI: not setting up bridge %s "
523 "for bus %d\n", pci_name(dev), b->number);
524 break;
525 }
526 }
527}
528EXPORT_SYMBOL(pci_bus_assign_resources);
529
530void __init
531pci_assign_unassigned_resources(void)
532{
533 struct pci_bus *bus;
534
535 /* Depth first, calculate sizes and alignments of all
536 subordinate buses. */
537 list_for_each_entry(bus, &pci_root_buses, node) {
538 pci_bus_size_bridges(bus);
539 }
540 /* Depth last, allocate resources and update the hardware. */
541 list_for_each_entry(bus, &pci_root_buses, node) {
542 pci_bus_assign_resources(bus);
543 pci_enable_bridges(bus);
544 }
545}