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Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +09001/*
Tomoya MORINAGA8956dc12011-10-28 09:40:11 +09002 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +09003 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +090012 */
13
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/delay.h>
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +090017#include <linux/errno.h>
18#include <linux/i2c.h>
19#include <linux/fs.h>
20#include <linux/io.h>
21#include <linux/types.h>
22#include <linux/interrupt.h>
23#include <linux/jiffies.h>
24#include <linux/pci.h>
25#include <linux/mutex.h>
26#include <linux/ktime.h>
Wolfram Sang6dbc2f32011-02-23 11:11:35 +010027#include <linux/slab.h>
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +090028
29#define PCH_EVENT_SET 0 /* I2C Interrupt Event Set Status */
30#define PCH_EVENT_NONE 1 /* I2C Interrupt Event Clear Status */
31#define PCH_MAX_CLK 100000 /* Maximum Clock speed in MHz */
32#define PCH_BUFFER_MODE_ENABLE 0x0002 /* flag for Buffer mode enable */
33#define PCH_EEPROM_SW_RST_MODE_ENABLE 0x0008 /* EEPROM SW RST enable flag */
34
35#define PCH_I2CSADR 0x00 /* I2C slave address register */
36#define PCH_I2CCTL 0x04 /* I2C control register */
37#define PCH_I2CSR 0x08 /* I2C status register */
38#define PCH_I2CDR 0x0C /* I2C data register */
39#define PCH_I2CMON 0x10 /* I2C bus monitor register */
40#define PCH_I2CBC 0x14 /* I2C bus transfer rate setup counter */
41#define PCH_I2CMOD 0x18 /* I2C mode register */
42#define PCH_I2CBUFSLV 0x1C /* I2C buffer mode slave address register */
43#define PCH_I2CBUFSUB 0x20 /* I2C buffer mode subaddress register */
44#define PCH_I2CBUFFOR 0x24 /* I2C buffer mode format register */
45#define PCH_I2CBUFCTL 0x28 /* I2C buffer mode control register */
46#define PCH_I2CBUFMSK 0x2C /* I2C buffer mode interrupt mask register */
47#define PCH_I2CBUFSTA 0x30 /* I2C buffer mode status register */
48#define PCH_I2CBUFLEV 0x34 /* I2C buffer mode level register */
49#define PCH_I2CESRFOR 0x38 /* EEPROM software reset mode format register */
50#define PCH_I2CESRCTL 0x3C /* EEPROM software reset mode ctrl register */
51#define PCH_I2CESRMSK 0x40 /* EEPROM software reset mode */
52#define PCH_I2CESRSTA 0x44 /* EEPROM software reset mode status register */
53#define PCH_I2CTMR 0x48 /* I2C timer register */
54#define PCH_I2CSRST 0xFC /* I2C reset register */
55#define PCH_I2CNF 0xF8 /* I2C noise filter register */
56
57#define BUS_IDLE_TIMEOUT 20
58#define PCH_I2CCTL_I2CMEN 0x0080
59#define TEN_BIT_ADDR_DEFAULT 0xF000
60#define TEN_BIT_ADDR_MASK 0xF0
61#define PCH_START 0x0020
Tomoya MORINAGAc249ac22011-10-12 13:13:02 +090062#define PCH_RESTART 0x0004
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +090063#define PCH_ESR_START 0x0001
64#define PCH_BUFF_START 0x1
65#define PCH_REPSTART 0x0004
66#define PCH_ACK 0x0008
67#define PCH_GETACK 0x0001
68#define CLR_REG 0x0
69#define I2C_RD 0x1
70#define I2CMCF_BIT 0x0080
71#define I2CMIF_BIT 0x0002
72#define I2CMAL_BIT 0x0010
73#define I2CBMFI_BIT 0x0001
74#define I2CBMAL_BIT 0x0002
75#define I2CBMNA_BIT 0x0004
76#define I2CBMTO_BIT 0x0008
77#define I2CBMIS_BIT 0x0010
78#define I2CESRFI_BIT 0X0001
79#define I2CESRTO_BIT 0x0002
80#define I2CESRFIIE_BIT 0x1
81#define I2CESRTOIE_BIT 0x2
82#define I2CBMDZ_BIT 0x0040
83#define I2CBMAG_BIT 0x0020
84#define I2CMBB_BIT 0x0020
85#define BUFFER_MODE_MASK (I2CBMFI_BIT | I2CBMAL_BIT | I2CBMNA_BIT | \
86 I2CBMTO_BIT | I2CBMIS_BIT)
87#define I2C_ADDR_MSK 0xFF
88#define I2C_MSB_2B_MSK 0x300
89#define FAST_MODE_CLK 400
90#define FAST_MODE_EN 0x0001
91#define SUB_ADDR_LEN_MAX 4
92#define BUF_LEN_MAX 32
93#define PCH_BUFFER_MODE 0x1
94#define EEPROM_SW_RST_MODE 0x0002
95#define NORMAL_INTR_ENBL 0x0300
96#define EEPROM_RST_INTR_ENBL (I2CESRFIIE_BIT | I2CESRTOIE_BIT)
97#define EEPROM_RST_INTR_DISBL 0x0
98#define BUFFER_MODE_INTR_ENBL 0x001F
99#define BUFFER_MODE_INTR_DISBL 0x0
100#define NORMAL_MODE 0x0
101#define BUFFER_MODE 0x1
102#define EEPROM_SR_MODE 0x2
103#define I2C_TX_MODE 0x0010
104#define PCH_BUF_TX 0xFFF7
105#define PCH_BUF_RD 0x0008
106#define I2C_ERROR_MASK (I2CESRTO_EVENT | I2CBMIS_EVENT | I2CBMTO_EVENT | \
107 I2CBMNA_EVENT | I2CBMAL_EVENT | I2CMAL_EVENT)
108#define I2CMAL_EVENT 0x0001
109#define I2CMCF_EVENT 0x0002
110#define I2CBMFI_EVENT 0x0004
111#define I2CBMAL_EVENT 0x0008
112#define I2CBMNA_EVENT 0x0010
113#define I2CBMTO_EVENT 0x0020
114#define I2CBMIS_EVENT 0x0040
115#define I2CESRFI_EVENT 0x0080
116#define I2CESRTO_EVENT 0x0100
117#define PCI_DEVICE_ID_PCH_I2C 0x8817
118
119#define pch_dbg(adap, fmt, arg...) \
120 dev_dbg(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
121
122#define pch_err(adap, fmt, arg...) \
123 dev_err(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
124
125#define pch_pci_err(pdev, fmt, arg...) \
126 dev_err(&pdev->dev, "%s :" fmt, __func__, ##arg)
127
128#define pch_pci_dbg(pdev, fmt, arg...) \
129 dev_dbg(&pdev->dev, "%s :" fmt, __func__, ##arg)
130
Tomoya MORINAGA173442f2011-03-01 14:16:23 +0900131/*
132Set the number of I2C instance max
133Intel EG20T PCH : 1ch
Tomoya MORINAGA8956dc12011-10-28 09:40:11 +0900134LAPIS Semiconductor ML7213 IOH : 2ch
135LAPIS Semiconductor ML7831 IOH : 1ch
Tomoya MORINAGA173442f2011-03-01 14:16:23 +0900136*/
137#define PCH_I2C_MAX_DEV 2
138
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900139/**
140 * struct i2c_algo_pch_data - for I2C driver functionalities
141 * @pch_adapter: stores the reference to i2c_adapter structure
142 * @p_adapter_info: stores the reference to adapter_info structure
143 * @pch_base_address: specifies the remapped base address
144 * @pch_buff_mode_en: specifies if buffer mode is enabled
145 * @pch_event_flag: specifies occurrence of interrupt events
146 * @pch_i2c_xfer_in_progress: specifies whether the transfer is completed
147 */
148struct i2c_algo_pch_data {
149 struct i2c_adapter pch_adapter;
150 struct adapter_info *p_adapter_info;
151 void __iomem *pch_base_address;
152 int pch_buff_mode_en;
153 u32 pch_event_flag;
154 bool pch_i2c_xfer_in_progress;
155};
156
157/**
158 * struct adapter_info - This structure holds the adapter information for the
159 PCH i2c controller
160 * @pch_data: stores a list of i2c_algo_pch_data
161 * @pch_i2c_suspended: specifies whether the system is suspended or not
162 * perhaps with more lines and words.
Tomoya MORINAGA173442f2011-03-01 14:16:23 +0900163 * @ch_num: specifies the number of i2c instance
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900164 *
165 * pch_data has as many elements as maximum I2C channels
166 */
167struct adapter_info {
Tomoya MORINAGA173442f2011-03-01 14:16:23 +0900168 struct i2c_algo_pch_data pch_data[PCH_I2C_MAX_DEV];
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900169 bool pch_i2c_suspended;
Tomoya MORINAGA173442f2011-03-01 14:16:23 +0900170 int ch_num;
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900171};
172
173
174static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */
175static int pch_clk = 50000; /* specifies I2C clock speed in KHz */
176static wait_queue_head_t pch_event;
177static DEFINE_MUTEX(pch_mutex);
178
Tomoya MORINAGA8956dc12011-10-28 09:40:11 +0900179/* Definition for ML7213 by LAPIS Semiconductor */
Tomoya MORINAGA173442f2011-03-01 14:16:23 +0900180#define PCI_VENDOR_ID_ROHM 0x10DB
181#define PCI_DEVICE_ID_ML7213_I2C 0x802D
Tomoya MORINAGAefbe0f22011-05-09 16:32:31 +0900182#define PCI_DEVICE_ID_ML7223_I2C 0x8010
Tomoya MORINAGAc3f46612011-10-28 09:40:10 +0900183#define PCI_DEVICE_ID_ML7831_I2C 0x8817
Tomoya MORINAGA173442f2011-03-01 14:16:23 +0900184
Jingoo Han392debf2013-12-03 08:11:20 +0900185static const struct pci_device_id pch_pcidev_id[] = {
Tomoya MORINAGA173442f2011-03-01 14:16:23 +0900186 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH_I2C), 1, },
187 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_I2C), 2, },
Tomoya MORINAGAefbe0f22011-05-09 16:32:31 +0900188 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_I2C), 1, },
Tomoya MORINAGAc3f46612011-10-28 09:40:10 +0900189 { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_I2C), 1, },
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900190 {0,}
191};
192
193static irqreturn_t pch_i2c_handler(int irq, void *pData);
194
195static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask)
196{
197 u32 val;
198 val = ioread32(addr + offset);
199 val |= bitmask;
200 iowrite32(val, addr + offset);
201}
202
203static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask)
204{
205 u32 val;
206 val = ioread32(addr + offset);
207 val &= (~bitmask);
208 iowrite32(val, addr + offset);
209}
210
211/**
212 * pch_i2c_init() - hardware initialization of I2C module
213 * @adap: Pointer to struct i2c_algo_pch_data.
214 */
215static void pch_i2c_init(struct i2c_algo_pch_data *adap)
216{
217 void __iomem *p = adap->pch_base_address;
218 u32 pch_i2cbc;
219 u32 pch_i2ctmr;
220 u32 reg_value;
221
222 /* reset I2C controller */
223 iowrite32(0x01, p + PCH_I2CSRST);
224 msleep(20);
225 iowrite32(0x0, p + PCH_I2CSRST);
226
227 /* Initialize I2C registers */
228 iowrite32(0x21, p + PCH_I2CNF);
229
Tomoya MORINAGA173442f2011-03-01 14:16:23 +0900230 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_I2CCTL_I2CMEN);
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900231
232 if (pch_i2c_speed != 400)
233 pch_i2c_speed = 100;
234
235 reg_value = PCH_I2CCTL_I2CMEN;
236 if (pch_i2c_speed == FAST_MODE_CLK) {
237 reg_value |= FAST_MODE_EN;
238 pch_dbg(adap, "Fast mode enabled\n");
239 }
240
241 if (pch_clk > PCH_MAX_CLK)
242 pch_clk = 62500;
243
Toshiharu Okadaff35e8b2011-09-26 16:16:23 +0900244 pch_i2cbc = (pch_clk + (pch_i2c_speed * 4)) / (pch_i2c_speed * 8);
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900245 /* Set transfer speed in I2CBC */
246 iowrite32(pch_i2cbc, p + PCH_I2CBC);
247
248 pch_i2ctmr = (pch_clk) / 8;
249 iowrite32(pch_i2ctmr, p + PCH_I2CTMR);
250
251 reg_value |= NORMAL_INTR_ENBL; /* Enable interrupts in normal mode */
252 iowrite32(reg_value, p + PCH_I2CCTL);
253
254 pch_dbg(adap,
255 "I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
256 ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr);
257
258 init_waitqueue_head(&pch_event);
259}
260
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900261/**
262 * pch_i2c_wait_for_bus_idle() - check the status of bus.
263 * @adap: Pointer to struct i2c_algo_pch_data.
Alexander Stein0836c802012-02-20 09:14:16 +0100264 * @timeout: waiting time counter (ms).
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900265 */
266static s32 pch_i2c_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
Tomoya MORINAGA173442f2011-03-01 14:16:23 +0900267 s32 timeout)
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900268{
269 void __iomem *p = adap->pch_base_address;
Alexander Stein0836c802012-02-20 09:14:16 +0100270 int schedule = 0;
271 unsigned long end = jiffies + msecs_to_jiffies(timeout);
Tomoya MORINAGA93e4ad72011-10-12 13:13:00 +0900272
Alexander Stein0836c802012-02-20 09:14:16 +0100273 while (ioread32(p + PCH_I2CSR) & I2CMBB_BIT) {
274 if (time_after(jiffies, end)) {
275 pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR));
276 pch_err(adap, "%s: Timeout Error.return%d\n",
277 __func__, -ETIME);
278 pch_i2c_init(adap);
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900279
Alexander Stein0836c802012-02-20 09:14:16 +0100280 return -ETIME;
281 }
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900282
Alexander Stein0836c802012-02-20 09:14:16 +0100283 if (!schedule)
284 /* Retry after some usecs */
285 udelay(5);
286 else
287 /* Wait a bit more without consuming CPU */
288 usleep_range(20, 1000);
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900289
Alexander Stein0836c802012-02-20 09:14:16 +0100290 schedule = 1;
291 }
292
293 return 0;
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900294}
295
296/**
297 * pch_i2c_start() - Generate I2C start condition in normal mode.
298 * @adap: Pointer to struct i2c_algo_pch_data.
299 *
300 * Generate I2C start condition in normal mode by setting I2CCTL.I2CMSTA to 1.
301 */
302static void pch_i2c_start(struct i2c_algo_pch_data *adap)
303{
304 void __iomem *p = adap->pch_base_address;
305 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
306 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
307}
308
309/**
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900310 * pch_i2c_stop() - generate stop condition in normal mode.
311 * @adap: Pointer to struct i2c_algo_pch_data.
312 */
313static void pch_i2c_stop(struct i2c_algo_pch_data *adap)
314{
315 void __iomem *p = adap->pch_base_address;
316 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
317 /* clear the start bit */
318 pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
319}
320
Tomoya MORINAGA5cc05632012-04-19 15:38:04 +0900321static int pch_i2c_wait_for_check_xfer(struct i2c_algo_pch_data *adap)
322{
Tomoya MORINAGA199bca22012-04-19 15:38:05 +0900323 long ret;
Andreas Werner5e47eec2013-11-17 18:46:20 +0100324 void __iomem *p = adap->pch_base_address;
Tomoya MORINAGA5cc05632012-04-19 15:38:04 +0900325
Tomoya MORINAGA199bca22012-04-19 15:38:05 +0900326 ret = wait_event_timeout(pch_event,
327 (adap->pch_event_flag != 0), msecs_to_jiffies(1000));
328 if (!ret) {
329 pch_err(adap, "%s:wait-event timeout\n", __func__);
330 adap->pch_event_flag = 0;
331 pch_i2c_stop(adap);
332 pch_i2c_init(adap);
333 return -ETIMEDOUT;
334 }
335
336 if (adap->pch_event_flag & I2C_ERROR_MASK) {
Tomoya MORINAGA5cc05632012-04-19 15:38:04 +0900337 pch_err(adap, "Lost Arbitration\n");
Tomoya MORINAGA199bca22012-04-19 15:38:05 +0900338 adap->pch_event_flag = 0;
Tomoya MORINAGA5cc05632012-04-19 15:38:04 +0900339 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMAL_BIT);
340 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT);
341 pch_i2c_init(adap);
342 return -EAGAIN;
Tomoya MORINAGA199bca22012-04-19 15:38:05 +0900343 }
344
345 adap->pch_event_flag = 0;
346
Andreas Werner5e47eec2013-11-17 18:46:20 +0100347 if (ioread32(p + PCH_I2CSR) & PCH_GETACK) {
348 pch_dbg(adap, "Receive NACK for slave address setting\n");
349 return -ENXIO;
Tomoya MORINAGA5cc05632012-04-19 15:38:04 +0900350 }
351
352 return 0;
353}
354
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900355/**
356 * pch_i2c_repstart() - generate repeated start condition in normal mode
357 * @adap: Pointer to struct i2c_algo_pch_data.
358 */
359static void pch_i2c_repstart(struct i2c_algo_pch_data *adap)
360{
361 void __iomem *p = adap->pch_base_address;
362 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
363 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_REPSTART);
364}
365
366/**
367 * pch_i2c_writebytes() - write data to I2C bus in normal mode
368 * @i2c_adap: Pointer to the struct i2c_adapter.
369 * @last: specifies whether last message or not.
370 * In the case of compound mode it will be 1 for last message,
371 * otherwise 0.
372 * @first: specifies whether first message or not.
373 * 1 for first message otherwise 0.
374 */
375static s32 pch_i2c_writebytes(struct i2c_adapter *i2c_adap,
376 struct i2c_msg *msgs, u32 last, u32 first)
377{
378 struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
379 u8 *buf;
380 u32 length;
381 u32 addr;
382 u32 addr_2_msb;
383 u32 addr_8_lsb;
384 s32 wrcount;
Tomoya MORINAGA12bd3142011-10-12 13:13:03 +0900385 s32 rtn;
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900386 void __iomem *p = adap->pch_base_address;
387
388 length = msgs->len;
389 buf = msgs->buf;
390 addr = msgs->addr;
391
392 /* enable master tx */
393 pch_setbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
394
395 pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n", ioread32(p + PCH_I2CCTL),
396 length);
397
398 if (first) {
399 if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
400 return -ETIME;
401 }
402
403 if (msgs->flags & I2C_M_TEN) {
Tomoya MORINAGAc249ac22011-10-12 13:13:02 +0900404 addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7) & 0x06;
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900405 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
406 if (first)
407 pch_i2c_start(adap);
Tomoya MORINAGA12bd3142011-10-12 13:13:03 +0900408
Tomoya MORINAGA5cc05632012-04-19 15:38:04 +0900409 rtn = pch_i2c_wait_for_check_xfer(adap);
410 if (rtn)
411 return rtn;
412
413 addr_8_lsb = (addr & I2C_ADDR_MSK);
414 iowrite32(addr_8_lsb, p + PCH_I2CDR);
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900415 } else {
416 /* set 7 bit slave address and R/W bit as 0 */
417 iowrite32(addr << 1, p + PCH_I2CDR);
418 if (first)
419 pch_i2c_start(adap);
420 }
421
Tomoya MORINAGA5cc05632012-04-19 15:38:04 +0900422 rtn = pch_i2c_wait_for_check_xfer(adap);
423 if (rtn)
424 return rtn;
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900425
Tomoya MORINAGA12bd3142011-10-12 13:13:03 +0900426 for (wrcount = 0; wrcount < length; ++wrcount) {
427 /* write buffer value to I2C data register */
428 iowrite32(buf[wrcount], p + PCH_I2CDR);
429 pch_dbg(adap, "writing %x to Data register\n", buf[wrcount]);
430
Tomoya MORINAGA5cc05632012-04-19 15:38:04 +0900431 rtn = pch_i2c_wait_for_check_xfer(adap);
432 if (rtn)
433 return rtn;
434
435 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMCF_BIT);
436 pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT);
Tomoya MORINAGA12bd3142011-10-12 13:13:03 +0900437 }
438
439 /* check if this is the last message */
440 if (last)
441 pch_i2c_stop(adap);
442 else
443 pch_i2c_repstart(adap);
444
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900445 pch_dbg(adap, "return=%d\n", wrcount);
446
447 return wrcount;
448}
449
450/**
451 * pch_i2c_sendack() - send ACK
452 * @adap: Pointer to struct i2c_algo_pch_data.
453 */
454static void pch_i2c_sendack(struct i2c_algo_pch_data *adap)
455{
456 void __iomem *p = adap->pch_base_address;
457 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
458 pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
459}
460
461/**
462 * pch_i2c_sendnack() - send NACK
463 * @adap: Pointer to struct i2c_algo_pch_data.
464 */
465static void pch_i2c_sendnack(struct i2c_algo_pch_data *adap)
466{
467 void __iomem *p = adap->pch_base_address;
468 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
469 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
470}
471
472/**
Tomoya MORINAGAc249ac22011-10-12 13:13:02 +0900473 * pch_i2c_restart() - Generate I2C restart condition in normal mode.
474 * @adap: Pointer to struct i2c_algo_pch_data.
475 *
476 * Generate I2C restart condition in normal mode by setting I2CCTL.I2CRSTA.
477 */
478static void pch_i2c_restart(struct i2c_algo_pch_data *adap)
479{
480 void __iomem *p = adap->pch_base_address;
481 pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
482 pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_RESTART);
483}
484
485/**
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900486 * pch_i2c_readbytes() - read data from I2C bus in normal mode.
487 * @i2c_adap: Pointer to the struct i2c_adapter.
488 * @msgs: Pointer to i2c_msg structure.
489 * @last: specifies whether last message or not.
490 * @first: specifies whether first message or not.
491 */
Tomoya MORINAGA173442f2011-03-01 14:16:23 +0900492static s32 pch_i2c_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
493 u32 last, u32 first)
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900494{
495 struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
496
497 u8 *buf;
498 u32 count;
499 u32 length;
500 u32 addr;
501 u32 addr_2_msb;
Tomoya MORINAGAc249ac22011-10-12 13:13:02 +0900502 u32 addr_8_lsb;
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900503 void __iomem *p = adap->pch_base_address;
Tomoya MORINAGA12bd3142011-10-12 13:13:03 +0900504 s32 rtn;
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900505
506 length = msgs->len;
507 buf = msgs->buf;
508 addr = msgs->addr;
509
510 /* enable master reception */
511 pch_clrbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
512
513 if (first) {
514 if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
515 return -ETIME;
516 }
517
518 if (msgs->flags & I2C_M_TEN) {
Tomoya MORINAGAc249ac22011-10-12 13:13:02 +0900519 addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900520 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
Tomoya MORINAGAc249ac22011-10-12 13:13:02 +0900521 if (first)
522 pch_i2c_start(adap);
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900523
Tomoya MORINAGA5cc05632012-04-19 15:38:04 +0900524 rtn = pch_i2c_wait_for_check_xfer(adap);
525 if (rtn)
526 return rtn;
527
528 addr_8_lsb = (addr & I2C_ADDR_MSK);
529 iowrite32(addr_8_lsb, p + PCH_I2CDR);
530
Tomoya MORINAGAc249ac22011-10-12 13:13:02 +0900531 pch_i2c_restart(adap);
Tomoya MORINAGA5cc05632012-04-19 15:38:04 +0900532
533 rtn = pch_i2c_wait_for_check_xfer(adap);
534 if (rtn)
535 return rtn;
536
537 addr_2_msb |= I2C_RD;
538 iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900539 } else {
540 /* 7 address bits + R/W bit */
541 addr = (((addr) << 1) | (I2C_RD));
542 iowrite32(addr, p + PCH_I2CDR);
543 }
544
545 /* check if it is the first message */
546 if (first)
547 pch_i2c_start(adap);
548
Tomoya MORINAGA5cc05632012-04-19 15:38:04 +0900549 rtn = pch_i2c_wait_for_check_xfer(adap);
550 if (rtn)
551 return rtn;
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900552
Tomoya MORINAGA12bd3142011-10-12 13:13:03 +0900553 if (length == 0) {
554 pch_i2c_stop(adap);
555 ioread32(p + PCH_I2CDR); /* Dummy read needs */
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900556
Tomoya MORINAGA12bd3142011-10-12 13:13:03 +0900557 count = length;
558 } else {
559 int read_index;
560 int loop;
561 pch_i2c_sendack(adap);
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900562
Tomoya MORINAGA12bd3142011-10-12 13:13:03 +0900563 /* Dummy read */
564 for (loop = 1, read_index = 0; loop < length; loop++) {
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900565 buf[read_index] = ioread32(p + PCH_I2CDR);
566
Tomoya MORINAGA12bd3142011-10-12 13:13:03 +0900567 if (loop != 1)
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900568 read_index++;
569
Tomoya MORINAGA5cc05632012-04-19 15:38:04 +0900570 rtn = pch_i2c_wait_for_check_xfer(adap);
571 if (rtn)
572 return rtn;
Tomoya MORINAGA12bd3142011-10-12 13:13:03 +0900573 } /* end for */
574
575 pch_i2c_sendnack(adap);
576
577 buf[read_index] = ioread32(p + PCH_I2CDR); /* Read final - 1 */
578
579 if (length != 1)
580 read_index++;
581
Tomoya MORINAGA5cc05632012-04-19 15:38:04 +0900582 rtn = pch_i2c_wait_for_check_xfer(adap);
583 if (rtn)
584 return rtn;
Tomoya MORINAGA12bd3142011-10-12 13:13:03 +0900585
586 if (last)
587 pch_i2c_stop(adap);
588 else
589 pch_i2c_repstart(adap);
590
591 buf[read_index++] = ioread32(p + PCH_I2CDR); /* Read Final */
592 count = read_index;
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900593 }
594
595 return count;
596}
597
598/**
Tomoya MORINAGA173442f2011-03-01 14:16:23 +0900599 * pch_i2c_cb() - Interrupt handler Call back function
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900600 * @adap: Pointer to struct i2c_algo_pch_data.
601 */
Tomoya MORINAGA173442f2011-03-01 14:16:23 +0900602static void pch_i2c_cb(struct i2c_algo_pch_data *adap)
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900603{
604 u32 sts;
605 void __iomem *p = adap->pch_base_address;
606
607 sts = ioread32(p + PCH_I2CSR);
608 sts &= (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT);
609 if (sts & I2CMAL_BIT)
610 adap->pch_event_flag |= I2CMAL_EVENT;
611
612 if (sts & I2CMCF_BIT)
613 adap->pch_event_flag |= I2CMCF_EVENT;
614
615 /* clear the applicable bits */
616 pch_clrbit(adap->pch_base_address, PCH_I2CSR, sts);
617
618 pch_dbg(adap, "PCH_I2CSR = %x\n", ioread32(p + PCH_I2CSR));
619
620 wake_up(&pch_event);
621}
622
623/**
624 * pch_i2c_handler() - interrupt handler for the PCH I2C controller
625 * @irq: irq number.
626 * @pData: cookie passed back to the handler function.
627 */
628static irqreturn_t pch_i2c_handler(int irq, void *pData)
629{
Tomoya MORINAGA173442f2011-03-01 14:16:23 +0900630 u32 reg_val;
631 int flag;
632 int i;
633 struct adapter_info *adap_info = pData;
634 void __iomem *p;
635 u32 mode;
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900636
Tomoya MORINAGA173442f2011-03-01 14:16:23 +0900637 for (i = 0, flag = 0; i < adap_info->ch_num; i++) {
638 p = adap_info->pch_data[i].pch_base_address;
639 mode = ioread32(p + PCH_I2CMOD);
640 mode &= BUFFER_MODE | EEPROM_SR_MODE;
641 if (mode != NORMAL_MODE) {
642 pch_err(adap_info->pch_data,
643 "I2C-%d mode(%d) is not supported\n", mode, i);
644 continue;
645 }
646 reg_val = ioread32(p + PCH_I2CSR);
647 if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT)) {
648 pch_i2c_cb(&adap_info->pch_data[i]);
649 flag = 1;
650 }
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900651 }
652
Tomoya MORINAGA173442f2011-03-01 14:16:23 +0900653 return flag ? IRQ_HANDLED : IRQ_NONE;
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900654}
655
656/**
657 * pch_i2c_xfer() - Reading adnd writing data through I2C bus
658 * @i2c_adap: Pointer to the struct i2c_adapter.
659 * @msgs: Pointer to i2c_msg structure.
660 * @num: number of messages.
661 */
662static s32 pch_i2c_xfer(struct i2c_adapter *i2c_adap,
Tomoya MORINAGA173442f2011-03-01 14:16:23 +0900663 struct i2c_msg *msgs, s32 num)
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900664{
665 struct i2c_msg *pmsg;
666 u32 i = 0;
667 u32 status;
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900668 s32 ret;
669
670 struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
671
672 ret = mutex_lock_interruptible(&pch_mutex);
673 if (ret)
Wolfram Sang772ae992012-04-19 17:01:59 +0200674 return ret;
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900675
676 if (adap->p_adapter_info->pch_i2c_suspended) {
677 mutex_unlock(&pch_mutex);
678 return -EBUSY;
679 }
680
681 pch_dbg(adap, "adap->p_adapter_info->pch_i2c_suspended is %d\n",
682 adap->p_adapter_info->pch_i2c_suspended);
683 /* transfer not completed */
684 adap->pch_i2c_xfer_in_progress = true;
685
Tomoya MORINAGA07e729c2011-06-23 16:17:10 +0900686 for (i = 0; i < num && ret >= 0; i++) {
Tomoya MORINAGA7a9c42c2011-06-09 11:29:29 +0900687 pmsg = &msgs[i];
688 pmsg->flags |= adap->pch_buff_mode_en;
689 status = pmsg->flags;
690 pch_dbg(adap,
691 "After invoking I2C_MODE_SEL :flag= 0x%x\n", status);
Tomoya MORINAGA7a9c42c2011-06-09 11:29:29 +0900692
693 if ((status & (I2C_M_RD)) != false) {
694 ret = pch_i2c_readbytes(i2c_adap, pmsg, (i + 1 == num),
695 (i == 0));
696 } else {
697 ret = pch_i2c_writebytes(i2c_adap, pmsg, (i + 1 == num),
698 (i == 0));
699 }
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900700 }
701
702 adap->pch_i2c_xfer_in_progress = false; /* transfer completed */
703
704 mutex_unlock(&pch_mutex);
705
Tomoya MORINAGA07e729c2011-06-23 16:17:10 +0900706 return (ret < 0) ? ret : num;
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900707}
708
709/**
710 * pch_i2c_func() - return the functionality of the I2C driver
711 * @adap: Pointer to struct i2c_algo_pch_data.
712 */
713static u32 pch_i2c_func(struct i2c_adapter *adap)
714{
715 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
716}
717
718static struct i2c_algorithm pch_algorithm = {
719 .master_xfer = pch_i2c_xfer,
720 .functionality = pch_i2c_func
721};
722
723/**
724 * pch_i2c_disbl_int() - Disable PCH I2C interrupts
725 * @adap: Pointer to struct i2c_algo_pch_data.
726 */
727static void pch_i2c_disbl_int(struct i2c_algo_pch_data *adap)
728{
729 void __iomem *p = adap->pch_base_address;
730
731 pch_clrbit(adap->pch_base_address, PCH_I2CCTL, NORMAL_INTR_ENBL);
732
733 iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK);
734
735 iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK);
736}
737
Bill Pemberton0b255e92012-11-27 15:59:38 -0500738static int pch_i2c_probe(struct pci_dev *pdev,
Tomoya MORINAGA173442f2011-03-01 14:16:23 +0900739 const struct pci_device_id *id)
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900740{
741 void __iomem *base_addr;
Tomoya MORINAGA173442f2011-03-01 14:16:23 +0900742 int ret;
743 int i, j;
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900744 struct adapter_info *adap_info;
Tomoya MORINAGA173442f2011-03-01 14:16:23 +0900745 struct i2c_adapter *pch_adap;
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900746
747 pch_pci_dbg(pdev, "Entered.\n");
748
749 adap_info = kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
Jingoo Han46797a22014-05-13 10:51:58 +0900750 if (adap_info == NULL)
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900751 return -ENOMEM;
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900752
753 ret = pci_enable_device(pdev);
754 if (ret) {
755 pch_pci_err(pdev, "pci_enable_device FAILED\n");
756 goto err_pci_enable;
757 }
758
759 ret = pci_request_regions(pdev, KBUILD_MODNAME);
760 if (ret) {
761 pch_pci_err(pdev, "pci_request_regions FAILED\n");
762 goto err_pci_req;
763 }
764
765 base_addr = pci_iomap(pdev, 1, 0);
766
767 if (base_addr == NULL) {
768 pch_pci_err(pdev, "pci_iomap FAILED\n");
769 ret = -ENOMEM;
770 goto err_pci_iomap;
771 }
772
Tomoya MORINAGA173442f2011-03-01 14:16:23 +0900773 /* Set the number of I2C channel instance */
774 adap_info->ch_num = id->driver_data;
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900775
Feng Tang0d5fb5e2011-11-29 15:19:10 +0800776 ret = request_irq(pdev->irq, pch_i2c_handler, IRQF_SHARED,
777 KBUILD_MODNAME, adap_info);
778 if (ret) {
779 pch_pci_err(pdev, "request_irq FAILED\n");
780 goto err_request_irq;
781 }
782
Tomoya MORINAGA173442f2011-03-01 14:16:23 +0900783 for (i = 0; i < adap_info->ch_num; i++) {
784 pch_adap = &adap_info->pch_data[i].pch_adapter;
785 adap_info->pch_i2c_suspended = false;
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900786
Tomoya MORINAGA173442f2011-03-01 14:16:23 +0900787 adap_info->pch_data[i].p_adapter_info = adap_info;
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900788
Tomoya MORINAGA173442f2011-03-01 14:16:23 +0900789 pch_adap->owner = THIS_MODULE;
790 pch_adap->class = I2C_CLASS_HWMON;
Wolfram Sang6188a372012-04-19 17:31:01 +0200791 strlcpy(pch_adap->name, KBUILD_MODNAME, sizeof(pch_adap->name));
Tomoya MORINAGA173442f2011-03-01 14:16:23 +0900792 pch_adap->algo = &pch_algorithm;
793 pch_adap->algo_data = &adap_info->pch_data[i];
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900794
Tomoya MORINAGA173442f2011-03-01 14:16:23 +0900795 /* base_addr + offset; */
796 adap_info->pch_data[i].pch_base_address = base_addr + 0x100 * i;
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900797
Tomoya MORINAGA173442f2011-03-01 14:16:23 +0900798 pch_adap->dev.parent = &pdev->dev;
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900799
Feng Tang0d5fb5e2011-11-29 15:19:10 +0800800 pch_i2c_init(&adap_info->pch_data[i]);
Feng Tang07e8a512012-01-12 15:38:02 +0800801
802 pch_adap->nr = i;
803 ret = i2c_add_numbered_adapter(pch_adap);
Tomoya MORINAGA173442f2011-03-01 14:16:23 +0900804 if (ret) {
805 pch_pci_err(pdev, "i2c_add_adapter[ch:%d] FAILED\n", i);
Feng Tang0d5fb5e2011-11-29 15:19:10 +0800806 goto err_add_adapter;
Tomoya MORINAGA173442f2011-03-01 14:16:23 +0900807 }
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900808 }
809
810 pci_set_drvdata(pdev, adap_info);
811 pch_pci_dbg(pdev, "returns %d.\n", ret);
812 return 0;
813
Feng Tang0d5fb5e2011-11-29 15:19:10 +0800814err_add_adapter:
Tomoya MORINAGA173442f2011-03-01 14:16:23 +0900815 for (j = 0; j < i; j++)
816 i2c_del_adapter(&adap_info->pch_data[j].pch_adapter);
Feng Tang0d5fb5e2011-11-29 15:19:10 +0800817 free_irq(pdev->irq, adap_info);
818err_request_irq:
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900819 pci_iounmap(pdev, base_addr);
820err_pci_iomap:
821 pci_release_regions(pdev);
822err_pci_req:
823 pci_disable_device(pdev);
824err_pci_enable:
825 kfree(adap_info);
826 return ret;
827}
828
Bill Pemberton0b255e92012-11-27 15:59:38 -0500829static void pch_i2c_remove(struct pci_dev *pdev)
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900830{
Tomoya MORINAGA173442f2011-03-01 14:16:23 +0900831 int i;
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900832 struct adapter_info *adap_info = pci_get_drvdata(pdev);
833
Tomoya MORINAGA173442f2011-03-01 14:16:23 +0900834 free_irq(pdev->irq, adap_info);
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900835
Tomoya MORINAGA173442f2011-03-01 14:16:23 +0900836 for (i = 0; i < adap_info->ch_num; i++) {
837 pch_i2c_disbl_int(&adap_info->pch_data[i]);
838 i2c_del_adapter(&adap_info->pch_data[i].pch_adapter);
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900839 }
840
Tomoya MORINAGA173442f2011-03-01 14:16:23 +0900841 if (adap_info->pch_data[0].pch_base_address)
842 pci_iounmap(pdev, adap_info->pch_data[0].pch_base_address);
843
844 for (i = 0; i < adap_info->ch_num; i++)
Wolfram Sang75fb1f22012-04-19 16:53:49 +0200845 adap_info->pch_data[i].pch_base_address = NULL;
Tomoya MORINAGA173442f2011-03-01 14:16:23 +0900846
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900847 pci_release_regions(pdev);
848
849 pci_disable_device(pdev);
850 kfree(adap_info);
851}
852
853#ifdef CONFIG_PM
854static int pch_i2c_suspend(struct pci_dev *pdev, pm_message_t state)
855{
856 int ret;
Tomoya MORINAGA173442f2011-03-01 14:16:23 +0900857 int i;
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900858 struct adapter_info *adap_info = pci_get_drvdata(pdev);
Tomoya MORINAGA173442f2011-03-01 14:16:23 +0900859 void __iomem *p = adap_info->pch_data[0].pch_base_address;
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900860
861 adap_info->pch_i2c_suspended = true;
862
Tomoya MORINAGA173442f2011-03-01 14:16:23 +0900863 for (i = 0; i < adap_info->ch_num; i++) {
864 while ((adap_info->pch_data[i].pch_i2c_xfer_in_progress)) {
865 /* Wait until all channel transfers are completed */
866 msleep(20);
867 }
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900868 }
Tomoya MORINAGA173442f2011-03-01 14:16:23 +0900869
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900870 /* Disable the i2c interrupts */
Tomoya MORINAGA173442f2011-03-01 14:16:23 +0900871 for (i = 0; i < adap_info->ch_num; i++)
872 pch_i2c_disbl_int(&adap_info->pch_data[i]);
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900873
874 pch_pci_dbg(pdev, "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
875 "invoked function pch_i2c_disbl_int successfully\n",
876 ioread32(p + PCH_I2CSR), ioread32(p + PCH_I2CBUFSTA),
877 ioread32(p + PCH_I2CESRSTA));
878
879 ret = pci_save_state(pdev);
880
881 if (ret) {
882 pch_pci_err(pdev, "pci_save_state\n");
883 return ret;
884 }
885
886 pci_enable_wake(pdev, PCI_D3hot, 0);
887 pci_disable_device(pdev);
888 pci_set_power_state(pdev, pci_choose_state(pdev, state));
889
890 return 0;
891}
892
893static int pch_i2c_resume(struct pci_dev *pdev)
894{
Tomoya MORINAGA173442f2011-03-01 14:16:23 +0900895 int i;
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900896 struct adapter_info *adap_info = pci_get_drvdata(pdev);
897
898 pci_set_power_state(pdev, PCI_D0);
899 pci_restore_state(pdev);
900
901 if (pci_enable_device(pdev) < 0) {
902 pch_pci_err(pdev, "pch_i2c_resume:pci_enable_device FAILED\n");
903 return -EIO;
904 }
905
906 pci_enable_wake(pdev, PCI_D3hot, 0);
907
Tomoya MORINAGA173442f2011-03-01 14:16:23 +0900908 for (i = 0; i < adap_info->ch_num; i++)
909 pch_i2c_init(&adap_info->pch_data[i]);
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900910
911 adap_info->pch_i2c_suspended = false;
912
913 return 0;
914}
915#else
916#define pch_i2c_suspend NULL
917#define pch_i2c_resume NULL
918#endif
919
920static struct pci_driver pch_pcidriver = {
921 .name = KBUILD_MODNAME,
922 .id_table = pch_pcidev_id,
923 .probe = pch_i2c_probe,
Bill Pemberton0b255e92012-11-27 15:59:38 -0500924 .remove = pch_i2c_remove,
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900925 .suspend = pch_i2c_suspend,
926 .resume = pch_i2c_resume
927};
928
Axel Lin56f21782012-07-24 14:13:56 +0200929module_pci_driver(pch_pcidriver);
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900930
Tomoya MORINAGA8956dc12011-10-28 09:40:11 +0900931MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semico ML7213/ML7223/ML7831 IOH I2C");
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900932MODULE_LICENSE("GPL");
Tomoya MORINAGA09640712012-03-26 14:55:23 +0900933MODULE_AUTHOR("Tomoya MORINAGA. <tomoya.rohm@gmail.com>");
Tomoya MORINAGAe9bc8fa2010-11-09 13:25:22 +0900934module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR));
935module_param(pch_clk, int, (S_IRUSR | S_IWUSR));