Robert Jarzmik | dc94436 | 2009-01-06 14:42:14 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Real Time Clock interface for XScale PXA27x and PXA3xx |
| 3 | * |
| 4 | * Copyright (C) 2008 Robert Jarzmik |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 19 | * |
| 20 | */ |
| 21 | |
Alessandro Zummo | 0417ce2 | 2009-01-06 14:42:15 -0800 | [diff] [blame] | 22 | #include <linux/init.h> |
Robert Jarzmik | dc94436 | 2009-01-06 14:42:14 -0800 | [diff] [blame] | 23 | #include <linux/platform_device.h> |
| 24 | #include <linux/module.h> |
| 25 | #include <linux/rtc.h> |
| 26 | #include <linux/seq_file.h> |
| 27 | #include <linux/interrupt.h> |
Alessandro Zummo | 0417ce2 | 2009-01-06 14:42:15 -0800 | [diff] [blame] | 28 | #include <linux/io.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 29 | #include <linux/slab.h> |
Robert Jarzmik | dc94436 | 2009-01-06 14:42:14 -0800 | [diff] [blame] | 30 | |
Antonio Ospite | 4216d0b | 2009-01-15 13:50:54 -0800 | [diff] [blame] | 31 | #include <mach/hardware.h> |
| 32 | |
Robert Jarzmik | dc94436 | 2009-01-06 14:42:14 -0800 | [diff] [blame] | 33 | #define TIMER_FREQ CLOCK_TICK_RATE |
| 34 | #define RTC_DEF_DIVIDER (32768 - 1) |
| 35 | #define RTC_DEF_TRIM 0 |
| 36 | #define MAXFREQ_PERIODIC 1000 |
| 37 | |
| 38 | /* |
| 39 | * PXA Registers and bits definitions |
| 40 | */ |
| 41 | #define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */ |
| 42 | #define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */ |
| 43 | #define RTSR_PIAL (1 << 13) /* Periodic interrupt detected */ |
| 44 | #define RTSR_SWALE2 (1 << 11) /* RTC stopwatch alarm2 enable */ |
| 45 | #define RTSR_SWAL2 (1 << 10) /* RTC stopwatch alarm2 detected */ |
| 46 | #define RTSR_SWALE1 (1 << 9) /* RTC stopwatch alarm1 enable */ |
| 47 | #define RTSR_SWAL1 (1 << 8) /* RTC stopwatch alarm1 detected */ |
| 48 | #define RTSR_RDALE2 (1 << 7) /* RTC alarm2 enable */ |
| 49 | #define RTSR_RDAL2 (1 << 6) /* RTC alarm2 detected */ |
| 50 | #define RTSR_RDALE1 (1 << 5) /* RTC alarm1 enable */ |
| 51 | #define RTSR_RDAL1 (1 << 4) /* RTC alarm1 detected */ |
| 52 | #define RTSR_HZE (1 << 3) /* HZ interrupt enable */ |
| 53 | #define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */ |
| 54 | #define RTSR_HZ (1 << 1) /* HZ rising-edge detected */ |
| 55 | #define RTSR_AL (1 << 0) /* RTC alarm detected */ |
| 56 | #define RTSR_TRIG_MASK (RTSR_AL | RTSR_HZ | RTSR_RDAL1 | RTSR_RDAL2\ |
| 57 | | RTSR_SWAL1 | RTSR_SWAL2) |
| 58 | #define RYxR_YEAR_S 9 |
| 59 | #define RYxR_YEAR_MASK (0xfff << RYxR_YEAR_S) |
| 60 | #define RYxR_MONTH_S 5 |
| 61 | #define RYxR_MONTH_MASK (0xf << RYxR_MONTH_S) |
| 62 | #define RYxR_DAY_MASK 0x1f |
| 63 | #define RDxR_HOUR_S 12 |
| 64 | #define RDxR_HOUR_MASK (0x1f << RDxR_HOUR_S) |
| 65 | #define RDxR_MIN_S 6 |
| 66 | #define RDxR_MIN_MASK (0x3f << RDxR_MIN_S) |
| 67 | #define RDxR_SEC_MASK 0x3f |
| 68 | |
| 69 | #define RTSR 0x08 |
| 70 | #define RTTR 0x0c |
| 71 | #define RDCR 0x10 |
| 72 | #define RYCR 0x14 |
| 73 | #define RDAR1 0x18 |
| 74 | #define RYAR1 0x1c |
| 75 | #define RTCPICR 0x34 |
| 76 | #define PIAR 0x38 |
| 77 | |
| 78 | #define rtc_readl(pxa_rtc, reg) \ |
| 79 | __raw_readl((pxa_rtc)->base + (reg)) |
| 80 | #define rtc_writel(pxa_rtc, reg, value) \ |
| 81 | __raw_writel((value), (pxa_rtc)->base + (reg)) |
| 82 | |
| 83 | struct pxa_rtc { |
| 84 | struct resource *ress; |
| 85 | void __iomem *base; |
| 86 | int irq_1Hz; |
| 87 | int irq_Alrm; |
| 88 | struct rtc_device *rtc; |
| 89 | spinlock_t lock; /* Protects this structure */ |
Robert Jarzmik | dc94436 | 2009-01-06 14:42:14 -0800 | [diff] [blame] | 90 | }; |
| 91 | |
| 92 | static u32 ryxr_calc(struct rtc_time *tm) |
| 93 | { |
| 94 | return ((tm->tm_year + 1900) << RYxR_YEAR_S) |
| 95 | | ((tm->tm_mon + 1) << RYxR_MONTH_S) |
| 96 | | tm->tm_mday; |
| 97 | } |
| 98 | |
| 99 | static u32 rdxr_calc(struct rtc_time *tm) |
| 100 | { |
| 101 | return (tm->tm_hour << RDxR_HOUR_S) | (tm->tm_min << RDxR_MIN_S) |
| 102 | | tm->tm_sec; |
| 103 | } |
| 104 | |
| 105 | static void tm_calc(u32 rycr, u32 rdcr, struct rtc_time *tm) |
| 106 | { |
| 107 | tm->tm_year = ((rycr & RYxR_YEAR_MASK) >> RYxR_YEAR_S) - 1900; |
| 108 | tm->tm_mon = (((rycr & RYxR_MONTH_MASK) >> RYxR_MONTH_S)) - 1; |
| 109 | tm->tm_mday = (rycr & RYxR_DAY_MASK); |
| 110 | tm->tm_hour = (rdcr & RDxR_HOUR_MASK) >> RDxR_HOUR_S; |
| 111 | tm->tm_min = (rdcr & RDxR_MIN_MASK) >> RDxR_MIN_S; |
| 112 | tm->tm_sec = rdcr & RDxR_SEC_MASK; |
| 113 | } |
| 114 | |
| 115 | static void rtsr_clear_bits(struct pxa_rtc *pxa_rtc, u32 mask) |
| 116 | { |
| 117 | u32 rtsr; |
| 118 | |
| 119 | rtsr = rtc_readl(pxa_rtc, RTSR); |
| 120 | rtsr &= ~RTSR_TRIG_MASK; |
| 121 | rtsr &= ~mask; |
| 122 | rtc_writel(pxa_rtc, RTSR, rtsr); |
| 123 | } |
| 124 | |
| 125 | static void rtsr_set_bits(struct pxa_rtc *pxa_rtc, u32 mask) |
| 126 | { |
| 127 | u32 rtsr; |
| 128 | |
| 129 | rtsr = rtc_readl(pxa_rtc, RTSR); |
| 130 | rtsr &= ~RTSR_TRIG_MASK; |
| 131 | rtsr |= mask; |
| 132 | rtc_writel(pxa_rtc, RTSR, rtsr); |
| 133 | } |
| 134 | |
| 135 | static irqreturn_t pxa_rtc_irq(int irq, void *dev_id) |
| 136 | { |
| 137 | struct platform_device *pdev = to_platform_device(dev_id); |
| 138 | struct pxa_rtc *pxa_rtc = platform_get_drvdata(pdev); |
| 139 | u32 rtsr; |
| 140 | unsigned long events = 0; |
| 141 | |
| 142 | spin_lock(&pxa_rtc->lock); |
| 143 | |
| 144 | /* clear interrupt sources */ |
| 145 | rtsr = rtc_readl(pxa_rtc, RTSR); |
| 146 | rtc_writel(pxa_rtc, RTSR, rtsr); |
| 147 | |
| 148 | /* temporary disable rtc interrupts */ |
| 149 | rtsr_clear_bits(pxa_rtc, RTSR_RDALE1 | RTSR_PIALE | RTSR_HZE); |
| 150 | |
| 151 | /* clear alarm interrupt if it has occurred */ |
| 152 | if (rtsr & RTSR_RDAL1) |
| 153 | rtsr &= ~RTSR_RDALE1; |
| 154 | |
| 155 | /* update irq data & counter */ |
| 156 | if (rtsr & RTSR_RDAL1) |
| 157 | events |= RTC_AF | RTC_IRQF; |
| 158 | if (rtsr & RTSR_HZ) |
| 159 | events |= RTC_UF | RTC_IRQF; |
| 160 | if (rtsr & RTSR_PIAL) |
| 161 | events |= RTC_PF | RTC_IRQF; |
| 162 | |
| 163 | rtc_update_irq(pxa_rtc->rtc, 1, events); |
| 164 | |
| 165 | /* enable back rtc interrupts */ |
| 166 | rtc_writel(pxa_rtc, RTSR, rtsr & ~RTSR_TRIG_MASK); |
| 167 | |
| 168 | spin_unlock(&pxa_rtc->lock); |
| 169 | return IRQ_HANDLED; |
| 170 | } |
| 171 | |
| 172 | static int pxa_rtc_open(struct device *dev) |
| 173 | { |
| 174 | struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev); |
| 175 | int ret; |
| 176 | |
| 177 | ret = request_irq(pxa_rtc->irq_1Hz, pxa_rtc_irq, IRQF_DISABLED, |
| 178 | "rtc 1Hz", dev); |
| 179 | if (ret < 0) { |
| 180 | dev_err(dev, "can't get irq %i, err %d\n", pxa_rtc->irq_1Hz, |
| 181 | ret); |
| 182 | goto err_irq_1Hz; |
| 183 | } |
| 184 | ret = request_irq(pxa_rtc->irq_Alrm, pxa_rtc_irq, IRQF_DISABLED, |
| 185 | "rtc Alrm", dev); |
| 186 | if (ret < 0) { |
| 187 | dev_err(dev, "can't get irq %i, err %d\n", pxa_rtc->irq_Alrm, |
| 188 | ret); |
| 189 | goto err_irq_Alrm; |
| 190 | } |
| 191 | |
| 192 | return 0; |
| 193 | |
| 194 | err_irq_Alrm: |
| 195 | free_irq(pxa_rtc->irq_1Hz, dev); |
| 196 | err_irq_1Hz: |
| 197 | return ret; |
| 198 | } |
| 199 | |
| 200 | static void pxa_rtc_release(struct device *dev) |
| 201 | { |
| 202 | struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev); |
| 203 | |
| 204 | spin_lock_irq(&pxa_rtc->lock); |
| 205 | rtsr_clear_bits(pxa_rtc, RTSR_PIALE | RTSR_RDALE1 | RTSR_HZE); |
| 206 | spin_unlock_irq(&pxa_rtc->lock); |
| 207 | |
| 208 | free_irq(pxa_rtc->irq_Alrm, dev); |
| 209 | free_irq(pxa_rtc->irq_1Hz, dev); |
| 210 | } |
| 211 | |
| 212 | static int pxa_periodic_irq_set_freq(struct device *dev, int freq) |
| 213 | { |
| 214 | struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev); |
| 215 | int period_ms; |
| 216 | |
| 217 | if (freq < 1 || freq > MAXFREQ_PERIODIC) |
| 218 | return -EINVAL; |
| 219 | |
| 220 | period_ms = 1000 / freq; |
| 221 | rtc_writel(pxa_rtc, PIAR, period_ms); |
| 222 | |
| 223 | return 0; |
| 224 | } |
| 225 | |
| 226 | static int pxa_periodic_irq_set_state(struct device *dev, int enabled) |
| 227 | { |
| 228 | struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev); |
| 229 | |
| 230 | if (enabled) |
| 231 | rtsr_set_bits(pxa_rtc, RTSR_PIALE | RTSR_PICE); |
| 232 | else |
| 233 | rtsr_clear_bits(pxa_rtc, RTSR_PIALE | RTSR_PICE); |
| 234 | |
| 235 | return 0; |
| 236 | } |
| 237 | |
| 238 | static int pxa_rtc_ioctl(struct device *dev, unsigned int cmd, |
| 239 | unsigned long arg) |
| 240 | { |
| 241 | struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev); |
| 242 | int ret = 0; |
| 243 | |
| 244 | spin_lock_irq(&pxa_rtc->lock); |
| 245 | switch (cmd) { |
| 246 | case RTC_AIE_OFF: |
| 247 | rtsr_clear_bits(pxa_rtc, RTSR_RDALE1); |
| 248 | break; |
| 249 | case RTC_AIE_ON: |
| 250 | rtsr_set_bits(pxa_rtc, RTSR_RDALE1); |
| 251 | break; |
| 252 | case RTC_UIE_OFF: |
| 253 | rtsr_clear_bits(pxa_rtc, RTSR_HZE); |
| 254 | break; |
| 255 | case RTC_UIE_ON: |
| 256 | rtsr_set_bits(pxa_rtc, RTSR_HZE); |
| 257 | break; |
| 258 | default: |
| 259 | ret = -ENOIOCTLCMD; |
| 260 | } |
| 261 | |
| 262 | spin_unlock_irq(&pxa_rtc->lock); |
| 263 | return ret; |
| 264 | } |
| 265 | |
| 266 | static int pxa_rtc_read_time(struct device *dev, struct rtc_time *tm) |
| 267 | { |
| 268 | struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev); |
| 269 | u32 rycr, rdcr; |
| 270 | |
| 271 | rycr = rtc_readl(pxa_rtc, RYCR); |
| 272 | rdcr = rtc_readl(pxa_rtc, RDCR); |
| 273 | |
| 274 | tm_calc(rycr, rdcr, tm); |
| 275 | return 0; |
| 276 | } |
| 277 | |
| 278 | static int pxa_rtc_set_time(struct device *dev, struct rtc_time *tm) |
| 279 | { |
| 280 | struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev); |
| 281 | |
| 282 | rtc_writel(pxa_rtc, RYCR, ryxr_calc(tm)); |
| 283 | rtc_writel(pxa_rtc, RDCR, rdxr_calc(tm)); |
| 284 | |
| 285 | return 0; |
| 286 | } |
| 287 | |
| 288 | static int pxa_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) |
| 289 | { |
| 290 | struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev); |
| 291 | u32 rtsr, ryar, rdar; |
| 292 | |
| 293 | ryar = rtc_readl(pxa_rtc, RYAR1); |
| 294 | rdar = rtc_readl(pxa_rtc, RDAR1); |
| 295 | tm_calc(ryar, rdar, &alrm->time); |
| 296 | |
| 297 | rtsr = rtc_readl(pxa_rtc, RTSR); |
| 298 | alrm->enabled = (rtsr & RTSR_RDALE1) ? 1 : 0; |
| 299 | alrm->pending = (rtsr & RTSR_RDAL1) ? 1 : 0; |
| 300 | return 0; |
| 301 | } |
| 302 | |
| 303 | static int pxa_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) |
| 304 | { |
| 305 | struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev); |
| 306 | u32 rtsr; |
| 307 | |
| 308 | spin_lock_irq(&pxa_rtc->lock); |
| 309 | |
| 310 | rtc_writel(pxa_rtc, RYAR1, ryxr_calc(&alrm->time)); |
| 311 | rtc_writel(pxa_rtc, RDAR1, rdxr_calc(&alrm->time)); |
| 312 | |
| 313 | rtsr = rtc_readl(pxa_rtc, RTSR); |
| 314 | if (alrm->enabled) |
| 315 | rtsr |= RTSR_RDALE1; |
| 316 | else |
| 317 | rtsr &= ~RTSR_RDALE1; |
| 318 | rtc_writel(pxa_rtc, RTSR, rtsr); |
| 319 | |
| 320 | spin_unlock_irq(&pxa_rtc->lock); |
| 321 | |
| 322 | return 0; |
| 323 | } |
| 324 | |
| 325 | static int pxa_rtc_proc(struct device *dev, struct seq_file *seq) |
| 326 | { |
| 327 | struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev); |
| 328 | |
| 329 | seq_printf(seq, "trim/divider\t: 0x%08x\n", rtc_readl(pxa_rtc, RTTR)); |
| 330 | seq_printf(seq, "update_IRQ\t: %s\n", |
| 331 | (rtc_readl(pxa_rtc, RTSR) & RTSR_HZE) ? "yes" : "no"); |
| 332 | seq_printf(seq, "periodic_IRQ\t: %s\n", |
| 333 | (rtc_readl(pxa_rtc, RTSR) & RTSR_PIALE) ? "yes" : "no"); |
| 334 | seq_printf(seq, "periodic_freq\t: %u\n", rtc_readl(pxa_rtc, PIAR)); |
| 335 | |
| 336 | return 0; |
| 337 | } |
| 338 | |
| 339 | static const struct rtc_class_ops pxa_rtc_ops = { |
| 340 | .open = pxa_rtc_open, |
| 341 | .release = pxa_rtc_release, |
| 342 | .ioctl = pxa_rtc_ioctl, |
| 343 | .read_time = pxa_rtc_read_time, |
| 344 | .set_time = pxa_rtc_set_time, |
| 345 | .read_alarm = pxa_rtc_read_alarm, |
| 346 | .set_alarm = pxa_rtc_set_alarm, |
| 347 | .proc = pxa_rtc_proc, |
| 348 | .irq_set_state = pxa_periodic_irq_set_state, |
| 349 | .irq_set_freq = pxa_periodic_irq_set_freq, |
| 350 | }; |
| 351 | |
Alessandro Zummo | 0417ce2 | 2009-01-06 14:42:15 -0800 | [diff] [blame] | 352 | static int __init pxa_rtc_probe(struct platform_device *pdev) |
Robert Jarzmik | dc94436 | 2009-01-06 14:42:14 -0800 | [diff] [blame] | 353 | { |
| 354 | struct device *dev = &pdev->dev; |
| 355 | struct pxa_rtc *pxa_rtc; |
| 356 | int ret; |
| 357 | u32 rttr; |
| 358 | |
Robert Jarzmik | dc94436 | 2009-01-06 14:42:14 -0800 | [diff] [blame] | 359 | pxa_rtc = kzalloc(sizeof(struct pxa_rtc), GFP_KERNEL); |
| 360 | if (!pxa_rtc) |
Alessandro Zummo | 0417ce2 | 2009-01-06 14:42:15 -0800 | [diff] [blame] | 361 | return -ENOMEM; |
| 362 | |
| 363 | spin_lock_init(&pxa_rtc->lock); |
| 364 | platform_set_drvdata(pdev, pxa_rtc); |
Robert Jarzmik | dc94436 | 2009-01-06 14:42:14 -0800 | [diff] [blame] | 365 | |
| 366 | ret = -ENXIO; |
| 367 | pxa_rtc->ress = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 368 | if (!pxa_rtc->ress) { |
| 369 | dev_err(dev, "No I/O memory resource defined\n"); |
| 370 | goto err_ress; |
| 371 | } |
| 372 | |
| 373 | pxa_rtc->irq_1Hz = platform_get_irq(pdev, 0); |
| 374 | if (pxa_rtc->irq_1Hz < 0) { |
| 375 | dev_err(dev, "No 1Hz IRQ resource defined\n"); |
| 376 | goto err_ress; |
| 377 | } |
| 378 | pxa_rtc->irq_Alrm = platform_get_irq(pdev, 1); |
| 379 | if (pxa_rtc->irq_Alrm < 0) { |
| 380 | dev_err(dev, "No alarm IRQ resource defined\n"); |
| 381 | goto err_ress; |
| 382 | } |
| 383 | |
Robert Jarzmik | dc94436 | 2009-01-06 14:42:14 -0800 | [diff] [blame] | 384 | ret = -ENOMEM; |
| 385 | pxa_rtc->base = ioremap(pxa_rtc->ress->start, |
Alessandro Zummo | 0417ce2 | 2009-01-06 14:42:15 -0800 | [diff] [blame] | 386 | resource_size(pxa_rtc->ress)); |
Robert Jarzmik | dc94436 | 2009-01-06 14:42:14 -0800 | [diff] [blame] | 387 | if (!pxa_rtc->base) { |
| 388 | dev_err(&pdev->dev, "Unable to map pxa RTC I/O memory\n"); |
| 389 | goto err_map; |
| 390 | } |
| 391 | |
| 392 | /* |
| 393 | * If the clock divider is uninitialized then reset it to the |
| 394 | * default value to get the 1Hz clock. |
| 395 | */ |
| 396 | if (rtc_readl(pxa_rtc, RTTR) == 0) { |
| 397 | rttr = RTC_DEF_DIVIDER + (RTC_DEF_TRIM << 16); |
| 398 | rtc_writel(pxa_rtc, RTTR, rttr); |
| 399 | dev_warn(dev, "warning: initializing default clock" |
| 400 | " divider/trim value\n"); |
| 401 | } |
| 402 | |
| 403 | rtsr_clear_bits(pxa_rtc, RTSR_PIALE | RTSR_RDALE1 | RTSR_HZE); |
Alessandro Zummo | 0417ce2 | 2009-01-06 14:42:15 -0800 | [diff] [blame] | 404 | |
| 405 | pxa_rtc->rtc = rtc_device_register("pxa-rtc", &pdev->dev, &pxa_rtc_ops, |
| 406 | THIS_MODULE); |
| 407 | ret = PTR_ERR(pxa_rtc->rtc); |
| 408 | if (IS_ERR(pxa_rtc->rtc)) { |
| 409 | dev_err(dev, "Failed to register RTC device -> %d\n", ret); |
| 410 | goto err_rtc_reg; |
| 411 | } |
| 412 | |
Robert Jarzmik | dc94436 | 2009-01-06 14:42:14 -0800 | [diff] [blame] | 413 | device_init_wakeup(dev, 1); |
| 414 | |
| 415 | return 0; |
| 416 | |
Robert Jarzmik | dc94436 | 2009-01-06 14:42:14 -0800 | [diff] [blame] | 417 | err_rtc_reg: |
Alessandro Zummo | 0417ce2 | 2009-01-06 14:42:15 -0800 | [diff] [blame] | 418 | iounmap(pxa_rtc->base); |
Robert Jarzmik | dc94436 | 2009-01-06 14:42:14 -0800 | [diff] [blame] | 419 | err_ress: |
Alessandro Zummo | 0417ce2 | 2009-01-06 14:42:15 -0800 | [diff] [blame] | 420 | err_map: |
Robert Jarzmik | dc94436 | 2009-01-06 14:42:14 -0800 | [diff] [blame] | 421 | kfree(pxa_rtc); |
Robert Jarzmik | dc94436 | 2009-01-06 14:42:14 -0800 | [diff] [blame] | 422 | return ret; |
| 423 | } |
| 424 | |
Alessandro Zummo | 0417ce2 | 2009-01-06 14:42:15 -0800 | [diff] [blame] | 425 | static int __exit pxa_rtc_remove(struct platform_device *pdev) |
Robert Jarzmik | dc94436 | 2009-01-06 14:42:14 -0800 | [diff] [blame] | 426 | { |
| 427 | struct pxa_rtc *pxa_rtc = platform_get_drvdata(pdev); |
| 428 | |
Alessandro Zummo | 0417ce2 | 2009-01-06 14:42:15 -0800 | [diff] [blame] | 429 | rtc_device_unregister(pxa_rtc->rtc); |
| 430 | |
Robert Jarzmik | dc94436 | 2009-01-06 14:42:14 -0800 | [diff] [blame] | 431 | spin_lock_irq(&pxa_rtc->lock); |
| 432 | iounmap(pxa_rtc->base); |
Robert Jarzmik | dc94436 | 2009-01-06 14:42:14 -0800 | [diff] [blame] | 433 | spin_unlock_irq(&pxa_rtc->lock); |
| 434 | |
Robert Jarzmik | dc94436 | 2009-01-06 14:42:14 -0800 | [diff] [blame] | 435 | kfree(pxa_rtc); |
| 436 | |
| 437 | return 0; |
| 438 | } |
| 439 | |
| 440 | #ifdef CONFIG_PM |
Robert Jarzmik | e6e698a | 2009-07-21 22:47:32 +0200 | [diff] [blame] | 441 | static int pxa_rtc_suspend(struct device *dev) |
Robert Jarzmik | dc94436 | 2009-01-06 14:42:14 -0800 | [diff] [blame] | 442 | { |
Robert Jarzmik | e6e698a | 2009-07-21 22:47:32 +0200 | [diff] [blame] | 443 | struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev); |
Robert Jarzmik | dc94436 | 2009-01-06 14:42:14 -0800 | [diff] [blame] | 444 | |
Robert Jarzmik | e6e698a | 2009-07-21 22:47:32 +0200 | [diff] [blame] | 445 | if (device_may_wakeup(dev)) |
Robert Jarzmik | dc94436 | 2009-01-06 14:42:14 -0800 | [diff] [blame] | 446 | enable_irq_wake(pxa_rtc->irq_Alrm); |
| 447 | return 0; |
| 448 | } |
| 449 | |
Robert Jarzmik | e6e698a | 2009-07-21 22:47:32 +0200 | [diff] [blame] | 450 | static int pxa_rtc_resume(struct device *dev) |
Robert Jarzmik | dc94436 | 2009-01-06 14:42:14 -0800 | [diff] [blame] | 451 | { |
Robert Jarzmik | e6e698a | 2009-07-21 22:47:32 +0200 | [diff] [blame] | 452 | struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev); |
Robert Jarzmik | dc94436 | 2009-01-06 14:42:14 -0800 | [diff] [blame] | 453 | |
Robert Jarzmik | e6e698a | 2009-07-21 22:47:32 +0200 | [diff] [blame] | 454 | if (device_may_wakeup(dev)) |
Robert Jarzmik | dc94436 | 2009-01-06 14:42:14 -0800 | [diff] [blame] | 455 | disable_irq_wake(pxa_rtc->irq_Alrm); |
| 456 | return 0; |
| 457 | } |
Robert Jarzmik | e6e698a | 2009-07-21 22:47:32 +0200 | [diff] [blame] | 458 | |
Alexey Dobriyan | 4714521 | 2009-12-14 18:00:08 -0800 | [diff] [blame] | 459 | static const struct dev_pm_ops pxa_rtc_pm_ops = { |
Robert Jarzmik | e6e698a | 2009-07-21 22:47:32 +0200 | [diff] [blame] | 460 | .suspend = pxa_rtc_suspend, |
| 461 | .resume = pxa_rtc_resume, |
| 462 | }; |
Robert Jarzmik | dc94436 | 2009-01-06 14:42:14 -0800 | [diff] [blame] | 463 | #endif |
| 464 | |
| 465 | static struct platform_driver pxa_rtc_driver = { |
Robert Jarzmik | dc94436 | 2009-01-06 14:42:14 -0800 | [diff] [blame] | 466 | .remove = __exit_p(pxa_rtc_remove), |
Robert Jarzmik | dc94436 | 2009-01-06 14:42:14 -0800 | [diff] [blame] | 467 | .driver = { |
Robert Jarzmik | e6e698a | 2009-07-21 22:47:32 +0200 | [diff] [blame] | 468 | .name = "pxa-rtc", |
| 469 | #ifdef CONFIG_PM |
| 470 | .pm = &pxa_rtc_pm_ops, |
| 471 | #endif |
Robert Jarzmik | dc94436 | 2009-01-06 14:42:14 -0800 | [diff] [blame] | 472 | }, |
| 473 | }; |
| 474 | |
| 475 | static int __init pxa_rtc_init(void) |
| 476 | { |
| 477 | if (cpu_is_pxa27x() || cpu_is_pxa3xx()) |
Alessandro Zummo | 0417ce2 | 2009-01-06 14:42:15 -0800 | [diff] [blame] | 478 | return platform_driver_probe(&pxa_rtc_driver, pxa_rtc_probe); |
Robert Jarzmik | dc94436 | 2009-01-06 14:42:14 -0800 | [diff] [blame] | 479 | |
| 480 | return -ENODEV; |
| 481 | } |
| 482 | |
| 483 | static void __exit pxa_rtc_exit(void) |
| 484 | { |
| 485 | platform_driver_unregister(&pxa_rtc_driver); |
| 486 | } |
| 487 | |
| 488 | module_init(pxa_rtc_init); |
| 489 | module_exit(pxa_rtc_exit); |
| 490 | |
Robert Jarzmik | 57f63bc | 2009-02-11 13:04:19 -0800 | [diff] [blame] | 491 | MODULE_AUTHOR("Robert Jarzmik <robert.jarzmik@free.fr>"); |
Robert Jarzmik | dc94436 | 2009-01-06 14:42:14 -0800 | [diff] [blame] | 492 | MODULE_DESCRIPTION("PXA27x/PXA3xx Realtime Clock Driver (RTC)"); |
| 493 | MODULE_LICENSE("GPL"); |
| 494 | MODULE_ALIAS("platform:pxa-rtc"); |