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gerrit-public.fairphone.software / kernel / msm-4.9 / f4091322d7397c8eb85c071570cab0e82ee3e261 / . / arch / sparc / include / asm / ttable.h
blob: 71b5a67522abb2bb0d8457819612aa26e948fdc8 [file] [log] [blame]
Sam Ravnborga00736e2008-06-19 20:26:19 +0200[diff] [blame]1#ifndef _SPARC64_TTABLE_H
2#define _SPARC64_TTABLE_H
3
4#include <asm/utrap.h>
David S. Millerb4f43722008-11-23 21:55:29 -0800[diff] [blame]5#include <asm/pil.h>
Sam Ravnborga00736e2008-06-19 20:26:19 +0200[diff] [blame]6
7#ifdef __ASSEMBLY__
8#include <asm/thread_info.h>
9#endif
10
11#define BOOT_KERNEL b sparc64_boot; nop; nop; nop; nop; nop; nop; nop;
12
13/* We need a "cleaned" instruction... */
14#define CLEAN_WINDOW \
15 rdpr %cleanwin, %l0; add %l0, 1, %l0; \
16 wrpr %l0, 0x0, %cleanwin; \
17 clr %o0; clr %o1; clr %o2; clr %o3; \
18 clr %o4; clr %o5; clr %o6; clr %o7; \
19 clr %l0; clr %l1; clr %l2; clr %l3; \
20 clr %l4; clr %l5; clr %l6; clr %l7; \
21 retry; \
22 nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;
23
24#define TRAP(routine) \
25 sethi %hi(109f), %g7; \
26 ba,pt %xcc, etrap; \
27109: or %g7, %lo(109b), %g7; \
28 call routine; \
29 add %sp, PTREGS_OFF, %o0; \
30 ba,pt %xcc, rtrap; \
31 nop; \
32 nop;
33
34#define TRAP_7INSNS(routine) \
35 sethi %hi(109f), %g7; \
36 ba,pt %xcc, etrap; \
37109: or %g7, %lo(109b), %g7; \
38 call routine; \
39 add %sp, PTREGS_OFF, %o0; \
40 ba,pt %xcc, rtrap; \
41 nop;
42
43#define TRAP_SAVEFPU(routine) \
44 sethi %hi(109f), %g7; \
45 ba,pt %xcc, do_fptrap; \
46109: or %g7, %lo(109b), %g7; \
47 call routine; \
48 add %sp, PTREGS_OFF, %o0; \
49 ba,pt %xcc, rtrap; \
50 nop; \
51 nop;
52
53#define TRAP_NOSAVE(routine) \
54 ba,pt %xcc, routine; \
55 nop; \
56 nop; nop; nop; nop; nop; nop;
57
58#define TRAP_NOSAVE_7INSNS(routine) \
59 ba,pt %xcc, routine; \
60 nop; \
61 nop; nop; nop; nop; nop;
62
63#define TRAPTL1(routine) \
64 sethi %hi(109f), %g7; \
65 ba,pt %xcc, etraptl1; \
66109: or %g7, %lo(109b), %g7; \
67 call routine; \
68 add %sp, PTREGS_OFF, %o0; \
69 ba,pt %xcc, rtrap; \
70 nop; \
71 nop;
72
73#define TRAP_ARG(routine, arg) \
74 sethi %hi(109f), %g7; \
75 ba,pt %xcc, etrap; \
76109: or %g7, %lo(109b), %g7; \
77 add %sp, PTREGS_OFF, %o0; \
78 call routine; \
79 mov arg, %o1; \
80 ba,pt %xcc, rtrap; \
81 nop;
82
83#define TRAPTL1_ARG(routine, arg) \
84 sethi %hi(109f), %g7; \
85 ba,pt %xcc, etraptl1; \
86109: or %g7, %lo(109b), %g7; \
87 add %sp, PTREGS_OFF, %o0; \
88 call routine; \
89 mov arg, %o1; \
90 ba,pt %xcc, rtrap; \
91 nop;
92
93#define SYSCALL_TRAP(routine, systbl) \
94 rdpr %pil, %g2; \
95 mov TSTATE_SYSCALL, %g3; \
96 sethi %hi(109f), %g7; \
97 ba,pt %xcc, etrap_syscall; \
98109: or %g7, %lo(109b), %g7; \
99 sethi %hi(systbl), %l7; \
100 ba,pt %xcc, routine; \
101 or %l7, %lo(systbl), %l7;
102
103#define TRAP_UTRAP(handler,lvl) \
104 mov handler, %g3; \
105 ba,pt %xcc, utrap_trap; \
106 mov lvl, %g4; \
107 nop; \
108 nop; \
109 nop; \
110 nop; \
111 nop;
112
113#ifdef CONFIG_COMPAT
114#define LINUX_32BIT_SYSCALL_TRAP SYSCALL_TRAP(linux_sparc_syscall32, sys_call_table32)
115#else
116#define LINUX_32BIT_SYSCALL_TRAP BTRAP(0x110)
117#endif
118#define LINUX_64BIT_SYSCALL_TRAP SYSCALL_TRAP(linux_sparc_syscall, sys_call_table64)
119#define GETCC_TRAP TRAP(getcc)
120#define SETCC_TRAP TRAP(setcc)
121#define BREAKPOINT_TRAP TRAP(breakpoint_trap)
122
123#ifdef CONFIG_TRACE_IRQFLAGS
124
125#define TRAP_IRQ(routine, level) \
126 rdpr %pil, %g2; \
David S. Millerb4f43722008-11-23 21:55:29 -0800[diff] [blame]127 wrpr %g0, PIL_NORMAL_MAX, %pil; \
Sam Ravnborga00736e2008-06-19 20:26:19 +0200[diff] [blame]128 sethi %hi(1f-4), %g7; \
129 ba,pt %xcc, etrap_irq; \
130 or %g7, %lo(1f-4), %g7; \
131 nop; \
132 nop; \
133 nop; \
134 .subsection 2; \
1351: call trace_hardirqs_off; \
136 nop; \
137 mov level, %o0; \
138 call routine; \
139 add %sp, PTREGS_OFF, %o1; \
140 ba,a,pt %xcc, rtrap_irq; \
141 .previous;
142
143#else
144
145#define TRAP_IRQ(routine, level) \
146 rdpr %pil, %g2; \
David S. Millerb4f43722008-11-23 21:55:29 -0800[diff] [blame]147 wrpr %g0, PIL_NORMAL_MAX, %pil; \
Sam Ravnborga00736e2008-06-19 20:26:19 +0200[diff] [blame]148 ba,pt %xcc, etrap_irq; \
149 rd %pc, %g7; \
150 mov level, %o0; \
151 call routine; \
152 add %sp, PTREGS_OFF, %o1; \
153 ba,a,pt %xcc, rtrap_irq;
154
155#endif
156
David S. Millerb4f43722008-11-23 21:55:29 -0800[diff] [blame]157#define TRAP_NMI_IRQ(routine, level) \
158 rdpr %pil, %g2; \
159 wrpr %g0, PIL_NMI, %pil; \
160 ba,pt %xcc, etrap_irq; \
161 rd %pc, %g7; \
162 mov level, %o0; \
163 call routine; \
164 add %sp, PTREGS_OFF, %o1; \
David S. Miller55657362008-11-25 22:24:59 -0800[diff] [blame]165 ba,a,pt %xcc, rtrap_nmi;
David S. Millerb4f43722008-11-23 21:55:29 -0800[diff] [blame]166
Sam Ravnborga00736e2008-06-19 20:26:19 +0200[diff] [blame]167#define TRAP_IVEC TRAP_NOSAVE(do_ivec)
168
169#define BTRAP(lvl) TRAP_ARG(bad_trap, lvl)
170
171#define BTRAPTL1(lvl) TRAPTL1_ARG(bad_trap_tl1, lvl)
172
173#define FLUSH_WINDOW_TRAP \
174 ba,pt %xcc, etrap; \
175 rd %pc, %g7; \
176 flushw; \
177 ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %l1; \
178 add %l1, 4, %l2; \
179 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]; \
180 ba,pt %xcc, rtrap; \
181 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC];
182
183#ifdef CONFIG_KPROBES
184#define KPROBES_TRAP(lvl) TRAP_IRQ(kprobe_trap, lvl)
185#else
186#define KPROBES_TRAP(lvl) TRAP_ARG(bad_trap, lvl)
187#endif
188
189#ifdef CONFIG_KGDB
190#define KGDB_TRAP(lvl) TRAP_IRQ(kgdb_trap, lvl)
191#else
192#define KGDB_TRAP(lvl) TRAP_ARG(bad_trap, lvl)
193#endif
194
195#define SUN4V_ITSB_MISS \
196 ldxa [%g0] ASI_SCRATCHPAD, %g2; \
197 ldx [%g2 + HV_FAULT_I_ADDR_OFFSET], %g4; \
198 ldx [%g2 + HV_FAULT_I_CTX_OFFSET], %g5; \
199 srlx %g4, 22, %g6; \
200 ba,pt %xcc, sun4v_itsb_miss; \
201 nop; \
202 nop; \
203 nop;
204
205#define SUN4V_DTSB_MISS \
206 ldxa [%g0] ASI_SCRATCHPAD, %g2; \
207 ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4; \
208 ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5; \
209 srlx %g4, 22, %g6; \
210 ba,pt %xcc, sun4v_dtsb_miss; \
211 nop; \
212 nop; \
213 nop;
214
215/* Before touching these macros, you owe it to yourself to go and
216 * see how arch/sparc64/kernel/winfixup.S works... -DaveM
217 *
218 * For the user cases we used to use the %asi register, but
219 * it turns out that the "wr xxx, %asi" costs ~5 cycles, so
220 * now we use immediate ASI loads and stores instead. Kudos
221 * to Greg Onufer for pointing out this performance anomaly.
222 *
223 * Further note that we cannot use the g2, g4, g5, and g7 alternate
224 * globals in the spill routines, check out the save instruction in
225 * arch/sparc64/kernel/etrap.S to see what I mean about g2, and
226 * g4/g5 are the globals which are preserved by etrap processing
227 * for the caller of it. The g7 register is the return pc for
228 * etrap. Finally, g6 is the current thread register so we cannot
229 * us it in the spill handlers either. Most of these rules do not
230 * apply to fill processing, only g6 is not usable.
231 */
232
233/* Normal kernel spill */
234#define SPILL_0_NORMAL \
235 stx %l0, [%sp + STACK_BIAS + 0x00]; \
236 stx %l1, [%sp + STACK_BIAS + 0x08]; \
237 stx %l2, [%sp + STACK_BIAS + 0x10]; \
238 stx %l3, [%sp + STACK_BIAS + 0x18]; \
239 stx %l4, [%sp + STACK_BIAS + 0x20]; \
240 stx %l5, [%sp + STACK_BIAS + 0x28]; \
241 stx %l6, [%sp + STACK_BIAS + 0x30]; \
242 stx %l7, [%sp + STACK_BIAS + 0x38]; \
243 stx %i0, [%sp + STACK_BIAS + 0x40]; \
244 stx %i1, [%sp + STACK_BIAS + 0x48]; \
245 stx %i2, [%sp + STACK_BIAS + 0x50]; \
246 stx %i3, [%sp + STACK_BIAS + 0x58]; \
247 stx %i4, [%sp + STACK_BIAS + 0x60]; \
248 stx %i5, [%sp + STACK_BIAS + 0x68]; \
249 stx %i6, [%sp + STACK_BIAS + 0x70]; \
250 stx %i7, [%sp + STACK_BIAS + 0x78]; \
251 saved; retry; nop; nop; nop; nop; nop; nop; \
252 nop; nop; nop; nop; nop; nop; nop; nop;
253
254#define SPILL_0_NORMAL_ETRAP \
255etrap_kernel_spill: \
256 stx %l0, [%sp + STACK_BIAS + 0x00]; \
257 stx %l1, [%sp + STACK_BIAS + 0x08]; \
258 stx %l2, [%sp + STACK_BIAS + 0x10]; \
259 stx %l3, [%sp + STACK_BIAS + 0x18]; \
260 stx %l4, [%sp + STACK_BIAS + 0x20]; \
261 stx %l5, [%sp + STACK_BIAS + 0x28]; \
262 stx %l6, [%sp + STACK_BIAS + 0x30]; \
263 stx %l7, [%sp + STACK_BIAS + 0x38]; \
264 stx %i0, [%sp + STACK_BIAS + 0x40]; \
265 stx %i1, [%sp + STACK_BIAS + 0x48]; \
266 stx %i2, [%sp + STACK_BIAS + 0x50]; \
267 stx %i3, [%sp + STACK_BIAS + 0x58]; \
268 stx %i4, [%sp + STACK_BIAS + 0x60]; \
269 stx %i5, [%sp + STACK_BIAS + 0x68]; \
270 stx %i6, [%sp + STACK_BIAS + 0x70]; \
271 stx %i7, [%sp + STACK_BIAS + 0x78]; \
272 saved; \
273 sub %g1, 2, %g1; \
274 ba,pt %xcc, etrap_save; \
275 wrpr %g1, %cwp; \
276 nop; nop; nop; nop; nop; nop; nop; nop; \
277 nop; nop; nop; nop;
278
279/* Normal 64bit spill */
280#define SPILL_1_GENERIC(ASI) \
281 add %sp, STACK_BIAS + 0x00, %g1; \
282 stxa %l0, [%g1 + %g0] ASI; \
283 mov 0x08, %g3; \
284 stxa %l1, [%g1 + %g3] ASI; \
285 add %g1, 0x10, %g1; \
286 stxa %l2, [%g1 + %g0] ASI; \
287 stxa %l3, [%g1 + %g3] ASI; \
288 add %g1, 0x10, %g1; \
289 stxa %l4, [%g1 + %g0] ASI; \
290 stxa %l5, [%g1 + %g3] ASI; \
291 add %g1, 0x10, %g1; \
292 stxa %l6, [%g1 + %g0] ASI; \
293 stxa %l7, [%g1 + %g3] ASI; \
294 add %g1, 0x10, %g1; \
295 stxa %i0, [%g1 + %g0] ASI; \
296 stxa %i1, [%g1 + %g3] ASI; \
297 add %g1, 0x10, %g1; \
298 stxa %i2, [%g1 + %g0] ASI; \
299 stxa %i3, [%g1 + %g3] ASI; \
300 add %g1, 0x10, %g1; \
301 stxa %i4, [%g1 + %g0] ASI; \
302 stxa %i5, [%g1 + %g3] ASI; \
303 add %g1, 0x10, %g1; \
304 stxa %i6, [%g1 + %g0] ASI; \
305 stxa %i7, [%g1 + %g3] ASI; \
306 saved; \
307 retry; nop; nop; \
308 b,a,pt %xcc, spill_fixup_dax; \
309 b,a,pt %xcc, spill_fixup_mna; \
310 b,a,pt %xcc, spill_fixup;
311
312#define SPILL_1_GENERIC_ETRAP \
313etrap_user_spill_64bit: \
314 stxa %l0, [%sp + STACK_BIAS + 0x00] %asi; \
315 stxa %l1, [%sp + STACK_BIAS + 0x08] %asi; \
316 stxa %l2, [%sp + STACK_BIAS + 0x10] %asi; \
317 stxa %l3, [%sp + STACK_BIAS + 0x18] %asi; \
318 stxa %l4, [%sp + STACK_BIAS + 0x20] %asi; \
319 stxa %l5, [%sp + STACK_BIAS + 0x28] %asi; \
320 stxa %l6, [%sp + STACK_BIAS + 0x30] %asi; \
321 stxa %l7, [%sp + STACK_BIAS + 0x38] %asi; \
322 stxa %i0, [%sp + STACK_BIAS + 0x40] %asi; \
323 stxa %i1, [%sp + STACK_BIAS + 0x48] %asi; \
324 stxa %i2, [%sp + STACK_BIAS + 0x50] %asi; \
325 stxa %i3, [%sp + STACK_BIAS + 0x58] %asi; \
326 stxa %i4, [%sp + STACK_BIAS + 0x60] %asi; \
327 stxa %i5, [%sp + STACK_BIAS + 0x68] %asi; \
328 stxa %i6, [%sp + STACK_BIAS + 0x70] %asi; \
329 stxa %i7, [%sp + STACK_BIAS + 0x78] %asi; \
330 saved; \
331 sub %g1, 2, %g1; \
332 ba,pt %xcc, etrap_save; \
333 wrpr %g1, %cwp; \
334 nop; nop; nop; nop; nop; \
335 nop; nop; nop; nop; \
336 ba,a,pt %xcc, etrap_spill_fixup_64bit; \
337 ba,a,pt %xcc, etrap_spill_fixup_64bit; \
338 ba,a,pt %xcc, etrap_spill_fixup_64bit;
339
340#define SPILL_1_GENERIC_ETRAP_FIXUP \
341etrap_spill_fixup_64bit: \
342 ldub [%g6 + TI_WSAVED], %g1; \
343 sll %g1, 3, %g3; \
344 add %g6, %g3, %g3; \
345 stx %sp, [%g3 + TI_RWIN_SPTRS]; \
346 sll %g1, 7, %g3; \
347 add %g6, %g3, %g3; \
348 stx %l0, [%g3 + TI_REG_WINDOW + 0x00]; \
349 stx %l1, [%g3 + TI_REG_WINDOW + 0x08]; \
350 stx %l2, [%g3 + TI_REG_WINDOW + 0x10]; \
351 stx %l3, [%g3 + TI_REG_WINDOW + 0x18]; \
352 stx %l4, [%g3 + TI_REG_WINDOW + 0x20]; \
353 stx %l5, [%g3 + TI_REG_WINDOW + 0x28]; \
354 stx %l6, [%g3 + TI_REG_WINDOW + 0x30]; \
355 stx %l7, [%g3 + TI_REG_WINDOW + 0x38]; \
356 stx %i0, [%g3 + TI_REG_WINDOW + 0x40]; \
357 stx %i1, [%g3 + TI_REG_WINDOW + 0x48]; \
358 stx %i2, [%g3 + TI_REG_WINDOW + 0x50]; \
359 stx %i3, [%g3 + TI_REG_WINDOW + 0x58]; \
360 stx %i4, [%g3 + TI_REG_WINDOW + 0x60]; \
361 stx %i5, [%g3 + TI_REG_WINDOW + 0x68]; \
362 stx %i6, [%g3 + TI_REG_WINDOW + 0x70]; \
363 stx %i7, [%g3 + TI_REG_WINDOW + 0x78]; \
364 add %g1, 1, %g1; \
365 stb %g1, [%g6 + TI_WSAVED]; \
366 saved; \
367 rdpr %cwp, %g1; \
368 sub %g1, 2, %g1; \
369 ba,pt %xcc, etrap_save; \
370 wrpr %g1, %cwp; \
371 nop; nop; nop
372
373/* Normal 32bit spill */
374#define SPILL_2_GENERIC(ASI) \
David S. Miller517ffce2012-10-26 15:18:37 -0700[diff] [blame]375 and %sp, 1, %g3; \
376 brnz,pn %g3, (. - (128 + 4)); \
377 srl %sp, 0, %sp; \
Sam Ravnborga00736e2008-06-19 20:26:19 +0200[diff] [blame]378 stwa %l0, [%sp + %g0] ASI; \
379 mov 0x04, %g3; \
380 stwa %l1, [%sp + %g3] ASI; \
381 add %sp, 0x08, %g1; \
382 stwa %l2, [%g1 + %g0] ASI; \
383 stwa %l3, [%g1 + %g3] ASI; \
384 add %g1, 0x08, %g1; \
385 stwa %l4, [%g1 + %g0] ASI; \
386 stwa %l5, [%g1 + %g3] ASI; \
387 add %g1, 0x08, %g1; \
388 stwa %l6, [%g1 + %g0] ASI; \
389 stwa %l7, [%g1 + %g3] ASI; \
390 add %g1, 0x08, %g1; \
391 stwa %i0, [%g1 + %g0] ASI; \
392 stwa %i1, [%g1 + %g3] ASI; \
393 add %g1, 0x08, %g1; \
394 stwa %i2, [%g1 + %g0] ASI; \
395 stwa %i3, [%g1 + %g3] ASI; \
396 add %g1, 0x08, %g1; \
397 stwa %i4, [%g1 + %g0] ASI; \
398 stwa %i5, [%g1 + %g3] ASI; \
399 add %g1, 0x08, %g1; \
400 stwa %i6, [%g1 + %g0] ASI; \
401 stwa %i7, [%g1 + %g3] ASI; \
402 saved; \
David S. Miller517ffce2012-10-26 15:18:37 -0700[diff] [blame]403 retry; \
Sam Ravnborga00736e2008-06-19 20:26:19 +0200[diff] [blame]404 b,a,pt %xcc, spill_fixup_dax; \
405 b,a,pt %xcc, spill_fixup_mna; \
406 b,a,pt %xcc, spill_fixup;
407
408#define SPILL_2_GENERIC_ETRAP \
409etrap_user_spill_32bit: \
David S. Miller517ffce2012-10-26 15:18:37 -0700[diff] [blame]410 and %sp, 1, %g3; \
411 brnz,pn %g3, etrap_user_spill_64bit; \
412 srl %sp, 0, %sp; \
Sam Ravnborga00736e2008-06-19 20:26:19 +0200[diff] [blame]413 stwa %l0, [%sp + 0x00] %asi; \
414 stwa %l1, [%sp + 0x04] %asi; \
415 stwa %l2, [%sp + 0x08] %asi; \
416 stwa %l3, [%sp + 0x0c] %asi; \
417 stwa %l4, [%sp + 0x10] %asi; \
418 stwa %l5, [%sp + 0x14] %asi; \
419 stwa %l6, [%sp + 0x18] %asi; \
420 stwa %l7, [%sp + 0x1c] %asi; \
421 stwa %i0, [%sp + 0x20] %asi; \
422 stwa %i1, [%sp + 0x24] %asi; \
423 stwa %i2, [%sp + 0x28] %asi; \
424 stwa %i3, [%sp + 0x2c] %asi; \
425 stwa %i4, [%sp + 0x30] %asi; \
426 stwa %i5, [%sp + 0x34] %asi; \
427 stwa %i6, [%sp + 0x38] %asi; \
428 stwa %i7, [%sp + 0x3c] %asi; \
429 saved; \
430 sub %g1, 2, %g1; \
431 ba,pt %xcc, etrap_save; \
432 wrpr %g1, %cwp; \
433 nop; nop; nop; nop; \
David S. Miller517ffce2012-10-26 15:18:37 -0700[diff] [blame]434 nop; nop; \
Sam Ravnborga00736e2008-06-19 20:26:19 +0200[diff] [blame]435 ba,a,pt %xcc, etrap_spill_fixup_32bit; \
436 ba,a,pt %xcc, etrap_spill_fixup_32bit; \
437 ba,a,pt %xcc, etrap_spill_fixup_32bit;
438
439#define SPILL_2_GENERIC_ETRAP_FIXUP \
440etrap_spill_fixup_32bit: \
441 ldub [%g6 + TI_WSAVED], %g1; \
442 sll %g1, 3, %g3; \
443 add %g6, %g3, %g3; \
444 stx %sp, [%g3 + TI_RWIN_SPTRS]; \
445 sll %g1, 7, %g3; \
446 add %g6, %g3, %g3; \
447 stw %l0, [%g3 + TI_REG_WINDOW + 0x00]; \
448 stw %l1, [%g3 + TI_REG_WINDOW + 0x04]; \
449 stw %l2, [%g3 + TI_REG_WINDOW + 0x08]; \
450 stw %l3, [%g3 + TI_REG_WINDOW + 0x0c]; \
451 stw %l4, [%g3 + TI_REG_WINDOW + 0x10]; \
452 stw %l5, [%g3 + TI_REG_WINDOW + 0x14]; \
453 stw %l6, [%g3 + TI_REG_WINDOW + 0x18]; \
454 stw %l7, [%g3 + TI_REG_WINDOW + 0x1c]; \
455 stw %i0, [%g3 + TI_REG_WINDOW + 0x20]; \
456 stw %i1, [%g3 + TI_REG_WINDOW + 0x24]; \
457 stw %i2, [%g3 + TI_REG_WINDOW + 0x28]; \
458 stw %i3, [%g3 + TI_REG_WINDOW + 0x2c]; \
459 stw %i4, [%g3 + TI_REG_WINDOW + 0x30]; \
460 stw %i5, [%g3 + TI_REG_WINDOW + 0x34]; \
461 stw %i6, [%g3 + TI_REG_WINDOW + 0x38]; \
462 stw %i7, [%g3 + TI_REG_WINDOW + 0x3c]; \
463 add %g1, 1, %g1; \
464 stb %g1, [%g6 + TI_WSAVED]; \
465 saved; \
466 rdpr %cwp, %g1; \
467 sub %g1, 2, %g1; \
468 ba,pt %xcc, etrap_save; \
469 wrpr %g1, %cwp; \
470 nop; nop; nop
471
472#define SPILL_1_NORMAL SPILL_1_GENERIC(ASI_AIUP)
473#define SPILL_2_NORMAL SPILL_2_GENERIC(ASI_AIUP)
474#define SPILL_3_NORMAL SPILL_0_NORMAL
475#define SPILL_4_NORMAL SPILL_0_NORMAL
476#define SPILL_5_NORMAL SPILL_0_NORMAL
477#define SPILL_6_NORMAL SPILL_0_NORMAL
478#define SPILL_7_NORMAL SPILL_0_NORMAL
479
480#define SPILL_0_OTHER SPILL_0_NORMAL
481#define SPILL_1_OTHER SPILL_1_GENERIC(ASI_AIUS)
482#define SPILL_2_OTHER SPILL_2_GENERIC(ASI_AIUS)
483#define SPILL_3_OTHER SPILL_3_NORMAL
484#define SPILL_4_OTHER SPILL_4_NORMAL
485#define SPILL_5_OTHER SPILL_5_NORMAL
486#define SPILL_6_OTHER SPILL_6_NORMAL
487#define SPILL_7_OTHER SPILL_7_NORMAL
488
489/* Normal kernel fill */
490#define FILL_0_NORMAL \
491 ldx [%sp + STACK_BIAS + 0x00], %l0; \
492 ldx [%sp + STACK_BIAS + 0x08], %l1; \
493 ldx [%sp + STACK_BIAS + 0x10], %l2; \
494 ldx [%sp + STACK_BIAS + 0x18], %l3; \
495 ldx [%sp + STACK_BIAS + 0x20], %l4; \
496 ldx [%sp + STACK_BIAS + 0x28], %l5; \
497 ldx [%sp + STACK_BIAS + 0x30], %l6; \
498 ldx [%sp + STACK_BIAS + 0x38], %l7; \
499 ldx [%sp + STACK_BIAS + 0x40], %i0; \
500 ldx [%sp + STACK_BIAS + 0x48], %i1; \
501 ldx [%sp + STACK_BIAS + 0x50], %i2; \
502 ldx [%sp + STACK_BIAS + 0x58], %i3; \
503 ldx [%sp + STACK_BIAS + 0x60], %i4; \
504 ldx [%sp + STACK_BIAS + 0x68], %i5; \
505 ldx [%sp + STACK_BIAS + 0x70], %i6; \
506 ldx [%sp + STACK_BIAS + 0x78], %i7; \
507 restored; retry; nop; nop; nop; nop; nop; nop; \
508 nop; nop; nop; nop; nop; nop; nop; nop;
509
510#define FILL_0_NORMAL_RTRAP \
511kern_rtt_fill: \
512 rdpr %cwp, %g1; \
513 sub %g1, 1, %g1; \
514 wrpr %g1, %cwp; \
515 ldx [%sp + STACK_BIAS + 0x00], %l0; \
516 ldx [%sp + STACK_BIAS + 0x08], %l1; \
517 ldx [%sp + STACK_BIAS + 0x10], %l2; \
518 ldx [%sp + STACK_BIAS + 0x18], %l3; \
519 ldx [%sp + STACK_BIAS + 0x20], %l4; \
520 ldx [%sp + STACK_BIAS + 0x28], %l5; \
521 ldx [%sp + STACK_BIAS + 0x30], %l6; \
522 ldx [%sp + STACK_BIAS + 0x38], %l7; \
523 ldx [%sp + STACK_BIAS + 0x40], %i0; \
524 ldx [%sp + STACK_BIAS + 0x48], %i1; \
525 ldx [%sp + STACK_BIAS + 0x50], %i2; \
526 ldx [%sp + STACK_BIAS + 0x58], %i3; \
527 ldx [%sp + STACK_BIAS + 0x60], %i4; \
528 ldx [%sp + STACK_BIAS + 0x68], %i5; \
529 ldx [%sp + STACK_BIAS + 0x70], %i6; \
530 ldx [%sp + STACK_BIAS + 0x78], %i7; \
531 restored; \
532 add %g1, 1, %g1; \
533 ba,pt %xcc, kern_rtt_restore; \
534 wrpr %g1, %cwp; \
535 nop; nop; nop; nop; nop; \
536 nop; nop; nop; nop;
537
538
539/* Normal 64bit fill */
540#define FILL_1_GENERIC(ASI) \
541 add %sp, STACK_BIAS + 0x00, %g1; \
542 ldxa [%g1 + %g0] ASI, %l0; \
543 mov 0x08, %g2; \
544 mov 0x10, %g3; \
545 ldxa [%g1 + %g2] ASI, %l1; \
546 mov 0x18, %g5; \
547 ldxa [%g1 + %g3] ASI, %l2; \
548 ldxa [%g1 + %g5] ASI, %l3; \
549 add %g1, 0x20, %g1; \
550 ldxa [%g1 + %g0] ASI, %l4; \
551 ldxa [%g1 + %g2] ASI, %l5; \
552 ldxa [%g1 + %g3] ASI, %l6; \
553 ldxa [%g1 + %g5] ASI, %l7; \
554 add %g1, 0x20, %g1; \
555 ldxa [%g1 + %g0] ASI, %i0; \
556 ldxa [%g1 + %g2] ASI, %i1; \
557 ldxa [%g1 + %g3] ASI, %i2; \
558 ldxa [%g1 + %g5] ASI, %i3; \
559 add %g1, 0x20, %g1; \
560 ldxa [%g1 + %g0] ASI, %i4; \
561 ldxa [%g1 + %g2] ASI, %i5; \
562 ldxa [%g1 + %g3] ASI, %i6; \
563 ldxa [%g1 + %g5] ASI, %i7; \
564 restored; \
565 retry; nop; nop; nop; nop; \
566 b,a,pt %xcc, fill_fixup_dax; \
567 b,a,pt %xcc, fill_fixup_mna; \
568 b,a,pt %xcc, fill_fixup;
569
570#define FILL_1_GENERIC_RTRAP \
571user_rtt_fill_64bit: \
572 ldxa [%sp + STACK_BIAS + 0x00] %asi, %l0; \
573 ldxa [%sp + STACK_BIAS + 0x08] %asi, %l1; \
574 ldxa [%sp + STACK_BIAS + 0x10] %asi, %l2; \
575 ldxa [%sp + STACK_BIAS + 0x18] %asi, %l3; \
576 ldxa [%sp + STACK_BIAS + 0x20] %asi, %l4; \
577 ldxa [%sp + STACK_BIAS + 0x28] %asi, %l5; \
578 ldxa [%sp + STACK_BIAS + 0x30] %asi, %l6; \
579 ldxa [%sp + STACK_BIAS + 0x38] %asi, %l7; \
580 ldxa [%sp + STACK_BIAS + 0x40] %asi, %i0; \
581 ldxa [%sp + STACK_BIAS + 0x48] %asi, %i1; \
582 ldxa [%sp + STACK_BIAS + 0x50] %asi, %i2; \
583 ldxa [%sp + STACK_BIAS + 0x58] %asi, %i3; \
584 ldxa [%sp + STACK_BIAS + 0x60] %asi, %i4; \
585 ldxa [%sp + STACK_BIAS + 0x68] %asi, %i5; \
586 ldxa [%sp + STACK_BIAS + 0x70] %asi, %i6; \
587 ldxa [%sp + STACK_BIAS + 0x78] %asi, %i7; \
588 ba,pt %xcc, user_rtt_pre_restore; \
589 restored; \
590 nop; nop; nop; nop; nop; nop; \
591 nop; nop; nop; nop; nop; \
592 ba,a,pt %xcc, user_rtt_fill_fixup; \
593 ba,a,pt %xcc, user_rtt_fill_fixup; \
594 ba,a,pt %xcc, user_rtt_fill_fixup;
595
596
597/* Normal 32bit fill */
598#define FILL_2_GENERIC(ASI) \
David S. Miller517ffce2012-10-26 15:18:37 -0700[diff] [blame]599 and %sp, 1, %g3; \
600 brnz,pn %g3, (. - (128 + 4)); \
601 srl %sp, 0, %sp; \
Sam Ravnborga00736e2008-06-19 20:26:19 +0200[diff] [blame]602 lduwa [%sp + %g0] ASI, %l0; \
603 mov 0x04, %g2; \
604 mov 0x08, %g3; \
605 lduwa [%sp + %g2] ASI, %l1; \
606 mov 0x0c, %g5; \
607 lduwa [%sp + %g3] ASI, %l2; \
608 lduwa [%sp + %g5] ASI, %l3; \
609 add %sp, 0x10, %g1; \
610 lduwa [%g1 + %g0] ASI, %l4; \
611 lduwa [%g1 + %g2] ASI, %l5; \
612 lduwa [%g1 + %g3] ASI, %l6; \
613 lduwa [%g1 + %g5] ASI, %l7; \
614 add %g1, 0x10, %g1; \
615 lduwa [%g1 + %g0] ASI, %i0; \
616 lduwa [%g1 + %g2] ASI, %i1; \
617 lduwa [%g1 + %g3] ASI, %i2; \
618 lduwa [%g1 + %g5] ASI, %i3; \
619 add %g1, 0x10, %g1; \
620 lduwa [%g1 + %g0] ASI, %i4; \
621 lduwa [%g1 + %g2] ASI, %i5; \
622 lduwa [%g1 + %g3] ASI, %i6; \
623 lduwa [%g1 + %g5] ASI, %i7; \
624 restored; \
David S. Miller517ffce2012-10-26 15:18:37 -0700[diff] [blame]625 retry; nop; nop; \
Sam Ravnborga00736e2008-06-19 20:26:19 +0200[diff] [blame]626 b,a,pt %xcc, fill_fixup_dax; \
627 b,a,pt %xcc, fill_fixup_mna; \
628 b,a,pt %xcc, fill_fixup;
629
630#define FILL_2_GENERIC_RTRAP \
631user_rtt_fill_32bit: \
David S. Miller517ffce2012-10-26 15:18:37 -0700[diff] [blame]632 and %sp, 1, %g3; \
633 brnz,pn %g3, user_rtt_fill_64bit; \
634 srl %sp, 0, %sp; \
Sam Ravnborga00736e2008-06-19 20:26:19 +0200[diff] [blame]635 lduwa [%sp + 0x00] %asi, %l0; \
636 lduwa [%sp + 0x04] %asi, %l1; \
637 lduwa [%sp + 0x08] %asi, %l2; \
638 lduwa [%sp + 0x0c] %asi, %l3; \
639 lduwa [%sp + 0x10] %asi, %l4; \
640 lduwa [%sp + 0x14] %asi, %l5; \
641 lduwa [%sp + 0x18] %asi, %l6; \
642 lduwa [%sp + 0x1c] %asi, %l7; \
643 lduwa [%sp + 0x20] %asi, %i0; \
644 lduwa [%sp + 0x24] %asi, %i1; \
645 lduwa [%sp + 0x28] %asi, %i2; \
646 lduwa [%sp + 0x2c] %asi, %i3; \
647 lduwa [%sp + 0x30] %asi, %i4; \
648 lduwa [%sp + 0x34] %asi, %i5; \
649 lduwa [%sp + 0x38] %asi, %i6; \
650 lduwa [%sp + 0x3c] %asi, %i7; \
651 ba,pt %xcc, user_rtt_pre_restore; \
652 restored; \
653 nop; nop; nop; nop; nop; \
David S. Miller517ffce2012-10-26 15:18:37 -0700[diff] [blame]654 nop; nop; nop; \
Sam Ravnborga00736e2008-06-19 20:26:19 +0200[diff] [blame]655 ba,a,pt %xcc, user_rtt_fill_fixup; \
656 ba,a,pt %xcc, user_rtt_fill_fixup; \
657 ba,a,pt %xcc, user_rtt_fill_fixup;
658
659
660#define FILL_1_NORMAL FILL_1_GENERIC(ASI_AIUP)
661#define FILL_2_NORMAL FILL_2_GENERIC(ASI_AIUP)
662#define FILL_3_NORMAL FILL_0_NORMAL
663#define FILL_4_NORMAL FILL_0_NORMAL
664#define FILL_5_NORMAL FILL_0_NORMAL
665#define FILL_6_NORMAL FILL_0_NORMAL
666#define FILL_7_NORMAL FILL_0_NORMAL
667
668#define FILL_0_OTHER FILL_0_NORMAL
669#define FILL_1_OTHER FILL_1_GENERIC(ASI_AIUS)
670#define FILL_2_OTHER FILL_2_GENERIC(ASI_AIUS)
671#define FILL_3_OTHER FILL_3_NORMAL
672#define FILL_4_OTHER FILL_4_NORMAL
673#define FILL_5_OTHER FILL_5_NORMAL
674#define FILL_6_OTHER FILL_6_NORMAL
675#define FILL_7_OTHER FILL_7_NORMAL
676
677#endif /* !(_SPARC64_TTABLE_H) */