blob: 9995842e45b5cb75fcc296bb668df3638ded8088 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * drivers/pci/setup-bus.c
3 *
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
7 * David Miller (davem@redhat.com)
8 *
9 * Support routines for initializing a PCI subsystem.
10 */
11
12/*
13 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
14 * PCI-PCI bridges cleanup, sorted resource allocation.
15 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
16 * Converted to allocation in 3 passes, which gives
17 * tighter packing. Prefetchable range support.
18 */
19
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/pci.h>
24#include <linux/errno.h>
25#include <linux/ioport.h>
26#include <linux/cache.h>
27#include <linux/slab.h>
Chris Wright6faf17f2009-08-28 13:00:06 -070028#include "pci.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
Yinghai Lu568ddef2010-01-22 01:02:21 -080030struct resource_list_x {
31 struct resource_list_x *next;
32 struct resource *res;
33 struct pci_dev *dev;
34 resource_size_t start;
35 resource_size_t end;
Ram Paic8adf9a2011-02-14 17:43:20 -080036 resource_size_t add_size;
Yinghai Lu568ddef2010-01-22 01:02:21 -080037 unsigned long flags;
38};
39
Ram Pai094732a2011-02-14 17:43:18 -080040#define free_list(type, head) do { \
41 struct type *list, *tmp; \
42 for (list = (head)->next; list;) { \
43 tmp = list; \
44 list = list->next; \
45 kfree(tmp); \
46 } \
47 (head)->next = NULL; \
48} while (0)
49
Ram Paif483d392011-07-07 11:19:10 -070050int pci_realloc_enable = 0;
51#define pci_realloc_enabled() pci_realloc_enable
52void pci_realloc(void)
53{
54 pci_realloc_enable = 1;
55}
56
Ram Paic8adf9a2011-02-14 17:43:20 -080057/**
58 * add_to_list() - add a new resource tracker to the list
59 * @head: Head of the list
60 * @dev: device corresponding to which the resource
61 * belongs
62 * @res: The resource to be tracked
63 * @add_size: additional size to be optionally added
64 * to the resource
65 */
66static void add_to_list(struct resource_list_x *head,
67 struct pci_dev *dev, struct resource *res,
68 resource_size_t add_size)
Yinghai Lu568ddef2010-01-22 01:02:21 -080069{
70 struct resource_list_x *list = head;
71 struct resource_list_x *ln = list->next;
72 struct resource_list_x *tmp;
73
74 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
75 if (!tmp) {
Ram Paic8adf9a2011-02-14 17:43:20 -080076 pr_warning("add_to_list: kmalloc() failed!\n");
Yinghai Lu568ddef2010-01-22 01:02:21 -080077 return;
78 }
79
80 tmp->next = ln;
81 tmp->res = res;
82 tmp->dev = dev;
83 tmp->start = res->start;
84 tmp->end = res->end;
85 tmp->flags = res->flags;
Ram Paic8adf9a2011-02-14 17:43:20 -080086 tmp->add_size = add_size;
Yinghai Lu568ddef2010-01-22 01:02:21 -080087 list->next = tmp;
88}
89
Ram Paic8adf9a2011-02-14 17:43:20 -080090static void add_to_failed_list(struct resource_list_x *head,
91 struct pci_dev *dev, struct resource *res)
92{
93 add_to_list(head, dev, res, 0);
94}
95
Yinghai Lu6841ec62010-01-22 01:02:25 -080096static void __dev_sort_resources(struct pci_dev *dev,
97 struct resource_list *head)
Linus Torvalds1da177e2005-04-16 15:20:36 -070098{
Yinghai Lu6841ec62010-01-22 01:02:25 -080099 u16 class = dev->class >> 8;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700100
Yinghai Lu6841ec62010-01-22 01:02:25 -0800101 /* Don't touch classless devices or host bridges or ioapics. */
102 if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
103 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700104
Yinghai Lu6841ec62010-01-22 01:02:25 -0800105 /* Don't touch ioapic devices already enabled by firmware */
106 if (class == PCI_CLASS_SYSTEM_PIC) {
107 u16 command;
108 pci_read_config_word(dev, PCI_COMMAND, &command);
109 if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
110 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700111 }
112
Yinghai Lu6841ec62010-01-22 01:02:25 -0800113 pdev_sort_resources(dev, head);
114}
115
Ram Paifc075e12011-02-14 17:43:19 -0800116static inline void reset_resource(struct resource *res)
117{
118 res->start = 0;
119 res->end = 0;
120 res->flags = 0;
121}
122
Ram Paic8adf9a2011-02-14 17:43:20 -0800123/**
124 * adjust_resources_sorted() - satisfy any additional resource requests
125 *
126 * @add_head : head of the list tracking requests requiring additional
127 * resources
128 * @head : head of the list tracking requests with allocated
129 * resources
130 *
131 * Walk through each element of the add_head and try to procure
132 * additional resources for the element, provided the element
133 * is in the head list.
134 */
135static void adjust_resources_sorted(struct resource_list_x *add_head,
136 struct resource_list *head)
137{
138 struct resource *res;
139 struct resource_list_x *list, *tmp, *prev;
140 struct resource_list *hlist;
141 resource_size_t add_size;
142 int idx;
143
144 prev = add_head;
145 for (list = add_head->next; list;) {
146 res = list->res;
147 /* skip resource that has been reset */
148 if (!res->flags)
149 goto out;
150
151 /* skip this resource if not found in head list */
152 for (hlist = head->next; hlist && hlist->res != res;
153 hlist = hlist->next);
154 if (!hlist) { /* just skip */
155 prev = list;
156 list = list->next;
157 continue;
158 }
159
160 idx = res - &list->dev->resource[0];
161 add_size=list->add_size;
162 if (!resource_size(res) && add_size) {
163 res->end = res->start + add_size - 1;
164 if(pci_assign_resource(list->dev, idx))
165 reset_resource(res);
166 } else if (add_size) {
167 adjust_resource(res, res->start,
168 resource_size(res) + add_size);
169 }
170out:
171 tmp = list;
172 prev->next = list = list->next;
173 kfree(tmp);
174 }
175}
176
177/**
178 * assign_requested_resources_sorted() - satisfy resource requests
179 *
180 * @head : head of the list tracking requests for resources
181 * @failed_list : head of the list tracking requests that could
182 * not be allocated
183 *
184 * Satisfy resource requests of each element in the list. Add
185 * requests that could not satisfied to the failed_list.
186 */
187static void assign_requested_resources_sorted(struct resource_list *head,
Yinghai Lu6841ec62010-01-22 01:02:25 -0800188 struct resource_list_x *fail_head)
189{
190 struct resource *res;
Ram Paic8adf9a2011-02-14 17:43:20 -0800191 struct resource_list *list;
Yinghai Lu6841ec62010-01-22 01:02:25 -0800192 int idx;
193
Ram Paic8adf9a2011-02-14 17:43:20 -0800194 for (list = head->next; list; list = list->next) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700195 res = list->res;
196 idx = res - &list->dev->resource[0];
Ram Paic8adf9a2011-02-14 17:43:20 -0800197 if (resource_size(res) && pci_assign_resource(list->dev, idx)) {
Yinghai Lu9a928662010-02-28 15:49:39 -0800198 if (fail_head && !pci_is_root_bus(list->dev->bus)) {
199 /*
200 * if the failed res is for ROM BAR, and it will
201 * be enabled later, don't add it to the list
202 */
203 if (!((idx == PCI_ROM_RESOURCE) &&
204 (!(res->flags & IORESOURCE_ROM_ENABLE))))
205 add_to_failed_list(fail_head, list->dev, res);
206 }
Ram Paifc075e12011-02-14 17:43:19 -0800207 reset_resource(res);
Rajesh Shah542df5d2005-04-28 00:25:50 -0700208 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700209 }
210}
211
Ram Paic8adf9a2011-02-14 17:43:20 -0800212static void __assign_resources_sorted(struct resource_list *head,
213 struct resource_list_x *add_head,
214 struct resource_list_x *fail_head)
215{
216 /* Satisfy the must-have resource requests */
217 assign_requested_resources_sorted(head, fail_head);
218
219 /* Try to satisfy any additional nice-to-have resource
220 requests */
221 if (add_head)
222 adjust_resources_sorted(add_head, head);
223 free_list(resource_list, head);
224}
225
Yinghai Lu6841ec62010-01-22 01:02:25 -0800226static void pdev_assign_resources_sorted(struct pci_dev *dev,
227 struct resource_list_x *fail_head)
228{
229 struct resource_list head;
230
231 head.next = NULL;
232 __dev_sort_resources(dev, &head);
Ram Paic8adf9a2011-02-14 17:43:20 -0800233 __assign_resources_sorted(&head, NULL, fail_head);
Yinghai Lu6841ec62010-01-22 01:02:25 -0800234
235}
236
237static void pbus_assign_resources_sorted(const struct pci_bus *bus,
Ram Paic8adf9a2011-02-14 17:43:20 -0800238 struct resource_list_x *add_head,
Yinghai Lu6841ec62010-01-22 01:02:25 -0800239 struct resource_list_x *fail_head)
240{
241 struct pci_dev *dev;
242 struct resource_list head;
243
244 head.next = NULL;
245 list_for_each_entry(dev, &bus->devices, bus_list)
246 __dev_sort_resources(dev, &head);
247
Ram Paic8adf9a2011-02-14 17:43:20 -0800248 __assign_resources_sorted(&head, add_head, fail_head);
Yinghai Lu6841ec62010-01-22 01:02:25 -0800249}
250
Dominik Brodowskib3743fa2005-09-09 13:03:23 -0700251void pci_setup_cardbus(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700252{
253 struct pci_dev *bridge = bus->self;
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600254 struct resource *res;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700255 struct pci_bus_region region;
256
Bjorn Helgaas865df572009-11-04 10:32:57 -0700257 dev_info(&bridge->dev, "CardBus bridge to [bus %02x-%02x]\n",
258 bus->secondary, bus->subordinate);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700259
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600260 res = bus->resource[0];
261 pcibios_resource_to_bus(bridge, &region, res);
262 if (res->flags & IORESOURCE_IO) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700263 /*
264 * The IO resource is allocated a range twice as large as it
265 * would normally need. This allows us to set both IO regs.
266 */
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600267 dev_info(&bridge->dev, " bridge window %pR\n", res);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700268 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
269 region.start);
270 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
271 region.end);
272 }
273
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600274 res = bus->resource[1];
275 pcibios_resource_to_bus(bridge, &region, res);
276 if (res->flags & IORESOURCE_IO) {
277 dev_info(&bridge->dev, " bridge window %pR\n", res);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700278 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
279 region.start);
280 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
281 region.end);
282 }
283
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600284 res = bus->resource[2];
285 pcibios_resource_to_bus(bridge, &region, res);
286 if (res->flags & IORESOURCE_MEM) {
287 dev_info(&bridge->dev, " bridge window %pR\n", res);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700288 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
289 region.start);
290 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
291 region.end);
292 }
293
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600294 res = bus->resource[3];
295 pcibios_resource_to_bus(bridge, &region, res);
296 if (res->flags & IORESOURCE_MEM) {
297 dev_info(&bridge->dev, " bridge window %pR\n", res);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700298 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
299 region.start);
300 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
301 region.end);
302 }
303}
Dominik Brodowskib3743fa2005-09-09 13:03:23 -0700304EXPORT_SYMBOL(pci_setup_cardbus);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700305
306/* Initialize bridges with base/limit values we have collected.
307 PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
308 requires that if there is no I/O ports or memory behind the
309 bridge, corresponding range must be turned off by writing base
310 value greater than limit to the bridge's base/limit registers.
311
312 Note: care must be taken when updating I/O base/limit registers
313 of bridges which support 32-bit I/O. This update requires two
314 config space writes, so it's quite possible that an I/O window of
315 the bridge will have some undesirable address (e.g. 0) after the
316 first write. Ditto 64-bit prefetchable MMIO. */
Yinghai Lu7cc59972009-12-22 15:02:21 -0800317static void pci_setup_bridge_io(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700318{
319 struct pci_dev *bridge = bus->self;
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600320 struct resource *res;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700321 struct pci_bus_region region;
Yinghai Lu7cc59972009-12-22 15:02:21 -0800322 u32 l, io_upper16;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700323
324 /* Set up the top and bottom of the PCI I/O segment for this bus. */
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600325 res = bus->resource[0];
326 pcibios_resource_to_bus(bridge, &region, res);
327 if (res->flags & IORESOURCE_IO) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700328 pci_read_config_dword(bridge, PCI_IO_BASE, &l);
329 l &= 0xffff0000;
330 l |= (region.start >> 8) & 0x00f0;
331 l |= region.end & 0xf000;
332 /* Set up upper 16 bits of I/O base/limit. */
333 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600334 dev_info(&bridge->dev, " bridge window %pR\n", res);
Yinghai Lu7cc59972009-12-22 15:02:21 -0800335 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700336 /* Clear upper 16 bits of I/O base/limit. */
337 io_upper16 = 0;
338 l = 0x00f0;
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600339 dev_info(&bridge->dev, " bridge window [io disabled]\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700340 }
341 /* Temporarily disable the I/O range before updating PCI_IO_BASE. */
342 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
343 /* Update lower 16 bits of I/O base/limit. */
344 pci_write_config_dword(bridge, PCI_IO_BASE, l);
345 /* Update upper 16 bits of I/O base/limit. */
346 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
Yinghai Lu7cc59972009-12-22 15:02:21 -0800347}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700348
Yinghai Lu7cc59972009-12-22 15:02:21 -0800349static void pci_setup_bridge_mmio(struct pci_bus *bus)
350{
351 struct pci_dev *bridge = bus->self;
352 struct resource *res;
353 struct pci_bus_region region;
354 u32 l;
355
356 /* Set up the top and bottom of the PCI Memory segment for this bus. */
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600357 res = bus->resource[1];
358 pcibios_resource_to_bus(bridge, &region, res);
359 if (res->flags & IORESOURCE_MEM) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700360 l = (region.start >> 16) & 0xfff0;
361 l |= region.end & 0xfff00000;
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600362 dev_info(&bridge->dev, " bridge window %pR\n", res);
Yinghai Lu7cc59972009-12-22 15:02:21 -0800363 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700364 l = 0x0000fff0;
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600365 dev_info(&bridge->dev, " bridge window [mem disabled]\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700366 }
367 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
Yinghai Lu7cc59972009-12-22 15:02:21 -0800368}
369
370static void pci_setup_bridge_mmio_pref(struct pci_bus *bus)
371{
372 struct pci_dev *bridge = bus->self;
373 struct resource *res;
374 struct pci_bus_region region;
375 u32 l, bu, lu;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700376
377 /* Clear out the upper 32 bits of PREF limit.
378 If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
379 disables PREF range, which is ok. */
380 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
381
382 /* Set up PREF base/limit. */
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +1100383 bu = lu = 0;
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600384 res = bus->resource[2];
385 pcibios_resource_to_bus(bridge, &region, res);
386 if (res->flags & IORESOURCE_PREFETCH) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700387 l = (region.start >> 16) & 0xfff0;
388 l |= region.end & 0xfff00000;
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600389 if (res->flags & IORESOURCE_MEM_64) {
Yinghai Lu1f82de12009-04-23 20:48:32 -0700390 bu = upper_32_bits(region.start);
391 lu = upper_32_bits(region.end);
Yinghai Lu1f82de12009-04-23 20:48:32 -0700392 }
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600393 dev_info(&bridge->dev, " bridge window %pR\n", res);
Yinghai Lu7cc59972009-12-22 15:02:21 -0800394 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700395 l = 0x0000fff0;
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600396 dev_info(&bridge->dev, " bridge window [mem pref disabled]\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700397 }
398 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
399
Alex Williamson59353ea2009-11-30 14:51:44 -0700400 /* Set the upper 32 bits of PREF base & limit. */
401 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
402 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
Yinghai Lu7cc59972009-12-22 15:02:21 -0800403}
404
405static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type)
406{
407 struct pci_dev *bridge = bus->self;
408
Yinghai Lu7cc59972009-12-22 15:02:21 -0800409 dev_info(&bridge->dev, "PCI bridge to [bus %02x-%02x]\n",
410 bus->secondary, bus->subordinate);
411
412 if (type & IORESOURCE_IO)
413 pci_setup_bridge_io(bus);
414
415 if (type & IORESOURCE_MEM)
416 pci_setup_bridge_mmio(bus);
417
418 if (type & IORESOURCE_PREFETCH)
419 pci_setup_bridge_mmio_pref(bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700420
421 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
422}
423
Yinghai Lu7cc59972009-12-22 15:02:21 -0800424static void pci_setup_bridge(struct pci_bus *bus)
425{
426 unsigned long type = IORESOURCE_IO | IORESOURCE_MEM |
427 IORESOURCE_PREFETCH;
428
429 __pci_setup_bridge(bus, type);
430}
431
Linus Torvalds1da177e2005-04-16 15:20:36 -0700432/* Check whether the bridge supports optional I/O and
433 prefetchable memory ranges. If not, the respective
434 base/limit registers must be read-only and read as 0. */
Sam Ravnborg96bde062007-03-26 21:53:30 -0800435static void pci_bridge_check_ranges(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700436{
437 u16 io;
438 u32 pmem;
439 struct pci_dev *bridge = bus->self;
440 struct resource *b_res;
441
442 b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
443 b_res[1].flags |= IORESOURCE_MEM;
444
445 pci_read_config_word(bridge, PCI_IO_BASE, &io);
446 if (!io) {
447 pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0);
448 pci_read_config_word(bridge, PCI_IO_BASE, &io);
449 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
450 }
451 if (io)
452 b_res[0].flags |= IORESOURCE_IO;
453 /* DECchip 21050 pass 2 errata: the bridge may miss an address
454 disconnect boundary by one PCI data phase.
455 Workaround: do not use prefetching on this device. */
456 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
457 return;
458 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
459 if (!pmem) {
460 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
461 0xfff0fff0);
462 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
463 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
464 }
Yinghai Lu1f82de12009-04-23 20:48:32 -0700465 if (pmem) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700466 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
Yinghai Lu99586102010-01-22 01:02:28 -0800467 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) ==
468 PCI_PREF_RANGE_TYPE_64) {
Yinghai Lu1f82de12009-04-23 20:48:32 -0700469 b_res[2].flags |= IORESOURCE_MEM_64;
Yinghai Lu99586102010-01-22 01:02:28 -0800470 b_res[2].flags |= PCI_PREF_RANGE_TYPE_64;
471 }
Yinghai Lu1f82de12009-04-23 20:48:32 -0700472 }
473
474 /* double check if bridge does support 64 bit pref */
475 if (b_res[2].flags & IORESOURCE_MEM_64) {
476 u32 mem_base_hi, tmp;
477 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32,
478 &mem_base_hi);
479 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
480 0xffffffff);
481 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
482 if (!tmp)
483 b_res[2].flags &= ~IORESOURCE_MEM_64;
484 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
485 mem_base_hi);
486 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700487}
488
489/* Helper function for sizing routines: find first available
490 bus resource of a given type. Note: we intentionally skip
491 the bus resources which have already been assigned (that is,
492 have non-NULL parent resource). */
Sam Ravnborg96bde062007-03-26 21:53:30 -0800493static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700494{
495 int i;
496 struct resource *r;
497 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
498 IORESOURCE_PREFETCH;
499
Bjorn Helgaas89a74ec2010-02-23 10:24:31 -0700500 pci_bus_for_each_resource(bus, r, i) {
Ivan Kokshaysky299de032005-06-15 18:59:27 +0400501 if (r == &ioport_resource || r == &iomem_resource)
502 continue;
Jesse Barnes55a10982009-10-27 09:39:18 -0700503 if (r && (r->flags & type_mask) == type && !r->parent)
504 return r;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700505 }
506 return NULL;
507}
508
Ram Pai13583b12011-02-14 17:43:17 -0800509static resource_size_t calculate_iosize(resource_size_t size,
510 resource_size_t min_size,
511 resource_size_t size1,
512 resource_size_t old_size,
513 resource_size_t align)
514{
515 if (size < min_size)
516 size = min_size;
517 if (old_size == 1 )
518 old_size = 0;
519 /* To be fixed in 2.5: we should have sort of HAVE_ISA
520 flag in the struct pci_bus. */
521#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
522 size = (size & 0xff) + ((size & ~0xffUL) << 2);
523#endif
524 size = ALIGN(size + size1, align);
525 if (size < old_size)
526 size = old_size;
527 return size;
528}
529
530static resource_size_t calculate_memsize(resource_size_t size,
531 resource_size_t min_size,
532 resource_size_t size1,
533 resource_size_t old_size,
534 resource_size_t align)
535{
536 if (size < min_size)
537 size = min_size;
538 if (old_size == 1 )
539 old_size = 0;
540 if (size < old_size)
541 size = old_size;
542 size = ALIGN(size + size1, align);
543 return size;
544}
545
Ram Paic8adf9a2011-02-14 17:43:20 -0800546/**
547 * pbus_size_io() - size the io window of a given bus
548 *
549 * @bus : the bus
550 * @min_size : the minimum io window that must to be allocated
551 * @add_size : additional optional io window
552 * @add_head : track the additional io window on this list
553 *
554 * Sizing the IO windows of the PCI-PCI bridge is trivial,
555 * since these windows have 4K granularity and the IO ranges
556 * of non-bridge PCI devices are limited to 256 bytes.
557 * We must be careful with the ISA aliasing though.
558 */
559static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
560 resource_size_t add_size, struct resource_list_x *add_head)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700561{
562 struct pci_dev *dev;
563 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO);
Ram Paic8adf9a2011-02-14 17:43:20 -0800564 unsigned long size = 0, size0 = 0, size1 = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700565
566 if (!b_res)
567 return;
568
569 list_for_each_entry(dev, &bus->devices, bus_list) {
570 int i;
571
572 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
573 struct resource *r = &dev->resource[i];
574 unsigned long r_size;
575
576 if (r->parent || !(r->flags & IORESOURCE_IO))
577 continue;
Zhao, Yu022edd82008-10-13 19:24:28 +0800578 r_size = resource_size(r);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700579
580 if (r_size < 0x400)
581 /* Might be re-aligned for ISA */
582 size += r_size;
583 else
584 size1 += r_size;
585 }
586 }
Ram Paic8adf9a2011-02-14 17:43:20 -0800587 size0 = calculate_iosize(size, min_size, size1,
Ram Pai13583b12011-02-14 17:43:17 -0800588 resource_size(b_res), 4096);
Yinghai Lu93d21752011-05-13 18:06:17 -0700589 size1 = (!add_head || (add_head && !add_size)) ? size0 :
Ram Paic8adf9a2011-02-14 17:43:20 -0800590 calculate_iosize(size, min_size+add_size, size1,
591 resource_size(b_res), 4096);
592 if (!size0 && !size1) {
Bjorn Helgaas865df572009-11-04 10:32:57 -0700593 if (b_res->start || b_res->end)
594 dev_info(&bus->self->dev, "disabling bridge window "
595 "%pR to [bus %02x-%02x] (unused)\n", b_res,
596 bus->secondary, bus->subordinate);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700597 b_res->flags = 0;
598 return;
599 }
600 /* Alignment of the IO window is always 4K */
601 b_res->start = 4096;
Ram Paic8adf9a2011-02-14 17:43:20 -0800602 b_res->end = b_res->start + size0 - 1;
Ivan Kokshaysky88452562008-03-30 19:50:14 +0400603 b_res->flags |= IORESOURCE_STARTALIGN;
Ram Paic8adf9a2011-02-14 17:43:20 -0800604 if (size1 > size0 && add_head)
605 add_to_list(add_head, bus->self, b_res, size1-size0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700606}
607
Ram Paic8adf9a2011-02-14 17:43:20 -0800608/**
609 * pbus_size_mem() - size the memory window of a given bus
610 *
611 * @bus : the bus
612 * @min_size : the minimum memory window that must to be allocated
613 * @add_size : additional optional memory window
614 * @add_head : track the additional memory window on this list
615 *
616 * Calculate the size of the bus and minimal alignment which
617 * guarantees that all child resources fit in this size.
618 */
Eric W. Biederman28760482009-09-09 14:09:24 -0700619static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
Ram Paic8adf9a2011-02-14 17:43:20 -0800620 unsigned long type, resource_size_t min_size,
621 resource_size_t add_size,
622 struct resource_list_x *add_head)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700623{
624 struct pci_dev *dev;
Ram Paic8adf9a2011-02-14 17:43:20 -0800625 resource_size_t min_align, align, size, size0, size1;
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +1100626 resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700627 int order, max_order;
628 struct resource *b_res = find_free_bus_resource(bus, type);
Yinghai Lu1f82de12009-04-23 20:48:32 -0700629 unsigned int mem64_mask = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700630
631 if (!b_res)
632 return 0;
633
634 memset(aligns, 0, sizeof(aligns));
635 max_order = 0;
636 size = 0;
637
Yinghai Lu1f82de12009-04-23 20:48:32 -0700638 mem64_mask = b_res->flags & IORESOURCE_MEM_64;
639 b_res->flags &= ~IORESOURCE_MEM_64;
640
Linus Torvalds1da177e2005-04-16 15:20:36 -0700641 list_for_each_entry(dev, &bus->devices, bus_list) {
642 int i;
Yinghai Lu1f82de12009-04-23 20:48:32 -0700643
Linus Torvalds1da177e2005-04-16 15:20:36 -0700644 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
645 struct resource *r = &dev->resource[i];
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +1100646 resource_size_t r_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700647
648 if (r->parent || (r->flags & mask) != type)
649 continue;
Zhao, Yu022edd82008-10-13 19:24:28 +0800650 r_size = resource_size(r);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700651 /* For bridges size != alignment */
Chris Wright6faf17f2009-08-28 13:00:06 -0700652 align = pci_resource_alignment(dev, r);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700653 order = __ffs(align) - 20;
654 if (order > 11) {
Bjorn Helgaas865df572009-11-04 10:32:57 -0700655 dev_warn(&dev->dev, "disabling BAR %d: %pR "
656 "(bad alignment %#llx)\n", i, r,
657 (unsigned long long) align);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700658 r->flags = 0;
659 continue;
660 }
661 size += r_size;
662 if (order < 0)
663 order = 0;
664 /* Exclude ranges with size > align from
665 calculation of the alignment. */
666 if (r_size == align)
667 aligns[order] += align;
668 if (order > max_order)
669 max_order = order;
Yinghai Lu1f82de12009-04-23 20:48:32 -0700670 mem64_mask &= r->flags & IORESOURCE_MEM_64;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700671 }
672 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700673 align = 0;
674 min_align = 0;
675 for (order = 0; order <= max_order; order++) {
Jeremy Fitzhardinge8308c542008-09-11 01:31:50 -0700676 resource_size_t align1 = 1;
677
678 align1 <<= (order + 20);
679
Linus Torvalds1da177e2005-04-16 15:20:36 -0700680 if (!align)
681 min_align = align1;
Milind Arun Choudhary6f6f8c22007-07-09 11:55:51 -0700682 else if (ALIGN(align + min_align, min_align) < align1)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700683 min_align = align1 >> 1;
684 align += aligns[order];
685 }
Linus Torvaldsb42282e2011-04-11 10:53:11 -0700686 size0 = calculate_memsize(size, min_size, 0, resource_size(b_res), min_align);
Yinghai Lu93d21752011-05-13 18:06:17 -0700687 size1 = (!add_head || (add_head && !add_size)) ? size0 :
Ram Paic8adf9a2011-02-14 17:43:20 -0800688 calculate_memsize(size, min_size+add_size, 0,
Linus Torvaldsb42282e2011-04-11 10:53:11 -0700689 resource_size(b_res), min_align);
Ram Paic8adf9a2011-02-14 17:43:20 -0800690 if (!size0 && !size1) {
Bjorn Helgaas865df572009-11-04 10:32:57 -0700691 if (b_res->start || b_res->end)
692 dev_info(&bus->self->dev, "disabling bridge window "
693 "%pR to [bus %02x-%02x] (unused)\n", b_res,
694 bus->secondary, bus->subordinate);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700695 b_res->flags = 0;
696 return 1;
697 }
698 b_res->start = min_align;
Ram Paic8adf9a2011-02-14 17:43:20 -0800699 b_res->end = size0 + min_align - 1;
700 b_res->flags |= IORESOURCE_STARTALIGN | mem64_mask;
701 if (size1 > size0 && add_head)
702 add_to_list(add_head, bus->self, b_res, size1-size0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700703 return 1;
704}
705
Adrian Bunk5468ae62008-04-18 13:53:56 -0700706static void pci_bus_size_cardbus(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700707{
708 struct pci_dev *bridge = bus->self;
709 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
710 u16 ctrl;
711
712 /*
713 * Reserve some resources for CardBus. We reserve
714 * a fixed amount of bus space for CardBus bridges.
715 */
Linus Torvalds934b7022008-04-22 18:16:30 -0700716 b_res[0].start = 0;
717 b_res[0].end = pci_cardbus_io_size - 1;
718 b_res[0].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700719
Linus Torvalds934b7022008-04-22 18:16:30 -0700720 b_res[1].start = 0;
721 b_res[1].end = pci_cardbus_io_size - 1;
722 b_res[1].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700723
724 /*
725 * Check whether prefetchable memory is supported
726 * by this bridge.
727 */
728 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
729 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
730 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
731 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
732 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
733 }
734
735 /*
736 * If we have prefetchable memory support, allocate
737 * two regions. Otherwise, allocate one region of
738 * twice the size.
739 */
740 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
Linus Torvalds934b7022008-04-22 18:16:30 -0700741 b_res[2].start = 0;
742 b_res[2].end = pci_cardbus_mem_size - 1;
743 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_SIZEALIGN;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700744
Linus Torvalds934b7022008-04-22 18:16:30 -0700745 b_res[3].start = 0;
746 b_res[3].end = pci_cardbus_mem_size - 1;
747 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700748 } else {
Linus Torvalds934b7022008-04-22 18:16:30 -0700749 b_res[3].start = 0;
750 b_res[3].end = pci_cardbus_mem_size * 2 - 1;
751 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700752 }
753}
754
Ram Paic8adf9a2011-02-14 17:43:20 -0800755void __ref __pci_bus_size_bridges(struct pci_bus *bus,
756 struct resource_list_x *add_head)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700757{
758 struct pci_dev *dev;
759 unsigned long mask, prefmask;
Ram Paic8adf9a2011-02-14 17:43:20 -0800760 resource_size_t additional_mem_size = 0, additional_io_size = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700761
762 list_for_each_entry(dev, &bus->devices, bus_list) {
763 struct pci_bus *b = dev->subordinate;
764 if (!b)
765 continue;
766
767 switch (dev->class >> 8) {
768 case PCI_CLASS_BRIDGE_CARDBUS:
769 pci_bus_size_cardbus(b);
770 break;
771
772 case PCI_CLASS_BRIDGE_PCI:
773 default:
Ram Paic8adf9a2011-02-14 17:43:20 -0800774 __pci_bus_size_bridges(b, add_head);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700775 break;
776 }
777 }
778
779 /* The root bus? */
780 if (!bus->self)
781 return;
782
783 switch (bus->self->class >> 8) {
784 case PCI_CLASS_BRIDGE_CARDBUS:
785 /* don't size cardbuses yet. */
786 break;
787
788 case PCI_CLASS_BRIDGE_PCI:
789 pci_bridge_check_ranges(bus);
Eric W. Biederman28760482009-09-09 14:09:24 -0700790 if (bus->self->is_hotplug_bridge) {
Ram Paic8adf9a2011-02-14 17:43:20 -0800791 additional_io_size = pci_hotplug_io_size;
792 additional_mem_size = pci_hotplug_mem_size;
Eric W. Biederman28760482009-09-09 14:09:24 -0700793 }
Ram Paic8adf9a2011-02-14 17:43:20 -0800794 /*
795 * Follow thru
796 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700797 default:
Ram Paic8adf9a2011-02-14 17:43:20 -0800798 pbus_size_io(bus, 0, additional_io_size, add_head);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700799 /* If the bridge supports prefetchable range, size it
800 separately. If it doesn't, or its prefetchable window
801 has already been allocated by arch code, try
802 non-prefetchable range for both types of PCI memory
803 resources. */
804 mask = IORESOURCE_MEM;
805 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
Ram Paic8adf9a2011-02-14 17:43:20 -0800806 if (pbus_size_mem(bus, prefmask, prefmask, 0, additional_mem_size, add_head))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700807 mask = prefmask; /* Success, size non-prefetch only. */
Eric W. Biederman28760482009-09-09 14:09:24 -0700808 else
Ram Paic8adf9a2011-02-14 17:43:20 -0800809 additional_mem_size += additional_mem_size;
810 pbus_size_mem(bus, mask, IORESOURCE_MEM, 0, additional_mem_size, add_head);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700811 break;
812 }
813}
Ram Paic8adf9a2011-02-14 17:43:20 -0800814
815void __ref pci_bus_size_bridges(struct pci_bus *bus)
816{
817 __pci_bus_size_bridges(bus, NULL);
818}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700819EXPORT_SYMBOL(pci_bus_size_bridges);
820
Yinghai Lu568ddef2010-01-22 01:02:21 -0800821static void __ref __pci_bus_assign_resources(const struct pci_bus *bus,
Ram Paic8adf9a2011-02-14 17:43:20 -0800822 struct resource_list_x *add_head,
Yinghai Lu568ddef2010-01-22 01:02:21 -0800823 struct resource_list_x *fail_head)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700824{
825 struct pci_bus *b;
826 struct pci_dev *dev;
827
Ram Paic8adf9a2011-02-14 17:43:20 -0800828 pbus_assign_resources_sorted(bus, add_head, fail_head);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700829
Linus Torvalds1da177e2005-04-16 15:20:36 -0700830 list_for_each_entry(dev, &bus->devices, bus_list) {
831 b = dev->subordinate;
832 if (!b)
833 continue;
834
Ram Paic8adf9a2011-02-14 17:43:20 -0800835 __pci_bus_assign_resources(b, add_head, fail_head);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700836
837 switch (dev->class >> 8) {
838 case PCI_CLASS_BRIDGE_PCI:
Yinghai Lu6841ec62010-01-22 01:02:25 -0800839 if (!pci_is_enabled(dev))
840 pci_setup_bridge(b);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700841 break;
842
843 case PCI_CLASS_BRIDGE_CARDBUS:
844 pci_setup_cardbus(b);
845 break;
846
847 default:
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600848 dev_info(&dev->dev, "not setting up bridge for bus "
849 "%04x:%02x\n", pci_domain_nr(b), b->number);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700850 break;
851 }
852 }
853}
Yinghai Lu568ddef2010-01-22 01:02:21 -0800854
855void __ref pci_bus_assign_resources(const struct pci_bus *bus)
856{
Ram Paic8adf9a2011-02-14 17:43:20 -0800857 __pci_bus_assign_resources(bus, NULL, NULL);
Yinghai Lu568ddef2010-01-22 01:02:21 -0800858}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700859EXPORT_SYMBOL(pci_bus_assign_resources);
860
Yinghai Lu6841ec62010-01-22 01:02:25 -0800861static void __ref __pci_bridge_assign_resources(const struct pci_dev *bridge,
862 struct resource_list_x *fail_head)
863{
864 struct pci_bus *b;
865
866 pdev_assign_resources_sorted((struct pci_dev *)bridge, fail_head);
867
868 b = bridge->subordinate;
869 if (!b)
870 return;
871
Ram Paic8adf9a2011-02-14 17:43:20 -0800872 __pci_bus_assign_resources(b, NULL, fail_head);
Yinghai Lu6841ec62010-01-22 01:02:25 -0800873
874 switch (bridge->class >> 8) {
875 case PCI_CLASS_BRIDGE_PCI:
876 pci_setup_bridge(b);
877 break;
878
879 case PCI_CLASS_BRIDGE_CARDBUS:
880 pci_setup_cardbus(b);
881 break;
882
883 default:
884 dev_info(&bridge->dev, "not setting up bridge for bus "
885 "%04x:%02x\n", pci_domain_nr(b), b->number);
886 break;
887 }
888}
Yinghai Lu5009b462010-01-22 01:02:20 -0800889static void pci_bridge_release_resources(struct pci_bus *bus,
890 unsigned long type)
891{
892 int idx;
893 bool changed = false;
894 struct pci_dev *dev;
895 struct resource *r;
896 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
897 IORESOURCE_PREFETCH;
898
899 dev = bus->self;
900 for (idx = PCI_BRIDGE_RESOURCES; idx <= PCI_BRIDGE_RESOURCE_END;
901 idx++) {
902 r = &dev->resource[idx];
903 if ((r->flags & type_mask) != type)
904 continue;
905 if (!r->parent)
906 continue;
907 /*
908 * if there are children under that, we should release them
909 * all
910 */
911 release_child_resources(r);
912 if (!release_resource(r)) {
913 dev_printk(KERN_DEBUG, &dev->dev,
914 "resource %d %pR released\n", idx, r);
915 /* keep the old size */
916 r->end = resource_size(r) - 1;
917 r->start = 0;
918 r->flags = 0;
919 changed = true;
920 }
921 }
922
923 if (changed) {
924 /* avoiding touch the one without PREF */
925 if (type & IORESOURCE_PREFETCH)
926 type = IORESOURCE_PREFETCH;
927 __pci_setup_bridge(bus, type);
928 }
929}
930
931enum release_type {
932 leaf_only,
933 whole_subtree,
934};
935/*
936 * try to release pci bridge resources that is from leaf bridge,
937 * so we can allocate big new one later
938 */
939static void __ref pci_bus_release_bridge_resources(struct pci_bus *bus,
940 unsigned long type,
941 enum release_type rel_type)
942{
943 struct pci_dev *dev;
944 bool is_leaf_bridge = true;
945
946 list_for_each_entry(dev, &bus->devices, bus_list) {
947 struct pci_bus *b = dev->subordinate;
948 if (!b)
949 continue;
950
951 is_leaf_bridge = false;
952
953 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
954 continue;
955
956 if (rel_type == whole_subtree)
957 pci_bus_release_bridge_resources(b, type,
958 whole_subtree);
959 }
960
961 if (pci_is_root_bus(bus))
962 return;
963
964 if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI)
965 return;
966
967 if ((rel_type == whole_subtree) || is_leaf_bridge)
968 pci_bridge_release_resources(bus, type);
969}
970
Yinghai Lu76fbc262008-06-23 20:33:06 +0200971static void pci_bus_dump_res(struct pci_bus *bus)
972{
Bjorn Helgaas89a74ec2010-02-23 10:24:31 -0700973 struct resource *res;
974 int i;
Yinghai Lu76fbc262008-06-23 20:33:06 +0200975
Bjorn Helgaas89a74ec2010-02-23 10:24:31 -0700976 pci_bus_for_each_resource(bus, res, i) {
Yinghai Lu7c9342b2009-12-22 15:02:24 -0800977 if (!res || !res->end || !res->flags)
Yinghai Lu76fbc262008-06-23 20:33:06 +0200978 continue;
979
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -0600980 dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res);
Yinghai Lu76fbc262008-06-23 20:33:06 +0200981 }
982}
983
984static void pci_bus_dump_resources(struct pci_bus *bus)
985{
986 struct pci_bus *b;
987 struct pci_dev *dev;
988
989
990 pci_bus_dump_res(bus);
991
992 list_for_each_entry(dev, &bus->devices, bus_list) {
993 b = dev->subordinate;
994 if (!b)
995 continue;
996
997 pci_bus_dump_resources(b);
998 }
999}
1000
Yinghai Luda7822e2011-05-12 17:11:37 -07001001static int __init pci_bus_get_depth(struct pci_bus *bus)
1002{
1003 int depth = 0;
1004 struct pci_dev *dev;
1005
1006 list_for_each_entry(dev, &bus->devices, bus_list) {
1007 int ret;
1008 struct pci_bus *b = dev->subordinate;
1009 if (!b)
1010 continue;
1011
1012 ret = pci_bus_get_depth(b);
1013 if (ret + 1 > depth)
1014 depth = ret + 1;
1015 }
1016
1017 return depth;
1018}
1019static int __init pci_get_max_depth(void)
1020{
1021 int depth = 0;
1022 struct pci_bus *bus;
1023
1024 list_for_each_entry(bus, &pci_root_buses, node) {
1025 int ret;
1026
1027 ret = pci_bus_get_depth(bus);
1028 if (ret > depth)
1029 depth = ret;
1030 }
1031
1032 return depth;
1033}
1034
Ram Paif483d392011-07-07 11:19:10 -07001035
Yinghai Luda7822e2011-05-12 17:11:37 -07001036/*
1037 * first try will not touch pci bridge res
1038 * second and later try will clear small leaf bridge res
1039 * will stop till to the max deepth if can not find good one
1040 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001041void __init
1042pci_assign_unassigned_resources(void)
1043{
1044 struct pci_bus *bus;
Ram Paic8adf9a2011-02-14 17:43:20 -08001045 struct resource_list_x add_list; /* list of resources that
1046 want additional resources */
Yinghai Luda7822e2011-05-12 17:11:37 -07001047 int tried_times = 0;
1048 enum release_type rel_type = leaf_only;
1049 struct resource_list_x head, *list;
1050 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1051 IORESOURCE_PREFETCH;
1052 unsigned long failed_type;
1053 int max_depth = pci_get_max_depth();
1054 int pci_try_num;
1055
1056
1057 head.next = NULL;
Ram Paic8adf9a2011-02-14 17:43:20 -08001058 add_list.next = NULL;
Yinghai Luda7822e2011-05-12 17:11:37 -07001059
1060 pci_try_num = max_depth + 1;
1061 printk(KERN_DEBUG "PCI: max bus depth: %d pci_try_num: %d\n",
1062 max_depth, pci_try_num);
1063
1064again:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001065 /* Depth first, calculate sizes and alignments of all
1066 subordinate buses. */
Yinghai Luda7822e2011-05-12 17:11:37 -07001067 list_for_each_entry(bus, &pci_root_buses, node)
Ram Paic8adf9a2011-02-14 17:43:20 -08001068 __pci_bus_size_bridges(bus, &add_list);
Ram Paic8adf9a2011-02-14 17:43:20 -08001069
Linus Torvalds1da177e2005-04-16 15:20:36 -07001070 /* Depth last, allocate resources and update the hardware. */
Yinghai Luda7822e2011-05-12 17:11:37 -07001071 list_for_each_entry(bus, &pci_root_buses, node)
1072 __pci_bus_assign_resources(bus, &add_list, &head);
Ram Paic8adf9a2011-02-14 17:43:20 -08001073 BUG_ON(add_list.next);
Yinghai Luda7822e2011-05-12 17:11:37 -07001074 tried_times++;
1075
1076 /* any device complain? */
1077 if (!head.next)
1078 goto enable_and_dump;
Ram Paif483d392011-07-07 11:19:10 -07001079
1080 /* don't realloc if asked to do so */
1081 if (!pci_realloc_enabled()) {
1082 free_list(resource_list_x, &head);
1083 goto enable_and_dump;
1084 }
1085
Yinghai Luda7822e2011-05-12 17:11:37 -07001086 failed_type = 0;
1087 for (list = head.next; list;) {
1088 failed_type |= list->flags;
1089 list = list->next;
1090 }
1091 /*
1092 * io port are tight, don't try extra
1093 * or if reach the limit, don't want to try more
1094 */
1095 failed_type &= type_mask;
1096 if ((failed_type == IORESOURCE_IO) || (tried_times >= pci_try_num)) {
1097 free_list(resource_list_x, &head);
1098 goto enable_and_dump;
1099 }
1100
1101 printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
1102 tried_times + 1);
1103
1104 /* third times and later will not check if it is leaf */
1105 if ((tried_times + 1) > 2)
1106 rel_type = whole_subtree;
1107
1108 /*
1109 * Try to release leaf bridge's resources that doesn't fit resource of
1110 * child device under that bridge
1111 */
1112 for (list = head.next; list;) {
1113 bus = list->dev->bus;
1114 pci_bus_release_bridge_resources(bus, list->flags & type_mask,
1115 rel_type);
1116 list = list->next;
1117 }
1118 /* restore size and flags */
1119 for (list = head.next; list;) {
1120 struct resource *res = list->res;
1121
1122 res->start = list->start;
1123 res->end = list->end;
1124 res->flags = list->flags;
1125 if (list->dev->subordinate)
1126 res->flags = 0;
1127
1128 list = list->next;
1129 }
1130 free_list(resource_list_x, &head);
1131
1132 goto again;
1133
1134enable_and_dump:
1135 /* Depth last, update the hardware. */
1136 list_for_each_entry(bus, &pci_root_buses, node)
1137 pci_enable_bridges(bus);
Yinghai Lu76fbc262008-06-23 20:33:06 +02001138
1139 /* dump the resource on buses */
Yinghai Luda7822e2011-05-12 17:11:37 -07001140 list_for_each_entry(bus, &pci_root_buses, node)
Yinghai Lu76fbc262008-06-23 20:33:06 +02001141 pci_bus_dump_resources(bus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001142}
Yinghai Lu6841ec62010-01-22 01:02:25 -08001143
1144void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
1145{
1146 struct pci_bus *parent = bridge->subordinate;
Yinghai Lu32180e42010-01-22 01:02:27 -08001147 int tried_times = 0;
1148 struct resource_list_x head, *list;
Yinghai Lu6841ec62010-01-22 01:02:25 -08001149 int retval;
Yinghai Lu32180e42010-01-22 01:02:27 -08001150 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1151 IORESOURCE_PREFETCH;
Yinghai Lu6841ec62010-01-22 01:02:25 -08001152
Yinghai Lu32180e42010-01-22 01:02:27 -08001153 head.next = NULL;
1154
1155again:
Yinghai Lu6841ec62010-01-22 01:02:25 -08001156 pci_bus_size_bridges(parent);
Yinghai Lu32180e42010-01-22 01:02:27 -08001157 __pci_bridge_assign_resources(bridge, &head);
Yinghai Lu32180e42010-01-22 01:02:27 -08001158
1159 tried_times++;
1160
1161 if (!head.next)
Yinghai Lu3f579c32010-05-21 14:35:06 -07001162 goto enable_all;
Yinghai Lu32180e42010-01-22 01:02:27 -08001163
1164 if (tried_times >= 2) {
1165 /* still fail, don't need to try more */
Ram Pai094732a2011-02-14 17:43:18 -08001166 free_list(resource_list_x, &head);
Yinghai Lu3f579c32010-05-21 14:35:06 -07001167 goto enable_all;
Yinghai Lu32180e42010-01-22 01:02:27 -08001168 }
1169
1170 printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
1171 tried_times + 1);
1172
1173 /*
1174 * Try to release leaf bridge's resources that doesn't fit resource of
1175 * child device under that bridge
1176 */
1177 for (list = head.next; list;) {
1178 struct pci_bus *bus = list->dev->bus;
1179 unsigned long flags = list->flags;
1180
1181 pci_bus_release_bridge_resources(bus, flags & type_mask,
1182 whole_subtree);
1183 list = list->next;
1184 }
1185 /* restore size and flags */
1186 for (list = head.next; list;) {
1187 struct resource *res = list->res;
1188
1189 res->start = list->start;
1190 res->end = list->end;
1191 res->flags = list->flags;
1192 if (list->dev->subordinate)
1193 res->flags = 0;
1194
1195 list = list->next;
1196 }
Ram Pai094732a2011-02-14 17:43:18 -08001197 free_list(resource_list_x, &head);
Yinghai Lu32180e42010-01-22 01:02:27 -08001198
1199 goto again;
Yinghai Lu3f579c32010-05-21 14:35:06 -07001200
1201enable_all:
1202 retval = pci_reenable_device(bridge);
1203 pci_set_master(bridge);
1204 pci_enable_bridges(parent);
Yinghai Lu6841ec62010-01-22 01:02:25 -08001205}
1206EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);