Gregory CLEMENT | c6d591c | 2016-07-19 15:42:21 +0200 | [diff] [blame] | 1 | * Peripheral Clock bindings for Marvell Armada 37xx SoCs |
| 2 | |
| 3 | Marvell Armada 37xx SoCs provide peripheral clocks which are |
| 4 | used as clock source for the peripheral of the SoC. |
| 5 | |
| 6 | There are two different blocks associated to north bridge and south |
| 7 | bridge. |
| 8 | |
| 9 | The peripheral clock consumer should specify the desired clock by |
| 10 | having the clock ID in its "clocks" phandle cell. |
| 11 | |
| 12 | The following is a list of provided IDs for Armada 370 North bridge clocks: |
| 13 | ID Clock name Description |
| 14 | ----------------------------------- |
| 15 | 0 mmc MMC controller |
| 16 | 1 sata_host Sata Host |
| 17 | 2 sec_at Security AT |
| 18 | 3 sac_dap Security DAP |
| 19 | 4 tsecm Security Engine |
| 20 | 5 setm_tmx Serial Embedded Trace Module |
| 21 | 6 avs Adaptive Voltage Scaling |
| 22 | 7 sqf SPI |
| 23 | 8 pwm PWM |
| 24 | 9 i2c_2 I2C 2 |
| 25 | 10 i2c_1 I2C 1 |
| 26 | 11 ddr_phy DDR PHY |
| 27 | 12 ddr_fclk DDR F clock |
| 28 | 13 trace Trace |
| 29 | 14 counter Counter |
| 30 | 15 eip97 EIP 97 |
| 31 | 16 cpu CPU |
| 32 | |
| 33 | The following is a list of provided IDs for Armada 370 South bridge clocks: |
| 34 | ID Clock name Description |
| 35 | ----------------------------------- |
| 36 | 0 gbe-50 50 MHz parent clock for Gigabit Ethernet |
| 37 | 1 gbe-core parent clock for Gigabit Ethernet core |
| 38 | 2 gbe-125 125 MHz parent clock for Gigabit Ethernet |
| 39 | 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1 |
| 40 | 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0 |
| 41 | 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1 |
| 42 | 6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0 |
| 43 | 7 gbe1-core Gigabit Ethernet core port 1 |
| 44 | 8 gbe0-core Gigabit Ethernet core port 0 |
| 45 | 9 gbe-bm Gigabit Ethernet Buffer Manager |
| 46 | 10 sdio SDIO |
| 47 | 11 usb32-sub2-sys USB 2 clock |
| 48 | 12 usb32-ss-sys USB 3 clock |
| 49 | |
| 50 | Required properties: |
| 51 | |
| 52 | - compatible : shall be "marvell,armada-3700-periph-clock-nb" for the |
| 53 | north bridge block, or |
| 54 | "marvell,armada-3700-periph-clock-sb" for the south bridge block |
| 55 | - reg : must be the register address of North/South Bridge Clock register |
| 56 | - #clock-cells : from common clock binding; shall be set to 1 |
| 57 | |
| 58 | - clocks : list of the parent clock phandle in the following order: |
| 59 | TBG-A P, TBG-B P, TBG-A S, TBG-B S and finally the xtal clock. |
| 60 | |
| 61 | |
| 62 | Example: |
| 63 | |
| 64 | nb_perih_clk: nb-periph-clk@13000{ |
| 65 | compatible = "marvell,armada-3700-periph-clock-nb"; |
| 66 | reg = <0x13000 0x1000>; |
| 67 | clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, |
| 68 | <&tbg 3>, <&xtalclk>; |
| 69 | #clock-cells = <1>; |
| 70 | }; |