Laurent Pinchart | abe844a | 2013-10-17 23:54:07 +0200 | [diff] [blame] | 1 | * Renesas CPG DIV6 Clock |
| 2 | |
| 3 | The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse |
Geert Uytterhoeven | 7a29f3f | 2015-09-09 14:57:11 +0200 | [diff] [blame] | 4 | Generator (CPG). Their clock input is divided by a configurable factor from 1 |
Laurent Pinchart | abe844a | 2013-10-17 23:54:07 +0200 | [diff] [blame] | 5 | to 64. |
| 6 | |
| 7 | Required Properties: |
| 8 | |
| 9 | - compatible: Must be one of the following |
Ulrich Hecht | bfadcad | 2014-11-07 16:51:08 +0100 | [diff] [blame] | 10 | - "renesas,r8a73a4-div6-clock" for R8A73A4 (R-Mobile APE6) DIV6 clocks |
| 11 | - "renesas,r8a7740-div6-clock" for R8A7740 (R-Mobile A1) DIV6 clocks |
Laurent Pinchart | abe844a | 2013-10-17 23:54:07 +0200 | [diff] [blame] | 12 | - "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks |
Ulrich Hecht | 0e0d8b7 | 2015-05-28 17:17:01 +0200 | [diff] [blame] | 13 | - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2-W) DIV6 clocks |
| 14 | - "renesas,r8a7793-div6-clock" for R8A7793 (R-Car M2-N) DIV6 clocks |
Geert Uytterhoeven | 0c933f3 | 2015-06-01 11:57:48 +0200 | [diff] [blame] | 15 | - "renesas,r8a7794-div6-clock" for R8A7794 (R-Car E2) DIV6 clocks |
Ulrich Hecht | bfadcad | 2014-11-07 16:51:08 +0100 | [diff] [blame] | 16 | - "renesas,sh73a0-div6-clock" for SH73A0 (SH-Mobile AG5) DIV6 clocks |
Geert Uytterhoeven | 3706262 | 2015-06-01 12:00:08 +0200 | [diff] [blame] | 17 | and "renesas,cpg-div6-clock" as a fallback. |
Laurent Pinchart | abe844a | 2013-10-17 23:54:07 +0200 | [diff] [blame] | 18 | - reg: Base address and length of the memory resource used by the DIV6 clock |
Ulrich Hecht | bfadcad | 2014-11-07 16:51:08 +0100 | [diff] [blame] | 19 | - clocks: Reference to the parent clock(s); either one, four, or eight |
| 20 | clocks must be specified. For clocks with multiple parents, invalid |
| 21 | settings must be specified as "<0>". |
Laurent Pinchart | abe844a | 2013-10-17 23:54:07 +0200 | [diff] [blame] | 22 | - #clock-cells: Must be 0 |
Geert Uytterhoeven | 0770558 | 2015-09-08 14:46:32 +0200 | [diff] [blame] | 23 | |
| 24 | |
| 25 | Optional Properties: |
| 26 | |
Laurent Pinchart | abe844a | 2013-10-17 23:54:07 +0200 | [diff] [blame] | 27 | - clock-output-names: The name of the clock as a free-form string |
| 28 | |
| 29 | |
| 30 | Example |
| 31 | ------- |
| 32 | |
Ulrich Hecht | bfadcad | 2014-11-07 16:51:08 +0100 | [diff] [blame] | 33 | sdhi2_clk: sdhi2_clk@e615007c { |
| 34 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
| 35 | reg = <0 0xe615007c 0 4>; |
| 36 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, |
| 37 | <0>, <&extal2_clk>; |
Laurent Pinchart | abe844a | 2013-10-17 23:54:07 +0200 | [diff] [blame] | 38 | #clock-cells = <0>; |
Ulrich Hecht | bfadcad | 2014-11-07 16:51:08 +0100 | [diff] [blame] | 39 | clock-output-names = "sdhi2ck"; |
Laurent Pinchart | abe844a | 2013-10-17 23:54:07 +0200 | [diff] [blame] | 40 | }; |