Ulrich Hecht | 1923ca9 | 2014-05-23 15:27:15 +0200 | [diff] [blame] | 1 | These bindings should be considered EXPERIMENTAL for now. |
| 2 | |
| 3 | * Renesas R8A7740 Clock Pulse Generator (CPG) |
| 4 | |
| 5 | The CPG generates core clocks for the R8A7740 SoC. It includes three PLLs |
| 6 | and several fixed ratio and variable ratio dividers. |
| 7 | |
| 8 | Required Properties: |
| 9 | |
| 10 | - compatible: Must be "renesas,r8a7740-cpg-clocks" |
| 11 | |
| 12 | - reg: Base address and length of the memory resource used by the CPG |
| 13 | |
| 14 | - clocks: Reference to the three parent clocks |
| 15 | - #clock-cells: Must be 1 |
| 16 | - clock-output-names: The names of the clocks. Supported clocks are |
| 17 | "system", "pllc0", "pllc1", "pllc2", "r", "usb24s", "i", "zg", "b", |
| 18 | "m1", "hp", "hpp", "usbp", "s", "zb", "m3", and "cp". |
| 19 | |
| 20 | - renesas,mode: board-specific settings of the MD_CK* bits |
| 21 | |
| 22 | |
| 23 | Example |
| 24 | ------- |
| 25 | |
| 26 | cpg_clocks: cpg_clocks@e6150000 { |
| 27 | compatible = "renesas,r8a7740-cpg-clocks"; |
| 28 | reg = <0xe6150000 0x10000>; |
| 29 | clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>; |
| 30 | #clock-cells = <1>; |
| 31 | clock-output-names = "system", "pllc0", "pllc1", |
| 32 | "pllc2", "r", |
| 33 | "usb24s", |
| 34 | "i", "zg", "b", "m1", "hp", |
| 35 | "hpp", "usbp", "s", "zb", "m3", |
| 36 | "cp"; |
| 37 | }; |
| 38 | |
| 39 | &cpg_clocks { |
| 40 | renesas,mode = <0x05>; |
| 41 | }; |