| Tai Nguyen | eef691c | 2016-07-15 10:38:03 -0700 | [diff] [blame] | 1 | * APM X-Gene SoC PMU bindings |
| 2 | |
| 3 | This is APM X-Gene SoC PMU (Performance Monitoring Unit) module. |
| 4 | The following PMU devices are supported: |
| 5 | |
| 6 | L3C - L3 cache controller |
| 7 | IOB - IO bridge |
| 8 | MCB - Memory controller bridge |
| 9 | MC - Memory controller |
| 10 | |
| 11 | The following section describes the SoC PMU DT node binding. |
| 12 | |
| 13 | Required properties: |
| 14 | - compatible : Shall be "apm,xgene-pmu" for revision 1 or |
| 15 | "apm,xgene-pmu-v2" for revision 2. |
| 16 | - regmap-csw : Regmap of the CPU switch fabric (CSW) resource. |
| 17 | - regmap-mcba : Regmap of the MCB-A (memory bridge) resource. |
| 18 | - regmap-mcbb : Regmap of the MCB-B (memory bridge) resource. |
| 19 | - reg : First resource shall be the CPU bus PMU resource. |
| 20 | - interrupts : Interrupt-specifier for PMU IRQ. |
| 21 | |
| 22 | Required properties for L3C subnode: |
| 23 | - compatible : Shall be "apm,xgene-pmu-l3c". |
| 24 | - reg : First resource shall be the L3C PMU resource. |
| 25 | |
| 26 | Required properties for IOB subnode: |
| 27 | - compatible : Shall be "apm,xgene-pmu-iob". |
| 28 | - reg : First resource shall be the IOB PMU resource. |
| 29 | |
| 30 | Required properties for MCB subnode: |
| 31 | - compatible : Shall be "apm,xgene-pmu-mcb". |
| 32 | - reg : First resource shall be the MCB PMU resource. |
| 33 | - enable-bit-index : The bit indicates if the according MCB is enabled. |
| 34 | |
| 35 | Required properties for MC subnode: |
| 36 | - compatible : Shall be "apm,xgene-pmu-mc". |
| 37 | - reg : First resource shall be the MC PMU resource. |
| 38 | - enable-bit-index : The bit indicates if the according MC is enabled. |
| 39 | |
| 40 | Example: |
| 41 | csw: csw@7e200000 { |
| 42 | compatible = "apm,xgene-csw", "syscon"; |
| 43 | reg = <0x0 0x7e200000 0x0 0x1000>; |
| 44 | }; |
| 45 | |
| 46 | mcba: mcba@7e700000 { |
| 47 | compatible = "apm,xgene-mcb", "syscon"; |
| 48 | reg = <0x0 0x7e700000 0x0 0x1000>; |
| 49 | }; |
| 50 | |
| 51 | mcbb: mcbb@7e720000 { |
| 52 | compatible = "apm,xgene-mcb", "syscon"; |
| 53 | reg = <0x0 0x7e720000 0x0 0x1000>; |
| 54 | }; |
| 55 | |
| 56 | pmu: pmu@78810000 { |
| 57 | compatible = "apm,xgene-pmu-v2"; |
| 58 | #address-cells = <2>; |
| 59 | #size-cells = <2>; |
| 60 | ranges; |
| 61 | regmap-csw = <&csw>; |
| 62 | regmap-mcba = <&mcba>; |
| 63 | regmap-mcbb = <&mcbb>; |
| 64 | reg = <0x0 0x78810000 0x0 0x1000>; |
| 65 | interrupts = <0x0 0x22 0x4>; |
| 66 | |
| 67 | pmul3c@7e610000 { |
| 68 | compatible = "apm,xgene-pmu-l3c"; |
| 69 | reg = <0x0 0x7e610000 0x0 0x1000>; |
| 70 | }; |
| 71 | |
| 72 | pmuiob@7e940000 { |
| 73 | compatible = "apm,xgene-pmu-iob"; |
| 74 | reg = <0x0 0x7e940000 0x0 0x1000>; |
| 75 | }; |
| 76 | |
| 77 | pmucmcb@7e710000 { |
| 78 | compatible = "apm,xgene-pmu-mcb"; |
| 79 | reg = <0x0 0x7e710000 0x0 0x1000>; |
| 80 | enable-bit-index = <0>; |
| 81 | }; |
| 82 | |
| 83 | pmucmcb@7e730000 { |
| 84 | compatible = "apm,xgene-pmu-mcb"; |
| 85 | reg = <0x0 0x7e730000 0x0 0x1000>; |
| 86 | enable-bit-index = <1>; |
| 87 | }; |
| 88 | |
| 89 | pmucmc@7e810000 { |
| 90 | compatible = "apm,xgene-pmu-mc"; |
| 91 | reg = <0x0 0x7e810000 0x0 0x1000>; |
| 92 | enable-bit-index = <0>; |
| 93 | }; |
| 94 | |
| 95 | pmucmc@7e850000 { |
| 96 | compatible = "apm,xgene-pmu-mc"; |
| 97 | reg = <0x0 0x7e850000 0x0 0x1000>; |
| 98 | enable-bit-index = <1>; |
| 99 | }; |
| 100 | |
| 101 | pmucmc@7e890000 { |
| 102 | compatible = "apm,xgene-pmu-mc"; |
| 103 | reg = <0x0 0x7e890000 0x0 0x1000>; |
| 104 | enable-bit-index = <2>; |
| 105 | }; |
| 106 | |
| 107 | pmucmc@7e8d0000 { |
| 108 | compatible = "apm,xgene-pmu-mc"; |
| 109 | reg = <0x0 0x7e8d0000 0x0 0x1000>; |
| 110 | enable-bit-index = <3>; |
| 111 | }; |
| 112 | }; |