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Paul Mundt96de1a82008-02-26 14:52:45 +09001#ifndef __LINUX_SERIAL_SCI_H
2#define __LINUX_SERIAL_SCI_H
Paul Mundtecd95612006-09-27 17:32:30 +09003
4#include <linux/serial_core.h>
Paul Mundt14baf9d2010-05-24 16:31:08 +09005#include <linux/sh_dma.h>
Paul Mundtecd95612006-09-27 17:32:30 +09006
7/*
Guenter Roeck4b084782013-08-30 06:01:49 -07008 * Generic header for SuperH (H)SCI(F) (used by sh/sh64 and related parts)
Paul Mundtecd95612006-09-27 17:32:30 +09009 */
10
Paul Mundtdebf9502011-06-08 18:19:37 +090011#define SCIx_NOT_SUPPORTED (-1)
12
Geert Uytterhoeven26de4f12014-03-11 11:11:19 +010013/* SCSMR (Serial Mode Register) */
14#define SCSMR_CHR (1 << 6) /* 7-bit Character Length */
15#define SCSMR_PE (1 << 5) /* Parity Enable */
16#define SCSMR_ODD (1 << 4) /* Odd Parity */
17#define SCSMR_STOP (1 << 3) /* Stop Bit Length */
18#define SCSMR_CKS 0x0003 /* Clock Select */
Paul Mundt00b9de92009-06-24 17:53:33 +090019
Geert Uytterhoeven26de4f12014-03-11 11:11:19 +010020/* Serial Control Register (@ = not supported by all parts) */
21#define SCSCR_TIE (1 << 7) /* Transmit Interrupt Enable */
22#define SCSCR_RIE (1 << 6) /* Receive Interrupt Enable */
23#define SCSCR_TE (1 << 5) /* Transmit Enable */
24#define SCSCR_RE (1 << 4) /* Receive Enable */
25#define SCSCR_REIE (1 << 3) /* Receive Error Interrupt Enable @ */
26#define SCSCR_TOIE (1 << 2) /* Timeout Interrupt Enable @ */
27#define SCSCR_CKE1 (1 << 1) /* Clock Enable 1 */
28#define SCSCR_CKE0 (1 << 0) /* Clock Enable 0 */
29/* SCIFA/SCIFB only */
30#define SCSCR_TDRQE (1 << 15) /* Tx Data Transfer Request Enable */
31#define SCSCR_RDRQE (1 << 14) /* Rx Data Transfer Request Enable */
32
33/* SCxSR (Serial Status Register) on SCI */
34#define SCI_TDRE 0x80 /* Transmit Data Register Empty */
35#define SCI_RDRF 0x40 /* Receive Data Register Full */
36#define SCI_ORER 0x20 /* Overrun Error */
37#define SCI_FER 0x10 /* Framing Error */
38#define SCI_PER 0x08 /* Parity Error */
39#define SCI_TEND 0x04 /* Transmit End */
Paul Mundtdebf9502011-06-08 18:19:37 +090040
41#define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER)
42
Geert Uytterhoeven26de4f12014-03-11 11:11:19 +010043/* SCxSR (Serial Status Register) on SCIF, HSCIF */
44#define SCIF_ER 0x0080 /* Receive Error */
45#define SCIF_TEND 0x0040 /* Transmission End */
46#define SCIF_TDFE 0x0020 /* Transmit FIFO Data Empty */
47#define SCIF_BRK 0x0010 /* Break Detect */
48#define SCIF_FER 0x0008 /* Framing Error */
49#define SCIF_PER 0x0004 /* Parity Error */
50#define SCIF_RDF 0x0002 /* Receive FIFO Data Full */
51#define SCIF_DR 0x0001 /* Receive Data Ready */
Paul Mundtdebf9502011-06-08 18:19:37 +090052
53#define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
54
Geert Uytterhoeven26de4f12014-03-11 11:11:19 +010055/* SCFCR (FIFO Control Register) */
56#define SCFCR_LOOP (1 << 0) /* Loopback Test */
57
58/* SCSPTR (Serial Port Register), optional */
59#define SCSPTR_RTSIO (1 << 7) /* Serial Port RTS Pin Input/Output */
60#define SCSPTR_CTSIO (1 << 5) /* Serial Port CTS Pin Input/Output */
61#define SCSPTR_SPB2IO (1 << 1) /* Serial Port Break Input/Output */
62#define SCSPTR_SPB2DT (1 << 0) /* Serial Port Break Data */
Paul Mundtfaf02f82011-12-02 17:44:50 +090063
Ulrich Hechtf303b362013-05-31 17:57:01 +020064/* HSSRR HSCIF */
Geert Uytterhoeven26de4f12014-03-11 11:11:19 +010065#define HSCIF_SRE 0x8000 /* Sampling Rate Register Enable */
Ulrich Hechtf303b362013-05-31 17:57:01 +020066
Paul Mundt61a69762011-06-14 12:40:19 +090067enum {
68 SCIx_PROBE_REGTYPE,
69
70 SCIx_SCI_REGTYPE,
71 SCIx_IRDA_REGTYPE,
72 SCIx_SCIFA_REGTYPE,
73 SCIx_SCIFB_REGTYPE,
Phil Edworthy3af1f8a2011-10-03 15:16:47 +010074 SCIx_SH2_SCIF_FIFODATA_REGTYPE,
Paul Mundt61a69762011-06-14 12:40:19 +090075 SCIx_SH3_SCIF_REGTYPE,
76 SCIx_SH4_SCIF_REGTYPE,
77 SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
78 SCIx_SH4_SCIF_FIFODATA_REGTYPE,
79 SCIx_SH7705_SCIF_REGTYPE,
Ulrich Hechtf303b362013-05-31 17:57:01 +020080 SCIx_HSCIF_REGTYPE,
Paul Mundt61a69762011-06-14 12:40:19 +090081
82 SCIx_NR_REGTYPES,
83};
84
Paul Mundt61a69762011-06-14 12:40:19 +090085/*
86 * SCI register subset common for all port types.
87 * Not all registers will exist on all parts.
88 */
89enum {
Geert Uytterhoeven26de4f12014-03-11 11:11:19 +010090 SCSMR, /* Serial Mode Register */
91 SCBRR, /* Bit Rate Register */
92 SCSCR, /* Serial Control Register */
93 SCxSR, /* Serial Status Register */
94 SCFCR, /* FIFO Control Register */
95 SCFDR, /* FIFO Data Count Register */
96 SCxTDR, /* Transmit (FIFO) Data Register */
97 SCxRDR, /* Receive (FIFO) Data Register */
98 SCLSR, /* Line Status Register */
99 SCTFDR, /* Transmit FIFO Data Count Register */
100 SCRFDR, /* Receive FIFO Data Count Register */
101 SCSPTR, /* Serial Port Register */
102 HSSRR, /* Sampling Rate Register */
Paul Mundt61a69762011-06-14 12:40:19 +0900103
104 SCIx_NR_REGS,
105};
106
Guennadi Liakhovetski73a19e42010-03-02 11:39:15 +0900107struct device;
108
Paul Mundt61a69762011-06-14 12:40:19 +0900109struct plat_sci_port_ops {
110 void (*init_pins)(struct uart_port *, unsigned int cflag);
111};
112
Paul Mundtecd95612006-09-27 17:32:30 +0900113/*
Paul Mundtfaf02f82011-12-02 17:44:50 +0900114 * Port-specific capabilities
115 */
116#define SCIx_HAVE_RTSCTS (1 << 0)
117
118/*
Paul Mundtecd95612006-09-27 17:32:30 +0900119 * Platform device specific platform_data struct
120 */
121struct plat_sci_port {
Ulrich Hechtf303b362013-05-31 17:57:01 +0200122 unsigned int type; /* SCI / SCIF / IRDA / HSCIF */
Paul Mundtecd95612006-09-27 17:32:30 +0900123 upf_t flags; /* UPF_* flags */
Paul Mundtfaf02f82011-12-02 17:44:50 +0900124 unsigned long capabilities; /* Port features/capabilities */
Paul Mundt00b9de92009-06-24 17:53:33 +0900125
Laurent Pinchartec09c5e2013-12-06 10:59:20 +0100126 unsigned int sampling_rate;
Paul Mundt00b9de92009-06-24 17:53:33 +0900127 unsigned int scscr; /* SCSCR initialization */
Paul Mundtf43dc232011-01-13 15:06:28 +0900128
Paul Mundtdebf9502011-06-08 18:19:37 +0900129 /*
130 * Platform overrides if necessary, defaults otherwise.
131 */
Paul Mundt514820e2011-06-08 18:51:32 +0900132 int port_reg;
Paul Mundt61a69762011-06-14 12:40:19 +0900133 unsigned char regshift;
134 unsigned char regtype;
135
136 struct plat_sci_port_ops *ops;
Paul Mundt514820e2011-06-08 18:51:32 +0900137
Paul Mundt27bd1072011-01-19 15:37:31 +0900138 unsigned int dma_slave_tx;
139 unsigned int dma_slave_rx;
Paul Mundtecd95612006-09-27 17:32:30 +0900140};
141
Paul Mundt96de1a82008-02-26 14:52:45 +0900142#endif /* __LINUX_SERIAL_SCI_H */