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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
Dave Airlie0d6aa602006-01-02 20:14:23 +11003/*
Dave Airliebc54fd12005-06-23 22:46:46 +10004 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
Dave Airliebc54fd12005-06-23 22:46:46 +10007 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110028 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
Jesse Barnes585fb112008-07-29 11:54:06 -070033#include "i915_reg.h"
Jesse Barnes79e53942008-11-07 14:24:08 -080034#include "intel_bios.h"
Zou Nan hai8187a2b2010-05-21 09:08:55 +080035#include "intel_ringbuffer.h"
Keith Packard0839ccb2008-10-30 19:38:48 -070036#include <linux/io-mapping.h>
Chris Wilsonf899fc62010-07-20 15:44:45 -070037#include <linux/i2c.h>
Daniel Vetterc167a6f2012-02-28 00:43:09 +010038#include <linux/i2c-algo-bit.h>
Daniel Vetter0ade6382010-08-24 22:18:41 +020039#include <drm/intel-gtt.h>
Matthew Garrettaaa6fd22011-08-12 12:11:33 +020040#include <linux/backlight.h>
Ben Widawsky2911a352012-04-05 14:47:36 -070041#include <linux/intel-iommu.h>
Daniel Vetter742cbee2012-04-27 15:17:39 +020042#include <linux/kref.h>
Jesse Barnes585fb112008-07-29 11:54:06 -070043
Linus Torvalds1da177e2005-04-16 15:20:36 -070044/* General customization:
45 */
46
47#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
48
49#define DRIVER_NAME "i915"
50#define DRIVER_DESC "Intel Graphics"
Eric Anholt673a3942008-07-30 12:06:12 -070051#define DRIVER_DATE "20080730"
Linus Torvalds1da177e2005-04-16 15:20:36 -070052
Jesse Barnes317c35d2008-08-25 15:11:06 -070053enum pipe {
54 PIPE_A = 0,
55 PIPE_B,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -080056 PIPE_C,
57 I915_MAX_PIPES
Jesse Barnes317c35d2008-08-25 15:11:06 -070058};
Jesse Barnes9db4a9c2011-02-07 12:26:52 -080059#define pipe_name(p) ((p) + 'A')
Jesse Barnes317c35d2008-08-25 15:11:06 -070060
Paulo Zanonia5c961d2012-10-24 15:59:34 -020061enum transcoder {
62 TRANSCODER_A = 0,
63 TRANSCODER_B,
64 TRANSCODER_C,
65 TRANSCODER_EDP = 0xF,
66};
67#define transcoder_name(t) ((t) + 'A')
68
Jesse Barnes80824002009-09-10 15:28:06 -070069enum plane {
70 PLANE_A = 0,
71 PLANE_B,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -080072 PLANE_C,
Jesse Barnes80824002009-09-10 15:28:06 -070073};
Jesse Barnes9db4a9c2011-02-07 12:26:52 -080074#define plane_name(p) ((p) + 'A')
Keith Packard52440212008-11-18 09:30:25 -080075
Eugeni Dodonov2b139522012-03-29 12:32:22 -030076enum port {
77 PORT_A = 0,
78 PORT_B,
79 PORT_C,
80 PORT_D,
81 PORT_E,
82 I915_MAX_PORTS
83};
84#define port_name(p) ((p) + 'A')
85
Eric Anholt62fdfea2010-05-21 13:26:39 -070086#define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
87
Jesse Barnes9db4a9c2011-02-07 12:26:52 -080088#define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
89
Daniel Vetter6c2b7c122012-07-05 09:50:24 +020090#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
91 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
92 if ((intel_encoder)->base.crtc == (__crtc))
93
Jesse Barnesee7b9f92012-04-20 17:11:53 +010094struct intel_pch_pll {
95 int refcount; /* count of number of CRTCs sharing this PLL */
96 int active; /* count of number of active CRTCs (i.e. DPMS on) */
97 bool on; /* is the PLL actually active? Disabled during modeset */
98 int pll_reg;
99 int fp0_reg;
100 int fp1_reg;
101};
102#define I915_NUM_PLLS 2
103
Paulo Zanoni6441ab52012-10-05 12:05:58 -0300104struct intel_ddi_plls {
105 int spll_refcount;
106 int wrpll1_refcount;
107 int wrpll2_refcount;
108};
109
Linus Torvalds1da177e2005-04-16 15:20:36 -0700110/* Interface history:
111 *
112 * 1.1: Original.
Dave Airlie0d6aa602006-01-02 20:14:23 +1100113 * 1.2: Add Power Management
114 * 1.3: Add vblank support
Dave Airliede227f52006-01-25 15:31:43 +1100115 * 1.4: Fix cmdbuffer path, add heap destroy
Dave Airlie702880f2006-06-24 17:07:34 +1000116 * 1.5: Add vblank pipe configuration
=?utf-8?q?Michel_D=C3=A4nzer?=2228ed62006-10-25 01:05:09 +1000117 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
118 * - Support vertical blank on secondary display pipe
Linus Torvalds1da177e2005-04-16 15:20:36 -0700119 */
120#define DRIVER_MAJOR 1
=?utf-8?q?Michel_D=C3=A4nzer?=2228ed62006-10-25 01:05:09 +1000121#define DRIVER_MINOR 6
Linus Torvalds1da177e2005-04-16 15:20:36 -0700122#define DRIVER_PATCHLEVEL 0
123
Eric Anholt673a3942008-07-30 12:06:12 -0700124#define WATCH_COHERENCY 0
Chris Wilson23bc5982010-09-29 16:10:57 +0100125#define WATCH_LISTS 0
Chris Wilson42d6ab42012-07-26 11:49:32 +0100126#define WATCH_GTT 0
Eric Anholt673a3942008-07-30 12:06:12 -0700127
Dave Airlie71acb5e2008-12-30 20:31:46 +1000128#define I915_GEM_PHYS_CURSOR_0 1
129#define I915_GEM_PHYS_CURSOR_1 2
130#define I915_GEM_PHYS_OVERLAY_REGS 3
131#define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
132
133struct drm_i915_gem_phys_object {
134 int id;
135 struct page **page_list;
136 drm_dma_handle_t *handle;
Chris Wilson05394f32010-11-08 19:18:58 +0000137 struct drm_i915_gem_object *cur_obj;
Dave Airlie71acb5e2008-12-30 20:31:46 +1000138};
139
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700140struct opregion_header;
141struct opregion_acpi;
142struct opregion_swsci;
143struct opregion_asle;
Keith Packard8d715f02011-11-18 20:39:01 -0800144struct drm_i915_private;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700145
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100146struct intel_opregion {
Ben Widawsky5bc44182012-04-16 14:07:42 -0700147 struct opregion_header __iomem *header;
148 struct opregion_acpi __iomem *acpi;
149 struct opregion_swsci __iomem *swsci;
150 struct opregion_asle __iomem *asle;
151 void __iomem *vbt;
Chris Wilson01fe9db2011-01-16 19:37:30 +0000152 u32 __iomem *lid_state;
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100153};
Chris Wilson44834a62010-08-19 16:09:23 +0100154#define OPREGION_SIZE (8*1024)
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +0100155
Chris Wilson6ef3d422010-08-04 20:26:07 +0100156struct intel_overlay;
157struct intel_overlay_error_state;
158
Dave Airlie7c1c2872008-11-28 14:22:24 +1000159struct drm_i915_master_private {
160 drm_local_map_t *sarea;
161 struct _drm_i915_sarea *sarea_priv;
162};
Jesse Barnesde151cf2008-11-12 10:03:55 -0800163#define I915_FENCE_REG_NONE -1
Daniel Vetter4b9de732011-10-09 21:52:02 +0200164#define I915_MAX_NUM_FENCES 16
165/* 16 fences + sign bit for FENCE_REG_NONE */
166#define I915_MAX_NUM_FENCE_BITS 5
Jesse Barnesde151cf2008-11-12 10:03:55 -0800167
168struct drm_i915_fence_reg {
Daniel Vetter007cc8a2010-04-28 11:02:31 +0200169 struct list_head lru_list;
Chris Wilsoncaea7472010-11-12 13:53:37 +0000170 struct drm_i915_gem_object *obj;
Chris Wilson1690e1e2011-12-14 13:57:08 +0100171 int pin_count;
Jesse Barnesde151cf2008-11-12 10:03:55 -0800172};
Dave Airlie7c1c2872008-11-28 14:22:24 +1000173
yakui_zhao9b9d1722009-05-31 17:17:17 +0800174struct sdvo_device_mapping {
Chris Wilsone957d772010-09-24 12:52:03 +0100175 u8 initialized;
yakui_zhao9b9d1722009-05-31 17:17:17 +0800176 u8 dvo_port;
177 u8 slave_addr;
178 u8 dvo_wiring;
Chris Wilsone957d772010-09-24 12:52:03 +0100179 u8 i2c_pin;
Adam Jacksonb1083332010-04-23 16:07:40 -0400180 u8 ddc_pin;
yakui_zhao9b9d1722009-05-31 17:17:17 +0800181};
182
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +0000183struct intel_display_error_state;
184
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700185struct drm_i915_error_state {
Daniel Vetter742cbee2012-04-27 15:17:39 +0200186 struct kref ref;
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700187 u32 eir;
188 u32 pgtbl_er;
Ben Widawskybe998e22012-04-26 16:03:00 -0700189 u32 ier;
Ben Widawskyb9a39062012-06-04 14:42:52 -0700190 u32 ccid;
Ben Widawsky9574b3f2012-04-26 16:03:01 -0700191 bool waiting[I915_NUM_RINGS];
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800192 u32 pipestat[I915_MAX_PIPES];
Daniel Vetterc1cd90e2011-12-14 13:57:02 +0100193 u32 tail[I915_NUM_RINGS];
194 u32 head[I915_NUM_RINGS];
Daniel Vetterd27b1e02011-12-14 13:57:01 +0100195 u32 ipeir[I915_NUM_RINGS];
196 u32 ipehr[I915_NUM_RINGS];
197 u32 instdone[I915_NUM_RINGS];
198 u32 acthd[I915_NUM_RINGS];
Daniel Vetter7e3b8732012-02-01 22:26:45 +0100199 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
Chris Wilson12f55812012-07-05 17:14:01 +0100200 u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */
Daniel Vetter7e3b8732012-02-01 22:26:45 +0100201 /* our own tracking of ring head and tail */
202 u32 cpu_ring_head[I915_NUM_RINGS];
203 u32 cpu_ring_tail[I915_NUM_RINGS];
Chris Wilson1d8f38f2010-10-29 19:00:51 +0100204 u32 error; /* gen6+ */
Ben Widawsky71e172e2012-08-20 16:15:13 -0700205 u32 err_int; /* gen7 */
Daniel Vetterc1cd90e2011-12-14 13:57:02 +0100206 u32 instpm[I915_NUM_RINGS];
207 u32 instps[I915_NUM_RINGS];
Ben Widawsky050ee912012-08-22 11:32:15 -0700208 u32 extra_instdone[I915_NUM_INSTDONE_REG];
Daniel Vetterd27b1e02011-12-14 13:57:01 +0100209 u32 seqno[I915_NUM_RINGS];
Chris Wilson9df30792010-02-18 10:24:56 +0000210 u64 bbaddr;
Daniel Vetter33f3f512011-12-14 13:57:39 +0100211 u32 fault_reg[I915_NUM_RINGS];
212 u32 done_reg;
Daniel Vetterc1cd90e2011-12-14 13:57:02 +0100213 u32 faddr[I915_NUM_RINGS];
Daniel Vetter4b9de732011-10-09 21:52:02 +0200214 u64 fence[I915_MAX_NUM_FENCES];
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700215 struct timeval time;
Chris Wilson52d39a22012-02-15 11:25:37 +0000216 struct drm_i915_error_ring {
217 struct drm_i915_error_object {
218 int page_count;
219 u32 gtt_offset;
220 u32 *pages[0];
221 } *ringbuffer, *batchbuffer;
222 struct drm_i915_error_request {
223 long jiffies;
224 u32 seqno;
Chris Wilsonee4f42b2012-02-15 11:25:38 +0000225 u32 tail;
Chris Wilson52d39a22012-02-15 11:25:37 +0000226 } *requests;
227 int num_requests;
228 } ring[I915_NUM_RINGS];
Chris Wilson9df30792010-02-18 10:24:56 +0000229 struct drm_i915_error_buffer {
Chris Wilsona779e5a2011-01-09 21:07:49 +0000230 u32 size;
Chris Wilson9df30792010-02-18 10:24:56 +0000231 u32 name;
Chris Wilson0201f1e2012-07-20 12:41:01 +0100232 u32 rseqno, wseqno;
Chris Wilson9df30792010-02-18 10:24:56 +0000233 u32 gtt_offset;
234 u32 read_domains;
235 u32 write_domain;
Daniel Vetter4b9de732011-10-09 21:52:02 +0200236 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
Chris Wilson9df30792010-02-18 10:24:56 +0000237 s32 pinned:2;
238 u32 tiling:2;
239 u32 dirty:1;
240 u32 purgeable:1;
Daniel Vetter5d1333f2012-02-16 11:03:29 +0100241 s32 ring:4;
Chris Wilson93dfb402011-03-29 16:59:50 -0700242 u32 cache_level:2;
Chris Wilsonc724e8a2010-11-22 08:07:02 +0000243 } *active_bo, *pinned_bo;
244 u32 active_bo_count, pinned_bo_count;
Chris Wilson6ef3d422010-08-04 20:26:07 +0100245 struct intel_overlay_error_state *overlay;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +0000246 struct intel_display_error_state *display;
Jesse Barnes63eeaf32009-06-18 16:56:52 -0700247};
248
Jesse Barnese70236a2009-09-21 10:42:27 -0700249struct drm_i915_display_funcs {
Adam Jacksonee5382a2010-04-23 11:17:39 -0400250 bool (*fbc_enabled)(struct drm_device *dev);
Jesse Barnese70236a2009-09-21 10:42:27 -0700251 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
252 void (*disable_fbc)(struct drm_device *dev);
253 int (*get_display_clock_speed)(struct drm_device *dev);
254 int (*get_fifo_size)(struct drm_device *dev, int plane);
Chris Wilsond2102462011-01-24 17:43:27 +0000255 void (*update_wm)(struct drm_device *dev);
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800256 void (*update_sprite_wm)(struct drm_device *dev, int pipe,
257 uint32_t sprite_width, int pixel_size);
Eugeni Dodonov1f8eeab2012-05-09 15:37:24 -0300258 void (*update_linetime_wm)(struct drm_device *dev, int pipe,
259 struct drm_display_mode *mode);
Daniel Vetter47fab732012-10-26 10:58:18 +0200260 void (*modeset_global_resources)(struct drm_device *dev);
Eric Anholtf564048e2011-03-30 13:01:02 -0700261 int (*crtc_mode_set)(struct drm_crtc *crtc,
262 struct drm_display_mode *mode,
263 struct drm_display_mode *adjusted_mode,
264 int x, int y,
265 struct drm_framebuffer *old_fb);
Daniel Vetter76e5a892012-06-29 22:39:33 +0200266 void (*crtc_enable)(struct drm_crtc *crtc);
267 void (*crtc_disable)(struct drm_crtc *crtc);
Jesse Barnesee7b9f92012-04-20 17:11:53 +0100268 void (*off)(struct drm_crtc *crtc);
Wu Fengguange0dac652011-09-05 14:25:34 +0800269 void (*write_eld)(struct drm_connector *connector,
270 struct drm_crtc *crtc);
Jesse Barnes674cf962011-04-28 14:27:04 -0700271 void (*fdi_link_train)(struct drm_crtc *crtc);
Jesse Barnes6067aae2011-04-28 15:04:31 -0700272 void (*init_clock_gating)(struct drm_device *dev);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -0700273 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
274 struct drm_framebuffer *fb,
275 struct drm_i915_gem_object *obj);
Jesse Barnes17638cd2011-06-24 12:19:23 -0700276 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
277 int x, int y);
Jesse Barnese70236a2009-09-21 10:42:27 -0700278 /* clock updates for mode set */
279 /* cursor updates */
280 /* render clock increase/decrease */
281 /* display clock increase/decrease */
282 /* pll clock increase/decrease */
Jesse Barnese70236a2009-09-21 10:42:27 -0700283};
284
Chris Wilson990bbda2012-07-02 11:51:02 -0300285struct drm_i915_gt_funcs {
286 void (*force_wake_get)(struct drm_i915_private *dev_priv);
287 void (*force_wake_put)(struct drm_i915_private *dev_priv);
288};
289
Daniel Vetterc96ea642012-08-08 22:01:51 +0200290#define DEV_INFO_FLAGS \
291 DEV_INFO_FLAG(is_mobile) DEV_INFO_SEP \
292 DEV_INFO_FLAG(is_i85x) DEV_INFO_SEP \
293 DEV_INFO_FLAG(is_i915g) DEV_INFO_SEP \
294 DEV_INFO_FLAG(is_i945gm) DEV_INFO_SEP \
295 DEV_INFO_FLAG(is_g33) DEV_INFO_SEP \
296 DEV_INFO_FLAG(need_gfx_hws) DEV_INFO_SEP \
297 DEV_INFO_FLAG(is_g4x) DEV_INFO_SEP \
298 DEV_INFO_FLAG(is_pineview) DEV_INFO_SEP \
299 DEV_INFO_FLAG(is_broadwater) DEV_INFO_SEP \
300 DEV_INFO_FLAG(is_crestline) DEV_INFO_SEP \
301 DEV_INFO_FLAG(is_ivybridge) DEV_INFO_SEP \
302 DEV_INFO_FLAG(is_valleyview) DEV_INFO_SEP \
303 DEV_INFO_FLAG(is_haswell) DEV_INFO_SEP \
304 DEV_INFO_FLAG(has_force_wake) DEV_INFO_SEP \
305 DEV_INFO_FLAG(has_fbc) DEV_INFO_SEP \
306 DEV_INFO_FLAG(has_pipe_cxsr) DEV_INFO_SEP \
307 DEV_INFO_FLAG(has_hotplug) DEV_INFO_SEP \
308 DEV_INFO_FLAG(cursor_needs_physical) DEV_INFO_SEP \
309 DEV_INFO_FLAG(has_overlay) DEV_INFO_SEP \
310 DEV_INFO_FLAG(overlay_needs_physical) DEV_INFO_SEP \
311 DEV_INFO_FLAG(supports_tv) DEV_INFO_SEP \
312 DEV_INFO_FLAG(has_bsd_ring) DEV_INFO_SEP \
313 DEV_INFO_FLAG(has_blt_ring) DEV_INFO_SEP \
314 DEV_INFO_FLAG(has_llc)
315
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500316struct intel_device_info {
Chris Wilsonc96c3a8c2010-08-11 09:59:24 +0100317 u8 gen;
Akshay Joshi0206e352011-08-16 15:34:10 -0400318 u8 is_mobile:1;
319 u8 is_i85x:1;
320 u8 is_i915g:1;
321 u8 is_i945gm:1;
322 u8 is_g33:1;
323 u8 need_gfx_hws:1;
324 u8 is_g4x:1;
325 u8 is_pineview:1;
326 u8 is_broadwater:1;
327 u8 is_crestline:1;
328 u8 is_ivybridge:1;
Jesse Barnes70a3eb72012-03-28 13:39:21 -0700329 u8 is_valleyview:1;
Daniel Vetterb7884eb2012-06-04 11:18:15 +0200330 u8 has_force_wake:1;
Eugeni Dodonov4cae9ae2012-03-29 12:32:18 -0300331 u8 is_haswell:1;
Akshay Joshi0206e352011-08-16 15:34:10 -0400332 u8 has_fbc:1;
333 u8 has_pipe_cxsr:1;
334 u8 has_hotplug:1;
335 u8 cursor_needs_physical:1;
336 u8 has_overlay:1;
337 u8 overlay_needs_physical:1;
338 u8 supports_tv:1;
339 u8 has_bsd_ring:1;
340 u8 has_blt_ring:1;
Eugeni Dodonov3d29b842012-01-17 14:43:53 -0200341 u8 has_llc:1;
Kristian Høgsbergcfdf1fa2009-12-16 15:16:16 -0500342};
343
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100344#define I915_PPGTT_PD_ENTRIES 512
345#define I915_PPGTT_PT_ENTRIES 1024
346struct i915_hw_ppgtt {
Ben Widawsky8f2c59f2012-09-24 08:55:51 -0700347 struct drm_device *dev;
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100348 unsigned num_pd_entries;
349 struct page **pt_pages;
350 uint32_t pd_offset;
351 dma_addr_t *pt_dma_addr;
352 dma_addr_t scratch_page_dma_addr;
353};
354
Ben Widawsky40521052012-06-04 14:42:43 -0700355
356/* This must match up with the value previously used for execbuf2.rsvd1. */
357#define DEFAULT_CONTEXT_ID 0
358struct i915_hw_context {
359 int id;
Ben Widawskye0556842012-06-04 14:42:46 -0700360 bool is_initialized;
Ben Widawsky40521052012-06-04 14:42:43 -0700361 struct drm_i915_file_private *file_priv;
362 struct intel_ring_buffer *ring;
363 struct drm_i915_gem_object *obj;
364};
365
Jesse Barnesb5e50c32010-02-05 12:42:41 -0800366enum no_fbc_reason {
Chris Wilsonbed4a672010-09-11 10:47:47 +0100367 FBC_NO_OUTPUT, /* no outputs enabled to compress */
Jesse Barnesb5e50c32010-02-05 12:42:41 -0800368 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
369 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
370 FBC_MODE_TOO_LARGE, /* mode too large for compression */
371 FBC_BAD_PLANE, /* fbc not supported on plane */
372 FBC_NOT_TILED, /* buffer not tiled */
Jesse Barnes9c928d12010-07-23 15:20:00 -0700373 FBC_MULTIPLE_PIPES, /* more than one pipe active */
Jesse Barnesc1a9f042011-05-05 15:24:21 -0700374 FBC_MODULE_PARAM,
Jesse Barnesb5e50c32010-02-05 12:42:41 -0800375};
376
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800377enum intel_pch {
Paulo Zanonif0350832012-07-03 18:48:16 -0300378 PCH_NONE = 0, /* No PCH present */
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800379 PCH_IBX, /* Ibexpeak PCH */
380 PCH_CPT, /* Cougarpoint PCH */
Eugeni Dodonoveb877eb2012-03-29 12:32:20 -0300381 PCH_LPT, /* Lynxpoint PCH */
Zhenyu Wang3bad0782010-04-07 16:15:53 +0800382};
383
Jesse Barnesb690e962010-07-19 13:53:12 -0700384#define QUIRK_PIPEA_FORCE (1<<0)
Keith Packard435793d2011-07-12 14:56:22 -0700385#define QUIRK_LVDS_SSC_DISABLE (1<<1)
Carsten Emde4dca20e2012-03-15 15:56:26 +0100386#define QUIRK_INVERT_BRIGHTNESS (1<<2)
Jesse Barnesb690e962010-07-19 13:53:12 -0700387
Dave Airlie8be48d92010-03-30 05:34:14 +0000388struct intel_fbdev;
Chris Wilson1630fe72011-07-08 12:22:42 +0100389struct intel_fbc_work;
Dave Airlie38651672010-03-30 05:34:13 +0000390
Daniel Vetterc2b91522012-02-14 22:37:19 +0100391struct intel_gmbus {
392 struct i2c_adapter adapter;
Daniel Vetterf6f808c2012-02-14 18:58:49 +0100393 bool force_bit;
Daniel Vetterc2b91522012-02-14 22:37:19 +0100394 u32 reg0;
Daniel Vetter36c785f2012-02-14 22:37:22 +0100395 u32 gpio_reg;
Daniel Vetterc167a6f2012-02-28 00:43:09 +0100396 struct i2c_algo_bit_data bit_algo;
Daniel Vetterc2b91522012-02-14 22:37:19 +0100397 struct drm_i915_private *dev_priv;
398};
399
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100400struct i915_suspend_saved_registers {
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000401 u8 saveLBB;
402 u32 saveDSPACNTR;
403 u32 saveDSPBCNTR;
Keith Packarde948e992008-05-07 12:27:53 +1000404 u32 saveDSPARB;
Chris Wilson968b5032011-03-23 18:16:55 +0000405 u32 saveHWS;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000406 u32 savePIPEACONF;
407 u32 savePIPEBCONF;
408 u32 savePIPEASRC;
409 u32 savePIPEBSRC;
410 u32 saveFPA0;
411 u32 saveFPA1;
412 u32 saveDPLL_A;
413 u32 saveDPLL_A_MD;
414 u32 saveHTOTAL_A;
415 u32 saveHBLANK_A;
416 u32 saveHSYNC_A;
417 u32 saveVTOTAL_A;
418 u32 saveVBLANK_A;
419 u32 saveVSYNC_A;
420 u32 saveBCLRPAT_A;
Zhenyu Wang5586c8b2009-11-06 02:13:02 +0000421 u32 saveTRANSACONF;
Zhenyu Wang42048782009-10-21 15:27:01 +0800422 u32 saveTRANS_HTOTAL_A;
423 u32 saveTRANS_HBLANK_A;
424 u32 saveTRANS_HSYNC_A;
425 u32 saveTRANS_VTOTAL_A;
426 u32 saveTRANS_VBLANK_A;
427 u32 saveTRANS_VSYNC_A;
Jesse Barnes0da3ea12008-02-20 09:39:58 +1000428 u32 savePIPEASTAT;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000429 u32 saveDSPASTRIDE;
430 u32 saveDSPASIZE;
431 u32 saveDSPAPOS;
Jesse Barnes585fb112008-07-29 11:54:06 -0700432 u32 saveDSPAADDR;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000433 u32 saveDSPASURF;
434 u32 saveDSPATILEOFF;
435 u32 savePFIT_PGM_RATIOS;
Jesse Barnes0eb96d62009-10-14 12:33:41 -0700436 u32 saveBLC_HIST_CTL;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000437 u32 saveBLC_PWM_CTL;
438 u32 saveBLC_PWM_CTL2;
Zhenyu Wang42048782009-10-21 15:27:01 +0800439 u32 saveBLC_CPU_PWM_CTL;
440 u32 saveBLC_CPU_PWM_CTL2;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000441 u32 saveFPB0;
442 u32 saveFPB1;
443 u32 saveDPLL_B;
444 u32 saveDPLL_B_MD;
445 u32 saveHTOTAL_B;
446 u32 saveHBLANK_B;
447 u32 saveHSYNC_B;
448 u32 saveVTOTAL_B;
449 u32 saveVBLANK_B;
450 u32 saveVSYNC_B;
451 u32 saveBCLRPAT_B;
Zhenyu Wang5586c8b2009-11-06 02:13:02 +0000452 u32 saveTRANSBCONF;
Zhenyu Wang42048782009-10-21 15:27:01 +0800453 u32 saveTRANS_HTOTAL_B;
454 u32 saveTRANS_HBLANK_B;
455 u32 saveTRANS_HSYNC_B;
456 u32 saveTRANS_VTOTAL_B;
457 u32 saveTRANS_VBLANK_B;
458 u32 saveTRANS_VSYNC_B;
Jesse Barnes0da3ea12008-02-20 09:39:58 +1000459 u32 savePIPEBSTAT;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000460 u32 saveDSPBSTRIDE;
461 u32 saveDSPBSIZE;
462 u32 saveDSPBPOS;
Jesse Barnes585fb112008-07-29 11:54:06 -0700463 u32 saveDSPBADDR;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000464 u32 saveDSPBSURF;
465 u32 saveDSPBTILEOFF;
Jesse Barnes585fb112008-07-29 11:54:06 -0700466 u32 saveVGA0;
467 u32 saveVGA1;
468 u32 saveVGA_PD;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000469 u32 saveVGACNTRL;
470 u32 saveADPA;
471 u32 saveLVDS;
Jesse Barnes585fb112008-07-29 11:54:06 -0700472 u32 savePP_ON_DELAYS;
473 u32 savePP_OFF_DELAYS;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000474 u32 saveDVOA;
475 u32 saveDVOB;
476 u32 saveDVOC;
477 u32 savePP_ON;
478 u32 savePP_OFF;
479 u32 savePP_CONTROL;
Jesse Barnes585fb112008-07-29 11:54:06 -0700480 u32 savePP_DIVISOR;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000481 u32 savePFIT_CONTROL;
482 u32 save_palette_a[256];
483 u32 save_palette_b[256];
Jesse Barnes06027f92009-10-05 13:47:26 -0700484 u32 saveDPFC_CB_BASE;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000485 u32 saveFBC_CFB_BASE;
486 u32 saveFBC_LL_BASE;
487 u32 saveFBC_CONTROL;
488 u32 saveFBC_CONTROL2;
Jesse Barnes0da3ea12008-02-20 09:39:58 +1000489 u32 saveIER;
490 u32 saveIIR;
491 u32 saveIMR;
Zhenyu Wang42048782009-10-21 15:27:01 +0800492 u32 saveDEIER;
493 u32 saveDEIMR;
494 u32 saveGTIER;
495 u32 saveGTIMR;
496 u32 saveFDI_RXA_IMR;
497 u32 saveFDI_RXB_IMR;
Keith Packard1f84e552008-02-16 19:19:29 -0800498 u32 saveCACHE_MODE_0;
Keith Packard1f84e552008-02-16 19:19:29 -0800499 u32 saveMI_ARB_STATE;
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000500 u32 saveSWF0[16];
501 u32 saveSWF1[16];
502 u32 saveSWF2[3];
503 u8 saveMSR;
504 u8 saveSR[8];
Jesse Barnes123f7942008-02-07 11:15:20 -0800505 u8 saveGR[25];
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000506 u8 saveAR_INDEX;
Jesse Barnesa59e1222008-05-07 12:25:46 +1000507 u8 saveAR[21];
Jesse Barnesba8bbcf2007-11-22 14:14:14 +1000508 u8 saveDACMASK;
Jesse Barnesa59e1222008-05-07 12:25:46 +1000509 u8 saveCR[37];
Daniel Vetter4b9de732011-10-09 21:52:02 +0200510 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
Eric Anholt1fd1c622009-06-03 07:26:58 +0000511 u32 saveCURACNTR;
512 u32 saveCURAPOS;
513 u32 saveCURABASE;
514 u32 saveCURBCNTR;
515 u32 saveCURBPOS;
516 u32 saveCURBBASE;
517 u32 saveCURSIZE;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700518 u32 saveDP_B;
519 u32 saveDP_C;
520 u32 saveDP_D;
521 u32 savePIPEA_GMCH_DATA_M;
522 u32 savePIPEB_GMCH_DATA_M;
523 u32 savePIPEA_GMCH_DATA_N;
524 u32 savePIPEB_GMCH_DATA_N;
525 u32 savePIPEA_DP_LINK_M;
526 u32 savePIPEB_DP_LINK_M;
527 u32 savePIPEA_DP_LINK_N;
528 u32 savePIPEB_DP_LINK_N;
Zhenyu Wang42048782009-10-21 15:27:01 +0800529 u32 saveFDI_RXA_CTL;
530 u32 saveFDI_TXA_CTL;
531 u32 saveFDI_RXB_CTL;
532 u32 saveFDI_TXB_CTL;
533 u32 savePFA_CTL_1;
534 u32 savePFB_CTL_1;
535 u32 savePFA_WIN_SZ;
536 u32 savePFB_WIN_SZ;
537 u32 savePFA_WIN_POS;
538 u32 savePFB_WIN_POS;
Zhenyu Wang5586c8b2009-11-06 02:13:02 +0000539 u32 savePCH_DREF_CONTROL;
540 u32 saveDISP_ARB_CTL;
541 u32 savePIPEA_DATA_M1;
542 u32 savePIPEA_DATA_N1;
543 u32 savePIPEA_LINK_M1;
544 u32 savePIPEA_LINK_N1;
545 u32 savePIPEB_DATA_M1;
546 u32 savePIPEB_DATA_N1;
547 u32 savePIPEB_LINK_M1;
548 u32 savePIPEB_LINK_N1;
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000549 u32 saveMCHBAR_RENDER_STANDBY;
Adam Jacksoncda2bb72011-07-26 16:53:06 -0400550 u32 savePCH_PORT_HOTPLUG;
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100551};
552typedef struct drm_i915_private {
553 struct drm_device *dev;
554
555 const struct intel_device_info *info;
556
557 int relative_constants_mode;
558
559 void __iomem *regs;
560
561 struct drm_i915_gt_funcs gt;
562 /** gt_fifo_count and the subsequent register write are synchronized
563 * with dev->struct_mutex. */
564 unsigned gt_fifo_count;
565 /** forcewake_count is protected by gt_lock */
566 unsigned forcewake_count;
567 /** gt_lock is also taken in irq contexts. */
568 struct spinlock gt_lock;
569
570 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
571
572 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
573 * controller on different i2c buses. */
574 struct mutex gmbus_mutex;
575
576 /**
577 * Base address of the gmbus and gpio block.
578 */
579 uint32_t gpio_mmio_base;
580
581 struct pci_dev *bridge_dev;
582 struct intel_ring_buffer ring[I915_NUM_RINGS];
583 uint32_t next_seqno;
584
585 drm_dma_handle_t *status_page_dmah;
586 uint32_t counter;
587 struct drm_i915_gem_object *pwrctx;
588 struct drm_i915_gem_object *renderctx;
589
590 struct resource mch_res;
591
592 atomic_t irq_received;
593
594 /* protects the irq masks */
595 spinlock_t irq_lock;
596
597 /* DPIO indirect register protection */
598 spinlock_t dpio_lock;
599
600 /** Cached value of IMR to avoid reads in updating the bitfield */
601 u32 pipestat[2];
602 u32 irq_mask;
603 u32 gt_irq_mask;
604 u32 pch_irq_mask;
605
606 u32 hotplug_supported_mask;
607 struct work_struct hotplug_work;
608
609 int num_pipe;
610 int num_pch_pll;
611
612 /* For hangcheck timer */
613#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
614#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
615 struct timer_list hangcheck_timer;
616 int hangcheck_count;
617 uint32_t last_acthd[I915_NUM_RINGS];
618 uint32_t prev_instdone[I915_NUM_INSTDONE_REG];
619
620 unsigned int stop_rings;
621
622 unsigned long cfb_size;
623 unsigned int cfb_fb;
624 enum plane cfb_plane;
625 int cfb_y;
626 struct intel_fbc_work *fbc_work;
627
628 struct intel_opregion opregion;
629
630 /* overlay */
631 struct intel_overlay *overlay;
632 bool sprite_scaling_enabled;
633
634 /* LVDS info */
635 int backlight_level; /* restore backlight to this value */
636 bool backlight_enabled;
637 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
638 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
639
640 /* Feature bits from the VBIOS */
641 unsigned int int_tv_support:1;
642 unsigned int lvds_dither:1;
643 unsigned int lvds_vbt:1;
644 unsigned int int_crt_support:1;
645 unsigned int lvds_use_ssc:1;
646 unsigned int display_clock_mode:1;
647 int lvds_ssc_freq;
648 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
649 unsigned int lvds_val; /* used for checking LVDS channel mode */
650 struct {
651 int rate;
652 int lanes;
653 int preemphasis;
654 int vswing;
655
656 bool initialized;
657 bool support;
658 int bpp;
659 struct edp_power_seq pps;
660 } edp;
661 bool no_aux_handshake;
662
663 int crt_ddc_pin;
664 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
665 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
666 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
667
668 unsigned int fsb_freq, mem_freq, is_ddr3;
669
670 spinlock_t error_lock;
671 /* Protected by dev->error_lock. */
672 struct drm_i915_error_state *first_error;
673 struct work_struct error_work;
674 struct completion error_completion;
675 struct workqueue_struct *wq;
676
677 /* Display functions */
678 struct drm_i915_display_funcs display;
679
680 /* PCH chipset type */
681 enum intel_pch pch_type;
682
683 unsigned long quirks;
684
685 /* Register state */
686 bool modeset_on_lid;
Eric Anholt673a3942008-07-30 12:06:12 -0700687
688 struct {
Daniel Vetter19966752010-09-06 20:08:44 +0200689 /** Bridge to intel-gtt-ko */
Chris Wilsonc64f7ba2010-11-23 14:24:24 +0000690 const struct intel_gtt *gtt;
Daniel Vetter19966752010-09-06 20:08:44 +0200691 /** Memory allocator for GTT stolen memory */
Chris Wilsonfe669bf2010-11-23 12:09:30 +0000692 struct drm_mm stolen;
Daniel Vetter19966752010-09-06 20:08:44 +0200693 /** Memory allocator for GTT */
Eric Anholt673a3942008-07-30 12:06:12 -0700694 struct drm_mm gtt_space;
Daniel Vetter93a37f22010-11-05 20:24:53 +0100695 /** List of all objects in gtt_space. Used to restore gtt
696 * mappings on resume */
Chris Wilson6c085a72012-08-20 11:40:46 +0200697 struct list_head bound_list;
698 /**
699 * List of objects which are not bound to the GTT (thus
700 * are idle and not used by the GPU) but still have
701 * (presumably uncached) pages still attached.
702 */
703 struct list_head unbound_list;
Chris Wilsonbee4a182011-01-21 10:54:32 +0000704
705 /** Usable portion of the GTT for GEM */
706 unsigned long gtt_start;
Daniel Vettera6e0aa42010-09-16 15:45:15 +0200707 unsigned long gtt_mappable_end;
Chris Wilsonbee4a182011-01-21 10:54:32 +0000708 unsigned long gtt_end;
Eric Anholt673a3942008-07-30 12:06:12 -0700709
Keith Packard0839ccb2008-10-30 19:38:48 -0700710 struct io_mapping *gtt_mapping;
Daniel Vetterdd2757f2012-06-07 15:55:57 +0200711 phys_addr_t gtt_base_addr;
Eric Anholtab657db12009-01-23 12:57:47 -0800712 int gtt_mtrr;
Keith Packard0839ccb2008-10-30 19:38:48 -0700713
Daniel Vetter1d2a3142012-02-09 17:15:46 +0100714 /** PPGTT used for aliasing the PPGTT with the GTT */
715 struct i915_hw_ppgtt *aliasing_ppgtt;
716
Ben Widawskyb9524a12012-05-25 16:56:24 -0700717 u32 *l3_remap_info;
718
Chris Wilson17250b72010-10-28 12:51:39 +0100719 struct shrinker inactive_shrinker;
Chris Wilson31169712009-09-14 16:50:28 +0100720
Eric Anholt673a3942008-07-30 12:06:12 -0700721 /**
Chris Wilson69dc4982010-10-19 10:36:51 +0100722 * List of objects currently involved in rendering.
723 *
724 * Includes buffers having the contents of their GPU caches
725 * flushed, not necessarily primitives. last_rendering_seqno
726 * represents when the rendering involved will be completed.
727 *
728 * A reference is held on the buffer while on this list.
729 */
730 struct list_head active_list;
731
732 /**
Eric Anholt673a3942008-07-30 12:06:12 -0700733 * LRU list of objects which are not in the ringbuffer and
734 * are ready to unbind, but are still in the GTT.
735 *
Eric Anholtce44b0e2008-11-06 16:00:31 -0800736 * last_rendering_seqno is 0 while an object is in this list.
737 *
Eric Anholt673a3942008-07-30 12:06:12 -0700738 * A reference is not held on the buffer while on this list,
739 * as merely being GTT-bound shouldn't prevent its being
740 * freed, and we'll pull it off the list in the free path.
741 */
742 struct list_head inactive_list;
743
Eric Anholta09ba7f2009-08-29 12:49:51 -0700744 /** LRU list of objects with fence regs on them. */
745 struct list_head fence_list;
746
Eric Anholt673a3942008-07-30 12:06:12 -0700747 /**
Eric Anholt673a3942008-07-30 12:06:12 -0700748 * We leave the user IRQ off as much as possible,
749 * but this means that requests will finish and never
750 * be retired once the system goes idle. Set a timer to
751 * fire periodically while the ring is running. When it
752 * fires, go retire requests.
753 */
754 struct delayed_work retire_work;
755
Eric Anholt673a3942008-07-30 12:06:12 -0700756 /**
Chris Wilsonce453d82011-02-21 14:43:56 +0000757 * Are we in a non-interruptible section of code like
758 * modesetting?
759 */
760 bool interruptible;
761
762 /**
Eric Anholt673a3942008-07-30 12:06:12 -0700763 * Flag if the X Server, and thus DRM, is not currently in
764 * control of the device.
765 *
766 * This is set between LeaveVT and EnterVT. It needs to be
767 * replaced with a semaphore. It also needs to be
768 * transitioned away from for kernel modesetting.
769 */
770 int suspended;
771
772 /**
773 * Flag if the hardware appears to be wedged.
774 *
775 * This is set when attempts to idle the device timeout.
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300776 * It prevents command submission from occurring and makes
Eric Anholt673a3942008-07-30 12:06:12 -0700777 * every pending request fail
778 */
Ben Gamariba1234d2009-09-14 17:48:47 -0400779 atomic_t wedged;
Eric Anholt673a3942008-07-30 12:06:12 -0700780
781 /** Bit 6 swizzling required for X tiling */
782 uint32_t bit_6_swizzle_x;
783 /** Bit 6 swizzling required for Y tiling */
784 uint32_t bit_6_swizzle_y;
Dave Airlie71acb5e2008-12-30 20:31:46 +1000785
786 /* storage for physical objects */
787 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
Chris Wilson92204342010-09-18 11:02:01 +0100788
Chris Wilson73aa8082010-09-30 11:46:12 +0100789 /* accounting, useful for userland debugging */
Chris Wilson73aa8082010-09-30 11:46:12 +0100790 size_t gtt_total;
Chris Wilson6299f992010-11-24 12:23:44 +0000791 size_t mappable_gtt_total;
792 size_t object_memory;
Chris Wilson73aa8082010-09-30 11:46:12 +0100793 u32 object_count;
Eric Anholt673a3942008-07-30 12:06:12 -0700794 } mm;
Daniel Vetter87813422012-05-02 11:49:32 +0200795
796 /* Old dri1 support infrastructure, beware the dragons ya fools entering
797 * here! */
798 struct {
799 unsigned allow_batchbuffer : 1;
Daniel Vetter316d3882012-04-26 23:28:15 +0200800 u32 __iomem *gfx_hws_cpu_addr;
Daniel Vetter5d985ac2012-08-12 19:27:13 +0200801
802 unsigned int cpp;
803 int back_offset;
804 int front_offset;
805 int current_page;
806 int page_flipping;
Daniel Vetter87813422012-05-02 11:49:32 +0200807 } dri1;
808
809 /* Kernel Modesetting */
810
yakui_zhao9b9d1722009-05-31 17:17:17 +0800811 struct sdvo_device_mapping sdvo_mappings[2];
Zhao Yakuia3e17eb2009-10-10 10:42:37 +0800812 /* indicate whether the LVDS_BORDER should be enabled or not */
813 unsigned int lvds_border_bits;
Chris Wilson1d8e1c72010-08-07 11:01:28 +0100814 /* Panel fitter placement and size for Ironlake+ */
815 u32 pch_pf_pos, pch_pf_size;
Jesse Barnes652c3932009-08-17 13:31:43 -0700816
Jesse Barnes27f82272011-09-02 12:54:37 -0700817 struct drm_crtc *plane_to_crtc_mapping[3];
818 struct drm_crtc *pipe_to_crtc_mapping[3];
Kristian Høgsberg6b95a202009-11-18 11:25:18 -0500819 wait_queue_head_t pending_flip_queue;
820
Jesse Barnesee7b9f92012-04-20 17:11:53 +0100821 struct intel_pch_pll pch_plls[I915_NUM_PLLS];
Paulo Zanoni6441ab52012-10-05 12:05:58 -0300822 struct intel_ddi_plls ddi_plls;
Jesse Barnesee7b9f92012-04-20 17:11:53 +0100823
Jesse Barnes652c3932009-08-17 13:31:43 -0700824 /* Reclocking support */
825 bool render_reclock_avail;
826 bool lvds_downclock_avail;
Zhao Yakui18f9ed12009-11-20 03:24:16 +0000827 /* indicates the reduced downclock for LVDS*/
828 int lvds_downclock;
Jesse Barnes652c3932009-08-17 13:31:43 -0700829 u16 orig_clock;
Zhao Yakui6363ee62009-11-24 09:48:44 +0800830 int child_dev_num;
831 struct child_device_config *child_dev;
Jesse Barnesf97108d2010-01-29 11:27:07 -0800832
Zhenyu Wangc48044112009-12-17 14:48:43 +0800833 bool mchbar_need_disable;
Jesse Barnesf97108d2010-01-29 11:27:07 -0800834
Daniel Vetterc6a828d2012-08-08 23:35:35 +0200835 /* gen6+ rps state */
836 struct {
837 struct work_struct work;
838 u32 pm_iir;
839 /* lock - irqsave spinlock that protectects the work_struct and
840 * pm_iir. */
841 spinlock_t lock;
842
843 /* The below variables an all the rps hw state are protected by
844 * dev->struct mutext. */
845 u8 cur_delay;
846 u8 min_delay;
847 u8 max_delay;
848 } rps;
849
Daniel Vetter20e4d402012-08-08 23:35:39 +0200850 /* ilk-only ips/rps state. Everything in here is protected by the global
851 * mchdev_lock in intel_pm.c */
852 struct {
853 u8 cur_delay;
854 u8 min_delay;
855 u8 max_delay;
856 u8 fmax;
857 u8 fstart;
Ben Widawsky4912d042011-04-25 11:25:20 -0700858
Daniel Vetter20e4d402012-08-08 23:35:39 +0200859 u64 last_count1;
860 unsigned long last_time1;
861 unsigned long chipset_power;
862 u64 last_count2;
863 struct timespec last_time2;
864 unsigned long gfx_power;
865 u8 corr;
Jesse Barnes7648fa92010-05-20 14:28:11 -0700866
Daniel Vetter20e4d402012-08-08 23:35:39 +0200867 int c_m;
868 int r_t;
869 } ips;
Jesse Barnesb5e50c32010-02-05 12:42:41 -0800870
871 enum no_fbc_reason no_fbc_reason;
Dave Airlie38651672010-03-30 05:34:13 +0000872
Jesse Barnes20bf3772010-04-21 11:39:22 -0700873 struct drm_mm_node *compressed_fb;
874 struct drm_mm_node *compressed_llb;
Eric Anholt34dc4d42010-05-07 14:30:03 -0700875
Chris Wilsonae681d92010-10-01 14:57:56 +0100876 unsigned long last_gpu_reset;
877
Dave Airlie8be48d92010-03-30 05:34:14 +0000878 /* list of fbdev register on this device */
879 struct intel_fbdev *fbdev;
Chris Wilsone953fd72011-02-21 22:23:52 +0000880
Matthew Garrettaaa6fd22011-08-12 12:11:33 +0200881 struct backlight_device *backlight;
882
Chris Wilsone953fd72011-02-21 22:23:52 +0000883 struct drm_property *broadcast_rgb_property;
Chris Wilson3f43c482011-05-12 22:17:24 +0100884 struct drm_property *force_audio_property;
Ben Widawskye3689192012-05-25 16:56:22 -0700885
886 struct work_struct parity_error_work;
Ben Widawsky254f9652012-06-04 14:42:42 -0700887 bool hw_contexts_disabled;
888 uint32_t hw_context_size;
Daniel Vetterf4c956a2012-11-02 19:55:02 +0100889
890 struct i915_suspend_saved_registers regfile;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700891} drm_i915_private_t;
892
Chris Wilsonb4519512012-05-11 14:29:30 +0100893/* Iterate over initialised rings */
894#define for_each_ring(ring__, dev_priv__, i__) \
895 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
896 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
897
Wu Fengguangb1d7e4b2012-02-14 11:45:36 +0800898enum hdmi_force_audio {
899 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
900 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
901 HDMI_AUDIO_AUTO, /* trust EDID */
902 HDMI_AUDIO_ON, /* force turn on HDMI audio */
903};
904
Chris Wilson93dfb402011-03-29 16:59:50 -0700905enum i915_cache_level {
Chris Wilsone6994ae2012-07-10 10:27:08 +0100906 I915_CACHE_NONE = 0,
Chris Wilson93dfb402011-03-29 16:59:50 -0700907 I915_CACHE_LLC,
Chris Wilsone6994ae2012-07-10 10:27:08 +0100908 I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */
Chris Wilson93dfb402011-03-29 16:59:50 -0700909};
910
Chris Wilson37e680a2012-06-07 15:38:42 +0100911struct drm_i915_gem_object_ops {
912 /* Interface between the GEM object and its backing storage.
913 * get_pages() is called once prior to the use of the associated set
914 * of pages before to binding them into the GTT, and put_pages() is
915 * called after we no longer need them. As we expect there to be
916 * associated cost with migrating pages between the backing storage
917 * and making them available for the GPU (e.g. clflush), we may hold
918 * onto the pages after they are no longer referenced by the GPU
919 * in case they may be used again shortly (for example migrating the
920 * pages to a different memory domain within the GTT). put_pages()
921 * will therefore most likely be called when the object itself is
922 * being released or under memory pressure (where we attempt to
923 * reap pages for the shrinker).
924 */
925 int (*get_pages)(struct drm_i915_gem_object *);
926 void (*put_pages)(struct drm_i915_gem_object *);
927};
928
Eric Anholt673a3942008-07-30 12:06:12 -0700929struct drm_i915_gem_object {
Daniel Vetterc397b902010-04-09 19:05:07 +0000930 struct drm_gem_object base;
Eric Anholt673a3942008-07-30 12:06:12 -0700931
Chris Wilson37e680a2012-06-07 15:38:42 +0100932 const struct drm_i915_gem_object_ops *ops;
933
Eric Anholt673a3942008-07-30 12:06:12 -0700934 /** Current space allocated to this object in the GTT, if any. */
935 struct drm_mm_node *gtt_space;
Daniel Vetter93a37f22010-11-05 20:24:53 +0100936 struct list_head gtt_list;
Eric Anholt673a3942008-07-30 12:06:12 -0700937
Chris Wilson65ce3022012-07-20 12:41:02 +0100938 /** This object's place on the active/inactive lists */
Chris Wilson69dc4982010-10-19 10:36:51 +0100939 struct list_head ring_list;
940 struct list_head mm_list;
Chris Wilson432e58e2010-11-25 19:32:06 +0000941 /** This object's place in the batchbuffer or on the eviction list */
942 struct list_head exec_list;
Eric Anholt673a3942008-07-30 12:06:12 -0700943
944 /**
Chris Wilson65ce3022012-07-20 12:41:02 +0100945 * This is set if the object is on the active lists (has pending
946 * rendering and so a non-zero seqno), and is not set if it i s on
947 * inactive (ready to be unbound) list.
Eric Anholt673a3942008-07-30 12:06:12 -0700948 */
Akshay Joshi0206e352011-08-16 15:34:10 -0400949 unsigned int active:1;
Eric Anholt673a3942008-07-30 12:06:12 -0700950
951 /**
952 * This is set if the object has been written to since last bound
953 * to the GTT
954 */
Akshay Joshi0206e352011-08-16 15:34:10 -0400955 unsigned int dirty:1;
Daniel Vetter778c3542010-05-13 11:49:44 +0200956
957 /**
958 * Fence register bits (if any) for this object. Will be set
959 * as needed when mapped into the GTT.
960 * Protected by dev->struct_mutex.
Daniel Vetter778c3542010-05-13 11:49:44 +0200961 */
Daniel Vetter4b9de732011-10-09 21:52:02 +0200962 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
Daniel Vetter778c3542010-05-13 11:49:44 +0200963
964 /**
Daniel Vetter778c3542010-05-13 11:49:44 +0200965 * Advice: are the backing pages purgeable?
966 */
Akshay Joshi0206e352011-08-16 15:34:10 -0400967 unsigned int madv:2;
Daniel Vetter778c3542010-05-13 11:49:44 +0200968
969 /**
Daniel Vetter778c3542010-05-13 11:49:44 +0200970 * Current tiling mode for the object.
971 */
Akshay Joshi0206e352011-08-16 15:34:10 -0400972 unsigned int tiling_mode:2;
Chris Wilson5d82e3e2012-04-21 16:23:23 +0100973 /**
974 * Whether the tiling parameters for the currently associated fence
975 * register have changed. Note that for the purposes of tracking
976 * tiling changes we also treat the unfenced register, the register
977 * slot that the object occupies whilst it executes a fenced
978 * command (such as BLT on gen2/3), as a "fence".
979 */
980 unsigned int fence_dirty:1;
Daniel Vetter778c3542010-05-13 11:49:44 +0200981
982 /** How many users have pinned this object in GTT space. The following
983 * users can each hold at most one reference: pwrite/pread, pin_ioctl
984 * (via user_pin_count), execbuffer (objects are not allowed multiple
985 * times for the same batchbuffer), and the framebuffer code. When
986 * switching/pageflipping, the framebuffer code has at most two buffers
987 * pinned per crtc.
988 *
989 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
990 * bits with absolutely no headroom. So use 4 bits. */
Akshay Joshi0206e352011-08-16 15:34:10 -0400991 unsigned int pin_count:4;
Daniel Vetter778c3542010-05-13 11:49:44 +0200992#define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
Eric Anholt673a3942008-07-30 12:06:12 -0700993
Daniel Vetterfb7d5162010-10-01 22:05:20 +0200994 /**
Daniel Vetter75e9e912010-11-04 17:11:09 +0100995 * Is the object at the current location in the gtt mappable and
996 * fenceable? Used to avoid costly recalculations.
997 */
Akshay Joshi0206e352011-08-16 15:34:10 -0400998 unsigned int map_and_fenceable:1;
Daniel Vetter75e9e912010-11-04 17:11:09 +0100999
1000 /**
Daniel Vetterfb7d5162010-10-01 22:05:20 +02001001 * Whether the current gtt mapping needs to be mappable (and isn't just
1002 * mappable by accident). Track pin and fault separate for a more
1003 * accurate mappable working set.
1004 */
Akshay Joshi0206e352011-08-16 15:34:10 -04001005 unsigned int fault_mappable:1;
1006 unsigned int pin_mappable:1;
Daniel Vetterfb7d5162010-10-01 22:05:20 +02001007
Chris Wilsoncaea7472010-11-12 13:53:37 +00001008 /*
1009 * Is the GPU currently using a fence to access this buffer,
1010 */
1011 unsigned int pending_fenced_gpu_access:1;
1012 unsigned int fenced_gpu_access:1;
1013
Chris Wilson93dfb402011-03-29 16:59:50 -07001014 unsigned int cache_level:2;
1015
Daniel Vetter7bddb012012-02-09 17:15:47 +01001016 unsigned int has_aliasing_ppgtt_mapping:1;
Daniel Vetter74898d72012-02-15 23:50:22 +01001017 unsigned int has_global_gtt_mapping:1;
Chris Wilson9da3da62012-06-01 15:20:22 +01001018 unsigned int has_dma_mapping:1;
Daniel Vetter7bddb012012-02-09 17:15:47 +01001019
Chris Wilson9da3da62012-06-01 15:20:22 +01001020 struct sg_table *pages;
Chris Wilsona5570172012-09-04 21:02:54 +01001021 int pages_pin_count;
Eric Anholt673a3942008-07-30 12:06:12 -07001022
Daniel Vetter1286ff72012-05-10 15:25:09 +02001023 /* prime dma-buf support */
Dave Airlie9a70cc22012-05-22 13:09:21 +01001024 void *dma_buf_vmapping;
1025 int vmapping_count;
1026
Daniel Vetter185cbcb2010-11-06 12:12:35 +01001027 /**
Chris Wilson67731b82010-12-08 10:38:14 +00001028 * Used for performing relocations during execbuffer insertion.
1029 */
1030 struct hlist_node exec_node;
1031 unsigned long exec_handle;
Chris Wilson6fe4f142011-01-10 17:35:37 +00001032 struct drm_i915_gem_exec_object2 *exec_entry;
Chris Wilson67731b82010-12-08 10:38:14 +00001033
1034 /**
Eric Anholt673a3942008-07-30 12:06:12 -07001035 * Current offset of the object in GTT space.
1036 *
1037 * This is the same as gtt_space->start
1038 */
1039 uint32_t gtt_offset;
Chris Wilsone67b8ce2009-09-14 16:50:26 +01001040
Chris Wilsoncaea7472010-11-12 13:53:37 +00001041 struct intel_ring_buffer *ring;
1042
Chris Wilson1c293ea2012-04-17 15:31:27 +01001043 /** Breadcrumb of last rendering to the buffer. */
Chris Wilson0201f1e2012-07-20 12:41:01 +01001044 uint32_t last_read_seqno;
1045 uint32_t last_write_seqno;
Chris Wilsoncaea7472010-11-12 13:53:37 +00001046 /** Breadcrumb of last fenced GPU access to the buffer. */
1047 uint32_t last_fenced_seqno;
Eric Anholt673a3942008-07-30 12:06:12 -07001048
Daniel Vetter778c3542010-05-13 11:49:44 +02001049 /** Current tiling stride for the object, if it's tiled. */
Jesse Barnesde151cf2008-11-12 10:03:55 -08001050 uint32_t stride;
Eric Anholt673a3942008-07-30 12:06:12 -07001051
Eric Anholt280b7132009-03-12 16:56:27 -07001052 /** Record of address bit 17 of each page at last unbind. */
Chris Wilsond312ec22010-06-06 15:40:22 +01001053 unsigned long *bit_17;
Eric Anholt280b7132009-03-12 16:56:27 -07001054
Jesse Barnes79e53942008-11-07 14:24:08 -08001055 /** User space pin count and filp owning the pin */
1056 uint32_t user_pin_count;
1057 struct drm_file *pin_filp;
Dave Airlie71acb5e2008-12-30 20:31:46 +10001058
1059 /** for phy allocated objects */
1060 struct drm_i915_gem_phys_object *phys_obj;
Kristian Høgsbergb70d11d2009-03-03 14:45:57 -05001061
1062 /**
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001063 * Number of crtcs where this object is currently the fb, but
1064 * will be page flipped away on the next vblank. When it
1065 * reaches 0, dev_priv->pending_flip_queue will be woken up.
1066 */
1067 atomic_t pending_flip;
Eric Anholt673a3942008-07-30 12:06:12 -07001068};
1069
Daniel Vetter62b8b212010-04-09 19:05:08 +00001070#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
Daniel Vetter23010e42010-03-08 13:35:02 +01001071
Eric Anholt673a3942008-07-30 12:06:12 -07001072/**
1073 * Request queue structure.
1074 *
1075 * The request queue allows us to note sequence numbers that have been emitted
1076 * and may be associated with active buffers to be retired.
1077 *
1078 * By keeping this list, we can avoid having to do questionable
1079 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1080 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1081 */
1082struct drm_i915_gem_request {
Zou Nan hai852835f2010-05-21 09:08:56 +08001083 /** On Which ring this request was generated */
1084 struct intel_ring_buffer *ring;
1085
Eric Anholt673a3942008-07-30 12:06:12 -07001086 /** GEM sequence number associated with this request. */
1087 uint32_t seqno;
1088
Chris Wilsona71d8d92012-02-15 11:25:36 +00001089 /** Postion in the ringbuffer of the end of the request */
1090 u32 tail;
1091
Eric Anholt673a3942008-07-30 12:06:12 -07001092 /** Time at which this request was emitted, in jiffies. */
1093 unsigned long emitted_jiffies;
1094
Eric Anholtb9624422009-06-03 07:27:35 +00001095 /** global list entry for this request */
Eric Anholt673a3942008-07-30 12:06:12 -07001096 struct list_head list;
Eric Anholtb9624422009-06-03 07:27:35 +00001097
Chris Wilsonf787a5f2010-09-24 16:02:42 +01001098 struct drm_i915_file_private *file_priv;
Eric Anholtb9624422009-06-03 07:27:35 +00001099 /** file_priv list entry for this request */
1100 struct list_head client_list;
Eric Anholt673a3942008-07-30 12:06:12 -07001101};
1102
1103struct drm_i915_file_private {
1104 struct {
Chris Wilson1c255952010-09-26 11:03:27 +01001105 struct spinlock lock;
Eric Anholtb9624422009-06-03 07:27:35 +00001106 struct list_head request_list;
Eric Anholt673a3942008-07-30 12:06:12 -07001107 } mm;
Ben Widawsky40521052012-06-04 14:42:43 -07001108 struct idr context_idr;
Eric Anholt673a3942008-07-30 12:06:12 -07001109};
1110
Zou Nan haicae58522010-11-09 17:17:32 +08001111#define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1112
1113#define IS_I830(dev) ((dev)->pci_device == 0x3577)
1114#define IS_845G(dev) ((dev)->pci_device == 0x2562)
1115#define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1116#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1117#define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1118#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1119#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1120#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1121#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1122#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1123#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1124#define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1125#define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1126#define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1127#define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1128#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1129#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1130#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
Jesse Barnes4b651772011-04-28 14:33:09 -07001131#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
Jesse Barnes8ab43972012-10-25 12:15:42 -07001132#define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \
1133 (dev)->pci_device == 0x0152 || \
1134 (dev)->pci_device == 0x015a)
Jesse Barnes70a3eb72012-03-28 13:39:21 -07001135#define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
Eugeni Dodonov4cae9ae2012-03-29 12:32:18 -03001136#define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
Zou Nan haicae58522010-11-09 17:17:32 +08001137#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1138
Jesse Barnes85436692011-04-06 12:11:14 -07001139/*
1140 * The genX designation typically refers to the render engine, so render
1141 * capability related checks should use IS_GEN, while display and other checks
1142 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1143 * chips, etc.).
1144 */
Zou Nan haicae58522010-11-09 17:17:32 +08001145#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1146#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1147#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1148#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1149#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
Jesse Barnes85436692011-04-06 12:11:14 -07001150#define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
Zou Nan haicae58522010-11-09 17:17:32 +08001151
1152#define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1153#define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
Eugeni Dodonov3d29b842012-01-17 14:43:53 -02001154#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
Zou Nan haicae58522010-11-09 17:17:32 +08001155#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1156
Ben Widawsky254f9652012-06-04 14:42:42 -07001157#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
Jesse Barnes93553602012-06-15 11:55:23 -07001158#define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001159
Chris Wilson05394f32010-11-08 19:18:58 +00001160#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
Zou Nan haicae58522010-11-09 17:17:32 +08001161#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1162
1163/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1164 * rows, which changed the alignment requirements and fence programming.
1165 */
1166#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1167 IS_I915GM(dev)))
1168#define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1169#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1170#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1171#define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1172#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1173#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1174/* dsparb controlled by hw only */
1175#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1176
1177#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1178#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1179#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
Zou Nan haicae58522010-11-09 17:17:32 +08001180
Jesse Barneseceae482011-04-06 12:15:08 -07001181#define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
Zou Nan haicae58522010-11-09 17:17:32 +08001182
1183#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
Eugeni Dodonoveb877eb2012-03-29 12:32:20 -03001184#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
Zou Nan haicae58522010-11-09 17:17:32 +08001185#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1186#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
Paulo Zanoni45e6e3a2012-07-03 15:57:32 -03001187#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
Zou Nan haicae58522010-11-09 17:17:32 +08001188
Daniel Vetterb7884eb2012-06-04 11:18:15 +02001189#define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1190
Ben Widawskyf27b9262012-07-24 20:47:32 -07001191#define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
Ben Widawskye1ef7cc2012-07-24 20:47:31 -07001192
Ben Widawskyc8735b02012-09-07 19:43:39 -07001193#define GT_FREQUENCY_MULTIPLIER 50
1194
Chris Wilson05394f32010-11-08 19:18:58 +00001195#include "i915_trace.h"
1196
Eugeni Dodonov83b7f9a2012-03-23 11:57:18 -03001197/**
1198 * RC6 is a special power stage which allows the GPU to enter an very
1199 * low-voltage mode when idle, using down to 0V while at this stage. This
1200 * stage is entered automatically when the GPU is idle when RC6 support is
1201 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1202 *
1203 * There are different RC6 modes available in Intel GPU, which differentiate
1204 * among each other with the latency required to enter and leave RC6 and
1205 * voltage consumed by the GPU in different states.
1206 *
1207 * The combination of the following flags define which states GPU is allowed
1208 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1209 * RC6pp is deepest RC6. Their support by hardware varies according to the
1210 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1211 * which brings the most power savings; deeper states save more power, but
1212 * require higher latency to switch to and wake up.
1213 */
1214#define INTEL_RC6_ENABLE (1<<0)
1215#define INTEL_RC6p_ENABLE (1<<1)
1216#define INTEL_RC6pp_ENABLE (1<<2)
1217
Eric Anholtc153f452007-09-03 12:06:45 +10001218extern struct drm_ioctl_desc i915_ioctls[];
Dave Airlieb3a83632005-09-30 18:37:36 +10001219extern int i915_max_ioctl;
Ben Widawskya35d9d32011-07-13 14:38:17 -07001220extern unsigned int i915_fbpercrtc __always_unused;
1221extern int i915_panel_ignore_lid __read_mostly;
1222extern unsigned int i915_powersave __read_mostly;
Eugeni Dodonovf45b5552011-12-09 17:16:37 -08001223extern int i915_semaphores __read_mostly;
Ben Widawskya35d9d32011-07-13 14:38:17 -07001224extern unsigned int i915_lvds_downclock __read_mostly;
Takashi Iwai121d5272012-03-20 13:07:06 +01001225extern int i915_lvds_channel_mode __read_mostly;
Keith Packard4415e632011-11-09 09:57:50 -08001226extern int i915_panel_use_ssc __read_mostly;
Ben Widawskya35d9d32011-07-13 14:38:17 -07001227extern int i915_vbt_sdvo_panel_type __read_mostly;
Keith Packardc0f372b32011-11-16 22:24:52 -08001228extern int i915_enable_rc6 __read_mostly;
Keith Packard4415e632011-11-09 09:57:50 -08001229extern int i915_enable_fbc __read_mostly;
Ben Widawskya35d9d32011-07-13 14:38:17 -07001230extern bool i915_enable_hangcheck __read_mostly;
Daniel Vetter650dc072012-04-02 10:08:35 +02001231extern int i915_enable_ppgtt __read_mostly;
Dave Airlieb3a83632005-09-30 18:37:36 +10001232
Dave Airlie6a9ee8a2010-02-01 15:38:10 +10001233extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1234extern int i915_resume(struct drm_device *dev);
Dave Airlie7c1c2872008-11-28 14:22:24 +10001235extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1236extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1237
Linus Torvalds1da177e2005-04-16 15:20:36 -07001238 /* i915_dma.c */
Daniel Vetterd05c6172012-04-26 23:28:09 +02001239void i915_update_dri1_breadcrumb(struct drm_device *dev);
Dave Airlie84b1fd12007-07-11 15:53:27 +10001240extern void i915_kernel_lost_context(struct drm_device * dev);
Dave Airlie22eae942005-11-10 22:16:34 +11001241extern int i915_driver_load(struct drm_device *, unsigned long flags);
Jesse Barnesba8bbcf2007-11-22 14:14:14 +10001242extern int i915_driver_unload(struct drm_device *);
Eric Anholt673a3942008-07-30 12:06:12 -07001243extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
Dave Airlie84b1fd12007-07-11 15:53:27 +10001244extern void i915_driver_lastclose(struct drm_device * dev);
Eric Anholt6c340ea2007-08-25 20:23:09 +10001245extern void i915_driver_preclose(struct drm_device *dev,
1246 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07001247extern void i915_driver_postclose(struct drm_device *dev,
1248 struct drm_file *file_priv);
Dave Airlie84b1fd12007-07-11 15:53:27 +10001249extern int i915_driver_device_is_agp(struct drm_device * dev);
Ben Widawskyc43b5632012-04-16 14:07:40 -07001250#ifdef CONFIG_COMPAT
Dave Airlie0d6aa602006-01-02 20:14:23 +11001251extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1252 unsigned long arg);
Ben Widawskyc43b5632012-04-16 14:07:40 -07001253#endif
Eric Anholt673a3942008-07-30 12:06:12 -07001254extern int i915_emit_box(struct drm_device *dev,
Chris Wilsonc4e7a412010-11-30 14:10:25 +00001255 struct drm_clip_rect *box,
1256 int DR1, int DR4);
Ben Widawsky8e96d9c2012-06-04 14:42:56 -07001257extern int intel_gpu_reset(struct drm_device *dev);
Daniel Vetterd4b8bb22012-04-27 15:17:44 +02001258extern int i915_reset(struct drm_device *dev);
Jesse Barnes7648fa92010-05-20 14:28:11 -07001259extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1260extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1261extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1262extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1263
Dave Airlieaf6061a2008-05-07 12:15:39 +10001264
Linus Torvalds1da177e2005-04-16 15:20:36 -07001265/* i915_irq.c */
Ben Gamarif65d9422009-09-14 17:48:44 -04001266void i915_hangcheck_elapsed(unsigned long data);
Chris Wilson527f9e92010-11-11 01:16:58 +00001267void i915_handle_error(struct drm_device *dev, bool wedged);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001268
Jesse Barnesf71d4af2011-06-28 13:00:41 -07001269extern void intel_irq_init(struct drm_device *dev);
Chris Wilson990bbda2012-07-02 11:51:02 -03001270extern void intel_gt_init(struct drm_device *dev);
Chris Wilson16995a92012-10-18 11:46:10 +01001271extern void intel_gt_reset(struct drm_device *dev);
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07001272
Daniel Vetter742cbee2012-04-27 15:17:39 +02001273void i915_error_state_free(struct kref *error_ref);
1274
Keith Packard7c463582008-11-04 02:03:27 -08001275void
1276i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1277
1278void
1279i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1280
Akshay Joshi0206e352011-08-16 15:34:10 -04001281void intel_enable_asle(struct drm_device *dev);
Zhao Yakui01c66882009-10-28 05:10:00 +00001282
Chris Wilson3bd3c932010-08-19 08:19:30 +01001283#ifdef CONFIG_DEBUG_FS
1284extern void i915_destroy_error_state(struct drm_device *dev);
1285#else
1286#define i915_destroy_error_state(x)
1287#endif
1288
Keith Packard7c463582008-11-04 02:03:27 -08001289
Eric Anholt673a3942008-07-30 12:06:12 -07001290/* i915_gem.c */
1291int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1292 struct drm_file *file_priv);
1293int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1294 struct drm_file *file_priv);
1295int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1296 struct drm_file *file_priv);
1297int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1298 struct drm_file *file_priv);
1299int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1300 struct drm_file *file_priv);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001301int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1302 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07001303int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1304 struct drm_file *file_priv);
1305int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1306 struct drm_file *file_priv);
1307int i915_gem_execbuffer(struct drm_device *dev, void *data,
1308 struct drm_file *file_priv);
Jesse Barnes76446ca2009-12-17 22:05:42 -05001309int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1310 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07001311int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1312 struct drm_file *file_priv);
1313int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1314 struct drm_file *file_priv);
1315int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1316 struct drm_file *file_priv);
Ben Widawsky199adf42012-09-21 17:01:20 -07001317int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
1318 struct drm_file *file);
1319int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
1320 struct drm_file *file);
Eric Anholt673a3942008-07-30 12:06:12 -07001321int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1322 struct drm_file *file_priv);
Chris Wilson3ef94da2009-09-14 16:50:29 +01001323int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1324 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07001325int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1326 struct drm_file *file_priv);
1327int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1328 struct drm_file *file_priv);
1329int i915_gem_set_tiling(struct drm_device *dev, void *data,
1330 struct drm_file *file_priv);
1331int i915_gem_get_tiling(struct drm_device *dev, void *data,
1332 struct drm_file *file_priv);
Eric Anholt5a125c32008-10-22 21:40:13 -07001333int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1334 struct drm_file *file_priv);
Ben Widawsky23ba4fd2012-05-24 15:03:10 -07001335int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
1336 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -07001337void i915_gem_load(struct drm_device *dev);
Eric Anholt673a3942008-07-30 12:06:12 -07001338int i915_gem_init_object(struct drm_gem_object *obj);
Chris Wilson37e680a2012-06-07 15:38:42 +01001339void i915_gem_object_init(struct drm_i915_gem_object *obj,
1340 const struct drm_i915_gem_object_ops *ops);
Chris Wilson05394f32010-11-08 19:18:58 +00001341struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1342 size_t size);
Eric Anholt673a3942008-07-30 12:06:12 -07001343void i915_gem_free_object(struct drm_gem_object *obj);
Chris Wilson20217462010-11-23 15:26:33 +00001344int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1345 uint32_t alignment,
Chris Wilson86a1ee22012-08-11 15:41:04 +01001346 bool map_and_fenceable,
1347 bool nonblocking);
Chris Wilson05394f32010-11-08 19:18:58 +00001348void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
Chris Wilson20217462010-11-23 15:26:33 +00001349int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
Chris Wilson05394f32010-11-08 19:18:58 +00001350void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
Eric Anholt673a3942008-07-30 12:06:12 -07001351void i915_gem_lastclose(struct drm_device *dev);
Chris Wilsonf787a5f2010-09-24 16:02:42 +01001352
Chris Wilson37e680a2012-06-07 15:38:42 +01001353int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
Chris Wilson9da3da62012-06-01 15:20:22 +01001354static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
1355{
1356 struct scatterlist *sg = obj->pages->sgl;
Chris Wilson1cf83782012-10-10 12:11:52 +01001357 int nents = obj->pages->nents;
1358 while (nents > SG_MAX_SINGLE_ALLOC) {
1359 if (n < SG_MAX_SINGLE_ALLOC - 1)
1360 break;
1361
Chris Wilson9da3da62012-06-01 15:20:22 +01001362 sg = sg_chain_ptr(sg + SG_MAX_SINGLE_ALLOC - 1);
1363 n -= SG_MAX_SINGLE_ALLOC - 1;
Chris Wilson1cf83782012-10-10 12:11:52 +01001364 nents -= SG_MAX_SINGLE_ALLOC - 1;
Chris Wilson9da3da62012-06-01 15:20:22 +01001365 }
1366 return sg_page(sg+n);
1367}
Chris Wilsona5570172012-09-04 21:02:54 +01001368static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
1369{
1370 BUG_ON(obj->pages == NULL);
1371 obj->pages_pin_count++;
1372}
1373static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
1374{
1375 BUG_ON(obj->pages_pin_count == 0);
1376 obj->pages_pin_count--;
1377}
1378
Chris Wilson54cf91d2010-11-25 18:00:26 +00001379int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
Ben Widawsky2911a352012-04-05 14:47:36 -07001380int i915_gem_object_sync(struct drm_i915_gem_object *obj,
1381 struct intel_ring_buffer *to);
Chris Wilson54cf91d2010-11-25 18:00:26 +00001382void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
Chris Wilson1ec14ad2010-12-04 11:30:53 +00001383 struct intel_ring_buffer *ring,
1384 u32 seqno);
Chris Wilson54cf91d2010-11-25 18:00:26 +00001385
Dave Airlieff72145b2011-02-07 12:16:14 +10001386int i915_gem_dumb_create(struct drm_file *file_priv,
1387 struct drm_device *dev,
1388 struct drm_mode_create_dumb *args);
1389int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1390 uint32_t handle, uint64_t *offset);
1391int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
Akshay Joshi0206e352011-08-16 15:34:10 -04001392 uint32_t handle);
Chris Wilsonf787a5f2010-09-24 16:02:42 +01001393/**
1394 * Returns true if seq1 is later than seq2.
1395 */
1396static inline bool
1397i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1398{
1399 return (int32_t)(seq1 - seq2) >= 0;
1400}
1401
Daniel Vetter53d227f2012-01-25 16:32:49 +01001402u32 i915_gem_next_request_seqno(struct intel_ring_buffer *ring);
Chris Wilson54cf91d2010-11-25 18:00:26 +00001403
Chris Wilson06d98132012-04-17 15:31:24 +01001404int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
Chris Wilsond9e86c02010-11-10 16:40:20 +00001405int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
Chris Wilson20217462010-11-23 15:26:33 +00001406
Chris Wilson9a5a53b2012-03-22 15:10:00 +00001407static inline bool
Chris Wilson1690e1e2011-12-14 13:57:08 +01001408i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
1409{
1410 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1411 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1412 dev_priv->fence_regs[obj->fence_reg].pin_count++;
Chris Wilson9a5a53b2012-03-22 15:10:00 +00001413 return true;
1414 } else
1415 return false;
Chris Wilson1690e1e2011-12-14 13:57:08 +01001416}
1417
1418static inline void
1419i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
1420{
1421 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1422 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1423 dev_priv->fence_regs[obj->fence_reg].pin_count--;
1424 }
1425}
1426
Chris Wilsonb09a1fe2010-07-23 23:18:49 +01001427void i915_gem_retire_requests(struct drm_device *dev);
Chris Wilsona71d8d92012-02-15 11:25:36 +00001428void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
Daniel Vetterd6b2c792012-07-04 22:54:13 +02001429int __must_check i915_gem_check_wedge(struct drm_i915_private *dev_priv,
1430 bool interruptible);
Chris Wilsona71d8d92012-02-15 11:25:36 +00001431
Chris Wilson069efc12010-09-30 16:53:18 +01001432void i915_gem_reset(struct drm_device *dev);
Chris Wilson05394f32010-11-08 19:18:58 +00001433void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
Chris Wilson20217462010-11-23 15:26:33 +00001434int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1435 uint32_t read_domains,
1436 uint32_t write_domain);
Chris Wilsona8198ee2011-04-13 22:04:09 +01001437int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
Chris Wilson1070a422012-04-24 15:47:41 +01001438int __must_check i915_gem_init(struct drm_device *dev);
Daniel Vetterf691e2f2012-02-02 09:58:12 +01001439int __must_check i915_gem_init_hw(struct drm_device *dev);
Ben Widawskyb9524a12012-05-25 16:56:24 -07001440void i915_gem_l3_remap(struct drm_device *dev);
Daniel Vetterf691e2f2012-02-02 09:58:12 +01001441void i915_gem_init_swizzling(struct drm_device *dev);
Daniel Vettere21af882012-02-09 20:53:27 +01001442void i915_gem_init_ppgtt(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08001443void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
Ben Widawskyb2da9fe2012-04-26 16:02:58 -07001444int __must_check i915_gpu_idle(struct drm_device *dev);
Chris Wilson20217462010-11-23 15:26:33 +00001445int __must_check i915_gem_idle(struct drm_device *dev);
Chris Wilson3bb73ab2012-07-20 12:40:59 +01001446int i915_add_request(struct intel_ring_buffer *ring,
1447 struct drm_file *file,
Chris Wilsonacb868d2012-09-26 13:47:30 +01001448 u32 *seqno);
Ben Widawsky199b2bc2012-05-24 15:03:11 -07001449int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
1450 uint32_t seqno);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001451int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
Chris Wilson20217462010-11-23 15:26:33 +00001452int __must_check
1453i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1454 bool write);
1455int __must_check
Chris Wilsondabdfe02012-03-26 10:10:27 +02001456i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
1457int __must_check
Chris Wilson2da3b9b2011-04-14 09:41:17 +01001458i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1459 u32 alignment,
Chris Wilson20217462010-11-23 15:26:33 +00001460 struct intel_ring_buffer *pipelined);
Dave Airlie71acb5e2008-12-30 20:31:46 +10001461int i915_gem_attach_phys_object(struct drm_device *dev,
Chris Wilson05394f32010-11-08 19:18:58 +00001462 struct drm_i915_gem_object *obj,
Chris Wilson6eeefaf2010-08-07 11:01:39 +01001463 int id,
1464 int align);
Dave Airlie71acb5e2008-12-30 20:31:46 +10001465void i915_gem_detach_phys_object(struct drm_device *dev,
Chris Wilson05394f32010-11-08 19:18:58 +00001466 struct drm_i915_gem_object *obj);
Dave Airlie71acb5e2008-12-30 20:31:46 +10001467void i915_gem_free_all_phys_object(struct drm_device *dev);
Chris Wilson05394f32010-11-08 19:18:58 +00001468void i915_gem_release(struct drm_device *dev, struct drm_file *file);
Eric Anholt673a3942008-07-30 12:06:12 -07001469
Chris Wilson467cffb2011-03-07 10:42:03 +00001470uint32_t
Chris Wilsone28f8712011-07-18 13:11:49 -07001471i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1472 uint32_t size,
1473 int tiling_mode);
Chris Wilson467cffb2011-03-07 10:42:03 +00001474
Chris Wilsone4ffd172011-04-04 09:44:39 +01001475int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1476 enum i915_cache_level cache_level);
1477
Daniel Vetter1286ff72012-05-10 15:25:09 +02001478struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1479 struct dma_buf *dma_buf);
1480
1481struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
1482 struct drm_gem_object *gem_obj, int flags);
1483
Ben Widawsky254f9652012-06-04 14:42:42 -07001484/* i915_gem_context.c */
1485void i915_gem_context_init(struct drm_device *dev);
1486void i915_gem_context_fini(struct drm_device *dev);
Ben Widawsky254f9652012-06-04 14:42:42 -07001487void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
Ben Widawskye0556842012-06-04 14:42:46 -07001488int i915_switch_context(struct intel_ring_buffer *ring,
1489 struct drm_file *file, int to_id);
Ben Widawsky84624812012-06-04 14:42:54 -07001490int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
1491 struct drm_file *file);
1492int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
1493 struct drm_file *file);
Daniel Vetter1286ff72012-05-10 15:25:09 +02001494
Daniel Vetter76aaf222010-11-05 22:23:30 +01001495/* i915_gem_gtt.c */
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001496int __must_check i915_gem_init_aliasing_ppgtt(struct drm_device *dev);
1497void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
Daniel Vetter7bddb012012-02-09 17:15:47 +01001498void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
1499 struct drm_i915_gem_object *obj,
1500 enum i915_cache_level cache_level);
1501void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
1502 struct drm_i915_gem_object *obj);
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001503
Daniel Vetter76aaf222010-11-05 22:23:30 +01001504void i915_gem_restore_gtt_mappings(struct drm_device *dev);
Daniel Vetter74163902012-02-15 23:50:21 +01001505int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
1506void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
Chris Wilsone4ffd172011-04-04 09:44:39 +01001507 enum i915_cache_level cache_level);
Chris Wilson05394f32010-11-08 19:18:58 +00001508void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
Daniel Vetter74163902012-02-15 23:50:21 +01001509void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
Daniel Vetter644ec022012-03-26 09:45:40 +02001510void i915_gem_init_global_gtt(struct drm_device *dev,
1511 unsigned long start,
1512 unsigned long mappable_end,
1513 unsigned long end);
Daniel Vetter76aaf222010-11-05 22:23:30 +01001514
Chris Wilsonb47eb4a2010-08-07 11:01:23 +01001515/* i915_gem_evict.c */
Chris Wilson20217462010-11-23 15:26:33 +00001516int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
Chris Wilson42d6ab42012-07-26 11:49:32 +01001517 unsigned alignment,
1518 unsigned cache_level,
Chris Wilson86a1ee22012-08-11 15:41:04 +01001519 bool mappable,
1520 bool nonblock);
Chris Wilson6c085a72012-08-20 11:40:46 +02001521int i915_gem_evict_everything(struct drm_device *dev);
Chris Wilsonb47eb4a2010-08-07 11:01:23 +01001522
Chris Wilson9797fbf2012-04-24 15:47:39 +01001523/* i915_gem_stolen.c */
1524int i915_gem_init_stolen(struct drm_device *dev);
1525void i915_gem_cleanup_stolen(struct drm_device *dev);
1526
Eric Anholt673a3942008-07-30 12:06:12 -07001527/* i915_gem_tiling.c */
1528void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
Chris Wilson05394f32010-11-08 19:18:58 +00001529void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1530void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
Eric Anholt673a3942008-07-30 12:06:12 -07001531
1532/* i915_gem_debug.c */
Chris Wilson05394f32010-11-08 19:18:58 +00001533void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
Eric Anholt673a3942008-07-30 12:06:12 -07001534 const char *where, uint32_t mark);
Chris Wilson23bc5982010-09-29 16:10:57 +01001535#if WATCH_LISTS
1536int i915_verify_lists(struct drm_device *dev);
Eric Anholt673a3942008-07-30 12:06:12 -07001537#else
Chris Wilson23bc5982010-09-29 16:10:57 +01001538#define i915_verify_lists(dev) 0
Eric Anholt673a3942008-07-30 12:06:12 -07001539#endif
Chris Wilson05394f32010-11-08 19:18:58 +00001540void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1541 int handle);
1542void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
Eric Anholt673a3942008-07-30 12:06:12 -07001543 const char *where, uint32_t mark);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001544
Ben Gamari20172632009-02-17 20:08:50 -05001545/* i915_debugfs.c */
Ben Gamari27c202a2009-07-01 22:26:52 -04001546int i915_debugfs_init(struct drm_minor *minor);
1547void i915_debugfs_cleanup(struct drm_minor *minor);
Ben Gamari20172632009-02-17 20:08:50 -05001548
Jesse Barnes317c35d2008-08-25 15:11:06 -07001549/* i915_suspend.c */
1550extern int i915_save_state(struct drm_device *dev);
1551extern int i915_restore_state(struct drm_device *dev);
1552
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07001553/* i915_suspend.c */
1554extern int i915_save_state(struct drm_device *dev);
1555extern int i915_restore_state(struct drm_device *dev);
1556
Ben Widawsky0136db582012-04-10 21:17:01 -07001557/* i915_sysfs.c */
1558void i915_setup_sysfs(struct drm_device *dev_priv);
1559void i915_teardown_sysfs(struct drm_device *dev_priv);
1560
Chris Wilsonf899fc62010-07-20 15:44:45 -07001561/* intel_i2c.c */
1562extern int intel_setup_gmbus(struct drm_device *dev);
1563extern void intel_teardown_gmbus(struct drm_device *dev);
Daniel Kurtz3bd7d902012-03-28 02:36:14 +08001564extern inline bool intel_gmbus_is_port_valid(unsigned port)
1565{
Daniel Kurtz2ed06c92012-03-28 02:36:15 +08001566 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
Daniel Kurtz3bd7d902012-03-28 02:36:14 +08001567}
1568
1569extern struct i2c_adapter *intel_gmbus_get_adapter(
1570 struct drm_i915_private *dev_priv, unsigned port);
Chris Wilsone957d772010-09-24 12:52:03 +01001571extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1572extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
Chris Wilsonb8232e92010-09-28 16:41:32 +01001573extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1574{
1575 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1576}
Chris Wilsonf899fc62010-07-20 15:44:45 -07001577extern void intel_i2c_reset(struct drm_device *dev);
1578
Chris Wilson3b617962010-08-24 09:02:58 +01001579/* intel_opregion.c */
Chris Wilson44834a62010-08-19 16:09:23 +01001580extern int intel_opregion_setup(struct drm_device *dev);
1581#ifdef CONFIG_ACPI
1582extern void intel_opregion_init(struct drm_device *dev);
1583extern void intel_opregion_fini(struct drm_device *dev);
Chris Wilson3b617962010-08-24 09:02:58 +01001584extern void intel_opregion_asle_intr(struct drm_device *dev);
1585extern void intel_opregion_gse_intr(struct drm_device *dev);
1586extern void intel_opregion_enable_asle(struct drm_device *dev);
Len Brown65e082c2008-10-24 17:18:10 -04001587#else
Chris Wilson44834a62010-08-19 16:09:23 +01001588static inline void intel_opregion_init(struct drm_device *dev) { return; }
1589static inline void intel_opregion_fini(struct drm_device *dev) { return; }
Chris Wilson3b617962010-08-24 09:02:58 +01001590static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1591static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1592static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
Len Brown65e082c2008-10-24 17:18:10 -04001593#endif
Matthew Garrett8ee1c3d2008-08-05 19:37:25 +01001594
Jesse Barnes723bfd72010-10-07 16:01:13 -07001595/* intel_acpi.c */
1596#ifdef CONFIG_ACPI
1597extern void intel_register_dsm_handler(void);
1598extern void intel_unregister_dsm_handler(void);
1599#else
1600static inline void intel_register_dsm_handler(void) { return; }
1601static inline void intel_unregister_dsm_handler(void) { return; }
1602#endif /* CONFIG_ACPI */
1603
Jesse Barnes79e53942008-11-07 14:24:08 -08001604/* modesetting */
Daniel Vetterf8175862012-04-10 15:50:11 +02001605extern void intel_modeset_init_hw(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08001606extern void intel_modeset_init(struct drm_device *dev);
Chris Wilson2c7111d2011-03-29 10:40:27 +01001607extern void intel_modeset_gem_init(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08001608extern void intel_modeset_cleanup(struct drm_device *dev);
Dave Airlie28d52042009-09-21 14:33:58 +10001609extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
Daniel Vetter24929352012-07-02 20:28:59 +02001610extern void intel_modeset_setup_hw_state(struct drm_device *dev);
Adam Jacksonee5382a2010-04-23 11:17:39 -04001611extern bool intel_fbc_enabled(struct drm_device *dev);
Chris Wilson43a95392011-07-08 12:22:36 +01001612extern void intel_disable_fbc(struct drm_device *dev);
Jesse Barnes7648fa92010-05-20 14:28:11 -07001613extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
Keith Packard9fb526d2011-09-26 22:24:57 -07001614extern void ironlake_init_pch_refclk(struct drm_device *dev);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001615extern void gen6_set_rps(struct drm_device *dev, u8 val);
Akshay Joshi0206e352011-08-16 15:34:10 -04001616extern void intel_detect_pch(struct drm_device *dev);
1617extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
Ben Widawsky0136db582012-04-10 21:17:01 -07001618extern int intel_enable_rc6(const struct drm_device *dev);
Zhenyu Wang3bad0782010-04-07 16:15:53 +08001619
Ben Widawsky2911a352012-04-05 14:47:36 -07001620extern bool i915_semaphore_is_enabled(struct drm_device *dev);
Ben Widawskyc0c7bab2012-07-12 11:01:05 -07001621int i915_reg_read_ioctl(struct drm_device *dev, void *data,
1622 struct drm_file *file);
Jesse Barnes575155a2012-03-28 13:39:37 -07001623
Chris Wilson6ef3d422010-08-04 20:26:07 +01001624/* overlay */
Chris Wilson3bd3c932010-08-19 08:19:30 +01001625#ifdef CONFIG_DEBUG_FS
Chris Wilson6ef3d422010-08-04 20:26:07 +01001626extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1627extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00001628
1629extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1630extern void intel_display_print_error_state(struct seq_file *m,
1631 struct drm_device *dev,
1632 struct intel_display_error_state *error);
Chris Wilson3bd3c932010-08-19 08:19:30 +01001633#endif
Chris Wilson6ef3d422010-08-04 20:26:07 +01001634
Ben Widawskyb7287d82011-04-25 11:22:22 -07001635/* On SNB platform, before reading ring registers forcewake bit
1636 * must be set to prevent GT core from power down and stale values being
1637 * returned.
1638 */
Ben Widawskyfcca7922011-04-25 11:23:07 -07001639void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1640void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
Ben Widawsky67a37442012-02-09 10:15:20 +01001641int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
Ben Widawskyb7287d82011-04-25 11:22:22 -07001642
Ben Widawsky42c05262012-09-26 10:34:00 -07001643int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
1644int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
1645
Keith Packard5f753772010-11-22 09:24:22 +00001646#define __i915_read(x, y) \
Andi Kleenf7000882011-10-13 16:08:51 -07001647 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
Ben Widawskyfcca7922011-04-25 11:23:07 -07001648
Keith Packard5f753772010-11-22 09:24:22 +00001649__i915_read(8, b)
1650__i915_read(16, w)
1651__i915_read(32, l)
1652__i915_read(64, q)
1653#undef __i915_read
1654
1655#define __i915_write(x, y) \
Andi Kleenf7000882011-10-13 16:08:51 -07001656 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
1657
Keith Packard5f753772010-11-22 09:24:22 +00001658__i915_write(8, b)
1659__i915_write(16, w)
1660__i915_write(32, l)
1661__i915_write(64, q)
1662#undef __i915_write
1663
1664#define I915_READ8(reg) i915_read8(dev_priv, (reg))
1665#define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1666
1667#define I915_READ16(reg) i915_read16(dev_priv, (reg))
1668#define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1669#define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1670#define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1671
1672#define I915_READ(reg) i915_read32(dev_priv, (reg))
1673#define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
Zou Nan haicae58522010-11-09 17:17:32 +08001674#define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1675#define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
Keith Packard5f753772010-11-22 09:24:22 +00001676
1677#define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1678#define I915_READ64(reg) i915_read64(dev_priv, (reg))
Zou Nan haicae58522010-11-09 17:17:32 +08001679
1680#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1681#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
1682
Yuanhan Liuba4f01a2010-11-08 17:09:41 +08001683
Linus Torvalds1da177e2005-04-16 15:20:36 -07001684#endif