Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mach-integrator/pci_v3.c |
| 3 | * |
| 4 | * PCI functions for V3 host PCI bridge |
| 5 | * |
| 6 | * Copyright (C) 1999 ARM Limited |
| 7 | * Copyright (C) 2000-2001 Deep Blue Solutions Ltd |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 23 | #include <linux/kernel.h> |
| 24 | #include <linux/pci.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 25 | #include <linux/ioport.h> |
| 26 | #include <linux/interrupt.h> |
| 27 | #include <linux/spinlock.h> |
| 28 | #include <linux/init.h> |
Russell King | fced80c | 2008-09-06 12:10:45 +0100 | [diff] [blame] | 29 | #include <linux/io.h> |
Linus Walleij | 86adc39 | 2013-02-02 23:16:57 +0100 | [diff] [blame] | 30 | #include <linux/platform_device.h> |
Linus Walleij | f55b2b5 | 2013-03-01 02:20:55 +0100 | [diff] [blame^] | 31 | #include <linux/of.h> |
| 32 | #include <linux/of_address.h> |
| 33 | #include <linux/of_irq.h> |
| 34 | #include <linux/of_pci.h> |
Linus Walleij | 01ef310 | 2013-03-16 22:03:41 +0100 | [diff] [blame] | 35 | #include <video/vga.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 36 | |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 37 | #include <mach/hardware.h> |
Russell King | a285edc | 2010-01-14 19:59:37 +0000 | [diff] [blame] | 38 | #include <mach/platform.h> |
Linus Walleij | 695436e | 2012-02-26 10:46:48 +0100 | [diff] [blame] | 39 | #include <mach/irqs.h> |
| 40 | |
Linus Walleij | ae9daf2 | 2013-03-19 19:58:49 +0100 | [diff] [blame] | 41 | #include <asm/mach/map.h> |
Alexey Dobriyan | d43c36d | 2009-10-07 17:09:06 +0400 | [diff] [blame] | 42 | #include <asm/signal.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 43 | #include <asm/mach/pci.h> |
Russell King | c6af66b | 2007-05-17 10:16:55 +0100 | [diff] [blame] | 44 | #include <asm/irq_regs.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 45 | |
Linus Walleij | ae9daf2 | 2013-03-19 19:58:49 +0100 | [diff] [blame] | 46 | #include "pci_v3.h" |
| 47 | |
| 48 | /* |
| 49 | * Where in the memory map does PCI live? |
| 50 | * |
| 51 | * This represents a fairly liberal usage of address space. Even though |
| 52 | * the V3 only has two windows (therefore we need to map stuff on the fly), |
| 53 | * we maintain the same addresses, even if they're not mapped. |
| 54 | */ |
| 55 | #define PHYS_PCI_MEM_BASE 0x40000000 /* 512M */ |
| 56 | #define PHYS_PCI_IO_BASE 0x60000000 /* 16M */ |
| 57 | #define PHYS_PCI_CONFIG_BASE 0x61000000 /* 16M */ |
| 58 | #define PHYS_PCI_V3_BASE 0x62000000 /* 64K */ |
| 59 | |
| 60 | #define PCI_MEMORY_VADDR IOMEM(0xe8000000) |
| 61 | #define PCI_CONFIG_VADDR IOMEM(0xec000000) |
| 62 | |
Linus Walleij | 207bcf4 | 2013-02-03 00:20:44 +0100 | [diff] [blame] | 63 | /* |
| 64 | * V3 Local Bus to PCI Bridge definitions |
| 65 | * |
| 66 | * Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04 |
| 67 | * All V3 register names are prefaced by V3_ to avoid clashing with any other |
| 68 | * PCI definitions. Their names match the user's manual. |
| 69 | * |
| 70 | * I'm assuming that I20 is disabled. |
| 71 | * |
| 72 | */ |
| 73 | #define V3_PCI_VENDOR 0x00000000 |
| 74 | #define V3_PCI_DEVICE 0x00000002 |
| 75 | #define V3_PCI_CMD 0x00000004 |
| 76 | #define V3_PCI_STAT 0x00000006 |
| 77 | #define V3_PCI_CC_REV 0x00000008 |
| 78 | #define V3_PCI_HDR_CFG 0x0000000C |
| 79 | #define V3_PCI_IO_BASE 0x00000010 |
| 80 | #define V3_PCI_BASE0 0x00000014 |
| 81 | #define V3_PCI_BASE1 0x00000018 |
| 82 | #define V3_PCI_SUB_VENDOR 0x0000002C |
| 83 | #define V3_PCI_SUB_ID 0x0000002E |
| 84 | #define V3_PCI_ROM 0x00000030 |
| 85 | #define V3_PCI_BPARAM 0x0000003C |
| 86 | #define V3_PCI_MAP0 0x00000040 |
| 87 | #define V3_PCI_MAP1 0x00000044 |
| 88 | #define V3_PCI_INT_STAT 0x00000048 |
| 89 | #define V3_PCI_INT_CFG 0x0000004C |
| 90 | #define V3_LB_BASE0 0x00000054 |
| 91 | #define V3_LB_BASE1 0x00000058 |
| 92 | #define V3_LB_MAP0 0x0000005E |
| 93 | #define V3_LB_MAP1 0x00000062 |
| 94 | #define V3_LB_BASE2 0x00000064 |
| 95 | #define V3_LB_MAP2 0x00000066 |
| 96 | #define V3_LB_SIZE 0x00000068 |
| 97 | #define V3_LB_IO_BASE 0x0000006E |
| 98 | #define V3_FIFO_CFG 0x00000070 |
| 99 | #define V3_FIFO_PRIORITY 0x00000072 |
| 100 | #define V3_FIFO_STAT 0x00000074 |
| 101 | #define V3_LB_ISTAT 0x00000076 |
| 102 | #define V3_LB_IMASK 0x00000077 |
| 103 | #define V3_SYSTEM 0x00000078 |
| 104 | #define V3_LB_CFG 0x0000007A |
| 105 | #define V3_PCI_CFG 0x0000007C |
| 106 | #define V3_DMA_PCI_ADR0 0x00000080 |
| 107 | #define V3_DMA_PCI_ADR1 0x00000090 |
| 108 | #define V3_DMA_LOCAL_ADR0 0x00000084 |
| 109 | #define V3_DMA_LOCAL_ADR1 0x00000094 |
| 110 | #define V3_DMA_LENGTH0 0x00000088 |
| 111 | #define V3_DMA_LENGTH1 0x00000098 |
| 112 | #define V3_DMA_CSR0 0x0000008B |
| 113 | #define V3_DMA_CSR1 0x0000009B |
| 114 | #define V3_DMA_CTLB_ADR0 0x0000008C |
| 115 | #define V3_DMA_CTLB_ADR1 0x0000009C |
| 116 | #define V3_DMA_DELAY 0x000000E0 |
| 117 | #define V3_MAIL_DATA 0x000000C0 |
| 118 | #define V3_PCI_MAIL_IEWR 0x000000D0 |
| 119 | #define V3_PCI_MAIL_IERD 0x000000D2 |
| 120 | #define V3_LB_MAIL_IEWR 0x000000D4 |
| 121 | #define V3_LB_MAIL_IERD 0x000000D6 |
| 122 | #define V3_MAIL_WR_STAT 0x000000D8 |
| 123 | #define V3_MAIL_RD_STAT 0x000000DA |
| 124 | #define V3_QBA_MAP 0x000000DC |
| 125 | |
| 126 | /* PCI COMMAND REGISTER bits |
| 127 | */ |
| 128 | #define V3_COMMAND_M_FBB_EN (1 << 9) |
| 129 | #define V3_COMMAND_M_SERR_EN (1 << 8) |
| 130 | #define V3_COMMAND_M_PAR_EN (1 << 6) |
| 131 | #define V3_COMMAND_M_MASTER_EN (1 << 2) |
| 132 | #define V3_COMMAND_M_MEM_EN (1 << 1) |
| 133 | #define V3_COMMAND_M_IO_EN (1 << 0) |
| 134 | |
| 135 | /* SYSTEM REGISTER bits |
| 136 | */ |
| 137 | #define V3_SYSTEM_M_RST_OUT (1 << 15) |
| 138 | #define V3_SYSTEM_M_LOCK (1 << 14) |
| 139 | |
| 140 | /* PCI_CFG bits |
| 141 | */ |
| 142 | #define V3_PCI_CFG_M_I2O_EN (1 << 15) |
| 143 | #define V3_PCI_CFG_M_IO_REG_DIS (1 << 14) |
| 144 | #define V3_PCI_CFG_M_IO_DIS (1 << 13) |
| 145 | #define V3_PCI_CFG_M_EN3V (1 << 12) |
| 146 | #define V3_PCI_CFG_M_RETRY_EN (1 << 10) |
| 147 | #define V3_PCI_CFG_M_AD_LOW1 (1 << 9) |
| 148 | #define V3_PCI_CFG_M_AD_LOW0 (1 << 8) |
| 149 | |
| 150 | /* PCI_BASE register bits (PCI -> Local Bus) |
| 151 | */ |
| 152 | #define V3_PCI_BASE_M_ADR_BASE 0xFFF00000 |
| 153 | #define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00 |
| 154 | #define V3_PCI_BASE_M_PREFETCH (1 << 3) |
| 155 | #define V3_PCI_BASE_M_TYPE (3 << 1) |
| 156 | #define V3_PCI_BASE_M_IO (1 << 0) |
| 157 | |
| 158 | /* PCI MAP register bits (PCI -> Local bus) |
| 159 | */ |
| 160 | #define V3_PCI_MAP_M_MAP_ADR 0xFFF00000 |
| 161 | #define V3_PCI_MAP_M_RD_POST_INH (1 << 15) |
| 162 | #define V3_PCI_MAP_M_ROM_SIZE (3 << 10) |
| 163 | #define V3_PCI_MAP_M_SWAP (3 << 8) |
| 164 | #define V3_PCI_MAP_M_ADR_SIZE 0x000000F0 |
| 165 | #define V3_PCI_MAP_M_REG_EN (1 << 1) |
| 166 | #define V3_PCI_MAP_M_ENABLE (1 << 0) |
| 167 | |
| 168 | /* |
| 169 | * LB_BASE0,1 register bits (Local bus -> PCI) |
| 170 | */ |
| 171 | #define V3_LB_BASE_ADR_BASE 0xfff00000 |
| 172 | #define V3_LB_BASE_SWAP (3 << 8) |
| 173 | #define V3_LB_BASE_ADR_SIZE (15 << 4) |
| 174 | #define V3_LB_BASE_PREFETCH (1 << 3) |
| 175 | #define V3_LB_BASE_ENABLE (1 << 0) |
| 176 | |
| 177 | #define V3_LB_BASE_ADR_SIZE_1MB (0 << 4) |
| 178 | #define V3_LB_BASE_ADR_SIZE_2MB (1 << 4) |
| 179 | #define V3_LB_BASE_ADR_SIZE_4MB (2 << 4) |
| 180 | #define V3_LB_BASE_ADR_SIZE_8MB (3 << 4) |
| 181 | #define V3_LB_BASE_ADR_SIZE_16MB (4 << 4) |
| 182 | #define V3_LB_BASE_ADR_SIZE_32MB (5 << 4) |
| 183 | #define V3_LB_BASE_ADR_SIZE_64MB (6 << 4) |
| 184 | #define V3_LB_BASE_ADR_SIZE_128MB (7 << 4) |
| 185 | #define V3_LB_BASE_ADR_SIZE_256MB (8 << 4) |
| 186 | #define V3_LB_BASE_ADR_SIZE_512MB (9 << 4) |
| 187 | #define V3_LB_BASE_ADR_SIZE_1GB (10 << 4) |
| 188 | #define V3_LB_BASE_ADR_SIZE_2GB (11 << 4) |
| 189 | |
| 190 | #define v3_addr_to_lb_base(a) ((a) & V3_LB_BASE_ADR_BASE) |
| 191 | |
| 192 | /* |
| 193 | * LB_MAP0,1 register bits (Local bus -> PCI) |
| 194 | */ |
| 195 | #define V3_LB_MAP_MAP_ADR 0xfff0 |
| 196 | #define V3_LB_MAP_TYPE (7 << 1) |
| 197 | #define V3_LB_MAP_AD_LOW_EN (1 << 0) |
| 198 | |
| 199 | #define V3_LB_MAP_TYPE_IACK (0 << 1) |
| 200 | #define V3_LB_MAP_TYPE_IO (1 << 1) |
| 201 | #define V3_LB_MAP_TYPE_MEM (3 << 1) |
| 202 | #define V3_LB_MAP_TYPE_CONFIG (5 << 1) |
| 203 | #define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1) |
| 204 | |
| 205 | #define v3_addr_to_lb_map(a) (((a) >> 16) & V3_LB_MAP_MAP_ADR) |
| 206 | |
| 207 | /* |
| 208 | * LB_BASE2 register bits (Local bus -> PCI IO) |
| 209 | */ |
| 210 | #define V3_LB_BASE2_ADR_BASE 0xff00 |
| 211 | #define V3_LB_BASE2_SWAP (3 << 6) |
| 212 | #define V3_LB_BASE2_ENABLE (1 << 0) |
| 213 | |
| 214 | #define v3_addr_to_lb_base2(a) (((a) >> 16) & V3_LB_BASE2_ADR_BASE) |
| 215 | |
| 216 | /* |
| 217 | * LB_MAP2 register bits (Local bus -> PCI IO) |
| 218 | */ |
| 219 | #define V3_LB_MAP2_MAP_ADR 0xff00 |
| 220 | |
| 221 | #define v3_addr_to_lb_map2(a) (((a) >> 16) & V3_LB_MAP2_MAP_ADR) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 222 | |
| 223 | /* |
| 224 | * The V3 PCI interface chip in Integrator provides several windows from |
| 225 | * local bus memory into the PCI memory areas. Unfortunately, there |
Rob Herring | 29d3960 | 2012-07-13 16:27:43 -0500 | [diff] [blame] | 226 | * are not really enough windows for our usage, therefore we reuse |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 227 | * one of the windows for access to PCI configuration space. The |
| 228 | * memory map is as follows: |
Rob Herring | 29d3960 | 2012-07-13 16:27:43 -0500 | [diff] [blame] | 229 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 230 | * Local Bus Memory Usage |
Rob Herring | 29d3960 | 2012-07-13 16:27:43 -0500 | [diff] [blame] | 231 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 232 | * 40000000 - 4FFFFFFF PCI memory. 256M non-prefetchable |
| 233 | * 50000000 - 5FFFFFFF PCI memory. 256M prefetchable |
| 234 | * 60000000 - 60FFFFFF PCI IO. 16M |
| 235 | * 61000000 - 61FFFFFF PCI Configuration. 16M |
Rob Herring | 29d3960 | 2012-07-13 16:27:43 -0500 | [diff] [blame] | 236 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 237 | * There are three V3 windows, each described by a pair of V3 registers. |
| 238 | * These are LB_BASE0/LB_MAP0, LB_BASE1/LB_MAP1 and LB_BASE2/LB_MAP2. |
| 239 | * Base0 and Base1 can be used for any type of PCI memory access. Base2 |
| 240 | * can be used either for PCI I/O or for I20 accesses. By default, uHAL |
| 241 | * uses this only for PCI IO space. |
Rob Herring | 29d3960 | 2012-07-13 16:27:43 -0500 | [diff] [blame] | 242 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 243 | * Normally these spaces are mapped using the following base registers: |
Rob Herring | 29d3960 | 2012-07-13 16:27:43 -0500 | [diff] [blame] | 244 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 245 | * Usage Local Bus Memory Base/Map registers used |
Rob Herring | 29d3960 | 2012-07-13 16:27:43 -0500 | [diff] [blame] | 246 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 247 | * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0 |
| 248 | * Mem 50000000 - 5FFFFFFF LB_BASE1/LB_MAP1 |
| 249 | * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2 |
| 250 | * Cfg 61000000 - 61FFFFFF |
Rob Herring | 29d3960 | 2012-07-13 16:27:43 -0500 | [diff] [blame] | 251 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 252 | * This means that I20 and PCI configuration space accesses will fail. |
Rob Herring | 29d3960 | 2012-07-13 16:27:43 -0500 | [diff] [blame] | 253 | * When PCI configuration accesses are needed (via the uHAL PCI |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 254 | * configuration space primitives) we must remap the spaces as follows: |
Rob Herring | 29d3960 | 2012-07-13 16:27:43 -0500 | [diff] [blame] | 255 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 256 | * Usage Local Bus Memory Base/Map registers used |
Rob Herring | 29d3960 | 2012-07-13 16:27:43 -0500 | [diff] [blame] | 257 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 258 | * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0 |
| 259 | * Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0 |
| 260 | * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2 |
| 261 | * Cfg 61000000 - 61FFFFFF LB_BASE1/LB_MAP1 |
Rob Herring | 29d3960 | 2012-07-13 16:27:43 -0500 | [diff] [blame] | 262 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 263 | * To make this work, the code depends on overlapping windows working. |
Rob Herring | 29d3960 | 2012-07-13 16:27:43 -0500 | [diff] [blame] | 264 | * The V3 chip translates an address by checking its range within |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 265 | * each of the BASE/MAP pairs in turn (in ascending register number |
| 266 | * order). It will use the first matching pair. So, for example, |
| 267 | * if the same address is mapped by both LB_BASE0/LB_MAP0 and |
Rob Herring | 29d3960 | 2012-07-13 16:27:43 -0500 | [diff] [blame] | 268 | * LB_BASE1/LB_MAP1, the V3 will use the translation from |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 269 | * LB_BASE0/LB_MAP0. |
Rob Herring | 29d3960 | 2012-07-13 16:27:43 -0500 | [diff] [blame] | 270 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 271 | * To allow PCI Configuration space access, the code enlarges the |
| 272 | * window mapped by LB_BASE0/LB_MAP0 from 256M to 512M. This occludes |
| 273 | * the windows currently mapped by LB_BASE1/LB_MAP1 so that it can |
| 274 | * be remapped for use by configuration cycles. |
Rob Herring | 29d3960 | 2012-07-13 16:27:43 -0500 | [diff] [blame] | 275 | * |
| 276 | * At the end of the PCI Configuration space accesses, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 277 | * LB_BASE1/LB_MAP1 is reset to map PCI Memory. Finally the window |
| 278 | * mapped by LB_BASE0/LB_MAP0 is reduced in size from 512M to 256M to |
| 279 | * reveal the now restored LB_BASE1/LB_MAP1 window. |
Rob Herring | 29d3960 | 2012-07-13 16:27:43 -0500 | [diff] [blame] | 280 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 281 | * NOTE: We do not set up I2O mapping. I suspect that this is only |
| 282 | * for an intelligent (target) device. Using I2O disables most of |
| 283 | * the mappings into PCI memory. |
| 284 | */ |
| 285 | |
Linus Walleij | f55b2b5 | 2013-03-01 02:20:55 +0100 | [diff] [blame^] | 286 | /* Filled in by probe */ |
Linus Walleij | a5ecbab | 2013-03-16 21:51:02 +0100 | [diff] [blame] | 287 | static void __iomem *pci_v3_base; |
Linus Walleij | f55b2b5 | 2013-03-01 02:20:55 +0100 | [diff] [blame^] | 288 | static struct resource conf_mem; /* FIXME: remap this instead of static map */ |
| 289 | static struct resource io_mem; |
| 290 | static struct resource non_mem; |
| 291 | static struct resource pre_mem; |
Linus Walleij | a5ecbab | 2013-03-16 21:51:02 +0100 | [diff] [blame] | 292 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 293 | // V3 access routines |
Linus Walleij | a5ecbab | 2013-03-16 21:51:02 +0100 | [diff] [blame] | 294 | #define v3_writeb(o,v) __raw_writeb(v, pci_v3_base + (unsigned int)(o)) |
| 295 | #define v3_readb(o) (__raw_readb(pci_v3_base + (unsigned int)(o))) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 296 | |
Linus Walleij | a5ecbab | 2013-03-16 21:51:02 +0100 | [diff] [blame] | 297 | #define v3_writew(o,v) __raw_writew(v, pci_v3_base + (unsigned int)(o)) |
| 298 | #define v3_readw(o) (__raw_readw(pci_v3_base + (unsigned int)(o))) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 299 | |
Linus Walleij | a5ecbab | 2013-03-16 21:51:02 +0100 | [diff] [blame] | 300 | #define v3_writel(o,v) __raw_writel(v, pci_v3_base + (unsigned int)(o)) |
| 301 | #define v3_readl(o) (__raw_readl(pci_v3_base + (unsigned int)(o))) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 302 | |
| 303 | /*============================================================================ |
| 304 | * |
| 305 | * routine: uHALir_PCIMakeConfigAddress() |
| 306 | * |
| 307 | * parameters: bus = which bus |
| 308 | * device = which device |
| 309 | * function = which function |
| 310 | * offset = configuration space register we are interested in |
| 311 | * |
| 312 | * description: this routine will generate a platform dependent config |
| 313 | * address. |
| 314 | * |
| 315 | * calls: none |
| 316 | * |
| 317 | * returns: configuration address to play on the PCI bus |
| 318 | * |
Rob Herring | 29d3960 | 2012-07-13 16:27:43 -0500 | [diff] [blame] | 319 | * To generate the appropriate PCI configuration cycles in the PCI |
| 320 | * configuration address space, you present the V3 with the following pattern |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 321 | * (which is very nearly a type 1 (except that the lower two bits are 00 and |
| 322 | * not 01). In order for this mapping to work you need to set up one of |
| 323 | * the local to PCI aperatures to 16Mbytes in length translating to |
| 324 | * PCI configuration space starting at 0x0000.0000. |
| 325 | * |
| 326 | * PCI configuration cycles look like this: |
| 327 | * |
| 328 | * Type 0: |
| 329 | * |
Rob Herring | 29d3960 | 2012-07-13 16:27:43 -0500 | [diff] [blame] | 330 | * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 331 | * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 |
| 332 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ |
| 333 | * | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0| |
| 334 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ |
| 335 | * |
| 336 | * 31:11 Device select bit. |
| 337 | * 10:8 Function number |
| 338 | * 7:2 Register number |
| 339 | * |
| 340 | * Type 1: |
| 341 | * |
Rob Herring | 29d3960 | 2012-07-13 16:27:43 -0500 | [diff] [blame] | 342 | * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 343 | * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 |
| 344 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ |
| 345 | * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1| |
| 346 | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ |
| 347 | * |
| 348 | * 31:24 reserved |
| 349 | * 23:16 bus number (8 bits = 128 possible buses) |
| 350 | * 15:11 Device number (5 bits) |
| 351 | * 10:8 function number |
| 352 | * 7:2 register number |
Rob Herring | 29d3960 | 2012-07-13 16:27:43 -0500 | [diff] [blame] | 353 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 354 | */ |
Thomas Gleixner | bd31b85 | 2009-07-03 08:44:46 -0500 | [diff] [blame] | 355 | static DEFINE_RAW_SPINLOCK(v3_lock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 356 | |
| 357 | #define PCI_BUS_NONMEM_START 0x00000000 |
| 358 | #define PCI_BUS_NONMEM_SIZE SZ_256M |
| 359 | |
| 360 | #define PCI_BUS_PREMEM_START PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE |
| 361 | #define PCI_BUS_PREMEM_SIZE SZ_256M |
| 362 | |
| 363 | #if PCI_BUS_NONMEM_START & 0x000fffff |
| 364 | #error PCI_BUS_NONMEM_START must be megabyte aligned |
| 365 | #endif |
| 366 | #if PCI_BUS_PREMEM_START & 0x000fffff |
| 367 | #error PCI_BUS_PREMEM_START must be megabyte aligned |
| 368 | #endif |
| 369 | |
| 370 | #undef V3_LB_BASE_PREFETCH |
| 371 | #define V3_LB_BASE_PREFETCH 0 |
| 372 | |
Arnd Bergmann | b7a3f8d | 2012-09-14 20:16:39 +0000 | [diff] [blame] | 373 | static void __iomem *v3_open_config_window(struct pci_bus *bus, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 374 | unsigned int devfn, int offset) |
| 375 | { |
| 376 | unsigned int address, mapaddress, busnr; |
| 377 | |
| 378 | busnr = bus->number; |
| 379 | |
| 380 | /* |
| 381 | * Trap out illegal values |
| 382 | */ |
Sasha Levin | f7a9b36 | 2012-11-08 15:23:08 -0500 | [diff] [blame] | 383 | BUG_ON(offset > 255); |
| 384 | BUG_ON(busnr > 255); |
| 385 | BUG_ON(devfn > 255); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 386 | |
| 387 | if (busnr == 0) { |
| 388 | int slot = PCI_SLOT(devfn); |
| 389 | |
| 390 | /* |
| 391 | * local bus segment so need a type 0 config cycle |
| 392 | * |
| 393 | * build the PCI configuration "address" with one-hot in |
| 394 | * A31-A11 |
| 395 | * |
| 396 | * mapaddress: |
| 397 | * 3:1 = config cycle (101) |
| 398 | * 0 = PCI A1 & A0 are 0 (0) |
| 399 | */ |
| 400 | address = PCI_FUNC(devfn) << 8; |
| 401 | mapaddress = V3_LB_MAP_TYPE_CONFIG; |
| 402 | |
| 403 | if (slot > 12) |
| 404 | /* |
| 405 | * high order bits are handled by the MAP register |
| 406 | */ |
| 407 | mapaddress |= 1 << (slot - 5); |
| 408 | else |
| 409 | /* |
| 410 | * low order bits handled directly in the address |
| 411 | */ |
| 412 | address |= 1 << (slot + 11); |
| 413 | } else { |
| 414 | /* |
| 415 | * not the local bus segment so need a type 1 config cycle |
| 416 | * |
| 417 | * address: |
| 418 | * 23:16 = bus number |
| 419 | * 15:11 = slot number (7:3 of devfn) |
| 420 | * 10:8 = func number (2:0 of devfn) |
| 421 | * |
| 422 | * mapaddress: |
| 423 | * 3:1 = config cycle (101) |
| 424 | * 0 = PCI A1 & A0 from host bus (1) |
| 425 | */ |
| 426 | mapaddress = V3_LB_MAP_TYPE_CONFIG | V3_LB_MAP_AD_LOW_EN; |
| 427 | address = (busnr << 16) | (devfn << 8); |
| 428 | } |
| 429 | |
| 430 | /* |
| 431 | * Set up base0 to see all 512Mbytes of memory space (not |
| 432 | * prefetchable), this frees up base1 for re-use by |
| 433 | * configuration memory |
| 434 | */ |
Linus Walleij | f55b2b5 | 2013-03-01 02:20:55 +0100 | [diff] [blame^] | 435 | v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(non_mem.start) | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 436 | V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE); |
| 437 | |
| 438 | /* |
| 439 | * Set up base1/map1 to point into configuration space. |
| 440 | */ |
Linus Walleij | f55b2b5 | 2013-03-01 02:20:55 +0100 | [diff] [blame^] | 441 | v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(conf_mem.start) | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 442 | V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE); |
| 443 | v3_writew(V3_LB_MAP1, mapaddress); |
| 444 | |
| 445 | return PCI_CONFIG_VADDR + address + offset; |
| 446 | } |
| 447 | |
| 448 | static void v3_close_config_window(void) |
| 449 | { |
| 450 | /* |
| 451 | * Reassign base1 for use by prefetchable PCI memory |
| 452 | */ |
Linus Walleij | f55b2b5 | 2013-03-01 02:20:55 +0100 | [diff] [blame^] | 453 | v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(pre_mem.start) | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 454 | V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH | |
| 455 | V3_LB_BASE_ENABLE); |
| 456 | v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) | |
| 457 | V3_LB_MAP_TYPE_MEM_MULTIPLE); |
| 458 | |
| 459 | /* |
| 460 | * And shrink base0 back to a 256M window (NOTE: MAP0 already correct) |
| 461 | */ |
Linus Walleij | f55b2b5 | 2013-03-01 02:20:55 +0100 | [diff] [blame^] | 462 | v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(non_mem.start) | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 463 | V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE); |
| 464 | } |
| 465 | |
| 466 | static int v3_read_config(struct pci_bus *bus, unsigned int devfn, int where, |
| 467 | int size, u32 *val) |
| 468 | { |
Arnd Bergmann | b7a3f8d | 2012-09-14 20:16:39 +0000 | [diff] [blame] | 469 | void __iomem *addr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 470 | unsigned long flags; |
| 471 | u32 v; |
| 472 | |
Thomas Gleixner | bd31b85 | 2009-07-03 08:44:46 -0500 | [diff] [blame] | 473 | raw_spin_lock_irqsave(&v3_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 474 | addr = v3_open_config_window(bus, devfn, where); |
| 475 | |
| 476 | switch (size) { |
| 477 | case 1: |
| 478 | v = __raw_readb(addr); |
| 479 | break; |
| 480 | |
| 481 | case 2: |
| 482 | v = __raw_readw(addr); |
| 483 | break; |
| 484 | |
| 485 | default: |
| 486 | v = __raw_readl(addr); |
| 487 | break; |
| 488 | } |
| 489 | |
| 490 | v3_close_config_window(); |
Thomas Gleixner | bd31b85 | 2009-07-03 08:44:46 -0500 | [diff] [blame] | 491 | raw_spin_unlock_irqrestore(&v3_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 492 | |
| 493 | *val = v; |
| 494 | return PCIBIOS_SUCCESSFUL; |
| 495 | } |
| 496 | |
| 497 | static int v3_write_config(struct pci_bus *bus, unsigned int devfn, int where, |
| 498 | int size, u32 val) |
| 499 | { |
Arnd Bergmann | b7a3f8d | 2012-09-14 20:16:39 +0000 | [diff] [blame] | 500 | void __iomem *addr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 501 | unsigned long flags; |
| 502 | |
Thomas Gleixner | bd31b85 | 2009-07-03 08:44:46 -0500 | [diff] [blame] | 503 | raw_spin_lock_irqsave(&v3_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 504 | addr = v3_open_config_window(bus, devfn, where); |
| 505 | |
| 506 | switch (size) { |
| 507 | case 1: |
| 508 | __raw_writeb((u8)val, addr); |
| 509 | __raw_readb(addr); |
| 510 | break; |
| 511 | |
| 512 | case 2: |
| 513 | __raw_writew((u16)val, addr); |
| 514 | __raw_readw(addr); |
| 515 | break; |
| 516 | |
| 517 | case 4: |
| 518 | __raw_writel(val, addr); |
| 519 | __raw_readl(addr); |
| 520 | break; |
| 521 | } |
| 522 | |
| 523 | v3_close_config_window(); |
Thomas Gleixner | bd31b85 | 2009-07-03 08:44:46 -0500 | [diff] [blame] | 524 | raw_spin_unlock_irqrestore(&v3_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 525 | |
| 526 | return PCIBIOS_SUCCESSFUL; |
| 527 | } |
| 528 | |
Linus Walleij | f4bc4f0 | 2013-01-29 17:14:18 +0100 | [diff] [blame] | 529 | static struct pci_ops pci_v3_ops = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 530 | .read = v3_read_config, |
| 531 | .write = v3_write_config, |
| 532 | }; |
| 533 | |
Bjorn Helgaas | 37d1590 | 2011-10-28 16:26:16 -0600 | [diff] [blame] | 534 | static int __init pci_v3_setup_resources(struct pci_sys_data *sys) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 535 | { |
| 536 | if (request_resource(&iomem_resource, &non_mem)) { |
| 537 | printk(KERN_ERR "PCI: unable to allocate non-prefetchable " |
| 538 | "memory region\n"); |
| 539 | return -EBUSY; |
| 540 | } |
| 541 | if (request_resource(&iomem_resource, &pre_mem)) { |
| 542 | release_resource(&non_mem); |
| 543 | printk(KERN_ERR "PCI: unable to allocate prefetchable " |
| 544 | "memory region\n"); |
| 545 | return -EBUSY; |
| 546 | } |
| 547 | |
| 548 | /* |
Bjorn Helgaas | 37d1590 | 2011-10-28 16:26:16 -0600 | [diff] [blame] | 549 | * the mem resource for this bus |
| 550 | * the prefetch mem resource for this bus |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 551 | */ |
Bjorn Helgaas | 9f786d0 | 2012-02-23 20:19:01 -0700 | [diff] [blame] | 552 | pci_add_resource_offset(&sys->resources, &non_mem, sys->mem_offset); |
| 553 | pci_add_resource_offset(&sys->resources, &pre_mem, sys->mem_offset); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 554 | |
| 555 | return 1; |
| 556 | } |
| 557 | |
| 558 | /* |
| 559 | * These don't seem to be implemented on the Integrator I have, which |
| 560 | * means I can't get additional information on the reason for the pm2fb |
| 561 | * problems. I suppose I'll just have to mind-meld with the machine. ;) |
| 562 | */ |
Linus Walleij | 379df27 | 2012-11-17 19:24:23 +0100 | [diff] [blame] | 563 | static void __iomem *ap_syscon_base; |
| 564 | #define INTEGRATOR_SC_PCIENABLE_OFFSET 0x18 |
| 565 | #define INTEGRATOR_SC_LBFADDR_OFFSET 0x20 |
| 566 | #define INTEGRATOR_SC_LBFCODE_OFFSET 0x24 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 567 | |
| 568 | static int |
| 569 | v3_pci_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs) |
| 570 | { |
| 571 | unsigned long pc = instruction_pointer(regs); |
| 572 | unsigned long instr = *(unsigned long *)pc; |
| 573 | #if 0 |
| 574 | char buf[128]; |
| 575 | |
| 576 | sprintf(buf, "V3 fault: addr 0x%08lx, FSR 0x%03x, PC 0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x ISTAT=%02x\n", |
Linus Walleij | 379df27 | 2012-11-17 19:24:23 +0100 | [diff] [blame] | 577 | addr, fsr, pc, instr, __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFADDR_OFFSET), __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFCODE_OFFSET) & 255, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 578 | v3_readb(V3_LB_ISTAT)); |
| 579 | printk(KERN_DEBUG "%s", buf); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 580 | #endif |
| 581 | |
| 582 | v3_writeb(V3_LB_ISTAT, 0); |
Linus Walleij | 379df27 | 2012-11-17 19:24:23 +0100 | [diff] [blame] | 583 | __raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 584 | |
| 585 | /* |
| 586 | * If the instruction being executed was a read, |
| 587 | * make it look like it read all-ones. |
| 588 | */ |
| 589 | if ((instr & 0x0c100000) == 0x04100000) { |
| 590 | int reg = (instr >> 12) & 15; |
| 591 | unsigned long val; |
| 592 | |
| 593 | if (instr & 0x00400000) |
| 594 | val = 255; |
| 595 | else |
| 596 | val = -1; |
| 597 | |
| 598 | regs->uregs[reg] = val; |
| 599 | regs->ARM_pc += 4; |
| 600 | return 0; |
| 601 | } |
| 602 | |
| 603 | if ((instr & 0x0e100090) == 0x00100090) { |
| 604 | int reg = (instr >> 12) & 15; |
| 605 | |
| 606 | regs->uregs[reg] = -1; |
| 607 | regs->ARM_pc += 4; |
| 608 | return 0; |
| 609 | } |
| 610 | |
| 611 | return 1; |
| 612 | } |
| 613 | |
Jeff Garzik | e8f2af1 | 2007-10-26 05:40:25 -0400 | [diff] [blame] | 614 | static irqreturn_t v3_irq(int dummy, void *devid) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 615 | { |
| 616 | #ifdef CONFIG_DEBUG_LL |
Linus Torvalds | 0cd61b6 | 2006-10-06 10:53:39 -0700 | [diff] [blame] | 617 | struct pt_regs *regs = get_irq_regs(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 618 | unsigned long pc = instruction_pointer(regs); |
| 619 | unsigned long instr = *(unsigned long *)pc; |
| 620 | char buf[128]; |
Russell King | 7c28472 | 2008-05-23 19:35:52 +0100 | [diff] [blame] | 621 | extern void printascii(const char *); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 622 | |
Jeff Garzik | e8f2af1 | 2007-10-26 05:40:25 -0400 | [diff] [blame] | 623 | sprintf(buf, "V3 int %d: pc=0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x " |
| 624 | "ISTAT=%02x\n", IRQ_AP_V3INT, pc, instr, |
Linus Walleij | 379df27 | 2012-11-17 19:24:23 +0100 | [diff] [blame] | 625 | __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFADDR_OFFSET), |
| 626 | __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFCODE_OFFSET) & 255, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 627 | v3_readb(V3_LB_ISTAT)); |
| 628 | printascii(buf); |
| 629 | #endif |
| 630 | |
| 631 | v3_writew(V3_PCI_STAT, 0xf000); |
| 632 | v3_writeb(V3_LB_ISTAT, 0); |
Linus Walleij | 379df27 | 2012-11-17 19:24:23 +0100 | [diff] [blame] | 633 | __raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 634 | |
| 635 | #ifdef CONFIG_DEBUG_LL |
| 636 | /* |
| 637 | * If the instruction being executed was a read, |
| 638 | * make it look like it read all-ones. |
| 639 | */ |
| 640 | if ((instr & 0x0c100000) == 0x04100000) { |
| 641 | int reg = (instr >> 16) & 15; |
| 642 | sprintf(buf, " reg%d = %08lx\n", reg, regs->uregs[reg]); |
| 643 | printascii(buf); |
| 644 | } |
| 645 | #endif |
| 646 | return IRQ_HANDLED; |
| 647 | } |
| 648 | |
Linus Walleij | f4bc4f0 | 2013-01-29 17:14:18 +0100 | [diff] [blame] | 649 | static int __init pci_v3_setup(int nr, struct pci_sys_data *sys) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 650 | { |
| 651 | int ret = 0; |
| 652 | |
Linus Walleij | 67c6b2e | 2013-01-10 10:18:49 +0100 | [diff] [blame] | 653 | if (!ap_syscon_base) |
| 654 | return -EINVAL; |
| 655 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 656 | if (nr == 0) { |
Linus Walleij | f55b2b5 | 2013-03-01 02:20:55 +0100 | [diff] [blame^] | 657 | sys->mem_offset = non_mem.start; |
Bjorn Helgaas | 37d1590 | 2011-10-28 16:26:16 -0600 | [diff] [blame] | 658 | ret = pci_v3_setup_resources(sys); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 659 | } |
| 660 | |
| 661 | return ret; |
| 662 | } |
| 663 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 664 | /* |
| 665 | * V3_LB_BASE? - local bus address |
| 666 | * V3_LB_MAP? - pci bus address |
| 667 | */ |
Linus Walleij | f4bc4f0 | 2013-01-29 17:14:18 +0100 | [diff] [blame] | 668 | static void __init pci_v3_preinit(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 669 | { |
| 670 | unsigned long flags; |
| 671 | unsigned int temp; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 672 | |
Rob Herring | c9d95fb | 2011-06-28 21:16:13 -0500 | [diff] [blame] | 673 | pcibios_min_mem = 0x00100000; |
| 674 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 675 | /* |
| 676 | * Hook in our fault handler for PCI errors |
| 677 | */ |
Kirill A. Shutemov | 6338a6a | 2010-07-22 13:18:19 +0100 | [diff] [blame] | 678 | hook_fault_code(4, v3_pci_fault, SIGBUS, 0, "external abort on linefetch"); |
| 679 | hook_fault_code(6, v3_pci_fault, SIGBUS, 0, "external abort on linefetch"); |
| 680 | hook_fault_code(8, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch"); |
| 681 | hook_fault_code(10, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 682 | |
Thomas Gleixner | bd31b85 | 2009-07-03 08:44:46 -0500 | [diff] [blame] | 683 | raw_spin_lock_irqsave(&v3_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 684 | |
| 685 | /* |
| 686 | * Unlock V3 registers, but only if they were previously locked. |
| 687 | */ |
| 688 | if (v3_readw(V3_SYSTEM) & V3_SYSTEM_M_LOCK) |
| 689 | v3_writew(V3_SYSTEM, 0xa05f); |
| 690 | |
| 691 | /* |
| 692 | * Setup window 0 - PCI non-prefetchable memory |
| 693 | * Local: 0x40000000 Bus: 0x00000000 Size: 256MB |
| 694 | */ |
Linus Walleij | f55b2b5 | 2013-03-01 02:20:55 +0100 | [diff] [blame^] | 695 | v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(non_mem.start) | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 696 | V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE); |
| 697 | v3_writew(V3_LB_MAP0, v3_addr_to_lb_map(PCI_BUS_NONMEM_START) | |
| 698 | V3_LB_MAP_TYPE_MEM); |
| 699 | |
| 700 | /* |
| 701 | * Setup window 1 - PCI prefetchable memory |
| 702 | * Local: 0x50000000 Bus: 0x10000000 Size: 256MB |
| 703 | */ |
Linus Walleij | f55b2b5 | 2013-03-01 02:20:55 +0100 | [diff] [blame^] | 704 | v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(pre_mem.start) | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 705 | V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH | |
| 706 | V3_LB_BASE_ENABLE); |
| 707 | v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) | |
| 708 | V3_LB_MAP_TYPE_MEM_MULTIPLE); |
| 709 | |
| 710 | /* |
| 711 | * Setup window 2 - PCI IO |
| 712 | */ |
Linus Walleij | f55b2b5 | 2013-03-01 02:20:55 +0100 | [diff] [blame^] | 713 | v3_writel(V3_LB_BASE2, v3_addr_to_lb_base2(io_mem.start) | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 714 | V3_LB_BASE_ENABLE); |
| 715 | v3_writew(V3_LB_MAP2, v3_addr_to_lb_map2(0)); |
| 716 | |
| 717 | /* |
| 718 | * Disable PCI to host IO cycles |
| 719 | */ |
| 720 | temp = v3_readw(V3_PCI_CFG) & ~V3_PCI_CFG_M_I2O_EN; |
| 721 | temp |= V3_PCI_CFG_M_IO_REG_DIS | V3_PCI_CFG_M_IO_DIS; |
| 722 | v3_writew(V3_PCI_CFG, temp); |
| 723 | |
| 724 | printk(KERN_DEBUG "FIFO_CFG: %04x FIFO_PRIO: %04x\n", |
| 725 | v3_readw(V3_FIFO_CFG), v3_readw(V3_FIFO_PRIORITY)); |
| 726 | |
| 727 | /* |
| 728 | * Set the V3 FIFO such that writes have higher priority than |
| 729 | * reads, and local bus write causes local bus read fifo flush. |
| 730 | * Same for PCI. |
| 731 | */ |
| 732 | v3_writew(V3_FIFO_PRIORITY, 0x0a0a); |
| 733 | |
| 734 | /* |
| 735 | * Re-lock the system register. |
| 736 | */ |
| 737 | temp = v3_readw(V3_SYSTEM) | V3_SYSTEM_M_LOCK; |
| 738 | v3_writew(V3_SYSTEM, temp); |
| 739 | |
| 740 | /* |
| 741 | * Clear any error conditions, and enable write errors. |
| 742 | */ |
| 743 | v3_writeb(V3_LB_ISTAT, 0); |
| 744 | v3_writew(V3_LB_CFG, v3_readw(V3_LB_CFG) | (1 << 10)); |
| 745 | v3_writeb(V3_LB_IMASK, 0x28); |
Linus Walleij | 379df27 | 2012-11-17 19:24:23 +0100 | [diff] [blame] | 746 | __raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 747 | |
Thomas Gleixner | bd31b85 | 2009-07-03 08:44:46 -0500 | [diff] [blame] | 748 | raw_spin_unlock_irqrestore(&v3_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 749 | } |
| 750 | |
Linus Walleij | f4bc4f0 | 2013-01-29 17:14:18 +0100 | [diff] [blame] | 751 | static void __init pci_v3_postinit(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 752 | { |
| 753 | unsigned int pci_cmd; |
| 754 | |
| 755 | pci_cmd = PCI_COMMAND_MEMORY | |
| 756 | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE; |
| 757 | |
| 758 | v3_writew(V3_PCI_CMD, pci_cmd); |
| 759 | |
| 760 | v3_writeb(V3_LB_ISTAT, ~0x40); |
| 761 | v3_writeb(V3_LB_IMASK, 0x68); |
| 762 | |
| 763 | #if 0 |
| 764 | ret = request_irq(IRQ_AP_LBUSTIMEOUT, lb_timeout, 0, "bus timeout", NULL); |
| 765 | if (ret) |
| 766 | printk(KERN_ERR "PCI: unable to grab local bus timeout " |
| 767 | "interrupt: %d\n", ret); |
| 768 | #endif |
Russell King | 863dab4 | 2006-08-28 12:47:05 +0100 | [diff] [blame] | 769 | |
Linus Walleij | f55b2b5 | 2013-03-01 02:20:55 +0100 | [diff] [blame^] | 770 | register_isa_ports(non_mem.start, io_mem.start, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 771 | } |
Linus Walleij | f4bc4f0 | 2013-01-29 17:14:18 +0100 | [diff] [blame] | 772 | |
| 773 | /* |
| 774 | * A small note about bridges and interrupts. The DECchip 21050 (and |
| 775 | * later) adheres to the PCI-PCI bridge specification. This says that |
| 776 | * the interrupts on the other side of a bridge are swizzled in the |
| 777 | * following manner: |
| 778 | * |
| 779 | * Dev Interrupt Interrupt |
| 780 | * Pin on Pin on |
| 781 | * Device Connector |
| 782 | * |
| 783 | * 4 A A |
| 784 | * B B |
| 785 | * C C |
| 786 | * D D |
| 787 | * |
| 788 | * 5 A B |
| 789 | * B C |
| 790 | * C D |
| 791 | * D A |
| 792 | * |
| 793 | * 6 A C |
| 794 | * B D |
| 795 | * C A |
| 796 | * D B |
| 797 | * |
| 798 | * 7 A D |
| 799 | * B A |
| 800 | * C B |
| 801 | * D C |
| 802 | * |
| 803 | * Where A = pin 1, B = pin 2 and so on and pin=0 = default = A. |
| 804 | * Thus, each swizzle is ((pin-1) + (device#-4)) % 4 |
| 805 | */ |
| 806 | |
| 807 | /* |
| 808 | * This routine handles multiple bridges. |
| 809 | */ |
Linus Walleij | 86adc39 | 2013-02-02 23:16:57 +0100 | [diff] [blame] | 810 | static u8 __init pci_v3_swizzle(struct pci_dev *dev, u8 *pinp) |
Linus Walleij | f4bc4f0 | 2013-01-29 17:14:18 +0100 | [diff] [blame] | 811 | { |
| 812 | if (*pinp == 0) |
| 813 | *pinp = 1; |
| 814 | |
| 815 | return pci_common_swizzle(dev, pinp); |
| 816 | } |
| 817 | |
| 818 | static int irq_tab[4] __initdata = { |
| 819 | IRQ_AP_PCIINT0, IRQ_AP_PCIINT1, IRQ_AP_PCIINT2, IRQ_AP_PCIINT3 |
| 820 | }; |
| 821 | |
| 822 | /* |
| 823 | * map the specified device/slot/pin to an IRQ. This works out such |
| 824 | * that slot 9 pin 1 is INT0, pin 2 is INT1, and slot 10 pin 1 is INT1. |
| 825 | */ |
Linus Walleij | 86adc39 | 2013-02-02 23:16:57 +0100 | [diff] [blame] | 826 | static int __init pci_v3_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
Linus Walleij | f4bc4f0 | 2013-01-29 17:14:18 +0100 | [diff] [blame] | 827 | { |
| 828 | int intnr = ((slot - 9) + (pin - 1)) & 3; |
| 829 | |
| 830 | return irq_tab[intnr]; |
| 831 | } |
| 832 | |
Linus Walleij | 86adc39 | 2013-02-02 23:16:57 +0100 | [diff] [blame] | 833 | static struct hw_pci pci_v3 __initdata = { |
| 834 | .swizzle = pci_v3_swizzle, |
Linus Walleij | f4bc4f0 | 2013-01-29 17:14:18 +0100 | [diff] [blame] | 835 | .setup = pci_v3_setup, |
| 836 | .nr_controllers = 1, |
| 837 | .ops = &pci_v3_ops, |
| 838 | .preinit = pci_v3_preinit, |
| 839 | .postinit = pci_v3_postinit, |
| 840 | }; |
| 841 | |
Linus Walleij | f55b2b5 | 2013-03-01 02:20:55 +0100 | [diff] [blame^] | 842 | #ifdef CONFIG_OF |
| 843 | |
| 844 | static int __init pci_v3_map_irq_dt(const struct pci_dev *dev, u8 slot, u8 pin) |
| 845 | { |
| 846 | struct of_irq oirq; |
| 847 | int ret; |
| 848 | |
| 849 | ret = of_irq_map_pci(dev, &oirq); |
| 850 | if (ret) { |
| 851 | dev_err(&dev->dev, "of_irq_map_pci() %d\n", ret); |
| 852 | /* Proper return code 0 == NO_IRQ */ |
| 853 | return 0; |
| 854 | } |
| 855 | |
| 856 | return irq_create_of_mapping(oirq.controller, oirq.specifier, |
| 857 | oirq.size); |
| 858 | } |
| 859 | |
| 860 | static int __init pci_v3_dtprobe(struct platform_device *pdev, |
| 861 | struct device_node *np) |
| 862 | { |
| 863 | struct of_pci_range_parser parser; |
| 864 | struct of_pci_range range; |
| 865 | struct resource *res; |
| 866 | int irq, ret; |
| 867 | |
| 868 | if (of_pci_range_parser_init(&parser, np)) |
| 869 | return -EINVAL; |
| 870 | |
| 871 | /* Get base for bridge registers */ |
| 872 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 873 | if (!res) { |
| 874 | dev_err(&pdev->dev, "unable to obtain PCIv3 base\n"); |
| 875 | return -ENODEV; |
| 876 | } |
| 877 | pci_v3_base = devm_ioremap(&pdev->dev, res->start, |
| 878 | resource_size(res)); |
| 879 | if (!pci_v3_base) { |
| 880 | dev_err(&pdev->dev, "unable to remap PCIv3 base\n"); |
| 881 | return -ENODEV; |
| 882 | } |
| 883 | |
| 884 | /* Get and request error IRQ resource */ |
| 885 | irq = platform_get_irq(pdev, 0); |
| 886 | if (irq <= 0) { |
| 887 | dev_err(&pdev->dev, "unable to obtain PCIv3 error IRQ\n"); |
| 888 | return -ENODEV; |
| 889 | } |
| 890 | ret = devm_request_irq(&pdev->dev, irq, v3_irq, 0, |
| 891 | "PCIv3 error", NULL); |
| 892 | if (ret < 0) { |
| 893 | dev_err(&pdev->dev, "unable to request PCIv3 error IRQ %d (%d)\n", irq, ret); |
| 894 | return ret; |
| 895 | } |
| 896 | |
| 897 | for_each_of_pci_range(&parser, &range) { |
| 898 | if (!range.flags) { |
| 899 | of_pci_range_to_resource(&range, np, &conf_mem); |
| 900 | conf_mem.name = "PCIv3 config"; |
| 901 | } |
| 902 | if (range.flags & IORESOURCE_IO) { |
| 903 | of_pci_range_to_resource(&range, np, &io_mem); |
| 904 | io_mem.name = "PCIv3 I/O"; |
| 905 | } |
| 906 | if ((range.flags & IORESOURCE_MEM) && |
| 907 | !(range.flags & IORESOURCE_PREFETCH)) { |
| 908 | of_pci_range_to_resource(&range, np, &non_mem); |
| 909 | non_mem.name = "PCIv3 non-prefetched mem"; |
| 910 | } |
| 911 | if ((range.flags & IORESOURCE_MEM) && |
| 912 | (range.flags & IORESOURCE_PREFETCH)) { |
| 913 | of_pci_range_to_resource(&range, np, &pre_mem); |
| 914 | pre_mem.name = "PCIv3 prefetched mem"; |
| 915 | } |
| 916 | } |
| 917 | |
| 918 | if (!conf_mem.start || !io_mem.start || |
| 919 | !non_mem.start || !pre_mem.start) { |
| 920 | dev_err(&pdev->dev, "missing ranges in device node\n"); |
| 921 | return -EINVAL; |
| 922 | } |
| 923 | |
| 924 | pci_v3.map_irq = pci_v3_map_irq_dt; |
| 925 | pci_common_init_dev(&pdev->dev, &pci_v3); |
| 926 | |
| 927 | return 0; |
| 928 | } |
| 929 | |
| 930 | #else |
| 931 | |
| 932 | static inline int pci_v3_dtprobe(struct platform_device *pdev, |
| 933 | struct device_node *np) |
| 934 | { |
| 935 | return -EINVAL; |
| 936 | } |
| 937 | |
| 938 | #endif |
| 939 | |
Linus Walleij | 86adc39 | 2013-02-02 23:16:57 +0100 | [diff] [blame] | 940 | static int __init pci_v3_probe(struct platform_device *pdev) |
Linus Walleij | f4bc4f0 | 2013-01-29 17:14:18 +0100 | [diff] [blame] | 941 | { |
Linus Walleij | f55b2b5 | 2013-03-01 02:20:55 +0100 | [diff] [blame^] | 942 | struct device_node *np = pdev->dev.of_node; |
Linus Walleij | 5283456 | 2013-04-04 14:02:57 +0200 | [diff] [blame] | 943 | int ret; |
| 944 | |
Linus Walleij | 03884f4 | 2013-02-03 00:06:04 +0100 | [diff] [blame] | 945 | /* Remap the Integrator system controller */ |
| 946 | ap_syscon_base = ioremap(INTEGRATOR_SC_BASE, 0x100); |
| 947 | if (!ap_syscon_base) { |
| 948 | dev_err(&pdev->dev, "unable to remap the AP syscon for PCIv3\n"); |
| 949 | return -ENODEV; |
| 950 | } |
| 951 | |
Linus Walleij | f55b2b5 | 2013-03-01 02:20:55 +0100 | [diff] [blame^] | 952 | /* Device tree probe path */ |
| 953 | if (np) |
| 954 | return pci_v3_dtprobe(pdev, np); |
| 955 | |
Linus Walleij | a5ecbab | 2013-03-16 21:51:02 +0100 | [diff] [blame] | 956 | pci_v3_base = devm_ioremap(&pdev->dev, PHYS_PCI_V3_BASE, SZ_64K); |
| 957 | if (!pci_v3_base) { |
| 958 | dev_err(&pdev->dev, "unable to remap PCIv3 base\n"); |
| 959 | return -ENODEV; |
| 960 | } |
| 961 | |
Linus Walleij | 5283456 | 2013-04-04 14:02:57 +0200 | [diff] [blame] | 962 | ret = devm_request_irq(&pdev->dev, IRQ_AP_V3INT, v3_irq, 0, "V3", NULL); |
| 963 | if (ret) { |
| 964 | dev_err(&pdev->dev, "unable to grab PCI error interrupt: %d\n", |
| 965 | ret); |
| 966 | return -ENODEV; |
| 967 | } |
| 968 | |
Linus Walleij | f55b2b5 | 2013-03-01 02:20:55 +0100 | [diff] [blame^] | 969 | conf_mem.name = "PCIv3 config"; |
| 970 | conf_mem.start = PHYS_PCI_CONFIG_BASE; |
| 971 | conf_mem.end = PHYS_PCI_CONFIG_BASE + SZ_16M - 1; |
| 972 | conf_mem.flags = IORESOURCE_MEM; |
| 973 | |
| 974 | io_mem.name = "PCIv3 I/O"; |
| 975 | io_mem.start = PHYS_PCI_IO_BASE; |
| 976 | io_mem.end = PHYS_PCI_IO_BASE + SZ_16M - 1; |
| 977 | io_mem.flags = IORESOURCE_MEM; |
| 978 | |
| 979 | non_mem.name = "PCIv3 non-prefetched mem"; |
| 980 | non_mem.start = PHYS_PCI_MEM_BASE + PCI_BUS_NONMEM_START; |
| 981 | non_mem.end = PHYS_PCI_MEM_BASE + PCI_BUS_NONMEM_START + |
| 982 | PCI_BUS_NONMEM_SIZE - 1; |
| 983 | non_mem.flags = IORESOURCE_MEM; |
| 984 | |
| 985 | pre_mem.name = "PCIv3 prefetched mem"; |
| 986 | pre_mem.start = PHYS_PCI_MEM_BASE + PCI_BUS_PREMEM_START; |
| 987 | pre_mem.end = PHYS_PCI_MEM_BASE + PCI_BUS_PREMEM_START + |
| 988 | PCI_BUS_PREMEM_SIZE - 1; |
| 989 | pre_mem.flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; |
| 990 | |
| 991 | pci_v3.map_irq = pci_v3_map_irq; |
| 992 | |
| 993 | pci_common_init_dev(&pdev->dev, &pci_v3); |
Linus Walleij | 5283456 | 2013-04-04 14:02:57 +0200 | [diff] [blame] | 994 | |
Linus Walleij | f4bc4f0 | 2013-01-29 17:14:18 +0100 | [diff] [blame] | 995 | return 0; |
| 996 | } |
| 997 | |
Linus Walleij | f55b2b5 | 2013-03-01 02:20:55 +0100 | [diff] [blame^] | 998 | static const struct of_device_id pci_ids[] = { |
| 999 | { .compatible = "v3,v360epc-pci", }, |
| 1000 | {}, |
| 1001 | }; |
| 1002 | |
Linus Walleij | 86adc39 | 2013-02-02 23:16:57 +0100 | [diff] [blame] | 1003 | static struct platform_driver pci_v3_driver = { |
| 1004 | .driver = { |
| 1005 | .name = "pci-v3", |
Linus Walleij | f55b2b5 | 2013-03-01 02:20:55 +0100 | [diff] [blame^] | 1006 | .of_match_table = pci_ids, |
Linus Walleij | 86adc39 | 2013-02-02 23:16:57 +0100 | [diff] [blame] | 1007 | }, |
| 1008 | }; |
| 1009 | |
| 1010 | static int __init pci_v3_init(void) |
| 1011 | { |
| 1012 | return platform_driver_probe(&pci_v3_driver, pci_v3_probe); |
| 1013 | } |
| 1014 | |
| 1015 | subsys_initcall(pci_v3_init); |
Linus Walleij | ae9daf2 | 2013-03-19 19:58:49 +0100 | [diff] [blame] | 1016 | |
| 1017 | /* |
| 1018 | * Static mappings for the PCIv3 bridge |
| 1019 | * |
| 1020 | * e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M) |
| 1021 | * ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M) |
| 1022 | * fee00000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M) |
| 1023 | */ |
| 1024 | static struct map_desc pci_v3_io_desc[] __initdata __maybe_unused = { |
| 1025 | { |
| 1026 | .virtual = (unsigned long)PCI_MEMORY_VADDR, |
| 1027 | .pfn = __phys_to_pfn(PHYS_PCI_MEM_BASE), |
| 1028 | .length = SZ_16M, |
| 1029 | .type = MT_DEVICE |
| 1030 | }, { |
| 1031 | .virtual = (unsigned long)PCI_CONFIG_VADDR, |
| 1032 | .pfn = __phys_to_pfn(PHYS_PCI_CONFIG_BASE), |
| 1033 | .length = SZ_16M, |
| 1034 | .type = MT_DEVICE |
| 1035 | } |
| 1036 | }; |
| 1037 | |
| 1038 | int __init pci_v3_early_init(void) |
| 1039 | { |
| 1040 | iotable_init(pci_v3_io_desc, ARRAY_SIZE(pci_v3_io_desc)); |
| 1041 | vga_base = (unsigned long)PCI_MEMORY_VADDR; |
| 1042 | pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE)); |
| 1043 | return 0; |
| 1044 | } |