Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mach-mmp/pxa168.c |
| 3 | * |
| 4 | * Code specific to PXA168 |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | */ |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 10 | #include <linux/module.h> |
| 11 | #include <linux/kernel.h> |
| 12 | #include <linux/init.h> |
| 13 | #include <linux/list.h> |
Eric Miao | e2bb665 | 2009-01-20 14:38:24 +0800 | [diff] [blame] | 14 | #include <linux/io.h> |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 15 | #include <linux/clk.h> |
| 16 | |
| 17 | #include <asm/mach/time.h> |
| 18 | #include <mach/addr-map.h> |
| 19 | #include <mach/cputype.h> |
| 20 | #include <mach/regs-apbc.h> |
Haojian Zhuang | a0f266c | 2009-10-13 15:24:55 +0800 | [diff] [blame] | 21 | #include <mach/regs-apmu.h> |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 22 | #include <mach/irqs.h> |
Linus Walleij | f55be1b | 2011-09-28 09:11:30 +0100 | [diff] [blame^] | 23 | #include <mach/gpio-pxa.h> |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 24 | #include <mach/dma.h> |
| 25 | #include <mach/devices.h> |
Eric Miao | a7a89d9 | 2009-01-20 17:20:56 +0800 | [diff] [blame] | 26 | #include <mach/mfp.h> |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 27 | |
| 28 | #include "common.h" |
| 29 | #include "clock.h" |
| 30 | |
Eric Miao | a7a89d9 | 2009-01-20 17:20:56 +0800 | [diff] [blame] | 31 | #define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000) |
| 32 | |
| 33 | static struct mfp_addr_map pxa168_mfp_addr_map[] __initdata = |
| 34 | { |
| 35 | MFP_ADDR_X(GPIO0, GPIO36, 0x04c), |
| 36 | MFP_ADDR_X(GPIO37, GPIO55, 0x000), |
| 37 | MFP_ADDR_X(GPIO56, GPIO123, 0x0e0), |
| 38 | MFP_ADDR_X(GPIO124, GPIO127, 0x0f4), |
| 39 | |
| 40 | MFP_ADDR_END, |
| 41 | }; |
| 42 | |
Eric Miao | e2bb665 | 2009-01-20 14:38:24 +0800 | [diff] [blame] | 43 | #define APMASK(i) (GPIO_REGS_VIRT + BANK_OFF(i) + 0x09c) |
| 44 | |
| 45 | static void __init pxa168_init_gpio(void) |
| 46 | { |
| 47 | int i; |
| 48 | |
| 49 | /* enable GPIO clock */ |
| 50 | __raw_writel(APBC_APBCLK | APBC_FNCLK, APBC_PXA168_GPIO); |
| 51 | |
| 52 | /* unmask GPIO edge detection for all 4 banks - APMASKx */ |
| 53 | for (i = 0; i < 4; i++) |
| 54 | __raw_writel(0xffffffff, APMASK(i)); |
| 55 | |
| 56 | pxa_init_gpio(IRQ_PXA168_GPIOX, 0, 127, NULL); |
| 57 | } |
| 58 | |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 59 | void __init pxa168_init_irq(void) |
| 60 | { |
| 61 | icu_init_irq(); |
Eric Miao | e2bb665 | 2009-01-20 14:38:24 +0800 | [diff] [blame] | 62 | pxa168_init_gpio(); |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 63 | } |
| 64 | |
| 65 | /* APB peripheral clocks */ |
| 66 | static APBC_CLK(uart1, PXA168_UART1, 1, 14745600); |
| 67 | static APBC_CLK(uart2, PXA168_UART2, 1, 14745600); |
Tanmay Upadhyay | 26407f8 | 2011-05-02 11:29:58 +0530 | [diff] [blame] | 68 | static APBC_CLK(uart3, PXA168_UART3, 1, 14745600); |
Eric Miao | 1a77920 | 2009-04-13 15:34:54 +0800 | [diff] [blame] | 69 | static APBC_CLK(twsi0, PXA168_TWSI0, 1, 33000000); |
| 70 | static APBC_CLK(twsi1, PXA168_TWSI1, 1, 33000000); |
Eric Miao | a27ba76 | 2009-04-13 18:29:52 +0800 | [diff] [blame] | 71 | static APBC_CLK(pwm1, PXA168_PWM1, 1, 13000000); |
| 72 | static APBC_CLK(pwm2, PXA168_PWM2, 1, 13000000); |
| 73 | static APBC_CLK(pwm3, PXA168_PWM3, 1, 13000000); |
| 74 | static APBC_CLK(pwm4, PXA168_PWM4, 1, 13000000); |
Haojian Zhuang | 7e49922 | 2010-03-19 11:53:17 -0400 | [diff] [blame] | 75 | static APBC_CLK(ssp1, PXA168_SSP1, 4, 0); |
| 76 | static APBC_CLK(ssp2, PXA168_SSP2, 4, 0); |
| 77 | static APBC_CLK(ssp3, PXA168_SSP3, 4, 0); |
| 78 | static APBC_CLK(ssp4, PXA168_SSP4, 4, 0); |
| 79 | static APBC_CLK(ssp5, PXA168_SSP5, 4, 0); |
Mark F. Brown | 6d10946 | 2010-09-03 18:28:07 -0400 | [diff] [blame] | 80 | static APBC_CLK(keypad, PXA168_KPC, 0, 32000); |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 81 | |
Lei Wen | 6662498 | 2011-06-21 05:37:47 -0700 | [diff] [blame] | 82 | static APMU_CLK(nand, NAND, 0x19b, 156000000); |
Mark F. Brown | 58cf68b | 2010-08-25 23:51:54 -0400 | [diff] [blame] | 83 | static APMU_CLK(lcd, LCD, 0x7f, 312000000); |
Tanmay Upadhyay | 80def0d | 2011-05-02 11:29:59 +0530 | [diff] [blame] | 84 | static APMU_CLK(eth, ETH, 0x09, 0); |
Haojian Zhuang | a0f266c | 2009-10-13 15:24:55 +0800 | [diff] [blame] | 85 | |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 86 | /* device and clock bindings */ |
| 87 | static struct clk_lookup pxa168_clkregs[] = { |
| 88 | INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), |
| 89 | INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), |
Tanmay Upadhyay | 26407f8 | 2011-05-02 11:29:58 +0530 | [diff] [blame] | 90 | INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL), |
Eric Miao | 1a77920 | 2009-04-13 15:34:54 +0800 | [diff] [blame] | 91 | INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL), |
| 92 | INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL), |
Eric Miao | a27ba76 | 2009-04-13 18:29:52 +0800 | [diff] [blame] | 93 | INIT_CLKREG(&clk_pwm1, "pxa168-pwm.0", NULL), |
| 94 | INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL), |
| 95 | INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL), |
| 96 | INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL), |
Haojian Zhuang | 7e49922 | 2010-03-19 11:53:17 -0400 | [diff] [blame] | 97 | INIT_CLKREG(&clk_ssp1, "pxa168-ssp.0", NULL), |
| 98 | INIT_CLKREG(&clk_ssp2, "pxa168-ssp.1", NULL), |
| 99 | INIT_CLKREG(&clk_ssp3, "pxa168-ssp.2", NULL), |
| 100 | INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL), |
| 101 | INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL), |
Haojian Zhuang | a0f266c | 2009-10-13 15:24:55 +0800 | [diff] [blame] | 102 | INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), |
Mark F. Brown | 58cf68b | 2010-08-25 23:51:54 -0400 | [diff] [blame] | 103 | INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL), |
Mark F. Brown | 6d10946 | 2010-09-03 18:28:07 -0400 | [diff] [blame] | 104 | INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL), |
Tanmay Upadhyay | 80def0d | 2011-05-02 11:29:59 +0530 | [diff] [blame] | 105 | INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"), |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 106 | }; |
| 107 | |
| 108 | static int __init pxa168_init(void) |
| 109 | { |
| 110 | if (cpu_is_pxa168()) { |
Eric Miao | a7a89d9 | 2009-01-20 17:20:56 +0800 | [diff] [blame] | 111 | mfp_init_base(MFPR_VIRT_BASE); |
| 112 | mfp_init_addr(pxa168_mfp_addr_map); |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 113 | pxa_init_dma(IRQ_PXA168_DMA_INT0, 32); |
Russell King | 0a0300d | 2010-01-12 12:28:00 +0000 | [diff] [blame] | 114 | clkdev_add_table(ARRAY_AND_SIZE(pxa168_clkregs)); |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 115 | } |
| 116 | |
| 117 | return 0; |
| 118 | } |
| 119 | postcore_initcall(pxa168_init); |
| 120 | |
| 121 | /* system timer - clock enabled, 3.25MHz */ |
| 122 | #define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3)) |
| 123 | |
| 124 | static void __init pxa168_timer_init(void) |
| 125 | { |
| 126 | /* this is early, we have to initialize the CCU registers by |
| 127 | * ourselves instead of using clk_* API. Clock rate is defined |
| 128 | * by APBC_TIMERS_CLK_RST (3.25MHz) and enabled free-running |
| 129 | */ |
| 130 | __raw_writel(APBC_APBCLK | APBC_RST, APBC_PXA168_TIMERS); |
| 131 | |
| 132 | /* 3.25MHz, bus/functional clock enabled, release reset */ |
| 133 | __raw_writel(TIMER_CLK_RST, APBC_PXA168_TIMERS); |
| 134 | |
| 135 | timer_init(IRQ_PXA168_TIMER1); |
| 136 | } |
| 137 | |
| 138 | struct sys_timer pxa168_timer = { |
| 139 | .init = pxa168_timer_init, |
| 140 | }; |
| 141 | |
Mark F. Brown | ab5739a | 2010-09-03 18:28:10 -0400 | [diff] [blame] | 142 | void pxa168_clear_keypad_wakeup(void) |
| 143 | { |
| 144 | uint32_t val; |
| 145 | uint32_t mask = APMU_PXA168_KP_WAKE_CLR; |
| 146 | |
| 147 | /* wake event clear is needed in order to clear keypad interrupt */ |
| 148 | val = __raw_readl(APMU_WAKE_CLR); |
| 149 | __raw_writel(val | mask, APMU_WAKE_CLR); |
| 150 | } |
| 151 | |
Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 152 | /* on-chip devices */ |
| 153 | PXA168_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4017000, 0x30, 21, 22); |
| 154 | PXA168_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4018000, 0x30, 23, 24); |
Tanmay Upadhyay | 26407f8 | 2011-05-02 11:29:58 +0530 | [diff] [blame] | 155 | PXA168_DEVICE(uart3, "pxa2xx-uart", 2, UART3, 0xd4026000, 0x30, 23, 24); |
Eric Miao | 1a77920 | 2009-04-13 15:34:54 +0800 | [diff] [blame] | 156 | PXA168_DEVICE(twsi0, "pxa2xx-i2c", 0, TWSI0, 0xd4011000, 0x28); |
| 157 | PXA168_DEVICE(twsi1, "pxa2xx-i2c", 1, TWSI1, 0xd4025000, 0x28); |
Eric Miao | a27ba76 | 2009-04-13 18:29:52 +0800 | [diff] [blame] | 158 | PXA168_DEVICE(pwm1, "pxa168-pwm", 0, NONE, 0xd401a000, 0x10); |
| 159 | PXA168_DEVICE(pwm2, "pxa168-pwm", 1, NONE, 0xd401a400, 0x10); |
| 160 | PXA168_DEVICE(pwm3, "pxa168-pwm", 2, NONE, 0xd401a800, 0x10); |
| 161 | PXA168_DEVICE(pwm4, "pxa168-pwm", 3, NONE, 0xd401ac00, 0x10); |
Haojian Zhuang | a0f266c | 2009-10-13 15:24:55 +0800 | [diff] [blame] | 162 | PXA168_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x80, 97, 99); |
Haojian Zhuang | 7e49922 | 2010-03-19 11:53:17 -0400 | [diff] [blame] | 163 | PXA168_DEVICE(ssp1, "pxa168-ssp", 0, SSP1, 0xd401b000, 0x40, 52, 53); |
| 164 | PXA168_DEVICE(ssp2, "pxa168-ssp", 1, SSP2, 0xd401c000, 0x40, 54, 55); |
| 165 | PXA168_DEVICE(ssp3, "pxa168-ssp", 2, SSP3, 0xd401f000, 0x40, 56, 57); |
| 166 | PXA168_DEVICE(ssp4, "pxa168-ssp", 3, SSP4, 0xd4020000, 0x40, 58, 59); |
| 167 | PXA168_DEVICE(ssp5, "pxa168-ssp", 4, SSP5, 0xd4021000, 0x40, 60, 61); |
Mark F. Brown | 58cf68b | 2010-08-25 23:51:54 -0400 | [diff] [blame] | 168 | PXA168_DEVICE(fb, "pxa168-fb", -1, LCD, 0xd420b000, 0x1c8); |
Mark F. Brown | 6d10946 | 2010-09-03 18:28:07 -0400 | [diff] [blame] | 169 | PXA168_DEVICE(keypad, "pxa27x-keypad", -1, KEYPAD, 0xd4012000, 0x4c); |
Tanmay Upadhyay | 80def0d | 2011-05-02 11:29:59 +0530 | [diff] [blame] | 170 | PXA168_DEVICE(eth, "pxa168-eth", -1, MFU, 0xc0800000, 0x0fff); |