Will Deacon | f81ef4a | 2010-09-03 10:41:08 +0100 | [diff] [blame] | 1 | #ifndef _ARM_HW_BREAKPOINT_H |
| 2 | #define _ARM_HW_BREAKPOINT_H |
| 3 | |
| 4 | #ifdef __KERNEL__ |
Will Deacon | 864232f | 2010-09-03 10:42:55 +0100 | [diff] [blame] | 5 | |
| 6 | struct task_struct; |
| 7 | |
| 8 | #ifdef CONFIG_HAVE_HW_BREAKPOINT |
| 9 | |
Will Deacon | f81ef4a | 2010-09-03 10:41:08 +0100 | [diff] [blame] | 10 | struct arch_hw_breakpoint_ctrl { |
| 11 | u32 __reserved : 9, |
| 12 | mismatch : 1, |
| 13 | : 9, |
| 14 | len : 8, |
| 15 | type : 2, |
| 16 | privilege : 2, |
| 17 | enabled : 1; |
| 18 | }; |
| 19 | |
| 20 | struct arch_hw_breakpoint { |
| 21 | u32 address; |
| 22 | u32 trigger; |
Will Deacon | 9ebb3cb | 2010-12-01 14:12:13 +0000 | [diff] [blame] | 23 | struct arch_hw_breakpoint_ctrl step_ctrl; |
| 24 | struct arch_hw_breakpoint_ctrl ctrl; |
Will Deacon | f81ef4a | 2010-09-03 10:41:08 +0100 | [diff] [blame] | 25 | }; |
| 26 | |
| 27 | static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl) |
| 28 | { |
| 29 | return (ctrl.mismatch << 22) | (ctrl.len << 5) | (ctrl.type << 3) | |
| 30 | (ctrl.privilege << 1) | ctrl.enabled; |
| 31 | } |
| 32 | |
| 33 | static inline void decode_ctrl_reg(u32 reg, |
| 34 | struct arch_hw_breakpoint_ctrl *ctrl) |
| 35 | { |
| 36 | ctrl->enabled = reg & 0x1; |
| 37 | reg >>= 1; |
| 38 | ctrl->privilege = reg & 0x3; |
| 39 | reg >>= 2; |
| 40 | ctrl->type = reg & 0x3; |
| 41 | reg >>= 2; |
| 42 | ctrl->len = reg & 0xff; |
| 43 | reg >>= 17; |
| 44 | ctrl->mismatch = reg & 0x1; |
| 45 | } |
| 46 | |
| 47 | /* Debug architecture numbers. */ |
| 48 | #define ARM_DEBUG_ARCH_RESERVED 0 /* In case of ptrace ABI updates. */ |
| 49 | #define ARM_DEBUG_ARCH_V6 1 |
| 50 | #define ARM_DEBUG_ARCH_V6_1 2 |
| 51 | #define ARM_DEBUG_ARCH_V7_ECP14 3 |
| 52 | #define ARM_DEBUG_ARCH_V7_MM 4 |
Will Deacon | b5d5b8f | 2011-07-22 18:27:37 +0100 | [diff] [blame] | 53 | #define ARM_DEBUG_ARCH_V7_1 5 |
Will Deacon | f81ef4a | 2010-09-03 10:41:08 +0100 | [diff] [blame] | 54 | |
| 55 | /* Breakpoint */ |
| 56 | #define ARM_BREAKPOINT_EXECUTE 0 |
| 57 | |
| 58 | /* Watchpoints */ |
| 59 | #define ARM_BREAKPOINT_LOAD 1 |
| 60 | #define ARM_BREAKPOINT_STORE 2 |
Will Deacon | 6f26aa0 | 2011-08-02 16:16:57 +0100 | [diff] [blame] | 61 | #define ARM_FSR_ACCESS_MASK (1 << 11) |
Will Deacon | f81ef4a | 2010-09-03 10:41:08 +0100 | [diff] [blame] | 62 | |
| 63 | /* Privilege Levels */ |
| 64 | #define ARM_BREAKPOINT_PRIV 1 |
| 65 | #define ARM_BREAKPOINT_USER 2 |
| 66 | |
| 67 | /* Lengths */ |
| 68 | #define ARM_BREAKPOINT_LEN_1 0x1 |
| 69 | #define ARM_BREAKPOINT_LEN_2 0x3 |
| 70 | #define ARM_BREAKPOINT_LEN_4 0xf |
| 71 | #define ARM_BREAKPOINT_LEN_8 0xff |
| 72 | |
| 73 | /* Limits */ |
| 74 | #define ARM_MAX_BRP 16 |
| 75 | #define ARM_MAX_WRP 16 |
| 76 | #define ARM_MAX_HBP_SLOTS (ARM_MAX_BRP + ARM_MAX_WRP) |
| 77 | |
| 78 | /* DSCR method of entry bits. */ |
| 79 | #define ARM_DSCR_MOE(x) ((x >> 2) & 0xf) |
| 80 | #define ARM_ENTRY_BREAKPOINT 0x1 |
| 81 | #define ARM_ENTRY_ASYNC_WATCHPOINT 0x2 |
| 82 | #define ARM_ENTRY_SYNC_WATCHPOINT 0xa |
| 83 | |
| 84 | /* DSCR monitor/halting bits. */ |
| 85 | #define ARM_DSCR_HDBGEN (1 << 14) |
| 86 | #define ARM_DSCR_MDBGEN (1 << 15) |
| 87 | |
Dietmar Eggemann | 57ba899 | 2012-10-14 21:08:14 +0100 | [diff] [blame] | 88 | /* OSLSR os lock model bits */ |
| 89 | #define ARM_OSLSR_OSLM0 (1 << 0) |
| 90 | |
Will Deacon | f81ef4a | 2010-09-03 10:41:08 +0100 | [diff] [blame] | 91 | /* opcode2 numbers for the co-processor instructions. */ |
| 92 | #define ARM_OP2_BVR 4 |
| 93 | #define ARM_OP2_BCR 5 |
| 94 | #define ARM_OP2_WVR 6 |
| 95 | #define ARM_OP2_WCR 7 |
| 96 | |
| 97 | /* Base register numbers for the debug registers. */ |
| 98 | #define ARM_BASE_BVR 64 |
| 99 | #define ARM_BASE_BCR 80 |
| 100 | #define ARM_BASE_WVR 96 |
| 101 | #define ARM_BASE_WCR 112 |
| 102 | |
| 103 | /* Accessor macros for the debug registers. */ |
Dietmar Eggemann | 9e962f7 | 2012-09-26 17:28:47 +0100 | [diff] [blame] | 104 | #define ARM_DBG_READ(N, M, OP2, VAL) do {\ |
| 105 | asm volatile("mrc p14, 0, %0, " #N "," #M ", " #OP2 : "=r" (VAL));\ |
Will Deacon | f81ef4a | 2010-09-03 10:41:08 +0100 | [diff] [blame] | 106 | } while (0) |
| 107 | |
Dietmar Eggemann | 9e962f7 | 2012-09-26 17:28:47 +0100 | [diff] [blame] | 108 | #define ARM_DBG_WRITE(N, M, OP2, VAL) do {\ |
| 109 | asm volatile("mcr p14, 0, %0, " #N "," #M ", " #OP2 : : "r" (VAL));\ |
Will Deacon | f81ef4a | 2010-09-03 10:41:08 +0100 | [diff] [blame] | 110 | } while (0) |
| 111 | |
| 112 | struct notifier_block; |
| 113 | struct perf_event; |
| 114 | struct pmu; |
Will Deacon | f81ef4a | 2010-09-03 10:41:08 +0100 | [diff] [blame] | 115 | |
| 116 | extern struct pmu perf_ops_bp; |
| 117 | extern int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl, |
| 118 | int *gen_len, int *gen_type); |
| 119 | extern int arch_check_bp_in_kernelspace(struct perf_event *bp); |
| 120 | extern int arch_validate_hwbkpt_settings(struct perf_event *bp); |
| 121 | extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused, |
| 122 | unsigned long val, void *data); |
Will Deacon | 864232f | 2010-09-03 10:42:55 +0100 | [diff] [blame] | 123 | |
Will Deacon | f81ef4a | 2010-09-03 10:41:08 +0100 | [diff] [blame] | 124 | extern u8 arch_get_debug_arch(void); |
| 125 | extern u8 arch_get_max_wp_len(void); |
Will Deacon | 864232f | 2010-09-03 10:42:55 +0100 | [diff] [blame] | 126 | extern void clear_ptrace_hw_breakpoint(struct task_struct *tsk); |
Will Deacon | f81ef4a | 2010-09-03 10:41:08 +0100 | [diff] [blame] | 127 | |
| 128 | int arch_install_hw_breakpoint(struct perf_event *bp); |
| 129 | void arch_uninstall_hw_breakpoint(struct perf_event *bp); |
| 130 | void hw_breakpoint_pmu_read(struct perf_event *bp); |
| 131 | int hw_breakpoint_slots(int type); |
| 132 | |
Will Deacon | 864232f | 2010-09-03 10:42:55 +0100 | [diff] [blame] | 133 | #else |
| 134 | static inline void clear_ptrace_hw_breakpoint(struct task_struct *tsk) {} |
| 135 | |
| 136 | #endif /* CONFIG_HAVE_HW_BREAKPOINT */ |
Will Deacon | f81ef4a | 2010-09-03 10:41:08 +0100 | [diff] [blame] | 137 | #endif /* __KERNEL__ */ |
| 138 | #endif /* _ARM_HW_BREAKPOINT_H */ |