SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 1 | /* |
Andrew Victor | 9d04126 | 2007-02-05 11:42:07 +0100 | [diff] [blame] | 2 | * arch/arm/mach-at91/at91rm9200.c |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2005 SAN People |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | */ |
| 12 | |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 13 | #include <linux/module.h> |
| 14 | |
Russell King | 80b02c1 | 2009-01-08 10:01:47 +0000 | [diff] [blame] | 15 | #include <asm/irq.h> |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 16 | #include <asm/mach/arch.h> |
| 17 | #include <asm/mach/map.h> |
David Howells | 9f97da7 | 2012-03-28 18:30:01 +0100 | [diff] [blame] | 18 | #include <asm/system_misc.h> |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 19 | #include <mach/at91rm9200.h> |
Ludovic Desroches | 8fe82a5 | 2012-06-21 14:47:27 +0200 | [diff] [blame] | 20 | #include <mach/at91_aic.h> |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 21 | #include <mach/at91_pmc.h> |
| 22 | #include <mach/at91_st.h> |
Jean-Christophe PLAGNIOL-VILLARD | e57556e3 | 2011-04-24 11:40:22 +0800 | [diff] [blame] | 23 | #include <mach/cpu.h> |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 24 | |
Jean-Christophe PLAGNIOL-VILLARD | 21d08b9 | 2011-04-23 15:28:34 +0800 | [diff] [blame] | 25 | #include "soc.h" |
Andrew Victor | 10e8e1f | 2006-06-19 15:26:51 +0100 | [diff] [blame] | 26 | #include "generic.h" |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 27 | #include "clock.h" |
Jean-Christophe PLAGNIOL-VILLARD | faee0cc | 2011-10-14 01:37:09 +0800 | [diff] [blame] | 28 | #include "sam9_smc.h" |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 29 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 30 | /* -------------------------------------------------------------------- |
| 31 | * Clocks |
| 32 | * -------------------------------------------------------------------- */ |
| 33 | |
| 34 | /* |
| 35 | * The peripheral clocks. |
| 36 | */ |
| 37 | static struct clk udc_clk = { |
| 38 | .name = "udc_clk", |
| 39 | .pmc_mask = 1 << AT91RM9200_ID_UDP, |
| 40 | .type = CLK_TYPE_PERIPHERAL, |
| 41 | }; |
| 42 | static struct clk ohci_clk = { |
| 43 | .name = "ohci_clk", |
| 44 | .pmc_mask = 1 << AT91RM9200_ID_UHP, |
| 45 | .type = CLK_TYPE_PERIPHERAL, |
| 46 | }; |
| 47 | static struct clk ether_clk = { |
| 48 | .name = "ether_clk", |
| 49 | .pmc_mask = 1 << AT91RM9200_ID_EMAC, |
| 50 | .type = CLK_TYPE_PERIPHERAL, |
| 51 | }; |
| 52 | static struct clk mmc_clk = { |
| 53 | .name = "mci_clk", |
| 54 | .pmc_mask = 1 << AT91RM9200_ID_MCI, |
| 55 | .type = CLK_TYPE_PERIPHERAL, |
| 56 | }; |
| 57 | static struct clk twi_clk = { |
| 58 | .name = "twi_clk", |
| 59 | .pmc_mask = 1 << AT91RM9200_ID_TWI, |
| 60 | .type = CLK_TYPE_PERIPHERAL, |
| 61 | }; |
| 62 | static struct clk usart0_clk = { |
| 63 | .name = "usart0_clk", |
| 64 | .pmc_mask = 1 << AT91RM9200_ID_US0, |
| 65 | .type = CLK_TYPE_PERIPHERAL, |
| 66 | }; |
| 67 | static struct clk usart1_clk = { |
| 68 | .name = "usart1_clk", |
| 69 | .pmc_mask = 1 << AT91RM9200_ID_US1, |
| 70 | .type = CLK_TYPE_PERIPHERAL, |
| 71 | }; |
| 72 | static struct clk usart2_clk = { |
| 73 | .name = "usart2_clk", |
| 74 | .pmc_mask = 1 << AT91RM9200_ID_US2, |
| 75 | .type = CLK_TYPE_PERIPHERAL, |
| 76 | }; |
| 77 | static struct clk usart3_clk = { |
| 78 | .name = "usart3_clk", |
| 79 | .pmc_mask = 1 << AT91RM9200_ID_US3, |
| 80 | .type = CLK_TYPE_PERIPHERAL, |
| 81 | }; |
| 82 | static struct clk spi_clk = { |
| 83 | .name = "spi_clk", |
| 84 | .pmc_mask = 1 << AT91RM9200_ID_SPI, |
| 85 | .type = CLK_TYPE_PERIPHERAL, |
| 86 | }; |
| 87 | static struct clk pioA_clk = { |
| 88 | .name = "pioA_clk", |
| 89 | .pmc_mask = 1 << AT91RM9200_ID_PIOA, |
| 90 | .type = CLK_TYPE_PERIPHERAL, |
| 91 | }; |
| 92 | static struct clk pioB_clk = { |
| 93 | .name = "pioB_clk", |
| 94 | .pmc_mask = 1 << AT91RM9200_ID_PIOB, |
| 95 | .type = CLK_TYPE_PERIPHERAL, |
| 96 | }; |
| 97 | static struct clk pioC_clk = { |
| 98 | .name = "pioC_clk", |
| 99 | .pmc_mask = 1 << AT91RM9200_ID_PIOC, |
| 100 | .type = CLK_TYPE_PERIPHERAL, |
| 101 | }; |
| 102 | static struct clk pioD_clk = { |
| 103 | .name = "pioD_clk", |
| 104 | .pmc_mask = 1 << AT91RM9200_ID_PIOD, |
| 105 | .type = CLK_TYPE_PERIPHERAL, |
| 106 | }; |
Andrew Victor | e8788ba | 2007-05-02 17:14:57 +0100 | [diff] [blame] | 107 | static struct clk ssc0_clk = { |
| 108 | .name = "ssc0_clk", |
| 109 | .pmc_mask = 1 << AT91RM9200_ID_SSC0, |
| 110 | .type = CLK_TYPE_PERIPHERAL, |
| 111 | }; |
| 112 | static struct clk ssc1_clk = { |
| 113 | .name = "ssc1_clk", |
| 114 | .pmc_mask = 1 << AT91RM9200_ID_SSC1, |
| 115 | .type = CLK_TYPE_PERIPHERAL, |
| 116 | }; |
| 117 | static struct clk ssc2_clk = { |
| 118 | .name = "ssc2_clk", |
| 119 | .pmc_mask = 1 << AT91RM9200_ID_SSC2, |
| 120 | .type = CLK_TYPE_PERIPHERAL, |
| 121 | }; |
Andrew Victor | c177a1e | 2007-02-08 10:25:38 +0100 | [diff] [blame] | 122 | static struct clk tc0_clk = { |
| 123 | .name = "tc0_clk", |
| 124 | .pmc_mask = 1 << AT91RM9200_ID_TC0, |
| 125 | .type = CLK_TYPE_PERIPHERAL, |
| 126 | }; |
| 127 | static struct clk tc1_clk = { |
| 128 | .name = "tc1_clk", |
| 129 | .pmc_mask = 1 << AT91RM9200_ID_TC1, |
| 130 | .type = CLK_TYPE_PERIPHERAL, |
| 131 | }; |
| 132 | static struct clk tc2_clk = { |
| 133 | .name = "tc2_clk", |
| 134 | .pmc_mask = 1 << AT91RM9200_ID_TC2, |
| 135 | .type = CLK_TYPE_PERIPHERAL, |
| 136 | }; |
| 137 | static struct clk tc3_clk = { |
| 138 | .name = "tc3_clk", |
| 139 | .pmc_mask = 1 << AT91RM9200_ID_TC3, |
| 140 | .type = CLK_TYPE_PERIPHERAL, |
| 141 | }; |
| 142 | static struct clk tc4_clk = { |
| 143 | .name = "tc4_clk", |
| 144 | .pmc_mask = 1 << AT91RM9200_ID_TC4, |
| 145 | .type = CLK_TYPE_PERIPHERAL, |
| 146 | }; |
| 147 | static struct clk tc5_clk = { |
| 148 | .name = "tc5_clk", |
| 149 | .pmc_mask = 1 << AT91RM9200_ID_TC5, |
| 150 | .type = CLK_TYPE_PERIPHERAL, |
| 151 | }; |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 152 | |
| 153 | static struct clk *periph_clocks[] __initdata = { |
| 154 | &pioA_clk, |
| 155 | &pioB_clk, |
| 156 | &pioC_clk, |
| 157 | &pioD_clk, |
| 158 | &usart0_clk, |
| 159 | &usart1_clk, |
| 160 | &usart2_clk, |
| 161 | &usart3_clk, |
| 162 | &mmc_clk, |
| 163 | &udc_clk, |
| 164 | &twi_clk, |
| 165 | &spi_clk, |
Andrew Victor | e8788ba | 2007-05-02 17:14:57 +0100 | [diff] [blame] | 166 | &ssc0_clk, |
| 167 | &ssc1_clk, |
| 168 | &ssc2_clk, |
Andrew Victor | c177a1e | 2007-02-08 10:25:38 +0100 | [diff] [blame] | 169 | &tc0_clk, |
| 170 | &tc1_clk, |
| 171 | &tc2_clk, |
| 172 | &tc3_clk, |
| 173 | &tc4_clk, |
| 174 | &tc5_clk, |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 175 | &ohci_clk, |
| 176 | ðer_clk, |
| 177 | // irq0 .. irq6 |
| 178 | }; |
| 179 | |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 180 | static struct clk_lookup periph_clocks_lookups[] = { |
| 181 | CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk), |
| 182 | CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk), |
| 183 | CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk), |
| 184 | CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk), |
| 185 | CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk), |
| 186 | CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk), |
Bo Shen | 636036d2 | 2012-11-06 13:57:51 +0800 | [diff] [blame] | 187 | CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk), |
| 188 | CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk), |
| 189 | CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.2", &ssc2_clk), |
Bo Shen | 099343c | 2012-11-07 11:41:41 +0800 | [diff] [blame] | 190 | CLKDEV_CON_DEV_ID("pclk", "fffd0000.ssc", &ssc0_clk), |
| 191 | CLKDEV_CON_DEV_ID("pclk", "fffd4000.ssc", &ssc1_clk), |
| 192 | CLKDEV_CON_DEV_ID("pclk", "fffd8000.ssc", &ssc2_clk), |
Bo Shen | 302090a | 2012-10-15 17:30:28 +0800 | [diff] [blame] | 193 | CLKDEV_CON_DEV_ID(NULL, "i2c-at91rm9200.0", &twi_clk), |
Jean-Christophe PLAGNIOL-VILLARD | 0af4316 | 2011-08-30 03:29:28 +0200 | [diff] [blame] | 194 | /* fake hclk clock */ |
| 195 | CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk), |
Jean-Christophe PLAGNIOL-VILLARD | 619d4a4 | 2011-11-13 13:00:58 +0800 | [diff] [blame] | 196 | CLKDEV_CON_ID("pioA", &pioA_clk), |
| 197 | CLKDEV_CON_ID("pioB", &pioB_clk), |
| 198 | CLKDEV_CON_ID("pioC", &pioC_clk), |
| 199 | CLKDEV_CON_ID("pioD", &pioD_clk), |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 200 | }; |
| 201 | |
| 202 | static struct clk_lookup usart_clocks_lookups[] = { |
| 203 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck), |
| 204 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk), |
| 205 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk), |
| 206 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk), |
| 207 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk), |
| 208 | }; |
| 209 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 210 | /* |
| 211 | * The four programmable clocks. |
| 212 | * You must configure pin multiplexing to bring these signals out. |
| 213 | */ |
| 214 | static struct clk pck0 = { |
| 215 | .name = "pck0", |
| 216 | .pmc_mask = AT91_PMC_PCK0, |
| 217 | .type = CLK_TYPE_PROGRAMMABLE, |
| 218 | .id = 0, |
| 219 | }; |
| 220 | static struct clk pck1 = { |
| 221 | .name = "pck1", |
| 222 | .pmc_mask = AT91_PMC_PCK1, |
| 223 | .type = CLK_TYPE_PROGRAMMABLE, |
| 224 | .id = 1, |
| 225 | }; |
| 226 | static struct clk pck2 = { |
| 227 | .name = "pck2", |
| 228 | .pmc_mask = AT91_PMC_PCK2, |
| 229 | .type = CLK_TYPE_PROGRAMMABLE, |
| 230 | .id = 2, |
| 231 | }; |
| 232 | static struct clk pck3 = { |
| 233 | .name = "pck3", |
| 234 | .pmc_mask = AT91_PMC_PCK3, |
| 235 | .type = CLK_TYPE_PROGRAMMABLE, |
| 236 | .id = 3, |
| 237 | }; |
| 238 | |
| 239 | static void __init at91rm9200_register_clocks(void) |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 240 | { |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 241 | int i; |
| 242 | |
| 243 | for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) |
| 244 | clk_register(periph_clocks[i]); |
| 245 | |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 246 | clkdev_add_table(periph_clocks_lookups, |
| 247 | ARRAY_SIZE(periph_clocks_lookups)); |
| 248 | clkdev_add_table(usart_clocks_lookups, |
| 249 | ARRAY_SIZE(usart_clocks_lookups)); |
| 250 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 251 | clk_register(&pck0); |
| 252 | clk_register(&pck1); |
| 253 | clk_register(&pck2); |
| 254 | clk_register(&pck3); |
| 255 | } |
| 256 | |
Andrew Victor | f217383 | 2006-09-27 13:23:00 +0100 | [diff] [blame] | 257 | /* -------------------------------------------------------------------- |
| 258 | * GPIO |
| 259 | * -------------------------------------------------------------------- */ |
| 260 | |
Jean-Christophe PLAGNIOL-VILLARD | 1a2d915 | 2011-10-17 14:28:38 +0800 | [diff] [blame] | 261 | static struct at91_gpio_bank at91rm9200_gpio[] __initdata = { |
Andrew Victor | f217383 | 2006-09-27 13:23:00 +0100 | [diff] [blame] | 262 | { |
| 263 | .id = AT91RM9200_ID_PIOA, |
Jean-Christophe PLAGNIOL-VILLARD | 80e91cb | 2011-09-16 23:37:50 +0800 | [diff] [blame] | 264 | .regbase = AT91RM9200_BASE_PIOA, |
Andrew Victor | f217383 | 2006-09-27 13:23:00 +0100 | [diff] [blame] | 265 | }, { |
| 266 | .id = AT91RM9200_ID_PIOB, |
Jean-Christophe PLAGNIOL-VILLARD | 80e91cb | 2011-09-16 23:37:50 +0800 | [diff] [blame] | 267 | .regbase = AT91RM9200_BASE_PIOB, |
Andrew Victor | f217383 | 2006-09-27 13:23:00 +0100 | [diff] [blame] | 268 | }, { |
| 269 | .id = AT91RM9200_ID_PIOC, |
Jean-Christophe PLAGNIOL-VILLARD | 80e91cb | 2011-09-16 23:37:50 +0800 | [diff] [blame] | 270 | .regbase = AT91RM9200_BASE_PIOC, |
Andrew Victor | f217383 | 2006-09-27 13:23:00 +0100 | [diff] [blame] | 271 | }, { |
| 272 | .id = AT91RM9200_ID_PIOD, |
Jean-Christophe PLAGNIOL-VILLARD | 80e91cb | 2011-09-16 23:37:50 +0800 | [diff] [blame] | 273 | .regbase = AT91RM9200_BASE_PIOD, |
Andrew Victor | f217383 | 2006-09-27 13:23:00 +0100 | [diff] [blame] | 274 | } |
| 275 | }; |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 276 | |
Nicolas Pitre | c9dfafb | 2011-08-02 10:21:36 -0400 | [diff] [blame] | 277 | static void at91rm9200_idle(void) |
| 278 | { |
| 279 | /* |
| 280 | * Disable the processor clock. The processor will be automatically |
| 281 | * re-enabled by an interrupt or by a reset. |
| 282 | */ |
Jean-Christophe PLAGNIOL-VILLARD | b551495 | 2011-11-25 09:59:46 +0800 | [diff] [blame] | 283 | at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK); |
Nicolas Pitre | c9dfafb | 2011-08-02 10:21:36 -0400 | [diff] [blame] | 284 | } |
| 285 | |
Russell King | 1b2073e | 2011-11-03 09:53:29 +0000 | [diff] [blame] | 286 | static void at91rm9200_restart(char mode, const char *cmd) |
Andrew Victor | 1f4fd0a | 2006-11-30 10:01:47 +0100 | [diff] [blame] | 287 | { |
| 288 | /* |
| 289 | * Perform a hardware reset with the use of the Watchdog timer. |
| 290 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 5e9cf5e | 2012-02-20 11:07:39 +0100 | [diff] [blame] | 291 | at91_st_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1); |
| 292 | at91_st_write(AT91_ST_CR, AT91_ST_WDRST); |
Andrew Victor | 1f4fd0a | 2006-11-30 10:01:47 +0100 | [diff] [blame] | 293 | } |
| 294 | |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 295 | /* -------------------------------------------------------------------- |
| 296 | * AT91RM9200 processor initialization |
| 297 | * -------------------------------------------------------------------- */ |
Jean-Christophe PLAGNIOL-VILLARD | 21d08b9 | 2011-04-23 15:28:34 +0800 | [diff] [blame] | 298 | static void __init at91rm9200_map_io(void) |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 299 | { |
| 300 | /* Map peripherals */ |
Jean-Christophe PLAGNIOL-VILLARD | f0051d8 | 2011-05-10 03:20:09 +0800 | [diff] [blame] | 301 | at91_init_sram(0, AT91RM9200_SRAM_BASE, AT91RM9200_SRAM_SIZE); |
Jean-Christophe PLAGNIOL-VILLARD | 1b021a3 | 2011-04-28 20:19:32 +0800 | [diff] [blame] | 302 | } |
Andrew Victor | 2eeaaa2 | 2006-09-27 10:50:59 +0100 | [diff] [blame] | 303 | |
Jean-Christophe PLAGNIOL-VILLARD | cfa5a1f | 2011-10-14 01:17:18 +0800 | [diff] [blame] | 304 | static void __init at91rm9200_ioremap_registers(void) |
| 305 | { |
Jean-Christophe PLAGNIOL-VILLARD | 5e9cf5e | 2012-02-20 11:07:39 +0100 | [diff] [blame] | 306 | at91rm9200_ioremap_st(AT91RM9200_BASE_ST); |
Jean-Christophe PLAGNIOL-VILLARD | f363c40 | 2012-02-13 12:58:53 +0800 | [diff] [blame] | 307 | at91_ioremap_ramc(0, AT91RM9200_BASE_MC, 256); |
Jean-Christophe PLAGNIOL-VILLARD | cfa5a1f | 2011-10-14 01:17:18 +0800 | [diff] [blame] | 308 | } |
| 309 | |
Jean-Christophe PLAGNIOL-VILLARD | 4653937 | 2011-04-24 18:20:28 +0800 | [diff] [blame] | 310 | static void __init at91rm9200_initialize(void) |
Jean-Christophe PLAGNIOL-VILLARD | 1b021a3 | 2011-04-28 20:19:32 +0800 | [diff] [blame] | 311 | { |
Nicolas Pitre | c9dfafb | 2011-08-02 10:21:36 -0400 | [diff] [blame] | 312 | arm_pm_idle = at91rm9200_idle; |
Russell King | 1b2073e | 2011-11-03 09:53:29 +0000 | [diff] [blame] | 313 | arm_pm_restart = at91rm9200_restart; |
Andrew Victor | 1f4fd0a | 2006-11-30 10:01:47 +0100 | [diff] [blame] | 314 | at91_extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1) |
| 315 | | (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3) |
| 316 | | (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5) |
| 317 | | (1 << AT91RM9200_ID_IRQ6); |
| 318 | |
Andrew Victor | f217383 | 2006-09-27 13:23:00 +0100 | [diff] [blame] | 319 | /* Initialize GPIO subsystem */ |
Jean-Christophe PLAGNIOL-VILLARD | e57556e3 | 2011-04-24 11:40:22 +0800 | [diff] [blame] | 320 | at91_gpio_init(at91rm9200_gpio, |
| 321 | cpu_is_at91rm9200_bga() ? AT91RM9200_BGA : AT91RM9200_PQFP); |
SAN People | 73a59c1 | 2006-01-09 17:05:41 +0000 | [diff] [blame] | 322 | } |
| 323 | |
Andrew Victor | f217383 | 2006-09-27 13:23:00 +0100 | [diff] [blame] | 324 | |
| 325 | /* -------------------------------------------------------------------- |
| 326 | * Interrupt initialization |
| 327 | * -------------------------------------------------------------------- */ |
| 328 | |
Andrew Victor | ba854e1 | 2006-07-05 17:22:52 +0100 | [diff] [blame] | 329 | /* |
| 330 | * The default interrupt priority levels (0 = lowest, 7 = highest). |
| 331 | */ |
| 332 | static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = { |
| 333 | 7, /* Advanced Interrupt Controller (FIQ) */ |
| 334 | 7, /* System Peripherals */ |
Andrew Victor | 7cbed2b | 2007-11-20 08:46:53 +0100 | [diff] [blame] | 335 | 1, /* Parallel IO Controller A */ |
| 336 | 1, /* Parallel IO Controller B */ |
| 337 | 1, /* Parallel IO Controller C */ |
| 338 | 1, /* Parallel IO Controller D */ |
| 339 | 5, /* USART 0 */ |
| 340 | 5, /* USART 1 */ |
| 341 | 5, /* USART 2 */ |
| 342 | 5, /* USART 3 */ |
Andrew Victor | ba854e1 | 2006-07-05 17:22:52 +0100 | [diff] [blame] | 343 | 0, /* Multimedia Card Interface */ |
Andrew Victor | 7cbed2b | 2007-11-20 08:46:53 +0100 | [diff] [blame] | 344 | 2, /* USB Device Port */ |
| 345 | 6, /* Two-Wire Interface */ |
| 346 | 5, /* Serial Peripheral Interface */ |
| 347 | 4, /* Serial Synchronous Controller 0 */ |
| 348 | 4, /* Serial Synchronous Controller 1 */ |
| 349 | 4, /* Serial Synchronous Controller 2 */ |
Andrew Victor | ba854e1 | 2006-07-05 17:22:52 +0100 | [diff] [blame] | 350 | 0, /* Timer Counter 0 */ |
| 351 | 0, /* Timer Counter 1 */ |
| 352 | 0, /* Timer Counter 2 */ |
| 353 | 0, /* Timer Counter 3 */ |
| 354 | 0, /* Timer Counter 4 */ |
| 355 | 0, /* Timer Counter 5 */ |
Andrew Victor | 7cbed2b | 2007-11-20 08:46:53 +0100 | [diff] [blame] | 356 | 2, /* USB Host port */ |
Andrew Victor | ba854e1 | 2006-07-05 17:22:52 +0100 | [diff] [blame] | 357 | 3, /* Ethernet MAC */ |
| 358 | 0, /* Advanced Interrupt Controller (IRQ0) */ |
| 359 | 0, /* Advanced Interrupt Controller (IRQ1) */ |
| 360 | 0, /* Advanced Interrupt Controller (IRQ2) */ |
| 361 | 0, /* Advanced Interrupt Controller (IRQ3) */ |
| 362 | 0, /* Advanced Interrupt Controller (IRQ4) */ |
| 363 | 0, /* Advanced Interrupt Controller (IRQ5) */ |
| 364 | 0 /* Advanced Interrupt Controller (IRQ6) */ |
| 365 | }; |
| 366 | |
Jean-Christophe PLAGNIOL-VILLARD | 8c3583b | 2011-04-23 22:12:57 +0800 | [diff] [blame] | 367 | struct at91_init_soc __initdata at91rm9200_soc = { |
Jean-Christophe PLAGNIOL-VILLARD | 21d08b9 | 2011-04-23 15:28:34 +0800 | [diff] [blame] | 368 | .map_io = at91rm9200_map_io, |
Jean-Christophe PLAGNIOL-VILLARD | 92100c1 | 2011-04-23 15:28:34 +0800 | [diff] [blame] | 369 | .default_irq_priority = at91rm9200_default_irq_priority, |
Jean-Christophe PLAGNIOL-VILLARD | cfa5a1f | 2011-10-14 01:17:18 +0800 | [diff] [blame] | 370 | .ioremap_registers = at91rm9200_ioremap_registers, |
Jean-Christophe PLAGNIOL-VILLARD | 51ddec7 | 2011-04-24 18:15:34 +0800 | [diff] [blame] | 371 | .register_clocks = at91rm9200_register_clocks, |
Jean-Christophe PLAGNIOL-VILLARD | 21d08b9 | 2011-04-23 15:28:34 +0800 | [diff] [blame] | 372 | .init = at91rm9200_initialize, |
| 373 | }; |