Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 1 | /* |
Andrew Victor | 9d04126 | 2007-02-05 11:42:07 +0100 | [diff] [blame] | 2 | * arch/arm/mach-at91/at91sam9260.c |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2006 SAN People |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | */ |
| 12 | |
| 13 | #include <linux/module.h> |
| 14 | |
Nicolas Pitre | c9dfafb | 2011-08-02 10:21:36 -0400 | [diff] [blame] | 15 | #include <asm/proc-fns.h> |
Russell King | 80b02c1 | 2009-01-08 10:01:47 +0000 | [diff] [blame] | 16 | #include <asm/irq.h> |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 17 | #include <asm/mach/arch.h> |
| 18 | #include <asm/mach/map.h> |
David Howells | 9f97da7 | 2012-03-28 18:30:01 +0100 | [diff] [blame] | 19 | #include <asm/system_misc.h> |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 20 | #include <mach/cpu.h> |
Jean-Christophe PLAGNIOL-VILLARD | 8c3583b | 2011-04-23 22:12:57 +0800 | [diff] [blame] | 21 | #include <mach/at91_dbgu.h> |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 22 | #include <mach/at91sam9260.h> |
Ludovic Desroches | 8fe82a5 | 2012-06-21 14:47:27 +0200 | [diff] [blame] | 23 | #include <mach/at91_aic.h> |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 24 | #include <mach/at91_pmc.h> |
| 25 | #include <mach/at91_rstc.h> |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 26 | |
Jean-Christophe PLAGNIOL-VILLARD | 21d08b9 | 2011-04-23 15:28:34 +0800 | [diff] [blame] | 27 | #include "soc.h" |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 28 | #include "generic.h" |
| 29 | #include "clock.h" |
Jean-Christophe PLAGNIOL-VILLARD | faee0cc | 2011-10-14 01:37:09 +0800 | [diff] [blame] | 30 | #include "sam9_smc.h" |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 31 | |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 32 | /* -------------------------------------------------------------------- |
| 33 | * Clocks |
| 34 | * -------------------------------------------------------------------- */ |
| 35 | |
| 36 | /* |
| 37 | * The peripheral clocks. |
| 38 | */ |
| 39 | static struct clk pioA_clk = { |
| 40 | .name = "pioA_clk", |
| 41 | .pmc_mask = 1 << AT91SAM9260_ID_PIOA, |
| 42 | .type = CLK_TYPE_PERIPHERAL, |
| 43 | }; |
| 44 | static struct clk pioB_clk = { |
| 45 | .name = "pioB_clk", |
| 46 | .pmc_mask = 1 << AT91SAM9260_ID_PIOB, |
| 47 | .type = CLK_TYPE_PERIPHERAL, |
| 48 | }; |
| 49 | static struct clk pioC_clk = { |
| 50 | .name = "pioC_clk", |
| 51 | .pmc_mask = 1 << AT91SAM9260_ID_PIOC, |
| 52 | .type = CLK_TYPE_PERIPHERAL, |
| 53 | }; |
| 54 | static struct clk adc_clk = { |
| 55 | .name = "adc_clk", |
| 56 | .pmc_mask = 1 << AT91SAM9260_ID_ADC, |
| 57 | .type = CLK_TYPE_PERIPHERAL, |
| 58 | }; |
Maxime Ripard | 67b5d7b | 2012-05-11 15:35:34 +0200 | [diff] [blame] | 59 | |
| 60 | static struct clk adc_op_clk = { |
| 61 | .name = "adc_op_clk", |
| 62 | .type = CLK_TYPE_PERIPHERAL, |
| 63 | .rate_hz = 5000000, |
| 64 | }; |
| 65 | |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 66 | static struct clk usart0_clk = { |
| 67 | .name = "usart0_clk", |
| 68 | .pmc_mask = 1 << AT91SAM9260_ID_US0, |
| 69 | .type = CLK_TYPE_PERIPHERAL, |
| 70 | }; |
| 71 | static struct clk usart1_clk = { |
| 72 | .name = "usart1_clk", |
| 73 | .pmc_mask = 1 << AT91SAM9260_ID_US1, |
| 74 | .type = CLK_TYPE_PERIPHERAL, |
| 75 | }; |
| 76 | static struct clk usart2_clk = { |
| 77 | .name = "usart2_clk", |
| 78 | .pmc_mask = 1 << AT91SAM9260_ID_US2, |
| 79 | .type = CLK_TYPE_PERIPHERAL, |
| 80 | }; |
| 81 | static struct clk mmc_clk = { |
| 82 | .name = "mci_clk", |
| 83 | .pmc_mask = 1 << AT91SAM9260_ID_MCI, |
| 84 | .type = CLK_TYPE_PERIPHERAL, |
| 85 | }; |
| 86 | static struct clk udc_clk = { |
| 87 | .name = "udc_clk", |
| 88 | .pmc_mask = 1 << AT91SAM9260_ID_UDP, |
| 89 | .type = CLK_TYPE_PERIPHERAL, |
| 90 | }; |
| 91 | static struct clk twi_clk = { |
| 92 | .name = "twi_clk", |
| 93 | .pmc_mask = 1 << AT91SAM9260_ID_TWI, |
| 94 | .type = CLK_TYPE_PERIPHERAL, |
| 95 | }; |
| 96 | static struct clk spi0_clk = { |
| 97 | .name = "spi0_clk", |
| 98 | .pmc_mask = 1 << AT91SAM9260_ID_SPI0, |
| 99 | .type = CLK_TYPE_PERIPHERAL, |
| 100 | }; |
| 101 | static struct clk spi1_clk = { |
| 102 | .name = "spi1_clk", |
| 103 | .pmc_mask = 1 << AT91SAM9260_ID_SPI1, |
| 104 | .type = CLK_TYPE_PERIPHERAL, |
| 105 | }; |
Andrew Victor | e8788ba | 2007-05-02 17:14:57 +0100 | [diff] [blame] | 106 | static struct clk ssc_clk = { |
| 107 | .name = "ssc_clk", |
| 108 | .pmc_mask = 1 << AT91SAM9260_ID_SSC, |
| 109 | .type = CLK_TYPE_PERIPHERAL, |
| 110 | }; |
Andrew Victor | c177a1e | 2007-02-08 10:25:38 +0100 | [diff] [blame] | 111 | static struct clk tc0_clk = { |
| 112 | .name = "tc0_clk", |
| 113 | .pmc_mask = 1 << AT91SAM9260_ID_TC0, |
| 114 | .type = CLK_TYPE_PERIPHERAL, |
| 115 | }; |
| 116 | static struct clk tc1_clk = { |
| 117 | .name = "tc1_clk", |
| 118 | .pmc_mask = 1 << AT91SAM9260_ID_TC1, |
| 119 | .type = CLK_TYPE_PERIPHERAL, |
| 120 | }; |
| 121 | static struct clk tc2_clk = { |
| 122 | .name = "tc2_clk", |
| 123 | .pmc_mask = 1 << AT91SAM9260_ID_TC2, |
| 124 | .type = CLK_TYPE_PERIPHERAL, |
| 125 | }; |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 126 | static struct clk ohci_clk = { |
| 127 | .name = "ohci_clk", |
| 128 | .pmc_mask = 1 << AT91SAM9260_ID_UHP, |
| 129 | .type = CLK_TYPE_PERIPHERAL, |
| 130 | }; |
Andrew Victor | 69b2e99 | 2007-02-14 08:44:43 +0100 | [diff] [blame] | 131 | static struct clk macb_clk = { |
Jamie Iles | 865d605 | 2011-08-09 16:51:11 +0200 | [diff] [blame] | 132 | .name = "pclk", |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 133 | .pmc_mask = 1 << AT91SAM9260_ID_EMAC, |
| 134 | .type = CLK_TYPE_PERIPHERAL, |
| 135 | }; |
| 136 | static struct clk isi_clk = { |
| 137 | .name = "isi_clk", |
| 138 | .pmc_mask = 1 << AT91SAM9260_ID_ISI, |
| 139 | .type = CLK_TYPE_PERIPHERAL, |
| 140 | }; |
| 141 | static struct clk usart3_clk = { |
| 142 | .name = "usart3_clk", |
| 143 | .pmc_mask = 1 << AT91SAM9260_ID_US3, |
| 144 | .type = CLK_TYPE_PERIPHERAL, |
| 145 | }; |
| 146 | static struct clk usart4_clk = { |
| 147 | .name = "usart4_clk", |
| 148 | .pmc_mask = 1 << AT91SAM9260_ID_US4, |
| 149 | .type = CLK_TYPE_PERIPHERAL, |
| 150 | }; |
| 151 | static struct clk usart5_clk = { |
| 152 | .name = "usart5_clk", |
| 153 | .pmc_mask = 1 << AT91SAM9260_ID_US5, |
| 154 | .type = CLK_TYPE_PERIPHERAL, |
| 155 | }; |
Andrew Victor | c177a1e | 2007-02-08 10:25:38 +0100 | [diff] [blame] | 156 | static struct clk tc3_clk = { |
| 157 | .name = "tc3_clk", |
| 158 | .pmc_mask = 1 << AT91SAM9260_ID_TC3, |
| 159 | .type = CLK_TYPE_PERIPHERAL, |
| 160 | }; |
| 161 | static struct clk tc4_clk = { |
| 162 | .name = "tc4_clk", |
| 163 | .pmc_mask = 1 << AT91SAM9260_ID_TC4, |
| 164 | .type = CLK_TYPE_PERIPHERAL, |
| 165 | }; |
| 166 | static struct clk tc5_clk = { |
| 167 | .name = "tc5_clk", |
| 168 | .pmc_mask = 1 << AT91SAM9260_ID_TC5, |
| 169 | .type = CLK_TYPE_PERIPHERAL, |
| 170 | }; |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 171 | |
| 172 | static struct clk *periph_clocks[] __initdata = { |
| 173 | &pioA_clk, |
| 174 | &pioB_clk, |
| 175 | &pioC_clk, |
| 176 | &adc_clk, |
Maxime Ripard | 67b5d7b | 2012-05-11 15:35:34 +0200 | [diff] [blame] | 177 | &adc_op_clk, |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 178 | &usart0_clk, |
| 179 | &usart1_clk, |
| 180 | &usart2_clk, |
| 181 | &mmc_clk, |
| 182 | &udc_clk, |
| 183 | &twi_clk, |
| 184 | &spi0_clk, |
| 185 | &spi1_clk, |
Andrew Victor | e8788ba | 2007-05-02 17:14:57 +0100 | [diff] [blame] | 186 | &ssc_clk, |
Andrew Victor | c177a1e | 2007-02-08 10:25:38 +0100 | [diff] [blame] | 187 | &tc0_clk, |
| 188 | &tc1_clk, |
| 189 | &tc2_clk, |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 190 | &ohci_clk, |
Andrew Victor | 69b2e99 | 2007-02-14 08:44:43 +0100 | [diff] [blame] | 191 | &macb_clk, |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 192 | &isi_clk, |
| 193 | &usart3_clk, |
| 194 | &usart4_clk, |
| 195 | &usart5_clk, |
Andrew Victor | c177a1e | 2007-02-08 10:25:38 +0100 | [diff] [blame] | 196 | &tc3_clk, |
| 197 | &tc4_clk, |
| 198 | &tc5_clk, |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 199 | // irq0 .. irq2 |
| 200 | }; |
| 201 | |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 202 | static struct clk_lookup periph_clocks_lookups[] = { |
Jamie Iles | 865d605 | 2011-08-09 16:51:11 +0200 | [diff] [blame] | 203 | /* One additional fake clock for macb_hclk */ |
| 204 | CLKDEV_CON_ID("hclk", &macb_clk), |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 205 | CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk), |
| 206 | CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk), |
| 207 | CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk), |
| 208 | CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk), |
| 209 | CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk), |
Jean-Christophe PLAGNIOL-VILLARD | 1808958 | 2011-11-28 12:53:08 +0100 | [diff] [blame] | 210 | CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk), |
| 211 | CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk), |
| 212 | CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk), |
Bo Shen | 636036d2 | 2012-11-06 13:57:51 +0800 | [diff] [blame] | 213 | CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc_clk), |
Bo Shen | 099343c | 2012-11-07 11:41:41 +0800 | [diff] [blame] | 214 | CLKDEV_CON_DEV_ID("pclk", "fffbc000.ssc", &ssc_clk), |
Bo Shen | 302090a | 2012-10-15 17:30:28 +0800 | [diff] [blame] | 215 | CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260.0", &twi_clk), |
| 216 | CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi_clk), |
Jean-Christophe PLAGNIOL-VILLARD | fea3158 | 2011-10-14 09:40:52 +0800 | [diff] [blame] | 217 | /* more usart lookup table for DT entries */ |
| 218 | CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck), |
| 219 | CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk), |
| 220 | CLKDEV_CON_DEV_ID("usart", "fffb4000.serial", &usart1_clk), |
| 221 | CLKDEV_CON_DEV_ID("usart", "fffb8000.serial", &usart2_clk), |
| 222 | CLKDEV_CON_DEV_ID("usart", "fffd0000.serial", &usart3_clk), |
| 223 | CLKDEV_CON_DEV_ID("usart", "fffd4000.serial", &usart4_clk), |
| 224 | CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk), |
Ludovic Desroches | f7d19b9 | 2012-09-12 08:42:15 +0200 | [diff] [blame] | 225 | CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi_clk), |
Nicolas Ferre | 3a61a5d | 2012-01-19 10:13:40 +0100 | [diff] [blame] | 226 | /* more tc lookup table for DT entries */ |
| 227 | CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk), |
| 228 | CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk), |
| 229 | CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk), |
| 230 | CLKDEV_CON_DEV_ID("t0_clk", "fffdc000.timer", &tc3_clk), |
| 231 | CLKDEV_CON_DEV_ID("t1_clk", "fffdc000.timer", &tc4_clk), |
| 232 | CLKDEV_CON_DEV_ID("t2_clk", "fffdc000.timer", &tc5_clk), |
Jean-Christophe PLAGNIOL-VILLARD | 6a06245 | 2011-11-21 06:55:18 +0800 | [diff] [blame] | 233 | CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &ohci_clk), |
Jean-Christophe PLAGNIOL-VILLARD | 0af4316 | 2011-08-30 03:29:28 +0200 | [diff] [blame] | 234 | /* fake hclk clock */ |
| 235 | CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk), |
Jean-Christophe PLAGNIOL-VILLARD | 619d4a4 | 2011-11-13 13:00:58 +0800 | [diff] [blame] | 236 | CLKDEV_CON_ID("pioA", &pioA_clk), |
| 237 | CLKDEV_CON_ID("pioB", &pioB_clk), |
| 238 | CLKDEV_CON_ID("pioC", &pioC_clk), |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 239 | }; |
| 240 | |
| 241 | static struct clk_lookup usart_clocks_lookups[] = { |
| 242 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck), |
| 243 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk), |
| 244 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk), |
| 245 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk), |
| 246 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk), |
| 247 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.5", &usart4_clk), |
| 248 | CLKDEV_CON_DEV_ID("usart", "atmel_usart.6", &usart5_clk), |
| 249 | }; |
| 250 | |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 251 | /* |
| 252 | * The two programmable clocks. |
| 253 | * You must configure pin multiplexing to bring these signals out. |
| 254 | */ |
| 255 | static struct clk pck0 = { |
| 256 | .name = "pck0", |
| 257 | .pmc_mask = AT91_PMC_PCK0, |
| 258 | .type = CLK_TYPE_PROGRAMMABLE, |
| 259 | .id = 0, |
| 260 | }; |
| 261 | static struct clk pck1 = { |
| 262 | .name = "pck1", |
| 263 | .pmc_mask = AT91_PMC_PCK1, |
| 264 | .type = CLK_TYPE_PROGRAMMABLE, |
| 265 | .id = 1, |
| 266 | }; |
| 267 | |
| 268 | static void __init at91sam9260_register_clocks(void) |
| 269 | { |
| 270 | int i; |
| 271 | |
| 272 | for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) |
| 273 | clk_register(periph_clocks[i]); |
| 274 | |
Jean-Christophe PLAGNIOL-VILLARD | bd60299 | 2011-02-02 07:27:07 +0100 | [diff] [blame] | 275 | clkdev_add_table(periph_clocks_lookups, |
| 276 | ARRAY_SIZE(periph_clocks_lookups)); |
| 277 | clkdev_add_table(usart_clocks_lookups, |
| 278 | ARRAY_SIZE(usart_clocks_lookups)); |
| 279 | |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 280 | clk_register(&pck0); |
| 281 | clk_register(&pck1); |
| 282 | } |
| 283 | |
| 284 | /* -------------------------------------------------------------------- |
| 285 | * GPIO |
| 286 | * -------------------------------------------------------------------- */ |
| 287 | |
Jean-Christophe PLAGNIOL-VILLARD | 1a2d915 | 2011-10-17 14:28:38 +0800 | [diff] [blame] | 288 | static struct at91_gpio_bank at91sam9260_gpio[] __initdata = { |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 289 | { |
| 290 | .id = AT91SAM9260_ID_PIOA, |
Jean-Christophe PLAGNIOL-VILLARD | 80e91cb | 2011-09-16 23:37:50 +0800 | [diff] [blame] | 291 | .regbase = AT91SAM9260_BASE_PIOA, |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 292 | }, { |
| 293 | .id = AT91SAM9260_ID_PIOB, |
Jean-Christophe PLAGNIOL-VILLARD | 80e91cb | 2011-09-16 23:37:50 +0800 | [diff] [blame] | 294 | .regbase = AT91SAM9260_BASE_PIOB, |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 295 | }, { |
| 296 | .id = AT91SAM9260_ID_PIOC, |
Jean-Christophe PLAGNIOL-VILLARD | 80e91cb | 2011-09-16 23:37:50 +0800 | [diff] [blame] | 297 | .regbase = AT91SAM9260_BASE_PIOC, |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 298 | } |
| 299 | }; |
| 300 | |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 301 | /* -------------------------------------------------------------------- |
| 302 | * AT91SAM9260 processor initialization |
| 303 | * -------------------------------------------------------------------- */ |
| 304 | |
Jean-Christophe PLAGNIOL-VILLARD | 1b021a3 | 2011-04-28 20:19:32 +0800 | [diff] [blame] | 305 | static void __init at91sam9xe_map_io(void) |
Andrew Victor | f7eee89 | 2007-02-15 08:17:38 +0100 | [diff] [blame] | 306 | { |
Jean-Christophe PLAGNIOL-VILLARD | 8c3583b | 2011-04-23 22:12:57 +0800 | [diff] [blame] | 307 | unsigned long sram_size; |
Andrew Victor | f7eee89 | 2007-02-15 08:17:38 +0100 | [diff] [blame] | 308 | |
Jean-Christophe PLAGNIOL-VILLARD | 8c3583b | 2011-04-23 22:12:57 +0800 | [diff] [blame] | 309 | switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) { |
Andrew Victor | f7eee89 | 2007-02-15 08:17:38 +0100 | [diff] [blame] | 310 | case AT91_CIDR_SRAMSIZ_32K: |
| 311 | sram_size = 2 * SZ_16K; |
| 312 | break; |
| 313 | case AT91_CIDR_SRAMSIZ_16K: |
| 314 | default: |
| 315 | sram_size = SZ_16K; |
| 316 | } |
| 317 | |
Jean-Christophe PLAGNIOL-VILLARD | f0051d8 | 2011-05-10 03:20:09 +0800 | [diff] [blame] | 318 | at91_init_sram(0, AT91SAM9XE_SRAM_BASE, sram_size); |
Andrew Victor | f7eee89 | 2007-02-15 08:17:38 +0100 | [diff] [blame] | 319 | } |
| 320 | |
Jean-Christophe PLAGNIOL-VILLARD | 21d08b9 | 2011-04-23 15:28:34 +0800 | [diff] [blame] | 321 | static void __init at91sam9260_map_io(void) |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 322 | { |
Jean-Christophe PLAGNIOL-VILLARD | c9b1e3f | 2011-12-07 18:34:47 +0800 | [diff] [blame] | 323 | if (cpu_is_at91sam9xe()) |
Jean-Christophe PLAGNIOL-VILLARD | 1b021a3 | 2011-04-28 20:19:32 +0800 | [diff] [blame] | 324 | at91sam9xe_map_io(); |
Jean-Christophe PLAGNIOL-VILLARD | c9b1e3f | 2011-12-07 18:34:47 +0800 | [diff] [blame] | 325 | else if (cpu_is_at91sam9g20()) |
| 326 | at91_init_sram(0, AT91SAM9G20_SRAM_BASE, AT91SAM9G20_SRAM_SIZE); |
| 327 | else |
| 328 | at91_init_sram(0, AT91SAM9260_SRAM_BASE, AT91SAM9260_SRAM_SIZE); |
Jean-Christophe PLAGNIOL-VILLARD | 1b021a3 | 2011-04-28 20:19:32 +0800 | [diff] [blame] | 329 | } |
Andrew Victor | f7eee89 | 2007-02-15 08:17:38 +0100 | [diff] [blame] | 330 | |
Jean-Christophe PLAGNIOL-VILLARD | cfa5a1f | 2011-10-14 01:17:18 +0800 | [diff] [blame] | 331 | static void __init at91sam9260_ioremap_registers(void) |
| 332 | { |
Jean-Christophe PLAGNIOL-VILLARD | f22deee | 2011-11-01 01:23:20 +0800 | [diff] [blame] | 333 | at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC); |
Jean-Christophe PLAGNIOL-VILLARD | e9f68b5 | 2011-11-18 01:25:52 +0800 | [diff] [blame] | 334 | at91_ioremap_rstc(AT91SAM9260_BASE_RSTC); |
Jean-Christophe PLAGNIOL-VILLARD | f363c40 | 2012-02-13 12:58:53 +0800 | [diff] [blame] | 335 | at91_ioremap_ramc(0, AT91SAM9260_BASE_SDRAMC, 512); |
Jean-Christophe PLAGNIOL-VILLARD | 4ab0c599 | 2011-09-18 22:29:50 +0800 | [diff] [blame] | 336 | at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT); |
Jean-Christophe PLAGNIOL-VILLARD | faee0cc | 2011-10-14 01:37:09 +0800 | [diff] [blame] | 337 | at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC); |
Jean-Christophe PLAGNIOL-VILLARD | 4342d64 | 2011-11-27 23:15:50 +0800 | [diff] [blame] | 338 | at91_ioremap_matrix(AT91SAM9260_BASE_MATRIX); |
Jean-Christophe PLAGNIOL-VILLARD | cfa5a1f | 2011-10-14 01:17:18 +0800 | [diff] [blame] | 339 | } |
| 340 | |
Jean-Christophe PLAGNIOL-VILLARD | 4653937 | 2011-04-24 18:20:28 +0800 | [diff] [blame] | 341 | static void __init at91sam9260_initialize(void) |
Jean-Christophe PLAGNIOL-VILLARD | 1b021a3 | 2011-04-28 20:19:32 +0800 | [diff] [blame] | 342 | { |
Jean-Christophe PLAGNIOL-VILLARD | 0d78171 | 2012-02-05 20:25:32 +0800 | [diff] [blame] | 343 | arm_pm_idle = at91sam9_idle; |
Russell King | 1b2073e | 2011-11-03 09:53:29 +0000 | [diff] [blame] | 344 | arm_pm_restart = at91sam9_alt_restart; |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 345 | at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1) |
| 346 | | (1 << AT91SAM9260_ID_IRQ2); |
| 347 | |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 348 | /* Register GPIO subsystem */ |
| 349 | at91_gpio_init(at91sam9260_gpio, 3); |
| 350 | } |
| 351 | |
| 352 | /* -------------------------------------------------------------------- |
| 353 | * Interrupt initialization |
| 354 | * -------------------------------------------------------------------- */ |
| 355 | |
| 356 | /* |
| 357 | * The default interrupt priority levels (0 = lowest, 7 = highest). |
| 358 | */ |
| 359 | static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = { |
| 360 | 7, /* Advanced Interrupt Controller */ |
| 361 | 7, /* System Peripherals */ |
Andrew Victor | 7cbed2b | 2007-11-20 08:46:53 +0100 | [diff] [blame] | 362 | 1, /* Parallel IO Controller A */ |
| 363 | 1, /* Parallel IO Controller B */ |
| 364 | 1, /* Parallel IO Controller C */ |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 365 | 0, /* Analog-to-Digital Converter */ |
Andrew Victor | 7cbed2b | 2007-11-20 08:46:53 +0100 | [diff] [blame] | 366 | 5, /* USART 0 */ |
| 367 | 5, /* USART 1 */ |
| 368 | 5, /* USART 2 */ |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 369 | 0, /* Multimedia Card Interface */ |
Andrew Victor | 7cbed2b | 2007-11-20 08:46:53 +0100 | [diff] [blame] | 370 | 2, /* USB Device Port */ |
| 371 | 6, /* Two-Wire Interface */ |
| 372 | 5, /* Serial Peripheral Interface 0 */ |
| 373 | 5, /* Serial Peripheral Interface 1 */ |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 374 | 5, /* Serial Synchronous Controller */ |
| 375 | 0, |
| 376 | 0, |
| 377 | 0, /* Timer Counter 0 */ |
| 378 | 0, /* Timer Counter 1 */ |
| 379 | 0, /* Timer Counter 2 */ |
Andrew Victor | 7cbed2b | 2007-11-20 08:46:53 +0100 | [diff] [blame] | 380 | 2, /* USB Host port */ |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 381 | 3, /* Ethernet */ |
| 382 | 0, /* Image Sensor Interface */ |
Andrew Victor | 7cbed2b | 2007-11-20 08:46:53 +0100 | [diff] [blame] | 383 | 5, /* USART 3 */ |
| 384 | 5, /* USART 4 */ |
| 385 | 5, /* USART 5 */ |
Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 386 | 0, /* Timer Counter 3 */ |
| 387 | 0, /* Timer Counter 4 */ |
| 388 | 0, /* Timer Counter 5 */ |
| 389 | 0, /* Advanced Interrupt Controller */ |
| 390 | 0, /* Advanced Interrupt Controller */ |
| 391 | 0, /* Advanced Interrupt Controller */ |
| 392 | }; |
| 393 | |
Jean-Christophe PLAGNIOL-VILLARD | 8c3583b | 2011-04-23 22:12:57 +0800 | [diff] [blame] | 394 | struct at91_init_soc __initdata at91sam9260_soc = { |
Jean-Christophe PLAGNIOL-VILLARD | 21d08b9 | 2011-04-23 15:28:34 +0800 | [diff] [blame] | 395 | .map_io = at91sam9260_map_io, |
Jean-Christophe PLAGNIOL-VILLARD | 92100c1 | 2011-04-23 15:28:34 +0800 | [diff] [blame] | 396 | .default_irq_priority = at91sam9260_default_irq_priority, |
Jean-Christophe PLAGNIOL-VILLARD | cfa5a1f | 2011-10-14 01:17:18 +0800 | [diff] [blame] | 397 | .ioremap_registers = at91sam9260_ioremap_registers, |
Jean-Christophe PLAGNIOL-VILLARD | 51ddec7 | 2011-04-24 18:15:34 +0800 | [diff] [blame] | 398 | .register_clocks = at91sam9260_register_clocks, |
Jean-Christophe PLAGNIOL-VILLARD | 21d08b9 | 2011-04-23 15:28:34 +0800 | [diff] [blame] | 399 | .init = at91sam9260_initialize, |
| 400 | }; |