blob: b50f97811c25187db2408e18495bacf0de625537 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Uwe Zeisbergerf30c2262006-10-03 23:01:26 +02002 * arch/powerpc/sysdev/ipic.c
Linus Torvalds1da177e2005-04-16 15:20:36 -07003 *
4 * IPIC routines implementations.
5 *
6 * Copyright 2005 Freescale Semiconductor, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/errno.h>
16#include <linux/reboot.h>
17#include <linux/slab.h>
18#include <linux/stddef.h>
19#include <linux/sched.h>
20#include <linux/signal.h>
Rafael J. Wysockif5a592f2011-04-26 19:14:57 +020021#include <linux/syscore_ops.h>
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -050022#include <linux/device.h>
23#include <linux/bootmem.h>
24#include <linux/spinlock.h>
Scott Woodd49747b2007-10-09 12:37:13 -050025#include <linux/fsl_devices.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070026#include <asm/irq.h>
27#include <asm/io.h>
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -050028#include <asm/prom.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070029#include <asm/ipic.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070030
31#include "ipic.h"
32
Linus Torvalds1da177e2005-04-16 15:20:36 -070033static struct ipic * primary_ipic;
Li Yang77d43092007-12-04 19:01:40 +080034static struct irq_chip ipic_level_irq_chip, ipic_edge_irq_chip;
Thomas Gleixnera9e8bf22010-02-18 02:23:14 +000035static DEFINE_RAW_SPINLOCK(ipic_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -070036
37static struct ipic_info ipic_info[] = {
Li Yangf03ca952007-10-19 19:38:43 +080038 [1] = {
Li Yangf03ca952007-10-19 19:38:43 +080039 .mask = IPIC_SIMSR_H,
40 .prio = IPIC_SIPRR_C,
41 .force = IPIC_SIFCR_H,
42 .bit = 16,
43 .prio_mask = 0,
44 },
45 [2] = {
Li Yangf03ca952007-10-19 19:38:43 +080046 .mask = IPIC_SIMSR_H,
47 .prio = IPIC_SIPRR_C,
48 .force = IPIC_SIFCR_H,
49 .bit = 17,
50 .prio_mask = 1,
51 },
John Rigbya7267d62008-01-17 17:05:32 -070052 [3] = {
53 .mask = IPIC_SIMSR_H,
54 .prio = IPIC_SIPRR_C,
55 .force = IPIC_SIFCR_H,
56 .bit = 18,
57 .prio_mask = 2,
58 },
Li Yangf03ca952007-10-19 19:38:43 +080059 [4] = {
Li Yangf03ca952007-10-19 19:38:43 +080060 .mask = IPIC_SIMSR_H,
61 .prio = IPIC_SIPRR_C,
62 .force = IPIC_SIFCR_H,
63 .bit = 19,
64 .prio_mask = 3,
65 },
John Rigbya7267d62008-01-17 17:05:32 -070066 [5] = {
67 .mask = IPIC_SIMSR_H,
68 .prio = IPIC_SIPRR_C,
69 .force = IPIC_SIFCR_H,
70 .bit = 20,
71 .prio_mask = 4,
72 },
73 [6] = {
74 .mask = IPIC_SIMSR_H,
75 .prio = IPIC_SIPRR_C,
76 .force = IPIC_SIFCR_H,
77 .bit = 21,
78 .prio_mask = 5,
79 },
80 [7] = {
81 .mask = IPIC_SIMSR_H,
82 .prio = IPIC_SIPRR_C,
83 .force = IPIC_SIFCR_H,
84 .bit = 22,
85 .prio_mask = 6,
86 },
87 [8] = {
88 .mask = IPIC_SIMSR_H,
89 .prio = IPIC_SIPRR_C,
90 .force = IPIC_SIFCR_H,
91 .bit = 23,
92 .prio_mask = 7,
93 },
Linus Torvalds1da177e2005-04-16 15:20:36 -070094 [9] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -070095 .mask = IPIC_SIMSR_H,
96 .prio = IPIC_SIPRR_D,
97 .force = IPIC_SIFCR_H,
98 .bit = 24,
99 .prio_mask = 0,
100 },
101 [10] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700102 .mask = IPIC_SIMSR_H,
103 .prio = IPIC_SIPRR_D,
104 .force = IPIC_SIFCR_H,
105 .bit = 25,
106 .prio_mask = 1,
107 },
108 [11] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700109 .mask = IPIC_SIMSR_H,
110 .prio = IPIC_SIPRR_D,
111 .force = IPIC_SIFCR_H,
112 .bit = 26,
113 .prio_mask = 2,
114 },
Li Yangf03ca952007-10-19 19:38:43 +0800115 [12] = {
Li Yangf03ca952007-10-19 19:38:43 +0800116 .mask = IPIC_SIMSR_H,
117 .prio = IPIC_SIPRR_D,
118 .force = IPIC_SIFCR_H,
119 .bit = 27,
120 .prio_mask = 3,
121 },
122 [13] = {
Li Yangf03ca952007-10-19 19:38:43 +0800123 .mask = IPIC_SIMSR_H,
124 .prio = IPIC_SIPRR_D,
125 .force = IPIC_SIFCR_H,
126 .bit = 28,
127 .prio_mask = 4,
128 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700129 [14] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700130 .mask = IPIC_SIMSR_H,
131 .prio = IPIC_SIPRR_D,
132 .force = IPIC_SIFCR_H,
133 .bit = 29,
134 .prio_mask = 5,
135 },
136 [15] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700137 .mask = IPIC_SIMSR_H,
138 .prio = IPIC_SIPRR_D,
139 .force = IPIC_SIFCR_H,
140 .bit = 30,
141 .prio_mask = 6,
142 },
143 [16] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700144 .mask = IPIC_SIMSR_H,
145 .prio = IPIC_SIPRR_D,
146 .force = IPIC_SIFCR_H,
147 .bit = 31,
148 .prio_mask = 7,
149 },
150 [17] = {
Li Yang77d43092007-12-04 19:01:40 +0800151 .ack = IPIC_SEPNR,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700152 .mask = IPIC_SEMSR,
153 .prio = IPIC_SMPRR_A,
154 .force = IPIC_SEFCR,
155 .bit = 1,
156 .prio_mask = 5,
157 },
158 [18] = {
Li Yang77d43092007-12-04 19:01:40 +0800159 .ack = IPIC_SEPNR,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700160 .mask = IPIC_SEMSR,
161 .prio = IPIC_SMPRR_A,
162 .force = IPIC_SEFCR,
163 .bit = 2,
164 .prio_mask = 6,
165 },
166 [19] = {
Li Yang77d43092007-12-04 19:01:40 +0800167 .ack = IPIC_SEPNR,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700168 .mask = IPIC_SEMSR,
169 .prio = IPIC_SMPRR_A,
170 .force = IPIC_SEFCR,
171 .bit = 3,
172 .prio_mask = 7,
173 },
174 [20] = {
Li Yang77d43092007-12-04 19:01:40 +0800175 .ack = IPIC_SEPNR,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700176 .mask = IPIC_SEMSR,
177 .prio = IPIC_SMPRR_B,
178 .force = IPIC_SEFCR,
179 .bit = 4,
180 .prio_mask = 4,
181 },
182 [21] = {
Li Yang77d43092007-12-04 19:01:40 +0800183 .ack = IPIC_SEPNR,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700184 .mask = IPIC_SEMSR,
185 .prio = IPIC_SMPRR_B,
186 .force = IPIC_SEFCR,
187 .bit = 5,
188 .prio_mask = 5,
189 },
190 [22] = {
Li Yang77d43092007-12-04 19:01:40 +0800191 .ack = IPIC_SEPNR,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700192 .mask = IPIC_SEMSR,
193 .prio = IPIC_SMPRR_B,
194 .force = IPIC_SEFCR,
195 .bit = 6,
196 .prio_mask = 6,
197 },
198 [23] = {
Li Yang77d43092007-12-04 19:01:40 +0800199 .ack = IPIC_SEPNR,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700200 .mask = IPIC_SEMSR,
201 .prio = IPIC_SMPRR_B,
202 .force = IPIC_SEFCR,
203 .bit = 7,
204 .prio_mask = 7,
205 },
206 [32] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700207 .mask = IPIC_SIMSR_H,
208 .prio = IPIC_SIPRR_A,
209 .force = IPIC_SIFCR_H,
210 .bit = 0,
211 .prio_mask = 0,
212 },
213 [33] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700214 .mask = IPIC_SIMSR_H,
215 .prio = IPIC_SIPRR_A,
216 .force = IPIC_SIFCR_H,
217 .bit = 1,
218 .prio_mask = 1,
219 },
220 [34] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700221 .mask = IPIC_SIMSR_H,
222 .prio = IPIC_SIPRR_A,
223 .force = IPIC_SIFCR_H,
224 .bit = 2,
225 .prio_mask = 2,
226 },
227 [35] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700228 .mask = IPIC_SIMSR_H,
229 .prio = IPIC_SIPRR_A,
230 .force = IPIC_SIFCR_H,
231 .bit = 3,
232 .prio_mask = 3,
233 },
234 [36] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700235 .mask = IPIC_SIMSR_H,
236 .prio = IPIC_SIPRR_A,
237 .force = IPIC_SIFCR_H,
238 .bit = 4,
239 .prio_mask = 4,
240 },
241 [37] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700242 .mask = IPIC_SIMSR_H,
243 .prio = IPIC_SIPRR_A,
244 .force = IPIC_SIFCR_H,
245 .bit = 5,
246 .prio_mask = 5,
247 },
248 [38] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700249 .mask = IPIC_SIMSR_H,
250 .prio = IPIC_SIPRR_A,
251 .force = IPIC_SIFCR_H,
252 .bit = 6,
253 .prio_mask = 6,
254 },
255 [39] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700256 .mask = IPIC_SIMSR_H,
257 .prio = IPIC_SIPRR_A,
258 .force = IPIC_SIFCR_H,
259 .bit = 7,
260 .prio_mask = 7,
261 },
John Rigbya7267d62008-01-17 17:05:32 -0700262 [40] = {
263 .mask = IPIC_SIMSR_H,
264 .prio = IPIC_SIPRR_B,
265 .force = IPIC_SIFCR_H,
266 .bit = 8,
267 .prio_mask = 0,
268 },
269 [41] = {
270 .mask = IPIC_SIMSR_H,
271 .prio = IPIC_SIPRR_B,
272 .force = IPIC_SIFCR_H,
273 .bit = 9,
274 .prio_mask = 1,
275 },
Li Yangf03ca952007-10-19 19:38:43 +0800276 [42] = {
Li Yangf03ca952007-10-19 19:38:43 +0800277 .mask = IPIC_SIMSR_H,
278 .prio = IPIC_SIPRR_B,
279 .force = IPIC_SIFCR_H,
280 .bit = 10,
281 .prio_mask = 2,
282 },
John Rigbya7267d62008-01-17 17:05:32 -0700283 [43] = {
284 .mask = IPIC_SIMSR_H,
285 .prio = IPIC_SIPRR_B,
286 .force = IPIC_SIFCR_H,
287 .bit = 11,
288 .prio_mask = 3,
289 },
Li Yangf03ca952007-10-19 19:38:43 +0800290 [44] = {
Li Yangf03ca952007-10-19 19:38:43 +0800291 .mask = IPIC_SIMSR_H,
292 .prio = IPIC_SIPRR_B,
293 .force = IPIC_SIFCR_H,
294 .bit = 12,
295 .prio_mask = 4,
296 },
297 [45] = {
Li Yangf03ca952007-10-19 19:38:43 +0800298 .mask = IPIC_SIMSR_H,
299 .prio = IPIC_SIPRR_B,
300 .force = IPIC_SIFCR_H,
301 .bit = 13,
302 .prio_mask = 5,
303 },
304 [46] = {
Li Yangf03ca952007-10-19 19:38:43 +0800305 .mask = IPIC_SIMSR_H,
306 .prio = IPIC_SIPRR_B,
307 .force = IPIC_SIFCR_H,
308 .bit = 14,
309 .prio_mask = 6,
310 },
311 [47] = {
Li Yangf03ca952007-10-19 19:38:43 +0800312 .mask = IPIC_SIMSR_H,
313 .prio = IPIC_SIPRR_B,
314 .force = IPIC_SIFCR_H,
315 .bit = 15,
316 .prio_mask = 7,
317 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700318 [48] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700319 .mask = IPIC_SEMSR,
320 .prio = IPIC_SMPRR_A,
321 .force = IPIC_SEFCR,
322 .bit = 0,
323 .prio_mask = 4,
324 },
325 [64] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700326 .mask = IPIC_SIMSR_L,
327 .prio = IPIC_SMPRR_A,
328 .force = IPIC_SIFCR_L,
329 .bit = 0,
330 .prio_mask = 0,
331 },
332 [65] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700333 .mask = IPIC_SIMSR_L,
334 .prio = IPIC_SMPRR_A,
335 .force = IPIC_SIFCR_L,
336 .bit = 1,
337 .prio_mask = 1,
338 },
339 [66] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700340 .mask = IPIC_SIMSR_L,
341 .prio = IPIC_SMPRR_A,
342 .force = IPIC_SIFCR_L,
343 .bit = 2,
344 .prio_mask = 2,
345 },
346 [67] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700347 .mask = IPIC_SIMSR_L,
348 .prio = IPIC_SMPRR_A,
349 .force = IPIC_SIFCR_L,
350 .bit = 3,
351 .prio_mask = 3,
352 },
353 [68] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700354 .mask = IPIC_SIMSR_L,
355 .prio = IPIC_SMPRR_B,
356 .force = IPIC_SIFCR_L,
357 .bit = 4,
358 .prio_mask = 0,
359 },
360 [69] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700361 .mask = IPIC_SIMSR_L,
362 .prio = IPIC_SMPRR_B,
363 .force = IPIC_SIFCR_L,
364 .bit = 5,
365 .prio_mask = 1,
366 },
367 [70] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700368 .mask = IPIC_SIMSR_L,
369 .prio = IPIC_SMPRR_B,
370 .force = IPIC_SIFCR_L,
371 .bit = 6,
372 .prio_mask = 2,
373 },
374 [71] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700375 .mask = IPIC_SIMSR_L,
376 .prio = IPIC_SMPRR_B,
377 .force = IPIC_SIFCR_L,
378 .bit = 7,
379 .prio_mask = 3,
380 },
381 [72] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700382 .mask = IPIC_SIMSR_L,
383 .prio = 0,
384 .force = IPIC_SIFCR_L,
385 .bit = 8,
386 },
387 [73] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700388 .mask = IPIC_SIMSR_L,
389 .prio = 0,
390 .force = IPIC_SIFCR_L,
391 .bit = 9,
392 },
393 [74] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700394 .mask = IPIC_SIMSR_L,
395 .prio = 0,
396 .force = IPIC_SIFCR_L,
397 .bit = 10,
398 },
399 [75] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700400 .mask = IPIC_SIMSR_L,
401 .prio = 0,
402 .force = IPIC_SIFCR_L,
403 .bit = 11,
404 },
405 [76] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700406 .mask = IPIC_SIMSR_L,
407 .prio = 0,
408 .force = IPIC_SIFCR_L,
409 .bit = 12,
410 },
411 [77] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700412 .mask = IPIC_SIMSR_L,
413 .prio = 0,
414 .force = IPIC_SIFCR_L,
415 .bit = 13,
416 },
417 [78] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700418 .mask = IPIC_SIMSR_L,
419 .prio = 0,
420 .force = IPIC_SIFCR_L,
421 .bit = 14,
422 },
423 [79] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700424 .mask = IPIC_SIMSR_L,
425 .prio = 0,
426 .force = IPIC_SIFCR_L,
427 .bit = 15,
428 },
429 [80] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700430 .mask = IPIC_SIMSR_L,
431 .prio = 0,
432 .force = IPIC_SIFCR_L,
433 .bit = 16,
434 },
Li Yangf03ca952007-10-19 19:38:43 +0800435 [81] = {
Li Yangf03ca952007-10-19 19:38:43 +0800436 .mask = IPIC_SIMSR_L,
437 .prio = 0,
438 .force = IPIC_SIFCR_L,
439 .bit = 17,
440 },
441 [82] = {
Li Yangf03ca952007-10-19 19:38:43 +0800442 .mask = IPIC_SIMSR_L,
443 .prio = 0,
444 .force = IPIC_SIFCR_L,
445 .bit = 18,
446 },
John Rigbya7267d62008-01-17 17:05:32 -0700447 [83] = {
448 .mask = IPIC_SIMSR_L,
449 .prio = 0,
450 .force = IPIC_SIFCR_L,
451 .bit = 19,
452 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700453 [84] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700454 .mask = IPIC_SIMSR_L,
455 .prio = 0,
456 .force = IPIC_SIFCR_L,
457 .bit = 20,
458 },
459 [85] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700460 .mask = IPIC_SIMSR_L,
461 .prio = 0,
462 .force = IPIC_SIFCR_L,
463 .bit = 21,
464 },
Li Yangf03ca952007-10-19 19:38:43 +0800465 [86] = {
Li Yangf03ca952007-10-19 19:38:43 +0800466 .mask = IPIC_SIMSR_L,
467 .prio = 0,
468 .force = IPIC_SIFCR_L,
469 .bit = 22,
470 },
471 [87] = {
Li Yangf03ca952007-10-19 19:38:43 +0800472 .mask = IPIC_SIMSR_L,
473 .prio = 0,
474 .force = IPIC_SIFCR_L,
475 .bit = 23,
476 },
477 [88] = {
Li Yangf03ca952007-10-19 19:38:43 +0800478 .mask = IPIC_SIMSR_L,
479 .prio = 0,
480 .force = IPIC_SIFCR_L,
481 .bit = 24,
482 },
483 [89] = {
Li Yangf03ca952007-10-19 19:38:43 +0800484 .mask = IPIC_SIMSR_L,
485 .prio = 0,
486 .force = IPIC_SIFCR_L,
487 .bit = 25,
488 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700489 [90] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700490 .mask = IPIC_SIMSR_L,
491 .prio = 0,
492 .force = IPIC_SIFCR_L,
493 .bit = 26,
494 },
495 [91] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700496 .mask = IPIC_SIMSR_L,
497 .prio = 0,
498 .force = IPIC_SIFCR_L,
499 .bit = 27,
500 },
Kim Phillips8cf6b1952008-01-24 20:46:50 -0600501 [94] = {
502 .mask = IPIC_SIMSR_L,
503 .prio = 0,
504 .force = IPIC_SIFCR_L,
505 .bit = 30,
506 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700507};
508
509static inline u32 ipic_read(volatile u32 __iomem *base, unsigned int reg)
510{
511 return in_be32(base + (reg >> 2));
512}
513
514static inline void ipic_write(volatile u32 __iomem *base, unsigned int reg, u32 value)
515{
516 out_be32(base + (reg >> 2), value);
517}
518
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500519static inline struct ipic * ipic_from_irq(unsigned int virq)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700520{
521 return primary_ipic;
522}
523
Lennert Buytenhek687228a2011-03-07 13:59:58 +0000524static void ipic_unmask_irq(struct irq_data *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700525{
Lennert Buytenhek687228a2011-03-07 13:59:58 +0000526 struct ipic *ipic = ipic_from_irq(d->irq);
Grant Likely476eb492011-05-04 15:02:15 +1000527 unsigned int src = irqd_to_hwirq(d);
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500528 unsigned long flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700529 u32 temp;
530
Thomas Gleixnera9e8bf22010-02-18 02:23:14 +0000531 raw_spin_lock_irqsave(&ipic_lock, flags);
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500532
Linus Torvalds1da177e2005-04-16 15:20:36 -0700533 temp = ipic_read(ipic->regs, ipic_info[src].mask);
534 temp |= (1 << (31 - ipic_info[src].bit));
535 ipic_write(ipic->regs, ipic_info[src].mask, temp);
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500536
Thomas Gleixnera9e8bf22010-02-18 02:23:14 +0000537 raw_spin_unlock_irqrestore(&ipic_lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700538}
539
Lennert Buytenhek687228a2011-03-07 13:59:58 +0000540static void ipic_mask_irq(struct irq_data *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700541{
Lennert Buytenhek687228a2011-03-07 13:59:58 +0000542 struct ipic *ipic = ipic_from_irq(d->irq);
Grant Likely476eb492011-05-04 15:02:15 +1000543 unsigned int src = irqd_to_hwirq(d);
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500544 unsigned long flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700545 u32 temp;
546
Thomas Gleixnera9e8bf22010-02-18 02:23:14 +0000547 raw_spin_lock_irqsave(&ipic_lock, flags);
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500548
Linus Torvalds1da177e2005-04-16 15:20:36 -0700549 temp = ipic_read(ipic->regs, ipic_info[src].mask);
550 temp &= ~(1 << (31 - ipic_info[src].bit));
551 ipic_write(ipic->regs, ipic_info[src].mask, temp);
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500552
Li Yang77d43092007-12-04 19:01:40 +0800553 /* mb() can't guarantee that masking is finished. But it does finish
554 * for nearly all cases. */
555 mb();
556
Thomas Gleixnera9e8bf22010-02-18 02:23:14 +0000557 raw_spin_unlock_irqrestore(&ipic_lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700558}
559
Lennert Buytenhek687228a2011-03-07 13:59:58 +0000560static void ipic_ack_irq(struct irq_data *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700561{
Lennert Buytenhek687228a2011-03-07 13:59:58 +0000562 struct ipic *ipic = ipic_from_irq(d->irq);
Grant Likely476eb492011-05-04 15:02:15 +1000563 unsigned int src = irqd_to_hwirq(d);
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500564 unsigned long flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700565 u32 temp;
566
Thomas Gleixnera9e8bf22010-02-18 02:23:14 +0000567 raw_spin_lock_irqsave(&ipic_lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700568
dayu@datangmobile.cn30c40462009-02-18 13:47:42 +0800569 temp = 1 << (31 - ipic_info[src].bit);
Li Yang77d43092007-12-04 19:01:40 +0800570 ipic_write(ipic->regs, ipic_info[src].ack, temp);
571
572 /* mb() can't guarantee that ack is finished. But it does finish
573 * for nearly all cases. */
574 mb();
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500575
Thomas Gleixnera9e8bf22010-02-18 02:23:14 +0000576 raw_spin_unlock_irqrestore(&ipic_lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700577}
578
Lennert Buytenhek687228a2011-03-07 13:59:58 +0000579static void ipic_mask_irq_and_ack(struct irq_data *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700580{
Lennert Buytenhek687228a2011-03-07 13:59:58 +0000581 struct ipic *ipic = ipic_from_irq(d->irq);
Grant Likely476eb492011-05-04 15:02:15 +1000582 unsigned int src = irqd_to_hwirq(d);
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500583 unsigned long flags;
584 u32 temp;
585
Thomas Gleixnera9e8bf22010-02-18 02:23:14 +0000586 raw_spin_lock_irqsave(&ipic_lock, flags);
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500587
588 temp = ipic_read(ipic->regs, ipic_info[src].mask);
589 temp &= ~(1 << (31 - ipic_info[src].bit));
590 ipic_write(ipic->regs, ipic_info[src].mask, temp);
591
dayu@datangmobile.cn30c40462009-02-18 13:47:42 +0800592 temp = 1 << (31 - ipic_info[src].bit);
Li Yang77d43092007-12-04 19:01:40 +0800593 ipic_write(ipic->regs, ipic_info[src].ack, temp);
594
595 /* mb() can't guarantee that ack is finished. But it does finish
596 * for nearly all cases. */
597 mb();
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500598
Thomas Gleixnera9e8bf22010-02-18 02:23:14 +0000599 raw_spin_unlock_irqrestore(&ipic_lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700600}
601
Lennert Buytenhek687228a2011-03-07 13:59:58 +0000602static int ipic_set_irq_type(struct irq_data *d, unsigned int flow_type)
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500603{
Lennert Buytenhek687228a2011-03-07 13:59:58 +0000604 struct ipic *ipic = ipic_from_irq(d->irq);
Grant Likely476eb492011-05-04 15:02:15 +1000605 unsigned int src = irqd_to_hwirq(d);
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500606 unsigned int vold, vnew, edibit;
607
608 if (flow_type == IRQ_TYPE_NONE)
609 flow_type = IRQ_TYPE_LEVEL_LOW;
610
611 /* ipic supports only low assertion and high-to-low change senses
612 */
613 if (!(flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))) {
614 printk(KERN_ERR "ipic: sense type 0x%x not supported\n",
615 flow_type);
616 return -EINVAL;
617 }
Li Yang77d43092007-12-04 19:01:40 +0800618 /* ipic supports only edge mode on external interrupts */
619 if ((flow_type & IRQ_TYPE_EDGE_FALLING) && !ipic_info[src].ack) {
620 printk(KERN_ERR "ipic: edge sense not supported on internal "
621 "interrupts\n");
622 return -EINVAL;
Thomas Gleixnerecf4b192011-03-25 16:16:30 +0100623
Li Yang77d43092007-12-04 19:01:40 +0800624 }
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500625
Thomas Gleixnerecf4b192011-03-25 16:16:30 +0100626 irqd_set_trigger_type(d, flow_type);
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500627 if (flow_type & IRQ_TYPE_LEVEL_LOW) {
Thomas Gleixnerecf4b192011-03-25 16:16:30 +0100628 __irq_set_handler_locked(d->irq, handle_level_irq);
629 d->chip = &ipic_level_irq_chip;
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500630 } else {
Thomas Gleixnerecf4b192011-03-25 16:16:30 +0100631 __irq_set_handler_locked(d->irq, handle_edge_irq);
632 d->chip = &ipic_edge_irq_chip;
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500633 }
634
635 /* only EXT IRQ senses are programmable on ipic
636 * internal IRQ senses are LEVEL_LOW
637 */
638 if (src == IPIC_IRQ_EXT0)
639 edibit = 15;
640 else
641 if (src >= IPIC_IRQ_EXT1 && src <= IPIC_IRQ_EXT7)
642 edibit = (14 - (src - IPIC_IRQ_EXT1));
643 else
644 return (flow_type & IRQ_TYPE_LEVEL_LOW) ? 0 : -EINVAL;
645
646 vold = ipic_read(ipic->regs, IPIC_SECNR);
647 if ((flow_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_FALLING) {
648 vnew = vold | (1 << edibit);
649 } else {
650 vnew = vold & ~(1 << edibit);
651 }
652 if (vold != vnew)
653 ipic_write(ipic->regs, IPIC_SECNR, vnew);
Thomas Gleixnerecf4b192011-03-25 16:16:30 +0100654 return IRQ_SET_MASK_OK_NOCOPY;
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500655}
656
Li Yang77d43092007-12-04 19:01:40 +0800657/* level interrupts and edge interrupts have different ack operations */
658static struct irq_chip ipic_level_irq_chip = {
Anton Blanchardfc380c02010-01-31 20:33:41 +0000659 .name = "IPIC",
Lennert Buytenhek687228a2011-03-07 13:59:58 +0000660 .irq_unmask = ipic_unmask_irq,
661 .irq_mask = ipic_mask_irq,
662 .irq_mask_ack = ipic_mask_irq,
663 .irq_set_type = ipic_set_irq_type,
Li Yang77d43092007-12-04 19:01:40 +0800664};
665
666static struct irq_chip ipic_edge_irq_chip = {
Anton Blanchardfc380c02010-01-31 20:33:41 +0000667 .name = "IPIC",
Lennert Buytenhek687228a2011-03-07 13:59:58 +0000668 .irq_unmask = ipic_unmask_irq,
669 .irq_mask = ipic_mask_irq,
670 .irq_mask_ack = ipic_mask_irq_and_ack,
671 .irq_ack = ipic_ack_irq,
672 .irq_set_type = ipic_set_irq_type,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700673};
674
Grant Likelybae1d8f2012-02-14 14:06:50 -0700675static int ipic_host_match(struct irq_domain *h, struct device_node *node)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700676{
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500677 /* Exact match, unless ipic node is NULL */
Michael Ellerman52964f82007-08-28 18:47:54 +1000678 return h->of_node == NULL || h->of_node == node;
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500679}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700680
Grant Likelybae1d8f2012-02-14 14:06:50 -0700681static int ipic_host_map(struct irq_domain *h, unsigned int virq,
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500682 irq_hw_number_t hw)
683{
684 struct ipic *ipic = h->host_data;
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500685
Thomas Gleixnerec775d02011-03-25 16:45:20 +0100686 irq_set_chip_data(virq, ipic);
687 irq_set_chip_and_handler(virq, &ipic_level_irq_chip, handle_level_irq);
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500688
689 /* Set default irq type */
Thomas Gleixnerec775d02011-03-25 16:45:20 +0100690 irq_set_irq_type(virq, IRQ_TYPE_NONE);
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500691
692 return 0;
693}
694
Grant Likelybae1d8f2012-02-14 14:06:50 -0700695static struct irq_domain_ops ipic_host_ops = {
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500696 .match = ipic_host_match,
697 .map = ipic_host_map,
Grant Likelyff8c3ab2012-01-24 17:09:13 -0700698 .xlate = irq_domain_xlate_onetwocell,
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500699};
700
Kumar Gala126186a2007-01-26 01:45:32 -0600701struct ipic * __init ipic_init(struct device_node *node, unsigned int flags)
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500702{
703 struct ipic *ipic;
704 struct resource res;
705 u32 temp = 0, ret;
706
Michael Ellerman84f1c1e2008-05-26 12:12:30 +1000707 ret = of_address_to_resource(node, 0, &res);
708 if (ret)
709 return NULL;
710
Anton Vorontsovea960252009-07-01 10:59:57 +0000711 ipic = kzalloc(sizeof(*ipic), GFP_KERNEL);
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500712 if (ipic == NULL)
Kumar Gala126186a2007-01-26 01:45:32 -0600713 return NULL;
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500714
Grant Likelya8db8cf2012-02-14 14:06:54 -0700715 ipic->irqhost = irq_domain_add_linear(node, NR_IPIC_INTS,
716 &ipic_host_ops, ipic);
Julia Lawall7a626b62009-08-02 10:44:53 +0200717 if (ipic->irqhost == NULL) {
718 kfree(ipic);
Kumar Gala126186a2007-01-26 01:45:32 -0600719 return NULL;
Julia Lawall7a626b62009-08-02 10:44:53 +0200720 }
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500721
Joe Perches28f65c112011-06-09 09:13:32 -0700722 ipic->regs = ioremap(res.start, resource_size(&res));
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500723
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500724 /* init hw */
725 ipic_write(ipic->regs, IPIC_SICNR, 0x0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700726
727 /* default priority scheme is grouped. If spread mode is required
728 * configure SICFR accordingly */
729 if (flags & IPIC_SPREADMODE_GRP_A)
730 temp |= SICFR_IPSA;
Li Yangf03ca952007-10-19 19:38:43 +0800731 if (flags & IPIC_SPREADMODE_GRP_B)
732 temp |= SICFR_IPSB;
733 if (flags & IPIC_SPREADMODE_GRP_C)
734 temp |= SICFR_IPSC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700735 if (flags & IPIC_SPREADMODE_GRP_D)
736 temp |= SICFR_IPSD;
737 if (flags & IPIC_SPREADMODE_MIX_A)
738 temp |= SICFR_MPSA;
739 if (flags & IPIC_SPREADMODE_MIX_B)
740 temp |= SICFR_MPSB;
741
Li Yangf03ca952007-10-19 19:38:43 +0800742 ipic_write(ipic->regs, IPIC_SICFR, temp);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700743
744 /* handle MCP route */
745 temp = 0;
746 if (flags & IPIC_DISABLE_MCP_OUT)
747 temp = SERCR_MCPR;
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500748 ipic_write(ipic->regs, IPIC_SERCR, temp);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700749
750 /* handle routing of IRQ0 to MCP */
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500751 temp = ipic_read(ipic->regs, IPIC_SEMSR);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700752
753 if (flags & IPIC_IRQ0_MCP)
754 temp |= SEMSR_SIRQ0;
755 else
756 temp &= ~SEMSR_SIRQ0;
757
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500758 ipic_write(ipic->regs, IPIC_SEMSR, temp);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700759
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500760 primary_ipic = ipic;
761 irq_set_default_host(primary_ipic->irqhost);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700762
Sebastian Andrzej Siewior8640d3b2009-08-05 21:41:12 +0200763 ipic_write(ipic->regs, IPIC_SIMSR_H, 0);
764 ipic_write(ipic->regs, IPIC_SIMSR_L, 0);
765
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500766 printk ("IPIC (%d IRQ sources) at %p\n", NR_IPIC_INTS,
767 primary_ipic->regs);
Kumar Gala126186a2007-01-26 01:45:32 -0600768
769 return ipic;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700770}
771
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500772int ipic_set_priority(unsigned int virq, unsigned int priority)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700773{
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500774 struct ipic *ipic = ipic_from_irq(virq);
Grant Likely476eb492011-05-04 15:02:15 +1000775 unsigned int src = virq_to_hw(virq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700776 u32 temp;
777
778 if (priority > 7)
779 return -EINVAL;
780 if (src > 127)
781 return -EINVAL;
782 if (ipic_info[src].prio == 0)
783 return -EINVAL;
784
785 temp = ipic_read(ipic->regs, ipic_info[src].prio);
786
787 if (priority < 4) {
788 temp &= ~(0x7 << (20 + (3 - priority) * 3));
789 temp |= ipic_info[src].prio_mask << (20 + (3 - priority) * 3);
790 } else {
791 temp &= ~(0x7 << (4 + (7 - priority) * 3));
792 temp |= ipic_info[src].prio_mask << (4 + (7 - priority) * 3);
793 }
794
795 ipic_write(ipic->regs, ipic_info[src].prio, temp);
796
797 return 0;
798}
799
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500800void ipic_set_highest_priority(unsigned int virq)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700801{
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500802 struct ipic *ipic = ipic_from_irq(virq);
Grant Likely476eb492011-05-04 15:02:15 +1000803 unsigned int src = virq_to_hw(virq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700804 u32 temp;
805
806 temp = ipic_read(ipic->regs, IPIC_SICFR);
807
808 /* clear and set HPI */
809 temp &= 0x7f000000;
810 temp |= (src & 0x7f) << 24;
811
812 ipic_write(ipic->regs, IPIC_SICFR, temp);
813}
814
815void ipic_set_default_priority(void)
816{
Li Yangf03ca952007-10-19 19:38:43 +0800817 ipic_write(primary_ipic->regs, IPIC_SIPRR_A, IPIC_PRIORITY_DEFAULT);
818 ipic_write(primary_ipic->regs, IPIC_SIPRR_B, IPIC_PRIORITY_DEFAULT);
819 ipic_write(primary_ipic->regs, IPIC_SIPRR_C, IPIC_PRIORITY_DEFAULT);
820 ipic_write(primary_ipic->regs, IPIC_SIPRR_D, IPIC_PRIORITY_DEFAULT);
821 ipic_write(primary_ipic->regs, IPIC_SMPRR_A, IPIC_PRIORITY_DEFAULT);
822 ipic_write(primary_ipic->regs, IPIC_SMPRR_B, IPIC_PRIORITY_DEFAULT);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700823}
824
825void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq)
826{
827 struct ipic *ipic = primary_ipic;
828 u32 temp;
829
830 temp = ipic_read(ipic->regs, IPIC_SERMR);
831 temp |= (1 << (31 - mcp_irq));
832 ipic_write(ipic->regs, IPIC_SERMR, temp);
833}
834
835void ipic_disable_mcp(enum ipic_mcp_irq mcp_irq)
836{
837 struct ipic *ipic = primary_ipic;
838 u32 temp;
839
840 temp = ipic_read(ipic->regs, IPIC_SERMR);
841 temp &= (1 << (31 - mcp_irq));
842 ipic_write(ipic->regs, IPIC_SERMR, temp);
843}
844
845u32 ipic_get_mcp_status(void)
846{
847 return ipic_read(primary_ipic->regs, IPIC_SERMR);
848}
849
850void ipic_clear_mcp_status(u32 mask)
851{
852 ipic_write(primary_ipic->regs, IPIC_SERMR, mask);
853}
854
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500855/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
Olaf Hering35a84c22006-10-07 22:08:26 +1000856unsigned int ipic_get_irq(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700857{
858 int irq;
859
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500860 BUG_ON(primary_ipic == NULL);
861
862#define IPIC_SIVCR_VECTOR_MASK 0x7f
863 irq = ipic_read(primary_ipic->regs, IPIC_SIVCR) & IPIC_SIVCR_VECTOR_MASK;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700864
865 if (irq == 0) /* 0 --> no irq is pending */
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500866 return NO_IRQ;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700867
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -0500868 return irq_linear_revmap(primary_ipic->irqhost, irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700869}
870
Michael Neulinge2a02ba2009-02-06 11:10:27 +1100871#ifdef CONFIG_SUSPEND
Scott Woodd49747b2007-10-09 12:37:13 -0500872static struct {
873 u32 sicfr;
874 u32 siprr[2];
875 u32 simsr[2];
876 u32 sicnr;
877 u32 smprr[2];
878 u32 semsr;
879 u32 secnr;
880 u32 sermr;
881 u32 sercr;
882} ipic_saved_state;
883
Rafael J. Wysockif5a592f2011-04-26 19:14:57 +0200884static int ipic_suspend(void)
Scott Woodd49747b2007-10-09 12:37:13 -0500885{
886 struct ipic *ipic = primary_ipic;
887
888 ipic_saved_state.sicfr = ipic_read(ipic->regs, IPIC_SICFR);
889 ipic_saved_state.siprr[0] = ipic_read(ipic->regs, IPIC_SIPRR_A);
890 ipic_saved_state.siprr[1] = ipic_read(ipic->regs, IPIC_SIPRR_D);
891 ipic_saved_state.simsr[0] = ipic_read(ipic->regs, IPIC_SIMSR_H);
892 ipic_saved_state.simsr[1] = ipic_read(ipic->regs, IPIC_SIMSR_L);
893 ipic_saved_state.sicnr = ipic_read(ipic->regs, IPIC_SICNR);
894 ipic_saved_state.smprr[0] = ipic_read(ipic->regs, IPIC_SMPRR_A);
895 ipic_saved_state.smprr[1] = ipic_read(ipic->regs, IPIC_SMPRR_B);
896 ipic_saved_state.semsr = ipic_read(ipic->regs, IPIC_SEMSR);
897 ipic_saved_state.secnr = ipic_read(ipic->regs, IPIC_SECNR);
898 ipic_saved_state.sermr = ipic_read(ipic->regs, IPIC_SERMR);
899 ipic_saved_state.sercr = ipic_read(ipic->regs, IPIC_SERCR);
900
901 if (fsl_deep_sleep()) {
902 /* In deep sleep, make sure there can be no
903 * pending interrupts, as this can cause
904 * problems on 831x.
905 */
906 ipic_write(ipic->regs, IPIC_SIMSR_H, 0);
907 ipic_write(ipic->regs, IPIC_SIMSR_L, 0);
908 ipic_write(ipic->regs, IPIC_SEMSR, 0);
909 ipic_write(ipic->regs, IPIC_SERMR, 0);
910 }
911
912 return 0;
913}
914
Rafael J. Wysockif5a592f2011-04-26 19:14:57 +0200915static void ipic_resume(void)
Scott Woodd49747b2007-10-09 12:37:13 -0500916{
917 struct ipic *ipic = primary_ipic;
918
919 ipic_write(ipic->regs, IPIC_SICFR, ipic_saved_state.sicfr);
920 ipic_write(ipic->regs, IPIC_SIPRR_A, ipic_saved_state.siprr[0]);
921 ipic_write(ipic->regs, IPIC_SIPRR_D, ipic_saved_state.siprr[1]);
922 ipic_write(ipic->regs, IPIC_SIMSR_H, ipic_saved_state.simsr[0]);
923 ipic_write(ipic->regs, IPIC_SIMSR_L, ipic_saved_state.simsr[1]);
924 ipic_write(ipic->regs, IPIC_SICNR, ipic_saved_state.sicnr);
925 ipic_write(ipic->regs, IPIC_SMPRR_A, ipic_saved_state.smprr[0]);
926 ipic_write(ipic->regs, IPIC_SMPRR_B, ipic_saved_state.smprr[1]);
927 ipic_write(ipic->regs, IPIC_SEMSR, ipic_saved_state.semsr);
928 ipic_write(ipic->regs, IPIC_SECNR, ipic_saved_state.secnr);
929 ipic_write(ipic->regs, IPIC_SERMR, ipic_saved_state.sermr);
930 ipic_write(ipic->regs, IPIC_SERCR, ipic_saved_state.sercr);
Scott Woodd49747b2007-10-09 12:37:13 -0500931}
932#else
933#define ipic_suspend NULL
934#define ipic_resume NULL
935#endif
936
Rafael J. Wysockif5a592f2011-04-26 19:14:57 +0200937static struct syscore_ops ipic_syscore_ops = {
Scott Woodd49747b2007-10-09 12:37:13 -0500938 .suspend = ipic_suspend,
939 .resume = ipic_resume,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700940};
941
Rafael J. Wysockif5a592f2011-04-26 19:14:57 +0200942static int __init init_ipic_syscore(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700943{
Olaf Hering1428a9f2008-03-18 06:53:05 +1100944 if (!primary_ipic || !primary_ipic->regs)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700945 return -ENODEV;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700946
Rafael J. Wysockif5a592f2011-04-26 19:14:57 +0200947 printk(KERN_DEBUG "Registering ipic system core operations\n");
948 register_syscore_ops(&ipic_syscore_ops);
949
Linus Torvalds1da177e2005-04-16 15:20:36 -0700950 return 0;
951}
952
Rafael J. Wysockif5a592f2011-04-26 19:14:57 +0200953subsys_initcall(init_ipic_syscore);