blob: c3e37e46a18ad9881c98950c2eb8bb73c53ea210 [file] [log] [blame]
Olof Johanssonf5cd7872007-01-31 21:43:54 -06001/*
2 * Copyright (C) 2006 PA Semi, Inc
3 *
4 * Driver for the PA6T-1682M onchip 1G/10G Ethernet MACs, soft state and
5 * hardware register layouts.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef PASEMI_MAC_H
22#define PASEMI_MAC_H
23
24#include <linux/ethtool.h>
25#include <linux/netdevice.h>
26#include <linux/spinlock.h>
27
28struct pasemi_mac_txring {
29 spinlock_t lock;
30 struct pas_dma_xct_descr *desc;
31 dma_addr_t dma;
32 unsigned int size;
33 unsigned int next_to_use;
34 unsigned int next_to_clean;
35 struct pasemi_mac_buffer *desc_info;
36 char irq_name[10]; /* "eth%d tx" */
37};
38
39struct pasemi_mac_rxring {
40 spinlock_t lock;
41 struct pas_dma_xct_descr *desc; /* RX channel descriptor ring */
42 dma_addr_t dma;
43 u64 *buffers; /* RX interface buffer ring */
44 dma_addr_t buf_dma;
45 unsigned int size;
46 unsigned int next_to_fill;
47 unsigned int next_to_clean;
48 struct pasemi_mac_buffer *desc_info;
49 char irq_name[10]; /* "eth%d rx" */
50};
51
52struct pasemi_mac {
53 struct net_device *netdev;
54 struct pci_dev *pdev;
55 struct pci_dev *dma_pdev;
56 struct pci_dev *iob_pdev;
57 struct net_device_stats stats;
58
59 /* Pointer to the cacheable per-channel status registers */
60 u64 *rx_status;
61 u64 *tx_status;
62
63 u8 type;
64#define MAC_TYPE_GMAC 1
65#define MAC_TYPE_XAUI 2
66 u32 dma_txch;
67 u32 dma_if;
68 u32 dma_rxch;
69
70 u8 mac_addr[6];
71
72 struct timer_list rxtimer;
73
74 struct pasemi_mac_txring *tx;
75 struct pasemi_mac_rxring *rx;
76};
77
78/* Software status descriptor (desc_info) */
79struct pasemi_mac_buffer {
80 struct sk_buff *skb;
81 dma_addr_t dma;
82};
83
84
85/* status register layout in IOB region, at 0xfb800000 */
86struct pasdma_status {
87 u64 rx_sta[64];
88 u64 tx_sta[20];
89};
90
91/* descriptor structure */
92struct pas_dma_xct_descr {
93 union {
94 u64 mactx;
95 u64 macrx;
96 };
97 union {
98 u64 ptr;
99 u64 rxb;
100 };
101};
102
103/* MAC CFG register offsets */
104
105enum {
106 PAS_MAC_CFG_PCFG = 0x80,
107 PAS_MAC_CFG_TXP = 0x98,
108 PAS_MAC_IPC_CHNL = 0x208,
109};
110
111/* MAC CFG register fields */
112#define PAS_MAC_CFG_PCFG_PE 0x80000000
113#define PAS_MAC_CFG_PCFG_CE 0x40000000
114#define PAS_MAC_CFG_PCFG_BU 0x20000000
115#define PAS_MAC_CFG_PCFG_TT 0x10000000
116#define PAS_MAC_CFG_PCFG_TSR_M 0x0c000000
117#define PAS_MAC_CFG_PCFG_TSR_10M 0x00000000
118#define PAS_MAC_CFG_PCFG_TSR_100M 0x04000000
119#define PAS_MAC_CFG_PCFG_TSR_1G 0x08000000
120#define PAS_MAC_CFG_PCFG_TSR_10G 0x0c000000
121#define PAS_MAC_CFG_PCFG_T24 0x02000000
122#define PAS_MAC_CFG_PCFG_PR 0x01000000
123#define PAS_MAC_CFG_PCFG_CRO_M 0x00ff0000
124#define PAS_MAC_CFG_PCFG_CRO_S 16
125#define PAS_MAC_CFG_PCFG_IPO_M 0x0000ff00
126#define PAS_MAC_CFG_PCFG_IPO_S 8
127#define PAS_MAC_CFG_PCFG_S1 0x00000080
128#define PAS_MAC_CFG_PCFG_IO_M 0x00000060
129#define PAS_MAC_CFG_PCFG_IO_MAC 0x00000000
130#define PAS_MAC_CFG_PCFG_IO_OFF 0x00000020
131#define PAS_MAC_CFG_PCFG_IO_IND_ETH 0x00000040
132#define PAS_MAC_CFG_PCFG_IO_IND_IP 0x00000060
133#define PAS_MAC_CFG_PCFG_LP 0x00000010
134#define PAS_MAC_CFG_PCFG_TS 0x00000008
135#define PAS_MAC_CFG_PCFG_HD 0x00000004
136#define PAS_MAC_CFG_PCFG_SPD_M 0x00000003
137#define PAS_MAC_CFG_PCFG_SPD_10M 0x00000000
138#define PAS_MAC_CFG_PCFG_SPD_100M 0x00000001
139#define PAS_MAC_CFG_PCFG_SPD_1G 0x00000002
140#define PAS_MAC_CFG_PCFG_SPD_10G 0x00000003
141#define PAS_MAC_CFG_TXP_FCF 0x01000000
142#define PAS_MAC_CFG_TXP_FCE 0x00800000
143#define PAS_MAC_CFG_TXP_FC 0x00400000
144#define PAS_MAC_CFG_TXP_FPC_M 0x00300000
145#define PAS_MAC_CFG_TXP_FPC_S 20
146#define PAS_MAC_CFG_TXP_FPC(x) (((x) << PAS_MAC_CFG_TXP_FPC_S) & \
147 PAS_MAC_CFG_TXP_FPC_M)
148#define PAS_MAC_CFG_TXP_RT 0x00080000
149#define PAS_MAC_CFG_TXP_BL 0x00040000
150#define PAS_MAC_CFG_TXP_SL_M 0x00030000
151#define PAS_MAC_CFG_TXP_SL_S 16
152#define PAS_MAC_CFG_TXP_SL(x) (((x) << PAS_MAC_CFG_TXP_SL_S) & \
153 PAS_MAC_CFG_TXP_SL_M)
154#define PAS_MAC_CFG_TXP_COB_M 0x0000f000
155#define PAS_MAC_CFG_TXP_COB_S 12
156#define PAS_MAC_CFG_TXP_COB(x) (((x) << PAS_MAC_CFG_TXP_COB_S) & \
157 PAS_MAC_CFG_TXP_COB_M)
158#define PAS_MAC_CFG_TXP_TIFT_M 0x00000f00
159#define PAS_MAC_CFG_TXP_TIFT_S 8
160#define PAS_MAC_CFG_TXP_TIFT(x) (((x) << PAS_MAC_CFG_TXP_TIFT_S) & \
161 PAS_MAC_CFG_TXP_TIFT_M)
162#define PAS_MAC_CFG_TXP_TIFG_M 0x000000ff
163#define PAS_MAC_CFG_TXP_TIFG_S 0
164#define PAS_MAC_CFG_TXP_TIFG(x) (((x) << PAS_MAC_CFG_TXP_TIFG_S) & \
165 PAS_MAC_CFG_TXP_TIFG_M)
166
167#define PAS_MAC_IPC_CHNL_DCHNO_M 0x003f0000
168#define PAS_MAC_IPC_CHNL_DCHNO_S 16
169#define PAS_MAC_IPC_CHNL_DCHNO(x) (((x) << PAS_MAC_IPC_CHNL_DCHNO_S) & \
170 PAS_MAC_IPC_CHNL_DCHNO_M)
171#define PAS_MAC_IPC_CHNL_BCH_M 0x0000003f
172#define PAS_MAC_IPC_CHNL_BCH_S 0
173#define PAS_MAC_IPC_CHNL_BCH(x) (((x) << PAS_MAC_IPC_CHNL_BCH_S) & \
174 PAS_MAC_IPC_CHNL_BCH_M)
175
176/* All these registers live in the PCI configuration space for the DMA PCI
177 * device. Use the normal PCI config access functions for them.
178 */
179enum {
180 PAS_DMA_COM_TXCMD = 0x100, /* Transmit Command Register */
181 PAS_DMA_COM_TXSTA = 0x104, /* Transmit Status Register */
182 PAS_DMA_COM_RXCMD = 0x108, /* Receive Command Register */
183 PAS_DMA_COM_RXSTA = 0x10c, /* Receive Status Register */
184};
185#define PAS_DMA_COM_TXCMD_EN 0x00000001 /* enable */
186#define PAS_DMA_COM_TXSTA_ACT 0x00000001 /* active */
187#define PAS_DMA_COM_RXCMD_EN 0x00000001 /* enable */
188#define PAS_DMA_COM_RXSTA_ACT 0x00000001 /* active */
189
190
191/* Per-interface and per-channel registers */
192#define _PAS_DMA_RXINT_STRIDE 0x20
193#define PAS_DMA_RXINT_RCMDSTA(i) (0x200+(i)*_PAS_DMA_RXINT_STRIDE)
194#define PAS_DMA_RXINT_RCMDSTA_EN 0x00000001
195#define PAS_DMA_RXINT_RCMDSTA_ST 0x00000002
196#define PAS_DMA_RXINT_RCMDSTA_OO 0x00000100
197#define PAS_DMA_RXINT_RCMDSTA_BP 0x00000200
198#define PAS_DMA_RXINT_RCMDSTA_DR 0x00000400
199#define PAS_DMA_RXINT_RCMDSTA_BT 0x00000800
200#define PAS_DMA_RXINT_RCMDSTA_TB 0x00001000
201#define PAS_DMA_RXINT_RCMDSTA_ACT 0x00010000
202#define PAS_DMA_RXINT_RCMDSTA_DROPS_M 0xfffe0000
203#define PAS_DMA_RXINT_RCMDSTA_DROPS_S 17
204#define PAS_DMA_RXINT_INCR(i) (0x210+(i)*_PAS_DMA_RXINT_STRIDE)
205#define PAS_DMA_RXINT_INCR_INCR_M 0x0000ffff
206#define PAS_DMA_RXINT_INCR_INCR_S 0
207#define PAS_DMA_RXINT_INCR_INCR(x) ((x) & 0x0000ffff)
208#define PAS_DMA_RXINT_BASEL(i) (0x218+(i)*_PAS_DMA_RXINT_STRIDE)
209#define PAS_DMA_RXINT_BASEL_BRBL(x) ((x) & ~0x3f)
210#define PAS_DMA_RXINT_BASEU(i) (0x21c+(i)*_PAS_DMA_RXINT_STRIDE)
211#define PAS_DMA_RXINT_BASEU_BRBH(x) ((x) & 0xfff)
212#define PAS_DMA_RXINT_BASEU_SIZ_M 0x3fff0000 /* # of cache lines worth of buffer ring */
213#define PAS_DMA_RXINT_BASEU_SIZ_S 16 /* 0 = 16K */
214#define PAS_DMA_RXINT_BASEU_SIZ(x) (((x) << PAS_DMA_RXINT_BASEU_SIZ_S) & \
215 PAS_DMA_RXINT_BASEU_SIZ_M)
216
217
218#define _PAS_DMA_TXCHAN_STRIDE 0x20 /* Size per channel */
219#define _PAS_DMA_TXCHAN_TCMDSTA 0x300 /* Command / Status */
220#define _PAS_DMA_TXCHAN_CFG 0x304 /* Configuration */
221#define _PAS_DMA_TXCHAN_DSCRBU 0x308 /* Descriptor BU Allocation */
222#define _PAS_DMA_TXCHAN_INCR 0x310 /* Descriptor increment */
223#define _PAS_DMA_TXCHAN_CNT 0x314 /* Descriptor count/offset */
224#define _PAS_DMA_TXCHAN_BASEL 0x318 /* Descriptor ring base (low) */
225#define _PAS_DMA_TXCHAN_BASEU 0x31c /* (high) */
226#define PAS_DMA_TXCHAN_TCMDSTA(c) (0x300+(c)*_PAS_DMA_TXCHAN_STRIDE)
227#define PAS_DMA_TXCHAN_TCMDSTA_EN 0x00000001 /* Enabled */
228#define PAS_DMA_TXCHAN_TCMDSTA_ST 0x00000002 /* Stop interface */
229#define PAS_DMA_TXCHAN_TCMDSTA_ACT 0x00010000 /* Active */
230#define PAS_DMA_TXCHAN_CFG(c) (0x304+(c)*_PAS_DMA_TXCHAN_STRIDE)
231#define PAS_DMA_TXCHAN_CFG_TY_IFACE 0x00000000 /* Type = interface */
232#define PAS_DMA_TXCHAN_CFG_TATTR_M 0x0000003c
233#define PAS_DMA_TXCHAN_CFG_TATTR_S 2
234#define PAS_DMA_TXCHAN_CFG_TATTR(x) (((x) << PAS_DMA_TXCHAN_CFG_TATTR_S) & \
235 PAS_DMA_TXCHAN_CFG_TATTR_M)
236#define PAS_DMA_TXCHAN_CFG_WT_M 0x000001c0
237#define PAS_DMA_TXCHAN_CFG_WT_S 6
238#define PAS_DMA_TXCHAN_CFG_WT(x) (((x) << PAS_DMA_TXCHAN_CFG_WT_S) & \
239 PAS_DMA_TXCHAN_CFG_WT_M)
240#define PAS_DMA_TXCHAN_CFG_CF 0x00001000 /* Clean first line */
241#define PAS_DMA_TXCHAN_CFG_CL 0x00002000 /* Clean last line */
242#define PAS_DMA_TXCHAN_CFG_UP 0x00004000 /* update tx descr when sent */
243#define PAS_DMA_TXCHAN_INCR(c) (0x310+(c)*_PAS_DMA_TXCHAN_STRIDE)
244#define PAS_DMA_TXCHAN_BASEL(c) (0x318+(c)*_PAS_DMA_TXCHAN_STRIDE)
245#define PAS_DMA_TXCHAN_BASEL_BRBL_M 0xffffffc0
246#define PAS_DMA_TXCHAN_BASEL_BRBL_S 0
247#define PAS_DMA_TXCHAN_BASEL_BRBL(x) (((x) << PAS_DMA_TXCHAN_BASEL_BRBL_S) & \
248 PAS_DMA_TXCHAN_BASEL_BRBL_M)
249#define PAS_DMA_TXCHAN_BASEU(c) (0x31c+(c)*_PAS_DMA_TXCHAN_STRIDE)
250#define PAS_DMA_TXCHAN_BASEU_BRBH_M 0x00000fff
251#define PAS_DMA_TXCHAN_BASEU_BRBH_S 0
252#define PAS_DMA_TXCHAN_BASEU_BRBH(x) (((x) << PAS_DMA_TXCHAN_BASEU_BRBH_S) & \
253 PAS_DMA_TXCHAN_BASEU_BRBH_M)
254/* # of cache lines worth of buffer ring */
255#define PAS_DMA_TXCHAN_BASEU_SIZ_M 0x3fff0000
256#define PAS_DMA_TXCHAN_BASEU_SIZ_S 16 /* 0 = 16K */
257#define PAS_DMA_TXCHAN_BASEU_SIZ(x) (((x) << PAS_DMA_TXCHAN_BASEU_SIZ_S) & \
258 PAS_DMA_TXCHAN_BASEU_SIZ_M)
259
260#define _PAS_DMA_RXCHAN_STRIDE 0x20 /* Size per channel */
261#define _PAS_DMA_RXCHAN_CCMDSTA 0x800 /* Command / Status */
262#define _PAS_DMA_RXCHAN_CFG 0x804 /* Configuration */
263#define _PAS_DMA_RXCHAN_INCR 0x810 /* Descriptor increment */
264#define _PAS_DMA_RXCHAN_CNT 0x814 /* Descriptor count/offset */
265#define _PAS_DMA_RXCHAN_BASEL 0x818 /* Descriptor ring base (low) */
266#define _PAS_DMA_RXCHAN_BASEU 0x81c /* (high) */
267#define PAS_DMA_RXCHAN_CCMDSTA(c) (0x800+(c)*_PAS_DMA_RXCHAN_STRIDE)
268#define PAS_DMA_RXCHAN_CCMDSTA_EN 0x00000001 /* Enabled */
269#define PAS_DMA_RXCHAN_CCMDSTA_ST 0x00000002 /* Stop interface */
270#define PAS_DMA_RXCHAN_CCMDSTA_ACT 0x00010000 /* Active */
271#define PAS_DMA_RXCHAN_CCMDSTA_DU 0x00020000
272#define PAS_DMA_RXCHAN_CFG(c) (0x804+(c)*_PAS_DMA_RXCHAN_STRIDE)
273#define PAS_DMA_RXCHAN_CFG_HBU_M 0x00000380
274#define PAS_DMA_RXCHAN_CFG_HBU_S 7
275#define PAS_DMA_RXCHAN_CFG_HBU(x) (((x) << PAS_DMA_RXCHAN_CFG_HBU_S) & \
276 PAS_DMA_RXCHAN_CFG_HBU_M)
277#define PAS_DMA_RXCHAN_INCR(c) (0x810+(c)*_PAS_DMA_RXCHAN_STRIDE)
278#define PAS_DMA_RXCHAN_BASEL(c) (0x818+(c)*_PAS_DMA_RXCHAN_STRIDE)
279#define PAS_DMA_RXCHAN_BASEL_BRBL_M 0xffffffc0
280#define PAS_DMA_RXCHAN_BASEL_BRBL_S 0
281#define PAS_DMA_RXCHAN_BASEL_BRBL(x) (((x) << PAS_DMA_RXCHAN_BASEL_BRBL_S) & \
282 PAS_DMA_RXCHAN_BASEL_BRBL_M)
283#define PAS_DMA_RXCHAN_BASEU(c) (0x81c+(c)*_PAS_DMA_RXCHAN_STRIDE)
284#define PAS_DMA_RXCHAN_BASEU_BRBH_M 0x00000fff
285#define PAS_DMA_RXCHAN_BASEU_BRBH_S 0
286#define PAS_DMA_RXCHAN_BASEU_BRBH(x) (((x) << PAS_DMA_RXCHAN_BASEU_BRBH_S) & \
287 PAS_DMA_RXCHAN_BASEU_BRBH_M)
288/* # of cache lines worth of buffer ring */
289#define PAS_DMA_RXCHAN_BASEU_SIZ_M 0x3fff0000
290#define PAS_DMA_RXCHAN_BASEU_SIZ_S 16 /* 0 = 16K */
291#define PAS_DMA_RXCHAN_BASEU_SIZ(x) (((x) << PAS_DMA_RXCHAN_BASEU_SIZ_S) & \
292 PAS_DMA_RXCHAN_BASEU_SIZ_M)
293
294#define PAS_STATUS_PCNT_M 0x000000000000ffffull
295#define PAS_STATUS_PCNT_S 0
296#define PAS_STATUS_DCNT_M 0x00000000ffff0000ull
297#define PAS_STATUS_DCNT_S 16
298#define PAS_STATUS_BPCNT_M 0x0000ffff00000000ull
299#define PAS_STATUS_BPCNT_S 32
300#define PAS_STATUS_TIMER 0x1000000000000000ull
301#define PAS_STATUS_ERROR 0x2000000000000000ull
302#define PAS_STATUS_SOFT 0x4000000000000000ull
303#define PAS_STATUS_INT 0x8000000000000000ull
304
305#define PAS_IOB_DMA_RXCH_CFG(i) (0x1100 + (i)*4)
306#define PAS_IOB_DMA_RXCH_CFG_CNTTH_M 0x00000fff
307#define PAS_IOB_DMA_RXCH_CFG_CNTTH_S 0
308#define PAS_IOB_DMA_RXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_RXCH_CFG_CNTTH_S) & \
309 PAS_IOB_DMA_RXCH_CFG_CNTTH_M)
310#define PAS_IOB_DMA_TXCH_CFG(i) (0x1200 + (i)*4)
311#define PAS_IOB_DMA_TXCH_CFG_CNTTH_M 0x00000fff
312#define PAS_IOB_DMA_TXCH_CFG_CNTTH_S 0
313#define PAS_IOB_DMA_TXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_TXCH_CFG_CNTTH_S) & \
314 PAS_IOB_DMA_TXCH_CFG_CNTTH_M)
315#define PAS_IOB_DMA_RXCH_STAT(i) (0x1300 + (i)*4)
316#define PAS_IOB_DMA_RXCH_STAT_INTGEN 0x00001000
317#define PAS_IOB_DMA_RXCH_STAT_CNTDEL_M 0x00000fff
318#define PAS_IOB_DMA_RXCH_STAT_CNTDEL_S 0
319#define PAS_IOB_DMA_RXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_RXCH_STAT_CNTDEL_S) &\
320 PAS_IOB_DMA_RXCH_STAT_CNTDEL_M)
321#define PAS_IOB_DMA_TXCH_STAT(i) (0x1400 + (i)*4)
322#define PAS_IOB_DMA_TXCH_STAT_INTGEN 0x00001000
323#define PAS_IOB_DMA_TXCH_STAT_CNTDEL_M 0x00000fff
324#define PAS_IOB_DMA_TXCH_STAT_CNTDEL_S 0
325#define PAS_IOB_DMA_TXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_TXCH_STAT_CNTDEL_S) &\
326 PAS_IOB_DMA_TXCH_STAT_CNTDEL_M)
327#define PAS_IOB_DMA_RXCH_RESET(i) (0x1500 + (i)*4)
328#define PAS_IOB_DMA_RXCH_RESET_PCNT_M 0xffff0000
329#define PAS_IOB_DMA_RXCH_RESET_PCNT_S 0
330#define PAS_IOB_DMA_RXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_RXCH_RESET_PCNT_S) & \
331 PAS_IOB_DMA_RXCH_RESET_PCNT_M)
332#define PAS_IOB_DMA_RXCH_RESET_PCNTRST 0x00000020
333#define PAS_IOB_DMA_RXCH_RESET_DCNTRST 0x00000010
334#define PAS_IOB_DMA_RXCH_RESET_TINTC 0x00000008
335#define PAS_IOB_DMA_RXCH_RESET_DINTC 0x00000004
336#define PAS_IOB_DMA_RXCH_RESET_SINTC 0x00000002
337#define PAS_IOB_DMA_RXCH_RESET_PINTC 0x00000001
338#define PAS_IOB_DMA_TXCH_RESET(i) (0x1600 + (i)*4)
339#define PAS_IOB_DMA_TXCH_RESET_PCNT_M 0xffff0000
340#define PAS_IOB_DMA_TXCH_RESET_PCNT_S 0
341#define PAS_IOB_DMA_TXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_TXCH_RESET_PCNT_S) & \
342 PAS_IOB_DMA_TXCH_RESET_PCNT_M)
343#define PAS_IOB_DMA_TXCH_RESET_PCNTRST 0x00000020
344#define PAS_IOB_DMA_TXCH_RESET_DCNTRST 0x00000010
345#define PAS_IOB_DMA_TXCH_RESET_TINTC 0x00000008
346#define PAS_IOB_DMA_TXCH_RESET_DINTC 0x00000004
347#define PAS_IOB_DMA_TXCH_RESET_SINTC 0x00000002
348#define PAS_IOB_DMA_TXCH_RESET_PINTC 0x00000001
349
350#define PAS_IOB_DMA_COM_TIMEOUTCFG 0x1700
351#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M 0x00ffffff
352#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S 0
353#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(x) (((x) << PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S) & \
354 PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M)
355
356/* Transmit descriptor fields */
357#define XCT_MACTX_T 0x8000000000000000ull
358#define XCT_MACTX_ST 0x4000000000000000ull
359#define XCT_MACTX_NORES 0x0000000000000000ull
360#define XCT_MACTX_8BRES 0x1000000000000000ull
361#define XCT_MACTX_24BRES 0x2000000000000000ull
362#define XCT_MACTX_40BRES 0x3000000000000000ull
363#define XCT_MACTX_I 0x0800000000000000ull
364#define XCT_MACTX_O 0x0400000000000000ull
365#define XCT_MACTX_E 0x0200000000000000ull
366#define XCT_MACTX_VLAN_M 0x0180000000000000ull
367#define XCT_MACTX_VLAN_NOP 0x0000000000000000ull
368#define XCT_MACTX_VLAN_REMOVE 0x0080000000000000ull
369#define XCT_MACTX_VLAN_INSERT 0x0100000000000000ull
370#define XCT_MACTX_VLAN_REPLACE 0x0180000000000000ull
371#define XCT_MACTX_CRC_M 0x0060000000000000ull
372#define XCT_MACTX_CRC_NOP 0x0000000000000000ull
373#define XCT_MACTX_CRC_INSERT 0x0020000000000000ull
374#define XCT_MACTX_CRC_PAD 0x0040000000000000ull
375#define XCT_MACTX_CRC_REPLACE 0x0060000000000000ull
376#define XCT_MACTX_SS 0x0010000000000000ull
377#define XCT_MACTX_LLEN_M 0x00007fff00000000ull
378#define XCT_MACTX_LLEN_S 32ull
379#define XCT_MACTX_LLEN(x) ((((long)(x)) << XCT_MACTX_LLEN_S) & \
380 XCT_MACTX_LLEN_M)
381#define XCT_MACTX_IPH_M 0x00000000f8000000ull
382#define XCT_MACTX_IPH_S 27ull
383#define XCT_MACTX_IPH(x) ((((long)(x)) << XCT_MACTX_IPH_S) & \
384 XCT_MACTX_IPH_M)
385#define XCT_MACTX_IPO_M 0x0000000007c00000ull
386#define XCT_MACTX_IPO_S 22ull
387#define XCT_MACTX_IPO(x) ((((long)(x)) << XCT_MACTX_IPO_S) & \
388 XCT_MACTX_IPO_M)
389#define XCT_MACTX_CSUM_M 0x0000000000000060ull
390#define XCT_MACTX_CSUM_NOP 0x0000000000000000ull
391#define XCT_MACTX_CSUM_TCP 0x0000000000000040ull
392#define XCT_MACTX_CSUM_UDP 0x0000000000000060ull
393#define XCT_MACTX_V6 0x0000000000000010ull
394#define XCT_MACTX_C 0x0000000000000004ull
395#define XCT_MACTX_AL2 0x0000000000000002ull
396
397/* Receive descriptor fields */
398#define XCT_MACRX_T 0x8000000000000000ull
399#define XCT_MACRX_ST 0x4000000000000000ull
400#define XCT_MACRX_NORES 0x0000000000000000ull
401#define XCT_MACRX_8BRES 0x1000000000000000ull
402#define XCT_MACRX_24BRES 0x2000000000000000ull
403#define XCT_MACRX_40BRES 0x3000000000000000ull
404#define XCT_MACRX_O 0x0400000000000000ull
405#define XCT_MACRX_E 0x0200000000000000ull
406#define XCT_MACRX_FF 0x0100000000000000ull
407#define XCT_MACRX_PF 0x0080000000000000ull
408#define XCT_MACRX_OB 0x0040000000000000ull
409#define XCT_MACRX_OD 0x0020000000000000ull
410#define XCT_MACRX_FS 0x0010000000000000ull
411#define XCT_MACRX_NB_M 0x000fc00000000000ull
412#define XCT_MACRX_NB_S 46ULL
413#define XCT_MACRX_NB(x) ((((long)(x)) << XCT_MACRX_NB_S) & \
414 XCT_MACRX_NB_M)
415#define XCT_MACRX_LLEN_M 0x00003fff00000000ull
416#define XCT_MACRX_LLEN_S 32ULL
417#define XCT_MACRX_LLEN(x) ((((long)(x)) << XCT_MACRX_LLEN_S) & \
418 XCT_MACRX_LLEN_M)
419#define XCT_MACRX_CRC 0x0000000080000000ull
420#define XCT_MACRX_LEN_M 0x0000000060000000ull
421#define XCT_MACRX_LEN_TOOSHORT 0x0000000020000000ull
422#define XCT_MACRX_LEN_BELOWMIN 0x0000000040000000ull
423#define XCT_MACRX_LEN_TRUNC 0x0000000060000000ull
424#define XCT_MACRX_CAST_M 0x0000000018000000ull
425#define XCT_MACRX_CAST_UNI 0x0000000000000000ull
426#define XCT_MACRX_CAST_MULTI 0x0000000008000000ull
427#define XCT_MACRX_CAST_BROAD 0x0000000010000000ull
428#define XCT_MACRX_CAST_PAUSE 0x0000000018000000ull
429#define XCT_MACRX_VLC_M 0x0000000006000000ull
430#define XCT_MACRX_FM 0x0000000001000000ull
431#define XCT_MACRX_HTY_M 0x0000000000c00000ull
432#define XCT_MACRX_HTY_IPV4_OK 0x0000000000000000ull
433#define XCT_MACRX_HTY_IPV6 0x0000000000400000ull
434#define XCT_MACRX_HTY_IPV4_BAD 0x0000000000800000ull
435#define XCT_MACRX_HTY_NONIP 0x0000000000c00000ull
436#define XCT_MACRX_IPP_M 0x00000000003f0000ull
437#define XCT_MACRX_IPP_S 16
438#define XCT_MACRX_CSUM_M 0x000000000000ffffull
439#define XCT_MACRX_CSUM_S 0
440
441#define XCT_PTR_T 0x8000000000000000ull
442#define XCT_PTR_LEN_M 0x7ffff00000000000ull
443#define XCT_PTR_LEN_S 44
444#define XCT_PTR_LEN(x) ((((long)(x)) << XCT_PTR_LEN_S) & \
445 XCT_PTR_LEN_M)
446#define XCT_PTR_ADDR_M 0x00000fffffffffffull
447#define XCT_PTR_ADDR_S 0
448#define XCT_PTR_ADDR(x) ((((long)(x)) << XCT_PTR_ADDR_S) & \
449 XCT_PTR_ADDR_M)
450
451/* Receive interface buffer fields */
452#define XCT_RXB_LEN_M 0x0ffff00000000000ull
453#define XCT_RXB_LEN_S 44
454#define XCT_RXB_LEN(x) ((((long)(x)) << XCT_PTR_LEN_S) & XCT_PTR_LEN_M)
455#define XCT_RXB_ADDR_M 0x00000fffffffffffull
456#define XCT_RXB_ADDR_S 0
457#define XCT_RXB_ADDR(x) ((((long)(x)) << XCT_PTR_ADDR_S) & XCT_PTR_ADDR_M)
458
459
460#endif /* PASEMI_MAC_H */