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Tony Lindgren1dbae812005-11-10 14:26:51 +00001/*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
Santosh Shilimkar44169072009-05-28 14:16:04 -07007 * Copyright (C) 2007-2009 Texas Instruments
Tony Lindgren646e3ed2008-10-06 15:49:36 +03008 *
9 * Author:
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
Tony Lindgren1dbae812005-11-10 14:26:51 +000012 *
Santosh Shilimkar44169072009-05-28 14:16:04 -070013 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
14 *
Tony Lindgren1dbae812005-11-10 14:26:51 +000015 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
Tony Lindgren1dbae812005-11-10 14:26:51 +000020#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/init.h>
Russell Kingfced80c2008-09-06 12:10:45 +010023#include <linux/io.h>
Paul Walmsley2f135ea2009-06-19 19:08:25 -060024#include <linux/clk.h>
Tony Lindgren1dbae812005-11-10 14:26:51 +000025
Tony Lindgren120db2c2006-04-02 17:46:27 +010026#include <asm/tlb.h>
Tony Lindgren120db2c2006-04-02 17:46:27 +010027
28#include <asm/mach/map.h>
29
Russell Kinga09e64f2008-08-05 16:14:15 +010030#include <mach/mux.h>
31#include <mach/omapfb.h>
Tony Lindgren646e3ed2008-10-06 15:49:36 +030032#include <mach/sram.h>
Paul Walmsleyf8de9b22009-01-28 12:27:31 -070033#include <mach/sdrc.h>
34#include <mach/gpmc.h>
Paul Walmsleyb3c6df32009-09-03 20:14:02 +030035#include <mach/serial.h>
Tony Lindgren646e3ed2008-10-06 15:49:36 +030036
Santosh Shilimkar44169072009-05-28 14:16:04 -070037#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdev is ready */
Tony Lindgren646e3ed2008-10-06 15:49:36 +030038#include "clock.h"
Tony Lindgren1dbae812005-11-10 14:26:51 +000039
Paul Walmsleyc0407a92009-09-03 20:14:01 +030040#include <mach/omap-pm.h>
Paul Walmsley97171002008-08-19 11:08:40 +030041#include <mach/powerdomain.h>
Paul Walmsley97171002008-08-19 11:08:40 +030042#include "powerdomains.h"
43
Paul Walmsley801954d2008-08-19 11:08:44 +030044#include <mach/clockdomain.h>
45#include "clockdomains.h"
Santosh Shilimkar44169072009-05-28 14:16:04 -070046#endif
Paul Walmsley02bfc032009-09-03 20:14:05 +030047#include <mach/omap_hwmod.h>
48#include "omap_hwmod_2420.h"
49#include "omap_hwmod_2430.h"
50#include "omap_hwmod_34xx.h"
51
Tony Lindgren1dbae812005-11-10 14:26:51 +000052/*
53 * The machine specific code may provide the extra mapping besides the
54 * default mapping provided here.
55 */
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +030056
57#ifdef CONFIG_ARCH_OMAP24XX
58static struct map_desc omap24xx_io_desc[] __initdata = {
Tony Lindgren1dbae812005-11-10 14:26:51 +000059 {
60 .virtual = L3_24XX_VIRT,
61 .pfn = __phys_to_pfn(L3_24XX_PHYS),
62 .length = L3_24XX_SIZE,
63 .type = MT_DEVICE
64 },
Kyungmin Park09f21ed2008-02-20 15:30:06 -080065 {
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +030066 .virtual = L4_24XX_VIRT,
67 .pfn = __phys_to_pfn(L4_24XX_PHYS),
68 .length = L4_24XX_SIZE,
Syed Mohammed Khasim72d0f1c2006-12-06 17:14:05 -080069 .type = MT_DEVICE
70 },
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +030071};
72
73#ifdef CONFIG_ARCH_OMAP2420
74static struct map_desc omap242x_io_desc[] __initdata = {
Tony Lindgren1dbae812005-11-10 14:26:51 +000075 {
Tony Lindgrenc40fae952006-12-07 13:58:10 -080076 .virtual = DSP_MEM_24XX_VIRT,
77 .pfn = __phys_to_pfn(DSP_MEM_24XX_PHYS),
78 .length = DSP_MEM_24XX_SIZE,
79 .type = MT_DEVICE
80 },
81 {
82 .virtual = DSP_IPI_24XX_VIRT,
83 .pfn = __phys_to_pfn(DSP_IPI_24XX_PHYS),
84 .length = DSP_IPI_24XX_SIZE,
85 .type = MT_DEVICE
86 },
87 {
88 .virtual = DSP_MMU_24XX_VIRT,
89 .pfn = __phys_to_pfn(DSP_MMU_24XX_PHYS),
90 .length = DSP_MMU_24XX_SIZE,
Tony Lindgren1dbae812005-11-10 14:26:51 +000091 .type = MT_DEVICE
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +030092 },
Tony Lindgren1dbae812005-11-10 14:26:51 +000093};
94
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +030095#endif
96
97#ifdef CONFIG_ARCH_OMAP2430
98static struct map_desc omap243x_io_desc[] __initdata = {
99 {
100 .virtual = L4_WK_243X_VIRT,
101 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
102 .length = L4_WK_243X_SIZE,
103 .type = MT_DEVICE
104 },
105 {
106 .virtual = OMAP243X_GPMC_VIRT,
107 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
108 .length = OMAP243X_GPMC_SIZE,
109 .type = MT_DEVICE
110 },
111 {
112 .virtual = OMAP243X_SDRC_VIRT,
113 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
114 .length = OMAP243X_SDRC_SIZE,
115 .type = MT_DEVICE
116 },
117 {
118 .virtual = OMAP243X_SMS_VIRT,
119 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
120 .length = OMAP243X_SMS_SIZE,
121 .type = MT_DEVICE
122 },
123};
124#endif
125#endif
126
127#ifdef CONFIG_ARCH_OMAP34XX
128static struct map_desc omap34xx_io_desc[] __initdata = {
129 {
130 .virtual = L3_34XX_VIRT,
131 .pfn = __phys_to_pfn(L3_34XX_PHYS),
132 .length = L3_34XX_SIZE,
133 .type = MT_DEVICE
134 },
135 {
136 .virtual = L4_34XX_VIRT,
137 .pfn = __phys_to_pfn(L4_34XX_PHYS),
138 .length = L4_34XX_SIZE,
139 .type = MT_DEVICE
140 },
141 {
142 .virtual = L4_WK_34XX_VIRT,
143 .pfn = __phys_to_pfn(L4_WK_34XX_PHYS),
144 .length = L4_WK_34XX_SIZE,
145 .type = MT_DEVICE
146 },
147 {
148 .virtual = OMAP34XX_GPMC_VIRT,
149 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
150 .length = OMAP34XX_GPMC_SIZE,
151 .type = MT_DEVICE
152 },
153 {
154 .virtual = OMAP343X_SMS_VIRT,
155 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
156 .length = OMAP343X_SMS_SIZE,
157 .type = MT_DEVICE
158 },
159 {
160 .virtual = OMAP343X_SDRC_VIRT,
161 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
162 .length = OMAP343X_SDRC_SIZE,
163 .type = MT_DEVICE
164 },
165 {
166 .virtual = L4_PER_34XX_VIRT,
167 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
168 .length = L4_PER_34XX_SIZE,
169 .type = MT_DEVICE
170 },
171 {
172 .virtual = L4_EMU_34XX_VIRT,
173 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
174 .length = L4_EMU_34XX_SIZE,
175 .type = MT_DEVICE
176 },
177};
178#endif
Santosh Shilimkar44169072009-05-28 14:16:04 -0700179#ifdef CONFIG_ARCH_OMAP4
180static struct map_desc omap44xx_io_desc[] __initdata = {
181 {
182 .virtual = L3_44XX_VIRT,
183 .pfn = __phys_to_pfn(L3_44XX_PHYS),
184 .length = L3_44XX_SIZE,
185 .type = MT_DEVICE,
186 },
187 {
188 .virtual = L4_44XX_VIRT,
189 .pfn = __phys_to_pfn(L4_44XX_PHYS),
190 .length = L4_44XX_SIZE,
191 .type = MT_DEVICE,
192 },
193 {
194 .virtual = L4_WK_44XX_VIRT,
195 .pfn = __phys_to_pfn(L4_WK_44XX_PHYS),
196 .length = L4_WK_44XX_SIZE,
197 .type = MT_DEVICE,
198 },
199 {
200 .virtual = OMAP44XX_GPMC_VIRT,
201 .pfn = __phys_to_pfn(OMAP44XX_GPMC_PHYS),
202 .length = OMAP44XX_GPMC_SIZE,
203 .type = MT_DEVICE,
204 },
205 {
Santosh Shilimkarf5d2d652009-10-19 17:25:57 -0700206 .virtual = OMAP44XX_EMIF1_VIRT,
207 .pfn = __phys_to_pfn(OMAP44XX_EMIF1_PHYS),
208 .length = OMAP44XX_EMIF1_SIZE,
209 .type = MT_DEVICE,
210 },
211 {
212 .virtual = OMAP44XX_EMIF2_VIRT,
213 .pfn = __phys_to_pfn(OMAP44XX_EMIF2_PHYS),
214 .length = OMAP44XX_EMIF2_SIZE,
215 .type = MT_DEVICE,
216 },
217 {
218 .virtual = OMAP44XX_DMM_VIRT,
219 .pfn = __phys_to_pfn(OMAP44XX_DMM_PHYS),
220 .length = OMAP44XX_DMM_SIZE,
221 .type = MT_DEVICE,
222 },
223 {
Santosh Shilimkar44169072009-05-28 14:16:04 -0700224 .virtual = L4_PER_44XX_VIRT,
225 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
226 .length = L4_PER_44XX_SIZE,
227 .type = MT_DEVICE,
228 },
229 {
230 .virtual = L4_EMU_44XX_VIRT,
231 .pfn = __phys_to_pfn(L4_EMU_44XX_PHYS),
232 .length = L4_EMU_44XX_SIZE,
233 .type = MT_DEVICE,
234 },
235};
236#endif
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300237
Tony Lindgren120db2c2006-04-02 17:46:27 +0100238void __init omap2_map_common_io(void)
Tony Lindgren1dbae812005-11-10 14:26:51 +0000239{
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300240#if defined(CONFIG_ARCH_OMAP2420)
241 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
242 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
243#endif
244
245#if defined(CONFIG_ARCH_OMAP2430)
246 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
247 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
248#endif
249
250#if defined(CONFIG_ARCH_OMAP34XX)
251 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
252#endif
Tony Lindgren120db2c2006-04-02 17:46:27 +0100253
Santosh Shilimkar44169072009-05-28 14:16:04 -0700254#if defined(CONFIG_ARCH_OMAP4)
255 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
256#endif
Tony Lindgren120db2c2006-04-02 17:46:27 +0100257 /* Normally devicemaps_init() would flush caches and tlb after
258 * mdesc->map_io(), but we must also do it here because of the CPU
259 * revision check below.
260 */
261 local_flush_tlb_all();
262 flush_cache_all();
263
Tony Lindgren1dbae812005-11-10 14:26:51 +0000264 omap2_check_revision();
265 omap_sram_init();
Imre Deakb7cc6d42007-03-06 03:16:36 -0800266 omapfb_reserve_sdram();
Tony Lindgren120db2c2006-04-02 17:46:27 +0100267}
268
Paul Walmsley2f135ea2009-06-19 19:08:25 -0600269/*
270 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
271 *
272 * Sets the CORE DPLL3 M2 divider to the same value that it's at
273 * currently. This has the effect of setting the SDRC SDRAM AC timing
274 * registers to the values currently defined by the kernel. Currently
275 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
276 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
277 * or passes along the return value of clk_set_rate().
278 */
279static int __init _omap2_init_reprogram_sdrc(void)
280{
281 struct clk *dpll3_m2_ck;
282 int v = -EINVAL;
283 long rate;
284
285 if (!cpu_is_omap34xx())
286 return 0;
287
288 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
289 if (!dpll3_m2_ck)
290 return -EINVAL;
291
292 rate = clk_get_rate(dpll3_m2_ck);
293 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
294 v = clk_set_rate(dpll3_m2_ck, rate);
295 if (v)
296 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
297
298 clk_put(dpll3_m2_ck);
299
300 return v;
301}
302
Jean Pihet58cda882009-07-24 19:43:25 -0600303void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
304 struct omap_sdrc_params *sdrc_cs1)
Tony Lindgren120db2c2006-04-02 17:46:27 +0100305{
Paul Walmsley02bfc032009-09-03 20:14:05 +0300306 struct omap_hwmod **hwmods = NULL;
307
308 if (cpu_is_omap2420())
309 hwmods = omap2420_hwmods;
310 else if (cpu_is_omap2430())
311 hwmods = omap2430_hwmods;
312 else if (cpu_is_omap34xx())
313 hwmods = omap34xx_hwmods;
314
Santosh Shilimkar44169072009-05-28 14:16:04 -0700315#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */
Paul Walmsleyc0407a92009-09-03 20:14:01 +0300316 /* The OPP tables have to be registered before a clk init */
Tony Lindgren61f04ee2009-09-24 16:23:07 -0700317 omap_hwmod_init(hwmods);
318 omap2_mux_init();
Paul Walmsleyc0407a92009-09-03 20:14:01 +0300319 omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps);
Paul Walmsley97171002008-08-19 11:08:40 +0300320 pwrdm_init(powerdomains_omap);
Paul Walmsley801954d2008-08-19 11:08:44 +0300321 clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
Tony Lindgren1dbae812005-11-10 14:26:51 +0000322 omap2_clk_init();
Paul Walmsleyb3c6df32009-09-03 20:14:02 +0300323 omap_serial_early_init();
Paul Walmsley02bfc032009-09-03 20:14:05 +0300324 omap_hwmod_late_init();
Paul Walmsleyc0407a92009-09-03 20:14:01 +0300325 omap_pm_if_init();
Jean Pihet58cda882009-07-24 19:43:25 -0600326 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
Paul Walmsley2f135ea2009-06-19 19:08:25 -0600327 _omap2_init_reprogram_sdrc();
Santosh Shilimkar44169072009-05-28 14:16:04 -0700328#endif
Juha Yrjola4bbbc1a2006-06-26 16:16:16 -0700329 gpmc_init();
Tony Lindgren1dbae812005-11-10 14:26:51 +0000330}