Michael Buesch | 61e115a | 2007-09-18 15:12:50 -0400 | [diff] [blame] | 1 | #ifndef LINUX_SSB_REGS_H_ |
| 2 | #define LINUX_SSB_REGS_H_ |
| 3 | |
| 4 | |
| 5 | /* SiliconBackplane Address Map. |
| 6 | * All regions may not exist on all chips. |
| 7 | */ |
| 8 | #define SSB_SDRAM_BASE 0x00000000U /* Physical SDRAM */ |
| 9 | #define SSB_PCI_MEM 0x08000000U /* Host Mode sb2pcitranslation0 (64 MB) */ |
| 10 | #define SSB_PCI_CFG 0x0c000000U /* Host Mode sb2pcitranslation1 (64 MB) */ |
| 11 | #define SSB_SDRAM_SWAPPED 0x10000000U /* Byteswapped Physical SDRAM */ |
| 12 | #define SSB_ENUM_BASE 0x18000000U /* Enumeration space base */ |
| 13 | #define SSB_ENUM_LIMIT 0x18010000U /* Enumeration space limit */ |
| 14 | |
| 15 | #define SSB_FLASH2 0x1c000000U /* Flash Region 2 (region 1 shadowed here) */ |
| 16 | #define SSB_FLASH2_SZ 0x02000000U /* Size of Flash Region 2 */ |
| 17 | |
| 18 | #define SSB_EXTIF_BASE 0x1f000000U /* External Interface region base address */ |
| 19 | #define SSB_FLASH1 0x1fc00000U /* Flash Region 1 */ |
| 20 | #define SSB_FLASH1_SZ 0x00400000U /* Size of Flash Region 1 */ |
| 21 | |
| 22 | #define SSB_PCI_DMA 0x40000000U /* Client Mode sb2pcitranslation2 (1 GB) */ |
| 23 | #define SSB_PCI_DMA_SZ 0x40000000U /* Client Mode sb2pcitranslation2 size in bytes */ |
| 24 | #define SSB_PCIE_DMA_L32 0x00000000U /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), low 32 bits */ |
| 25 | #define SSB_PCIE_DMA_H32 0x80000000U /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */ |
| 26 | #define SSB_EUART (SSB_EXTIF_BASE + 0x00800000) |
| 27 | #define SSB_LED (SSB_EXTIF_BASE + 0x00900000) |
| 28 | |
| 29 | |
| 30 | /* Enumeration space constants */ |
| 31 | #define SSB_CORE_SIZE 0x1000 /* Size of a core MMIO area */ |
| 32 | #define SSB_MAX_NR_CORES ((SSB_ENUM_LIMIT - SSB_ENUM_BASE) / SSB_CORE_SIZE) |
| 33 | |
| 34 | |
| 35 | /* mips address */ |
| 36 | #define SSB_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */ |
| 37 | |
| 38 | |
| 39 | /* SSB PCI config space registers. */ |
| 40 | #define SSB_PMCSR 0x44 |
| 41 | #define SSB_PE 0x100 |
| 42 | #define SSB_BAR0_WIN 0x80 /* Backplane address space 0 */ |
| 43 | #define SSB_BAR1_WIN 0x84 /* Backplane address space 1 */ |
| 44 | #define SSB_SPROMCTL 0x88 /* SPROM control */ |
| 45 | #define SSB_SPROMCTL_WE 0x10 /* SPROM write enable */ |
| 46 | #define SSB_BAR1_CONTROL 0x8c /* Address space 1 burst control */ |
| 47 | #define SSB_PCI_IRQS 0x90 /* PCI interrupts */ |
| 48 | #define SSB_PCI_IRQMASK 0x94 /* PCI IRQ control and mask (pcirev >= 6 only) */ |
| 49 | #define SSB_BACKPLANE_IRQS 0x98 /* Backplane Interrupts */ |
| 50 | #define SSB_GPIO_IN 0xB0 /* GPIO Input (pcirev >= 3 only) */ |
| 51 | #define SSB_GPIO_OUT 0xB4 /* GPIO Output (pcirev >= 3 only) */ |
| 52 | #define SSB_GPIO_OUT_ENABLE 0xB8 /* GPIO Output Enable/Disable (pcirev >= 3 only) */ |
| 53 | #define SSB_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */ |
| 54 | #define SSB_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */ |
| 55 | #define SSB_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */ |
| 56 | #define SSB_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */ |
| 57 | |
| 58 | |
| 59 | #define SSB_BAR0_MAX_RETRIES 50 |
| 60 | |
| 61 | /* Silicon backplane configuration register definitions */ |
| 62 | #define SSB_IPSFLAG 0x0F08 |
| 63 | #define SSB_IPSFLAG_IRQ1 0x0000003F /* which sbflags get routed to mips interrupt 1 */ |
| 64 | #define SSB_IPSFLAG_IRQ1_SHIFT 0 |
| 65 | #define SSB_IPSFLAG_IRQ2 0x00003F00 /* which sbflags get routed to mips interrupt 2 */ |
| 66 | #define SSB_IPSFLAG_IRQ2_SHIFT 8 |
| 67 | #define SSB_IPSFLAG_IRQ3 0x003F0000 /* which sbflags get routed to mips interrupt 3 */ |
| 68 | #define SSB_IPSFLAG_IRQ3_SHIFT 16 |
| 69 | #define SSB_IPSFLAG_IRQ4 0x3F000000 /* which sbflags get routed to mips interrupt 4 */ |
| 70 | #define SSB_IPSFLAG_IRQ4_SHIFT 24 |
| 71 | #define SSB_TPSFLAG 0x0F18 |
| 72 | #define SSB_TPSFLAG_BPFLAG 0x0000003F /* Backplane flag # */ |
| 73 | #define SSB_TPSFLAG_ALWAYSIRQ 0x00000040 /* IRQ is always sent on the Backplane */ |
| 74 | #define SSB_TMERRLOGA 0x0F48 |
| 75 | #define SSB_TMERRLOG 0x0F50 |
| 76 | #define SSB_ADMATCH3 0x0F60 |
| 77 | #define SSB_ADMATCH2 0x0F68 |
| 78 | #define SSB_ADMATCH1 0x0F70 |
| 79 | #define SSB_IMSTATE 0x0F90 /* SB Initiator Agent State */ |
| 80 | #define SSB_IMSTATE_PC 0x0000000f /* Pipe Count */ |
| 81 | #define SSB_IMSTATE_AP_MASK 0x00000030 /* Arbitration Priority */ |
| 82 | #define SSB_IMSTATE_AP_BOTH 0x00000000 /* Use both timeslices and token */ |
| 83 | #define SSB_IMSTATE_AP_TS 0x00000010 /* Use timeslices only */ |
| 84 | #define SSB_IMSTATE_AP_TK 0x00000020 /* Use token only */ |
| 85 | #define SSB_IMSTATE_AP_RSV 0x00000030 /* Reserved */ |
| 86 | #define SSB_IMSTATE_IBE 0x00020000 /* In Band Error */ |
| 87 | #define SSB_IMSTATE_TO 0x00040000 /* Timeout */ |
| 88 | #define SSB_INTVEC 0x0F94 /* SB Interrupt Mask */ |
| 89 | #define SSB_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */ |
| 90 | #define SSB_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */ |
| 91 | #define SSB_INTVEC_ILINE20 0x00000004 /* Enable interrupts for iline20 */ |
| 92 | #define SSB_INTVEC_CODEC 0x00000008 /* Enable interrupts for v90 codec */ |
| 93 | #define SSB_INTVEC_USB 0x00000010 /* Enable interrupts for usb */ |
| 94 | #define SSB_INTVEC_EXTIF 0x00000020 /* Enable interrupts for external i/f */ |
| 95 | #define SSB_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */ |
| 96 | #define SSB_TMSLOW 0x0F98 /* SB Target State Low */ |
| 97 | #define SSB_TMSLOW_RESET 0x00000001 /* Reset */ |
| 98 | #define SSB_TMSLOW_REJECT_22 0x00000002 /* Reject (Backplane rev 2.2) */ |
| 99 | #define SSB_TMSLOW_REJECT_23 0x00000004 /* Reject (Backplane rev 2.3) */ |
| 100 | #define SSB_TMSLOW_CLOCK 0x00010000 /* Clock Enable */ |
| 101 | #define SSB_TMSLOW_FGC 0x00020000 /* Force Gated Clocks On */ |
| 102 | #define SSB_TMSLOW_PE 0x40000000 /* Power Management Enable */ |
| 103 | #define SSB_TMSLOW_BE 0x80000000 /* BIST Enable */ |
| 104 | #define SSB_TMSHIGH 0x0F9C /* SB Target State High */ |
| 105 | #define SSB_TMSHIGH_SERR 0x00000001 /* S-error */ |
| 106 | #define SSB_TMSHIGH_INT 0x00000002 /* Interrupt */ |
| 107 | #define SSB_TMSHIGH_BUSY 0x00000004 /* Busy */ |
| 108 | #define SSB_TMSHIGH_TO 0x00000020 /* Timeout. Backplane rev >= 2.3 only */ |
| 109 | #define SSB_TMSHIGH_COREFL 0x1FFF0000 /* Core specific flags */ |
| 110 | #define SSB_TMSHIGH_COREFL_SHIFT 16 |
| 111 | #define SSB_TMSHIGH_DMA64 0x10000000 /* 64bit DMA supported */ |
| 112 | #define SSB_TMSHIGH_GCR 0x20000000 /* Gated Clock Request */ |
| 113 | #define SSB_TMSHIGH_BISTF 0x40000000 /* BIST Failed */ |
| 114 | #define SSB_TMSHIGH_BISTD 0x80000000 /* BIST Done */ |
| 115 | #define SSB_BWA0 0x0FA0 |
| 116 | #define SSB_IMCFGLO 0x0FA8 |
| 117 | #define SSB_IMCFGLO_SERTO 0x00000007 /* Service timeout */ |
| 118 | #define SSB_IMCFGLO_REQTO 0x00000070 /* Request timeout */ |
| 119 | #define SSB_IMCFGLO_REQTO_SHIFT 4 |
| 120 | #define SSB_IMCFGLO_CONNID 0x00FF0000 /* Connection ID */ |
| 121 | #define SSB_IMCFGLO_CONNID_SHIFT 16 |
| 122 | #define SSB_IMCFGHI 0x0FAC |
| 123 | #define SSB_ADMATCH0 0x0FB0 |
| 124 | #define SSB_TMCFGLO 0x0FB8 |
| 125 | #define SSB_TMCFGHI 0x0FBC |
| 126 | #define SSB_BCONFIG 0x0FC0 |
| 127 | #define SSB_BSTATE 0x0FC8 |
| 128 | #define SSB_ACTCFG 0x0FD8 |
| 129 | #define SSB_FLAGST 0x0FE8 |
| 130 | #define SSB_IDLOW 0x0FF8 |
| 131 | #define SSB_IDLOW_CFGSP 0x00000003 /* Config Space */ |
| 132 | #define SSB_IDLOW_ADDRNGE 0x00000038 /* Address Ranges supported */ |
| 133 | #define SSB_IDLOW_ADDRNGE_SHIFT 3 |
| 134 | #define SSB_IDLOW_SYNC 0x00000040 |
| 135 | #define SSB_IDLOW_INITIATOR 0x00000080 |
| 136 | #define SSB_IDLOW_MIBL 0x00000F00 /* Minimum Backplane latency */ |
| 137 | #define SSB_IDLOW_MIBL_SHIFT 8 |
| 138 | #define SSB_IDLOW_MABL 0x0000F000 /* Maximum Backplane latency */ |
| 139 | #define SSB_IDLOW_MABL_SHIFT 12 |
| 140 | #define SSB_IDLOW_TIF 0x00010000 /* This Initiator is first */ |
| 141 | #define SSB_IDLOW_CCW 0x000C0000 /* Cycle counter width */ |
| 142 | #define SSB_IDLOW_CCW_SHIFT 18 |
| 143 | #define SSB_IDLOW_TPT 0x00F00000 /* Target ports */ |
| 144 | #define SSB_IDLOW_TPT_SHIFT 20 |
| 145 | #define SSB_IDLOW_INITP 0x0F000000 /* Initiator ports */ |
| 146 | #define SSB_IDLOW_INITP_SHIFT 24 |
| 147 | #define SSB_IDLOW_SSBREV 0xF0000000 /* Sonics Backplane Revision code */ |
| 148 | #define SSB_IDLOW_SSBREV_22 0x00000000 /* <= 2.2 */ |
| 149 | #define SSB_IDLOW_SSBREV_23 0x10000000 /* 2.3 */ |
Larry Finger | c272ef4 | 2007-11-09 16:56:25 -0600 | [diff] [blame] | 150 | #define SSB_IDLOW_SSBREV_24 0x40000000 /* ?? Found in BCM4328 */ |
| 151 | #define SSB_IDLOW_SSBREV_25 0x50000000 /* ?? Not Found yet */ |
| 152 | #define SSB_IDLOW_SSBREV_26 0x60000000 /* ?? Found in some BCM4311/2 */ |
| 153 | #define SSB_IDLOW_SSBREV_27 0x70000000 /* ?? Found in some BCM4311/2 */ |
Michael Buesch | 61e115a | 2007-09-18 15:12:50 -0400 | [diff] [blame] | 154 | #define SSB_IDHIGH 0x0FFC /* SB Identification High */ |
| 155 | #define SSB_IDHIGH_RCLO 0x0000000F /* Revision Code (low part) */ |
| 156 | #define SSB_IDHIGH_CC 0x00008FF0 /* Core Code */ |
| 157 | #define SSB_IDHIGH_CC_SHIFT 4 |
| 158 | #define SSB_IDHIGH_RCHI 0x00007000 /* Revision Code (high part) */ |
| 159 | #define SSB_IDHIGH_RCHI_SHIFT 8 /* yes, shift 8 is right */ |
| 160 | #define SSB_IDHIGH_VC 0xFFFF0000 /* Vendor Code */ |
| 161 | #define SSB_IDHIGH_VC_SHIFT 16 |
| 162 | |
| 163 | /* SPROM shadow area. If not otherwise noted, fields are |
| 164 | * two bytes wide. Note that the SPROM can _only_ be read |
Gábor Stefanik | f679056 | 2009-08-10 21:23:08 +0200 | [diff] [blame^] | 165 | * in two-byte quantities. |
Michael Buesch | 61e115a | 2007-09-18 15:12:50 -0400 | [diff] [blame] | 166 | */ |
| 167 | #define SSB_SPROMSIZE_WORDS 64 |
| 168 | #define SSB_SPROMSIZE_BYTES (SSB_SPROMSIZE_WORDS * sizeof(u16)) |
Larry Finger | c272ef4 | 2007-11-09 16:56:25 -0600 | [diff] [blame] | 169 | #define SSB_SPROMSIZE_WORDS_R123 64 |
| 170 | #define SSB_SPROMSIZE_WORDS_R4 220 |
| 171 | #define SSB_SPROMSIZE_BYTES_R123 (SSB_SPROMSIZE_WORDS_R123 * sizeof(u16)) |
| 172 | #define SSB_SPROMSIZE_BYTES_R4 (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16)) |
Michael Buesch | 61e115a | 2007-09-18 15:12:50 -0400 | [diff] [blame] | 173 | #define SSB_SPROM_BASE 0x1000 |
| 174 | #define SSB_SPROM_REVISION 0x107E |
| 175 | #define SSB_SPROM_REVISION_REV 0x00FF /* SPROM Revision number */ |
| 176 | #define SSB_SPROM_REVISION_CRC 0xFF00 /* SPROM CRC8 value */ |
| 177 | #define SSB_SPROM_REVISION_CRC_SHIFT 8 |
Larry Finger | d3c319f | 2007-11-09 16:58:20 -0600 | [diff] [blame] | 178 | |
Michael Buesch | 61e115a | 2007-09-18 15:12:50 -0400 | [diff] [blame] | 179 | /* SPROM Revision 1 */ |
| 180 | #define SSB_SPROM1_SPID 0x1004 /* Subsystem Product ID for PCI */ |
| 181 | #define SSB_SPROM1_SVID 0x1006 /* Subsystem Vendor ID for PCI */ |
| 182 | #define SSB_SPROM1_PID 0x1008 /* Product ID for PCI */ |
| 183 | #define SSB_SPROM1_IL0MAC 0x1048 /* 6 bytes MAC address for 802.11b/g */ |
| 184 | #define SSB_SPROM1_ET0MAC 0x104E /* 6 bytes MAC address for Ethernet */ |
| 185 | #define SSB_SPROM1_ET1MAC 0x1054 /* 6 bytes MAC address for 802.11a */ |
| 186 | #define SSB_SPROM1_ETHPHY 0x105A /* Ethernet PHY settings */ |
| 187 | #define SSB_SPROM1_ETHPHY_ET0A 0x001F /* MII Address for enet0 */ |
| 188 | #define SSB_SPROM1_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */ |
| 189 | #define SSB_SPROM1_ETHPHY_ET1A_SHIFT 5 |
| 190 | #define SSB_SPROM1_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */ |
| 191 | #define SSB_SPROM1_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */ |
| 192 | #define SSB_SPROM1_BINF 0x105C /* Board info */ |
| 193 | #define SSB_SPROM1_BINF_BREV 0x00FF /* Board Revision */ |
| 194 | #define SSB_SPROM1_BINF_CCODE 0x0F00 /* Country Code */ |
| 195 | #define SSB_SPROM1_BINF_CCODE_SHIFT 8 |
Michael Buesch | e861b98 | 2007-12-22 21:51:30 +0100 | [diff] [blame] | 196 | #define SSB_SPROM1_BINF_ANTBG 0x3000 /* Available B-PHY and G-PHY antennas */ |
| 197 | #define SSB_SPROM1_BINF_ANTBG_SHIFT 12 |
| 198 | #define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */ |
| 199 | #define SSB_SPROM1_BINF_ANTA_SHIFT 14 |
Michael Buesch | 61e115a | 2007-09-18 15:12:50 -0400 | [diff] [blame] | 200 | #define SSB_SPROM1_PA0B0 0x105E |
| 201 | #define SSB_SPROM1_PA0B1 0x1060 |
| 202 | #define SSB_SPROM1_PA0B2 0x1062 |
| 203 | #define SSB_SPROM1_GPIOA 0x1064 /* General Purpose IO pins 0 and 1 */ |
| 204 | #define SSB_SPROM1_GPIOA_P0 0x00FF /* Pin 0 */ |
| 205 | #define SSB_SPROM1_GPIOA_P1 0xFF00 /* Pin 1 */ |
| 206 | #define SSB_SPROM1_GPIOA_P1_SHIFT 8 |
| 207 | #define SSB_SPROM1_GPIOB 0x1066 /* General Purpuse IO pins 2 and 3 */ |
| 208 | #define SSB_SPROM1_GPIOB_P2 0x00FF /* Pin 2 */ |
| 209 | #define SSB_SPROM1_GPIOB_P3 0xFF00 /* Pin 3 */ |
| 210 | #define SSB_SPROM1_GPIOB_P3_SHIFT 8 |
| 211 | #define SSB_SPROM1_MAXPWR 0x1068 /* Power Amplifier Max Power */ |
| 212 | #define SSB_SPROM1_MAXPWR_BG 0x00FF /* B-PHY and G-PHY (in dBm Q5.2) */ |
| 213 | #define SSB_SPROM1_MAXPWR_A 0xFF00 /* A-PHY (in dBm Q5.2) */ |
| 214 | #define SSB_SPROM1_MAXPWR_A_SHIFT 8 |
| 215 | #define SSB_SPROM1_PA1B0 0x106A |
| 216 | #define SSB_SPROM1_PA1B1 0x106C |
| 217 | #define SSB_SPROM1_PA1B2 0x106E |
| 218 | #define SSB_SPROM1_ITSSI 0x1070 /* Idle TSSI Target */ |
| 219 | #define SSB_SPROM1_ITSSI_BG 0x00FF /* B-PHY and G-PHY*/ |
| 220 | #define SSB_SPROM1_ITSSI_A 0xFF00 /* A-PHY */ |
| 221 | #define SSB_SPROM1_ITSSI_A_SHIFT 8 |
| 222 | #define SSB_SPROM1_BFLLO 0x1072 /* Boardflags (low 16 bits) */ |
| 223 | #define SSB_SPROM1_AGAIN 0x1074 /* Antenna Gain (in dBm Q5.2) */ |
Michael Buesch | e861b98 | 2007-12-22 21:51:30 +0100 | [diff] [blame] | 224 | #define SSB_SPROM1_AGAIN_BG 0x00FF /* B-PHY and G-PHY */ |
| 225 | #define SSB_SPROM1_AGAIN_BG_SHIFT 0 |
| 226 | #define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */ |
| 227 | #define SSB_SPROM1_AGAIN_A_SHIFT 8 |
Larry Finger | d3c319f | 2007-11-09 16:58:20 -0600 | [diff] [blame] | 228 | |
Michael Buesch | 61e115a | 2007-09-18 15:12:50 -0400 | [diff] [blame] | 229 | /* SPROM Revision 2 (inherits from rev 1) */ |
| 230 | #define SSB_SPROM2_BFLHI 0x1038 /* Boardflags (high 16 bits) */ |
| 231 | #define SSB_SPROM2_MAXP_A 0x103A /* A-PHY Max Power */ |
| 232 | #define SSB_SPROM2_MAXP_A_HI 0x00FF /* Max Power High */ |
| 233 | #define SSB_SPROM2_MAXP_A_LO 0xFF00 /* Max Power Low */ |
| 234 | #define SSB_SPROM2_MAXP_A_LO_SHIFT 8 |
| 235 | #define SSB_SPROM2_PA1LOB0 0x103C /* A-PHY PowerAmplifier Low Settings */ |
| 236 | #define SSB_SPROM2_PA1LOB1 0x103E /* A-PHY PowerAmplifier Low Settings */ |
| 237 | #define SSB_SPROM2_PA1LOB2 0x1040 /* A-PHY PowerAmplifier Low Settings */ |
| 238 | #define SSB_SPROM2_PA1HIB0 0x1042 /* A-PHY PowerAmplifier High Settings */ |
| 239 | #define SSB_SPROM2_PA1HIB1 0x1044 /* A-PHY PowerAmplifier High Settings */ |
| 240 | #define SSB_SPROM2_PA1HIB2 0x1046 /* A-PHY PowerAmplifier High Settings */ |
| 241 | #define SSB_SPROM2_OPO 0x1078 /* OFDM Power Offset from CCK Level */ |
| 242 | #define SSB_SPROM2_OPO_VALUE 0x00FF |
| 243 | #define SSB_SPROM2_OPO_UNUSED 0xFF00 |
| 244 | #define SSB_SPROM2_CCODE 0x107C /* Two char Country Code */ |
Larry Finger | d3c319f | 2007-11-09 16:58:20 -0600 | [diff] [blame] | 245 | |
Larry Finger | c272ef4 | 2007-11-09 16:56:25 -0600 | [diff] [blame] | 246 | /* SPROM Revision 3 (inherits most data from rev 2) */ |
| 247 | #define SSB_SPROM3_IL0MAC 0x104A /* 6 bytes MAC address for 802.11b/g */ |
Michael Buesch | 61e115a | 2007-09-18 15:12:50 -0400 | [diff] [blame] | 248 | #define SSB_SPROM3_OFDMAPO 0x102C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */ |
| 249 | #define SSB_SPROM3_OFDMALPO 0x1030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */ |
| 250 | #define SSB_SPROM3_OFDMAHPO 0x1034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */ |
| 251 | #define SSB_SPROM3_GPIOLDC 0x1042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */ |
| 252 | #define SSB_SPROM3_GPIOLDC_OFF 0x0000FF00 /* Off Count */ |
| 253 | #define SSB_SPROM3_GPIOLDC_OFF_SHIFT 8 |
| 254 | #define SSB_SPROM3_GPIOLDC_ON 0x00FF0000 /* On Count */ |
| 255 | #define SSB_SPROM3_GPIOLDC_ON_SHIFT 16 |
| 256 | #define SSB_SPROM3_CCKPO 0x1078 /* CCK Power Offset */ |
| 257 | #define SSB_SPROM3_CCKPO_1M 0x000F /* 1M Rate PO */ |
| 258 | #define SSB_SPROM3_CCKPO_2M 0x00F0 /* 2M Rate PO */ |
| 259 | #define SSB_SPROM3_CCKPO_2M_SHIFT 4 |
| 260 | #define SSB_SPROM3_CCKPO_55M 0x0F00 /* 5.5M Rate PO */ |
| 261 | #define SSB_SPROM3_CCKPO_55M_SHIFT 8 |
| 262 | #define SSB_SPROM3_CCKPO_11M 0xF000 /* 11M Rate PO */ |
| 263 | #define SSB_SPROM3_CCKPO_11M_SHIFT 12 |
| 264 | #define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */ |
Larry Finger | d3c319f | 2007-11-09 16:58:20 -0600 | [diff] [blame] | 265 | |
Michael Buesch | e861b98 | 2007-12-22 21:51:30 +0100 | [diff] [blame] | 266 | /* SPROM Revision 4 */ |
Larry Finger | d3c319f | 2007-11-09 16:58:20 -0600 | [diff] [blame] | 267 | #define SSB_SPROM4_IL0MAC 0x104C /* 6 byte MAC address for a/b/g/n */ |
Larry Finger | d3c319f | 2007-11-09 16:58:20 -0600 | [diff] [blame] | 268 | #define SSB_SPROM4_ETHPHY 0x105A /* Ethernet PHY settings ?? */ |
Larry Finger | ac82fab | 2007-11-09 16:54:45 -0600 | [diff] [blame] | 269 | #define SSB_SPROM4_ETHPHY_ET0A 0x001F /* MII Address for enet0 */ |
| 270 | #define SSB_SPROM4_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */ |
| 271 | #define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5 |
| 272 | #define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */ |
| 273 | #define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */ |
| 274 | #define SSB_SPROM4_CCODE 0x1052 /* Country Code (2 bytes) */ |
Michael Buesch | e861b98 | 2007-12-22 21:51:30 +0100 | [diff] [blame] | 275 | #define SSB_SPROM4_ANTAVAIL 0x105D /* Antenna available bitfields */ |
| 276 | #define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */ |
| 277 | #define SSB_SPROM4_ANTAVAIL_A_SHIFT 0 |
| 278 | #define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */ |
| 279 | #define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8 |
Larry Finger | ac82fab | 2007-11-09 16:54:45 -0600 | [diff] [blame] | 280 | #define SSB_SPROM4_BFLLO 0x1044 /* Boardflags (low 16 bits) */ |
Michael Buesch | e861b98 | 2007-12-22 21:51:30 +0100 | [diff] [blame] | 281 | #define SSB_SPROM4_AGAIN01 0x105E /* Antenna Gain (in dBm Q5.2) */ |
| 282 | #define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */ |
| 283 | #define SSB_SPROM4_AGAIN0_SHIFT 0 |
| 284 | #define SSB_SPROM4_AGAIN1 0xFF00 /* Antenna 1 */ |
| 285 | #define SSB_SPROM4_AGAIN1_SHIFT 8 |
| 286 | #define SSB_SPROM4_AGAIN23 0x1060 |
| 287 | #define SSB_SPROM4_AGAIN2 0x00FF /* Antenna 2 */ |
| 288 | #define SSB_SPROM4_AGAIN2_SHIFT 0 |
| 289 | #define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */ |
| 290 | #define SSB_SPROM4_AGAIN3_SHIFT 8 |
Larry Finger | ac82fab | 2007-11-09 16:54:45 -0600 | [diff] [blame] | 291 | #define SSB_SPROM4_BFLHI 0x1046 /* Board Flags Hi */ |
Larry Finger | d3c319f | 2007-11-09 16:58:20 -0600 | [diff] [blame] | 292 | #define SSB_SPROM4_MAXP_BG 0x1080 /* Max Power BG in path 1 */ |
| 293 | #define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */ |
| 294 | #define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */ |
| 295 | #define SSB_SPROM4_ITSSI_BG_SHIFT 8 |
| 296 | #define SSB_SPROM4_MAXP_A 0x108A /* Max Power A in path 1 */ |
| 297 | #define SSB_SPROM4_MAXP_A_MASK 0x00FF /* Mask for Max Power A */ |
| 298 | #define SSB_SPROM4_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */ |
| 299 | #define SSB_SPROM4_ITSSI_A_SHIFT 8 |
| 300 | #define SSB_SPROM4_GPIOA 0x1056 /* Gen. Purpose IO # 0 and 1 */ |
| 301 | #define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */ |
| 302 | #define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */ |
| 303 | #define SSB_SPROM4_GPIOA_P1_SHIFT 8 |
| 304 | #define SSB_SPROM4_GPIOB 0x1058 /* Gen. Purpose IO # 2 and 3 */ |
| 305 | #define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */ |
| 306 | #define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */ |
| 307 | #define SSB_SPROM4_GPIOB_P3_SHIFT 8 |
| 308 | #define SSB_SPROM4_PA0B0 0x1082 /* The paXbY locations are */ |
| 309 | #define SSB_SPROM4_PA0B1 0x1084 /* only guesses */ |
| 310 | #define SSB_SPROM4_PA0B2 0x1086 |
| 311 | #define SSB_SPROM4_PA1B0 0x108E |
| 312 | #define SSB_SPROM4_PA1B1 0x1090 |
| 313 | #define SSB_SPROM4_PA1B2 0x1092 |
Michael Buesch | 61e115a | 2007-09-18 15:12:50 -0400 | [diff] [blame] | 314 | |
Larry Finger | 095f695 | 2008-08-19 12:50:31 -0500 | [diff] [blame] | 315 | /* SPROM Revision 5 (inherits most data from rev 4) */ |
| 316 | #define SSB_SPROM5_BFLLO 0x104A /* Boardflags (low 16 bits) */ |
| 317 | #define SSB_SPROM5_BFLHI 0x104C /* Board Flags Hi */ |
| 318 | #define SSB_SPROM5_IL0MAC 0x1052 /* 6 byte MAC address for a/b/g/n */ |
| 319 | #define SSB_SPROM5_CCODE 0x1044 /* Country Code (2 bytes) */ |
| 320 | #define SSB_SPROM5_GPIOA 0x1076 /* Gen. Purpose IO # 0 and 1 */ |
| 321 | #define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */ |
| 322 | #define SSB_SPROM5_GPIOA_P1 0xFF00 /* Pin 1 */ |
| 323 | #define SSB_SPROM5_GPIOA_P1_SHIFT 8 |
| 324 | #define SSB_SPROM5_GPIOB 0x1078 /* Gen. Purpose IO # 2 and 3 */ |
| 325 | #define SSB_SPROM5_GPIOB_P2 0x00FF /* Pin 2 */ |
| 326 | #define SSB_SPROM5_GPIOB_P3 0xFF00 /* Pin 3 */ |
| 327 | #define SSB_SPROM5_GPIOB_P3_SHIFT 8 |
| 328 | |
Michael Buesch | 6b1c7c6 | 2008-12-25 00:39:28 +0100 | [diff] [blame] | 329 | /* SPROM Revision 8 */ |
Gábor Stefanik | f679056 | 2009-08-10 21:23:08 +0200 | [diff] [blame^] | 330 | #define SSB_SPROM8_BOARDREV 0x1082 /* Board revision */ |
| 331 | #define SSB_SPROM8_BFLLO 0x1084 /* Board flags (bits 0-15) */ |
| 332 | #define SSB_SPROM8_BFLHI 0x1086 /* Board flags (bits 16-31) */ |
| 333 | #define SSB_SPROM8_BFL2LO 0x1088 /* Board flags (bits 32-47) */ |
| 334 | #define SSB_SPROM8_BFL2HI 0x108A /* Board flags (bits 48-63) */ |
Michael Buesch | 6b1c7c6 | 2008-12-25 00:39:28 +0100 | [diff] [blame] | 335 | #define SSB_SPROM8_IL0MAC 0x108C /* 6 byte MAC address */ |
| 336 | #define SSB_SPROM8_CCODE 0x1092 /* 2 byte country code */ |
| 337 | #define SSB_SPROM8_ANTAVAIL 0x109C /* Antenna available bitfields*/ |
| 338 | #define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */ |
| 339 | #define SSB_SPROM8_ANTAVAIL_A_SHIFT 8 |
| 340 | #define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */ |
| 341 | #define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0 |
| 342 | #define SSB_SPROM8_AGAIN01 0x109E /* Antenna Gain (in dBm Q5.2) */ |
| 343 | #define SSB_SPROM8_AGAIN0 0x00FF /* Antenna 0 */ |
| 344 | #define SSB_SPROM8_AGAIN0_SHIFT 0 |
| 345 | #define SSB_SPROM8_AGAIN1 0xFF00 /* Antenna 1 */ |
| 346 | #define SSB_SPROM8_AGAIN1_SHIFT 8 |
| 347 | #define SSB_SPROM8_AGAIN23 0x10A0 |
| 348 | #define SSB_SPROM8_AGAIN2 0x00FF /* Antenna 2 */ |
| 349 | #define SSB_SPROM8_AGAIN2_SHIFT 0 |
| 350 | #define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */ |
| 351 | #define SSB_SPROM8_AGAIN3_SHIFT 8 |
| 352 | #define SSB_SPROM8_GPIOA 0x1096 /*Gen. Purpose IO # 0 and 1 */ |
| 353 | #define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */ |
| 354 | #define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */ |
| 355 | #define SSB_SPROM8_GPIOA_P1_SHIFT 8 |
| 356 | #define SSB_SPROM8_GPIOB 0x1098 /* Gen. Purpose IO # 2 and 3 */ |
| 357 | #define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */ |
| 358 | #define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */ |
| 359 | #define SSB_SPROM8_GPIOB_P3_SHIFT 8 |
Gábor Stefanik | f679056 | 2009-08-10 21:23:08 +0200 | [diff] [blame^] | 360 | #define SSB_SPROM8_RSSIPARM2G 0x10A4 /* RSSI params for 2GHz */ |
| 361 | #define SSB_SPROM8_RSSISMF2G 0x000F |
| 362 | #define SSB_SPROM8_RSSISMC2G 0x00F0 |
| 363 | #define SSB_SPROM8_RSSISMC2G_SHIFT 4 |
| 364 | #define SSB_SPROM8_RSSISAV2G 0x0700 |
| 365 | #define SSB_SPROM8_RSSISAV2G_SHIFT 8 |
| 366 | #define SSB_SPROM8_BXA2G 0x1800 |
| 367 | #define SSB_SPROM8_BXA2G_SHIFT 11 |
| 368 | #define SSB_SPROM8_RSSIPARM5G 0x10A6 /* RSSI params for 5GHz */ |
| 369 | #define SSB_SPROM8_RSSISMF5G 0x000F |
| 370 | #define SSB_SPROM8_RSSISMC5G 0x00F0 |
| 371 | #define SSB_SPROM8_RSSISMC5G_SHIFT 4 |
| 372 | #define SSB_SPROM8_RSSISAV5G 0x0700 |
| 373 | #define SSB_SPROM8_RSSISAV5G_SHIFT 8 |
| 374 | #define SSB_SPROM8_BXA5G 0x1800 |
| 375 | #define SSB_SPROM8_BXA5G_SHIFT 11 |
| 376 | #define SSB_SPROM8_TRI25G 0x10A8 /* TX isolation 2.4&5.3GHz */ |
| 377 | #define SSB_SPROM8_TRI2G 0x00FF /* TX isolation 2.4GHz */ |
| 378 | #define SSB_SPROM8_TRI5G 0xFF00 /* TX isolation 5.3GHz */ |
| 379 | #define SSB_SPROM8_TRI5G_SHIFT 8 |
| 380 | #define SSB_SPROM8_TRI5GHL 0x10AA /* TX isolation 5.2/5.8GHz */ |
| 381 | #define SSB_SPROM8_TRI5GL 0x00FF /* TX isolation 5.2GHz */ |
| 382 | #define SSB_SPROM8_TRI5GH 0xFF00 /* TX isolation 5.8GHz */ |
| 383 | #define SSB_SPROM8_TRI5GH_SHIFT 8 |
| 384 | #define SSB_SPROM8_RXPO 0x10AC /* RX power offsets */ |
| 385 | #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */ |
| 386 | #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */ |
| 387 | #define SSB_SPROM8_RXPO5G_SHIFT 8 |
| 388 | #define SSB_SPROM8_MAXP_BG 0x10C0 /* Max Power 2GHz in path 1 */ |
| 389 | #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */ |
Michael Buesch | 6b1c7c6 | 2008-12-25 00:39:28 +0100 | [diff] [blame] | 390 | #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */ |
| 391 | #define SSB_SPROM8_ITSSI_BG_SHIFT 8 |
Gábor Stefanik | f679056 | 2009-08-10 21:23:08 +0200 | [diff] [blame^] | 392 | #define SSB_SPROM8_PA0B0 0x10C2 /* 2GHz power amp settings */ |
| 393 | #define SSB_SPROM8_PA0B1 0x10C4 |
| 394 | #define SSB_SPROM8_PA0B2 0x10C6 |
| 395 | #define SSB_SPROM8_MAXP_A 0x10C8 /* Max Power 5.3GHz */ |
| 396 | #define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power 5.3GHz */ |
Michael Buesch | 6b1c7c6 | 2008-12-25 00:39:28 +0100 | [diff] [blame] | 397 | #define SSB_SPROM8_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */ |
| 398 | #define SSB_SPROM8_ITSSI_A_SHIFT 8 |
Gábor Stefanik | f679056 | 2009-08-10 21:23:08 +0200 | [diff] [blame^] | 399 | #define SSB_SPROM8_MAXP_AHL 0x10CA /* Max Power 5.2/5.8GHz */ |
| 400 | #define SSB_SPROM8_MAXP_AH_MASK 0x00FF /* Mask for Max Power 5.8GHz */ |
| 401 | #define SSB_SPROM8_MAXP_AL_MASK 0xFF00 /* Mask for Max Power 5.2GHz */ |
| 402 | #define SSB_SPROM8_MAXP_AL_SHIFT 8 |
| 403 | #define SSB_SPROM8_PA1B0 0x10CC /* 5.3GHz power amp settings */ |
| 404 | #define SSB_SPROM8_PA1B1 0x10CE |
| 405 | #define SSB_SPROM8_PA1B2 0x10D0 |
| 406 | #define SSB_SPROM8_PA1LOB0 0x10D2 /* 5.2GHz power amp settings */ |
| 407 | #define SSB_SPROM8_PA1LOB1 0x10D4 |
| 408 | #define SSB_SPROM8_PA1LOB2 0x10D6 |
| 409 | #define SSB_SPROM8_PA1HIB0 0x10D8 /* 5.8GHz power amp settings */ |
| 410 | #define SSB_SPROM8_PA1HIB1 0x10DA |
| 411 | #define SSB_SPROM8_PA1HIB2 0x10DC |
| 412 | #define SSB_SPROM8_CCK2GPO 0x1140 /* CCK power offset */ |
| 413 | #define SSB_SPROM8_OFDM2GPO 0x1142 /* 2.4GHz OFDM power offset */ |
| 414 | #define SSB_SPROM8_OFDM5GPO 0x1146 /* 5.3GHz OFDM power offset */ |
| 415 | #define SSB_SPROM8_OFDM5GLPO 0x114A /* 5.2GHz OFDM power offset */ |
| 416 | #define SSB_SPROM8_OFDM5GHPO 0x114E /* 5.8GHz OFDM power offset */ |
Larry Finger | 095f695 | 2008-08-19 12:50:31 -0500 | [diff] [blame] | 417 | |
Michael Buesch | 61e115a | 2007-09-18 15:12:50 -0400 | [diff] [blame] | 418 | /* Values for SSB_SPROM1_BINF_CCODE */ |
| 419 | enum { |
| 420 | SSB_SPROM1CCODE_WORLD = 0, |
| 421 | SSB_SPROM1CCODE_THAILAND, |
| 422 | SSB_SPROM1CCODE_ISRAEL, |
| 423 | SSB_SPROM1CCODE_JORDAN, |
| 424 | SSB_SPROM1CCODE_CHINA, |
| 425 | SSB_SPROM1CCODE_JAPAN, |
| 426 | SSB_SPROM1CCODE_USA_CANADA_ANZ, |
| 427 | SSB_SPROM1CCODE_EUROPE, |
| 428 | SSB_SPROM1CCODE_USA_LOW, |
| 429 | SSB_SPROM1CCODE_JAPAN_HIGH, |
| 430 | SSB_SPROM1CCODE_ALL, |
| 431 | SSB_SPROM1CCODE_NONE, |
| 432 | }; |
| 433 | |
| 434 | /* Address-Match values and masks (SSB_ADMATCHxxx) */ |
| 435 | #define SSB_ADM_TYPE 0x00000003 /* Address type */ |
| 436 | #define SSB_ADM_TYPE0 0 |
| 437 | #define SSB_ADM_TYPE1 1 |
| 438 | #define SSB_ADM_TYPE2 2 |
| 439 | #define SSB_ADM_AD64 0x00000004 |
| 440 | #define SSB_ADM_SZ0 0x000000F8 /* Type0 size */ |
| 441 | #define SSB_ADM_SZ0_SHIFT 3 |
| 442 | #define SSB_ADM_SZ1 0x000001F8 /* Type1 size */ |
| 443 | #define SSB_ADM_SZ1_SHIFT 3 |
| 444 | #define SSB_ADM_SZ2 0x000001F8 /* Type2 size */ |
| 445 | #define SSB_ADM_SZ2_SHIFT 3 |
| 446 | #define SSB_ADM_EN 0x00000400 /* Enable */ |
| 447 | #define SSB_ADM_NEG 0x00000800 /* Negative decode */ |
| 448 | #define SSB_ADM_BASE0 0xFFFFFF00 /* Type0 base address */ |
| 449 | #define SSB_ADM_BASE0_SHIFT 8 |
| 450 | #define SSB_ADM_BASE1 0xFFFFF000 /* Type1 base address for the core */ |
| 451 | #define SSB_ADM_BASE1_SHIFT 12 |
| 452 | #define SSB_ADM_BASE2 0xFFFF0000 /* Type2 base address for the core */ |
| 453 | #define SSB_ADM_BASE2_SHIFT 16 |
| 454 | |
| 455 | |
| 456 | #endif /* LINUX_SSB_REGS_H_ */ |