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Paul Mackerras14cf11a2005-09-26 16:04:21 +10001/*
2 * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
3 */
Stephen Rothwellbbeb3f42005-09-27 13:51:59 +10004#ifndef _ASM_POWERPC_SYSTEM_H
5#define _ASM_POWERPC_SYSTEM_H
Paul Mackerras14cf11a2005-09-26 16:04:21 +10006
Paul Mackerras14cf11a2005-09-26 16:04:21 +10007#include <linux/kernel.h>
8
9#include <asm/hw_irq.h>
Paul Mackerras40ef8cb2005-10-10 22:50:37 +100010#include <asm/atomic.h>
Paul Mackerras14cf11a2005-09-26 16:04:21 +100011
12/*
13 * Memory barrier.
14 * The sync instruction guarantees that all memory accesses initiated
15 * by this processor have been performed (with respect to all other
16 * mechanisms that access memory). The eieio instruction is a barrier
17 * providing an ordering (separately) for (a) cacheable stores and (b)
18 * loads and stores to non-cacheable memory (e.g. I/O devices).
19 *
20 * mb() prevents loads and stores being reordered across this point.
21 * rmb() prevents loads being reordered across this point.
22 * wmb() prevents stores being reordered across this point.
23 * read_barrier_depends() prevents data-dependent loads being reordered
24 * across this point (nop on PPC).
25 *
26 * We have to use the sync instructions for mb(), since lwsync doesn't
27 * order loads with respect to previous stores. Lwsync is fine for
Andy Fleminge0da0da2006-10-27 14:31:07 -050028 * rmb(), though. Note that rmb() actually uses a sync on 32-bit
29 * architectures.
Paul Mackerras14cf11a2005-09-26 16:04:21 +100030 *
31 * For wmb(), we use sync since wmb is used in drivers to order
32 * stores to system memory with respect to writes to the device.
33 * However, smp_wmb() can be a lighter-weight eieio barrier on
34 * SMP since it is only used to order updates to system memory.
35 */
36#define mb() __asm__ __volatile__ ("sync" : : : "memory")
Andy Fleminge0da0da2006-10-27 14:31:07 -050037#define rmb() __asm__ __volatile__ (__stringify(LWSYNC) : : : "memory")
Paul Mackerras14cf11a2005-09-26 16:04:21 +100038#define wmb() __asm__ __volatile__ ("sync" : : : "memory")
39#define read_barrier_depends() do { } while(0)
40
41#define set_mb(var, value) do { var = value; mb(); } while (0)
Paul Mackerras14cf11a2005-09-26 16:04:21 +100042
Arnd Bergmann88ced032005-12-16 22:43:46 +010043#ifdef __KERNEL__
Paul Mackerras14cf11a2005-09-26 16:04:21 +100044#ifdef CONFIG_SMP
45#define smp_mb() mb()
46#define smp_rmb() rmb()
47#define smp_wmb() __asm__ __volatile__ ("eieio" : : : "memory")
48#define smp_read_barrier_depends() read_barrier_depends()
49#else
50#define smp_mb() barrier()
51#define smp_rmb() barrier()
52#define smp_wmb() barrier()
53#define smp_read_barrier_depends() do { } while(0)
54#endif /* CONFIG_SMP */
55
Nathan Lynch5db9fa92006-08-22 20:36:05 -050056/*
57 * This is a barrier which prevents following instructions from being
58 * started until the value of the argument x is known. For example, if
59 * x is a variable loaded from memory, this prevents following
60 * instructions from being executed until the load has been performed.
61 */
62#define data_barrier(x) \
63 asm volatile("twi 0,%0,0; isync" : : "r" (x) : "memory");
64
Paul Mackerras14cf11a2005-09-26 16:04:21 +100065struct task_struct;
66struct pt_regs;
67
68#ifdef CONFIG_DEBUGGER
69
70extern int (*__debugger)(struct pt_regs *regs);
71extern int (*__debugger_ipi)(struct pt_regs *regs);
72extern int (*__debugger_bpt)(struct pt_regs *regs);
73extern int (*__debugger_sstep)(struct pt_regs *regs);
74extern int (*__debugger_iabr_match)(struct pt_regs *regs);
75extern int (*__debugger_dabr_match)(struct pt_regs *regs);
76extern int (*__debugger_fault_handler)(struct pt_regs *regs);
77
78#define DEBUGGER_BOILERPLATE(__NAME) \
79static inline int __NAME(struct pt_regs *regs) \
80{ \
81 if (unlikely(__ ## __NAME)) \
82 return __ ## __NAME(regs); \
83 return 0; \
84}
85
86DEBUGGER_BOILERPLATE(debugger)
87DEBUGGER_BOILERPLATE(debugger_ipi)
88DEBUGGER_BOILERPLATE(debugger_bpt)
89DEBUGGER_BOILERPLATE(debugger_sstep)
90DEBUGGER_BOILERPLATE(debugger_iabr_match)
91DEBUGGER_BOILERPLATE(debugger_dabr_match)
92DEBUGGER_BOILERPLATE(debugger_fault_handler)
93
Paul Mackerras14cf11a2005-09-26 16:04:21 +100094#else
95static inline int debugger(struct pt_regs *regs) { return 0; }
96static inline int debugger_ipi(struct pt_regs *regs) { return 0; }
97static inline int debugger_bpt(struct pt_regs *regs) { return 0; }
98static inline int debugger_sstep(struct pt_regs *regs) { return 0; }
99static inline int debugger_iabr_match(struct pt_regs *regs) { return 0; }
100static inline int debugger_dabr_match(struct pt_regs *regs) { return 0; }
101static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; }
102#endif
103
104extern int set_dabr(unsigned long dabr);
105extern void print_backtrace(unsigned long *);
106extern void show_regs(struct pt_regs * regs);
107extern void flush_instruction_cache(void);
108extern void hard_reset_now(void);
109extern void poweroff_now(void);
110
111#ifdef CONFIG_6xx
112extern long _get_L2CR(void);
113extern long _get_L3CR(void);
114extern void _set_L2CR(unsigned long);
115extern void _set_L3CR(unsigned long);
116#else
117#define _get_L2CR() 0L
118#define _get_L3CR() 0L
119#define _set_L2CR(val) do { } while(0)
120#define _set_L3CR(val) do { } while(0)
121#endif
122
123extern void via_cuda_init(void);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000124extern void read_rtc_time(void);
125extern void pmac_find_display(void);
126extern void giveup_fpu(struct task_struct *);
Stephen Rothwellcabb5582005-09-30 16:16:52 +1000127extern void disable_kernel_fp(void);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000128extern void enable_kernel_fp(void);
129extern void flush_fp_to_thread(struct task_struct *);
130extern void enable_kernel_altivec(void);
131extern void giveup_altivec(struct task_struct *);
132extern void load_up_altivec(struct task_struct *);
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000133extern int emulate_altivec(struct pt_regs *);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000134extern void giveup_spe(struct task_struct *);
135extern void load_up_spe(struct task_struct *);
136extern int fix_alignment(struct pt_regs *);
David Gibson25c8a782005-10-27 16:27:25 +1000137extern void cvt_fd(float *from, double *to, struct thread_struct *thread);
138extern void cvt_df(double *from, float *to, struct thread_struct *thread);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000139
Paul Mackerras5388fb12006-01-11 22:11:39 +1100140#ifndef CONFIG_SMP
141extern void discard_lazy_cpu_state(void);
142#else
143static inline void discard_lazy_cpu_state(void)
144{
145}
146#endif
147
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000148#ifdef CONFIG_ALTIVEC
149extern void flush_altivec_to_thread(struct task_struct *);
150#else
151static inline void flush_altivec_to_thread(struct task_struct *t)
152{
153}
154#endif
155
156#ifdef CONFIG_SPE
157extern void flush_spe_to_thread(struct task_struct *);
158#else
159static inline void flush_spe_to_thread(struct task_struct *t)
160{
161}
162#endif
163
164extern int call_rtas(const char *, int, int, unsigned long *, ...);
165extern void cacheable_memzero(void *p, unsigned int nb);
166extern void *cacheable_memcpy(void *, const void *, unsigned int);
167extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
168extern void bad_page_fault(struct pt_regs *, unsigned long, int);
169extern int die(const char *, struct pt_regs *, long);
170extern void _exception(int, struct pt_regs *, int, unsigned long);
171#ifdef CONFIG_BOOKE_WDT
172extern u32 booke_wdt_enabled;
173extern u32 booke_wdt_period;
174#endif /* CONFIG_BOOKE_WDT */
175
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000176struct device_node;
177extern void note_scsi_host(struct device_node *, void *);
178
179extern struct task_struct *__switch_to(struct task_struct *,
180 struct task_struct *);
181#define switch_to(prev, next, last) ((last) = __switch_to((prev), (next)))
182
183struct thread_struct;
184extern struct task_struct *_switch(struct thread_struct *prev,
185 struct thread_struct *next);
186
Ingo Molnar4dc7a0b2006-01-12 01:05:27 -0800187/*
188 * On SMP systems, when the scheduler does migration-cost autodetection,
189 * it needs a way to flush as much of the CPU's caches as possible.
190 *
191 * TODO: fill this in!
192 */
193static inline void sched_cacheflush(void)
194{
195}
196
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000197extern unsigned int rtas_data;
Paul Mackerras40ef8cb2005-10-10 22:50:37 +1000198extern int mem_init_done; /* set on boot once kmalloc can be called */
Paul Mackerrascf00a8d2005-10-31 13:07:02 +1100199extern unsigned long memory_limit;
Paul Mackerras49b09852005-11-10 15:53:40 +1100200extern unsigned long klimit;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000201
Paul Mackerras17a63922005-10-20 21:10:09 +1000202extern int powersave_nap; /* set if nap mode can be used in idle loop */
203
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000204/*
205 * Atomic exchange
206 *
207 * Changes the memory location '*ptr' to be val and returns
208 * the previous value stored there.
209 */
210static __inline__ unsigned long
211__xchg_u32(volatile void *p, unsigned long val)
212{
213 unsigned long prev;
214
215 __asm__ __volatile__(
Anton Blanchard144b9c12006-01-13 15:37:17 +1100216 LWSYNC_ON_SMP
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000217"1: lwarx %0,0,%2 \n"
218 PPC405_ERR77(0,%2)
219" stwcx. %3,0,%2 \n\
220 bne- 1b"
221 ISYNC_ON_SMP
Linus Torvaldse2a3d402006-07-08 15:00:28 -0700222 : "=&r" (prev), "+m" (*(volatile unsigned int *)p)
223 : "r" (p), "r" (val)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000224 : "cc", "memory");
225
226 return prev;
227}
228
229#ifdef CONFIG_PPC64
230static __inline__ unsigned long
231__xchg_u64(volatile void *p, unsigned long val)
232{
233 unsigned long prev;
234
235 __asm__ __volatile__(
Anton Blanchard144b9c12006-01-13 15:37:17 +1100236 LWSYNC_ON_SMP
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000237"1: ldarx %0,0,%2 \n"
238 PPC405_ERR77(0,%2)
239" stdcx. %3,0,%2 \n\
240 bne- 1b"
241 ISYNC_ON_SMP
Linus Torvaldse2a3d402006-07-08 15:00:28 -0700242 : "=&r" (prev), "+m" (*(volatile unsigned long *)p)
243 : "r" (p), "r" (val)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000244 : "cc", "memory");
245
246 return prev;
247}
248#endif
249
250/*
251 * This function doesn't exist, so you'll get a linker error
252 * if something tries to do an invalid xchg().
253 */
254extern void __xchg_called_with_bad_pointer(void);
255
256static __inline__ unsigned long
257__xchg(volatile void *ptr, unsigned long x, unsigned int size)
258{
259 switch (size) {
260 case 4:
261 return __xchg_u32(ptr, x);
262#ifdef CONFIG_PPC64
263 case 8:
264 return __xchg_u64(ptr, x);
265#endif
266 }
267 __xchg_called_with_bad_pointer();
268 return x;
269}
270
271#define xchg(ptr,x) \
272 ({ \
273 __typeof__(*(ptr)) _x_ = (x); \
274 (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \
275 })
276
277#define tas(ptr) (xchg((ptr),1))
278
279/*
280 * Compare and exchange - if *p == old, set it to new,
281 * and return the old value of *p.
282 */
283#define __HAVE_ARCH_CMPXCHG 1
284
285static __inline__ unsigned long
286__cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new)
287{
288 unsigned int prev;
289
290 __asm__ __volatile__ (
Anton Blanchard144b9c12006-01-13 15:37:17 +1100291 LWSYNC_ON_SMP
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000292"1: lwarx %0,0,%2 # __cmpxchg_u32\n\
293 cmpw 0,%0,%3\n\
294 bne- 2f\n"
295 PPC405_ERR77(0,%2)
296" stwcx. %4,0,%2\n\
297 bne- 1b"
298 ISYNC_ON_SMP
299 "\n\
3002:"
Linus Torvaldse2a3d402006-07-08 15:00:28 -0700301 : "=&r" (prev), "+m" (*p)
302 : "r" (p), "r" (old), "r" (new)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000303 : "cc", "memory");
304
305 return prev;
306}
307
308#ifdef CONFIG_PPC64
309static __inline__ unsigned long
Benjamin Herrenschmidt3c726f82005-11-07 11:06:55 +1100310__cmpxchg_u64(volatile unsigned long *p, unsigned long old, unsigned long new)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000311{
312 unsigned long prev;
313
314 __asm__ __volatile__ (
Anton Blanchard144b9c12006-01-13 15:37:17 +1100315 LWSYNC_ON_SMP
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000316"1: ldarx %0,0,%2 # __cmpxchg_u64\n\
317 cmpd 0,%0,%3\n\
318 bne- 2f\n\
319 stdcx. %4,0,%2\n\
320 bne- 1b"
321 ISYNC_ON_SMP
322 "\n\
3232:"
Linus Torvaldse2a3d402006-07-08 15:00:28 -0700324 : "=&r" (prev), "+m" (*p)
325 : "r" (p), "r" (old), "r" (new)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000326 : "cc", "memory");
327
328 return prev;
329}
330#endif
331
332/* This function doesn't exist, so you'll get a linker error
333 if something tries to do an invalid cmpxchg(). */
334extern void __cmpxchg_called_with_bad_pointer(void);
335
336static __inline__ unsigned long
337__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new,
338 unsigned int size)
339{
340 switch (size) {
341 case 4:
342 return __cmpxchg_u32(ptr, old, new);
343#ifdef CONFIG_PPC64
344 case 8:
345 return __cmpxchg_u64(ptr, old, new);
346#endif
347 }
348 __cmpxchg_called_with_bad_pointer();
349 return old;
350}
351
352#define cmpxchg(ptr,o,n) \
353 ({ \
354 __typeof__(*(ptr)) _o_ = (o); \
355 __typeof__(*(ptr)) _n_ = (n); \
356 (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
357 (unsigned long)_n_, sizeof(*(ptr))); \
358 })
359
360#ifdef CONFIG_PPC64
361/*
362 * We handle most unaligned accesses in hardware. On the other hand
363 * unaligned DMA can be very expensive on some ppc64 IO chips (it does
364 * powers of 2 writes until it reaches sufficient alignment).
365 *
366 * Based on this we disable the IP header alignment in network drivers.
Anton Blanchard025be812006-03-31 02:27:06 -0800367 * We also modify NET_SKB_PAD to be a cacheline in size, thus maintaining
368 * cacheline alignment of buffers.
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000369 */
Anton Blanchard025be812006-03-31 02:27:06 -0800370#define NET_IP_ALIGN 0
371#define NET_SKB_PAD L1_CACHE_BYTES
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000372#endif
373
374#define arch_align_stack(x) (x)
375
Paul Mackerras9b6b5632005-10-06 12:06:20 +1000376/* Used in very early kernel initialization. */
Stephen Rothwellcabb5582005-09-30 16:16:52 +1000377extern unsigned long reloc_offset(void);
Paul Mackerras9b6b5632005-10-06 12:06:20 +1000378extern unsigned long add_reloc_offset(unsigned long);
379extern void reloc_got2(unsigned long);
380
381#define PTRRELOC(x) ((typeof(x)) add_reloc_offset((unsigned long)(x)))
Stephen Rothwellcabb5582005-09-30 16:16:52 +1000382
Michael Ellermanc87ef112005-11-03 17:57:53 +1100383static inline void create_instruction(unsigned long addr, unsigned int instr)
384{
385 unsigned int *p;
386 p = (unsigned int *)addr;
387 *p = instr;
388 asm ("dcbst 0, %0; sync; icbi 0,%0; sync; isync" : : "r" (p));
389}
390
391/* Flags for create_branch:
392 * "b" == create_branch(addr, target, 0);
393 * "ba" == create_branch(addr, target, BRANCH_ABSOLUTE);
394 * "bl" == create_branch(addr, target, BRANCH_SET_LINK);
395 * "bla" == create_branch(addr, target, BRANCH_ABSOLUTE | BRANCH_SET_LINK);
396 */
397#define BRANCH_SET_LINK 0x1
398#define BRANCH_ABSOLUTE 0x2
399
400static inline void create_branch(unsigned long addr,
401 unsigned long target, int flags)
402{
403 unsigned int instruction;
404
405 if (! (flags & BRANCH_ABSOLUTE))
406 target = target - addr;
407
408 /* Mask out the flags and target, so they don't step on each other. */
409 instruction = 0x48000000 | (flags & 0x3) | (target & 0x03FFFFFC);
410
411 create_instruction(addr, instruction);
412}
413
414static inline void create_function_call(unsigned long addr, void * func)
415{
416 unsigned long func_addr;
417
418#ifdef CONFIG_PPC64
419 /*
420 * On PPC64 the function pointer actually points to the function's
421 * descriptor. The first entry in the descriptor is the address
422 * of the function text.
423 */
424 func_addr = *(unsigned long *)func;
425#else
426 func_addr = (unsigned long)func;
427#endif
428 create_branch(addr, func_addr, BRANCH_SET_LINK);
429}
430
Paul Mackerrasc6622f62006-02-24 10:06:59 +1100431#ifdef CONFIG_VIRT_CPU_ACCOUNTING
432extern void account_system_vtime(struct task_struct *);
433#endif
434
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000435#endif /* __KERNEL__ */
Stephen Rothwellbbeb3f42005-09-27 13:51:59 +1000436#endif /* _ASM_POWERPC_SYSTEM_H */