blob: 47e5679c235303f5812eb1d4cd39a2140af89016 [file] [log] [blame]
Ralf Baechle0004a9d2006-10-31 03:45:07 +00001/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (c) 2006 Ralf Baechle (ralf@linux-mips.org)
7 */
Jakub Jelinek4732efb2005-09-06 15:16:25 -07008#ifndef _ASM_FUTEX_H
9#define _ASM_FUTEX_H
10
11#ifdef __KERNEL__
12
13#include <linux/futex.h>
Ralf Baechle0004a9d2006-10-31 03:45:07 +000014#include <asm/barrier.h>
Jakub Jelinek4732efb2005-09-06 15:16:25 -070015#include <asm/errno.h>
16#include <asm/uaccess.h>
Ralf Baechle6ee1da92006-05-03 20:42:39 +010017#include <asm/war.h>
Jakub Jelinek4732efb2005-09-06 15:16:25 -070018
Ralf Baechleebfaeba2005-09-15 08:52:34 +000019#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
20{ \
Ralf Baechle6ee1da92006-05-03 20:42:39 +010021 if (cpu_has_llsc && R10000_LLSC_WAR) { \
22 __asm__ __volatile__( \
23 " .set push \n" \
24 " .set noat \n" \
25 " .set mips3 \n" \
Atsushi Nemoto0307e8d2006-06-11 23:25:43 +090026 "1: ll %1, %4 # __futex_atomic_op \n" \
Ralf Baechle6ee1da92006-05-03 20:42:39 +010027 " .set mips0 \n" \
28 " " insn " \n" \
29 " .set mips3 \n" \
Atsushi Nemoto0307e8d2006-06-11 23:25:43 +090030 "2: sc $1, %2 \n" \
Ralf Baechle6ee1da92006-05-03 20:42:39 +010031 " beqzl $1, 1b \n" \
Ralf Baechle0004a9d2006-10-31 03:45:07 +000032 __WEAK_ORDERING_MB \
Ralf Baechle6ee1da92006-05-03 20:42:39 +010033 "3: \n" \
34 " .set pop \n" \
35 " .set mips0 \n" \
36 " .section .fixup,\"ax\" \n" \
Atsushi Nemoto0307e8d2006-06-11 23:25:43 +090037 "4: li %0, %6 \n" \
Ralf Baechle6ee1da92006-05-03 20:42:39 +010038 " j 2b \n" \
39 " .previous \n" \
40 " .section __ex_table,\"a\" \n" \
41 " "__UA_ADDR "\t1b, 4b \n" \
42 " "__UA_ADDR "\t2b, 4b \n" \
43 " .previous \n" \
Atsushi Nemoto0307e8d2006-06-11 23:25:43 +090044 : "=r" (ret), "=&r" (oldval), "=R" (*uaddr) \
45 : "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT) \
46 : "memory"); \
Ralf Baechle6ee1da92006-05-03 20:42:39 +010047 } else if (cpu_has_llsc) { \
48 __asm__ __volatile__( \
49 " .set push \n" \
50 " .set noat \n" \
51 " .set mips3 \n" \
Atsushi Nemoto0307e8d2006-06-11 23:25:43 +090052 "1: ll %1, %4 # __futex_atomic_op \n" \
Ralf Baechle6ee1da92006-05-03 20:42:39 +010053 " .set mips0 \n" \
54 " " insn " \n" \
55 " .set mips3 \n" \
Atsushi Nemoto0307e8d2006-06-11 23:25:43 +090056 "2: sc $1, %2 \n" \
Ralf Baechle6ee1da92006-05-03 20:42:39 +010057 " beqz $1, 1b \n" \
Ralf Baechle0004a9d2006-10-31 03:45:07 +000058 __WEAK_ORDERING_MB \
Ralf Baechle6ee1da92006-05-03 20:42:39 +010059 "3: \n" \
60 " .set pop \n" \
61 " .set mips0 \n" \
62 " .section .fixup,\"ax\" \n" \
Atsushi Nemoto0307e8d2006-06-11 23:25:43 +090063 "4: li %0, %6 \n" \
Ralf Baechle6ee1da92006-05-03 20:42:39 +010064 " j 2b \n" \
65 " .previous \n" \
66 " .section __ex_table,\"a\" \n" \
67 " "__UA_ADDR "\t1b, 4b \n" \
68 " "__UA_ADDR "\t2b, 4b \n" \
69 " .previous \n" \
Atsushi Nemoto0307e8d2006-06-11 23:25:43 +090070 : "=r" (ret), "=&r" (oldval), "=R" (*uaddr) \
71 : "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT) \
72 : "memory"); \
Ralf Baechle6ee1da92006-05-03 20:42:39 +010073 } else \
74 ret = -ENOSYS; \
Ralf Baechleebfaeba2005-09-15 08:52:34 +000075}
76
Jakub Jelinek4732efb2005-09-06 15:16:25 -070077static inline int
78futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
79{
80 int op = (encoded_op >> 28) & 7;
81 int cmp = (encoded_op >> 24) & 15;
82 int oparg = (encoded_op << 8) >> 20;
83 int cmparg = (encoded_op << 20) >> 20;
84 int oldval = 0, ret;
85 if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
86 oparg = 1 << oparg;
87
88 if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
89 return -EFAULT;
90
Peter Zijlstraa8663742006-12-06 20:32:20 -080091 pagefault_disable();
Jakub Jelinek4732efb2005-09-06 15:16:25 -070092
93 switch (op) {
94 case FUTEX_OP_SET:
Atsushi Nemoto0307e8d2006-06-11 23:25:43 +090095 __futex_atomic_op("move $1, %z5", ret, oldval, uaddr, oparg);
Ralf Baechleebfaeba2005-09-15 08:52:34 +000096 break;
97
Jakub Jelinek4732efb2005-09-06 15:16:25 -070098 case FUTEX_OP_ADD:
Atsushi Nemoto0307e8d2006-06-11 23:25:43 +090099 __futex_atomic_op("addu $1, %1, %z5",
Ralf Baechleebfaeba2005-09-15 08:52:34 +0000100 ret, oldval, uaddr, oparg);
101 break;
Jakub Jelinek4732efb2005-09-06 15:16:25 -0700102 case FUTEX_OP_OR:
Atsushi Nemoto0307e8d2006-06-11 23:25:43 +0900103 __futex_atomic_op("or $1, %1, %z5",
Ralf Baechleebfaeba2005-09-15 08:52:34 +0000104 ret, oldval, uaddr, oparg);
105 break;
Jakub Jelinek4732efb2005-09-06 15:16:25 -0700106 case FUTEX_OP_ANDN:
Atsushi Nemoto0307e8d2006-06-11 23:25:43 +0900107 __futex_atomic_op("and $1, %1, %z5",
Ralf Baechleebfaeba2005-09-15 08:52:34 +0000108 ret, oldval, uaddr, ~oparg);
109 break;
Jakub Jelinek4732efb2005-09-06 15:16:25 -0700110 case FUTEX_OP_XOR:
Atsushi Nemoto0307e8d2006-06-11 23:25:43 +0900111 __futex_atomic_op("xor $1, %1, %z5",
Ralf Baechleebfaeba2005-09-15 08:52:34 +0000112 ret, oldval, uaddr, oparg);
113 break;
Jakub Jelinek4732efb2005-09-06 15:16:25 -0700114 default:
115 ret = -ENOSYS;
116 }
117
Peter Zijlstraa8663742006-12-06 20:32:20 -0800118 pagefault_enable();
Jakub Jelinek4732efb2005-09-06 15:16:25 -0700119
120 if (!ret) {
121 switch (cmp) {
122 case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
123 case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
124 case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
125 case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
126 case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
127 case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
128 default: ret = -ENOSYS;
129 }
130 }
131 return ret;
132}
133
Ingo Molnare9056f12006-03-27 01:16:21 -0800134static inline int
Ingo Molnar8f17d3a2006-03-27 01:16:27 -0800135futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
Ingo Molnare9056f12006-03-27 01:16:21 -0800136{
Ralf Baechle6ee1da92006-05-03 20:42:39 +0100137 int retval;
138
139 if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
140 return -EFAULT;
141
142 if (cpu_has_llsc && R10000_LLSC_WAR) {
143 __asm__ __volatile__(
144 "# futex_atomic_cmpxchg_inatomic \n"
145 " .set push \n"
146 " .set noat \n"
147 " .set mips3 \n"
148 "1: ll %0, %2 \n"
149 " bne %0, %z3, 3f \n"
150 " .set mips0 \n"
151 " move $1, %z4 \n"
152 " .set mips3 \n"
153 "2: sc $1, %1 \n"
154 " beqzl $1, 1b \n"
Ralf Baechle0004a9d2006-10-31 03:45:07 +0000155 __WEAK_ORDERING_MB
Ralf Baechle6ee1da92006-05-03 20:42:39 +0100156 "3: \n"
157 " .set pop \n"
158 " .section .fixup,\"ax\" \n"
159 "4: li %0, %5 \n"
160 " j 3b \n"
161 " .previous \n"
162 " .section __ex_table,\"a\" \n"
163 " "__UA_ADDR "\t1b, 4b \n"
164 " "__UA_ADDR "\t2b, 4b \n"
165 " .previous \n"
166 : "=&r" (retval), "=R" (*uaddr)
167 : "R" (*uaddr), "Jr" (oldval), "Jr" (newval), "i" (-EFAULT)
168 : "memory");
169 } else if (cpu_has_llsc) {
170 __asm__ __volatile__(
171 "# futex_atomic_cmpxchg_inatomic \n"
172 " .set push \n"
173 " .set noat \n"
174 " .set mips3 \n"
175 "1: ll %0, %2 \n"
176 " bne %0, %z3, 3f \n"
177 " .set mips0 \n"
178 " move $1, %z4 \n"
179 " .set mips3 \n"
180 "2: sc $1, %1 \n"
181 " beqz $1, 1b \n"
Ralf Baechle0004a9d2006-10-31 03:45:07 +0000182 __WEAK_ORDERING_MB
Ralf Baechle6ee1da92006-05-03 20:42:39 +0100183 "3: \n"
184 " .set pop \n"
185 " .section .fixup,\"ax\" \n"
186 "4: li %0, %5 \n"
187 " j 3b \n"
188 " .previous \n"
189 " .section __ex_table,\"a\" \n"
190 " "__UA_ADDR "\t1b, 4b \n"
191 " "__UA_ADDR "\t2b, 4b \n"
192 " .previous \n"
193 : "=&r" (retval), "=R" (*uaddr)
194 : "R" (*uaddr), "Jr" (oldval), "Jr" (newval), "i" (-EFAULT)
195 : "memory");
196 } else
197 return -ENOSYS;
198
199 return retval;
Ingo Molnare9056f12006-03-27 01:16:21 -0800200}
201
Jakub Jelinek4732efb2005-09-06 15:16:25 -0700202#endif
203#endif