Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mach-omap2/clock.c |
| 3 | * |
Tony Lindgren | a16e970 | 2008-03-18 11:56:39 +0200 | [diff] [blame] | 4 | * Copyright (C) 2005-2008 Texas Instruments, Inc. |
Paul Walmsley | 8c34974 | 2010-02-22 22:09:24 -0700 | [diff] [blame] | 5 | * Copyright (C) 2004-2010 Nokia Corporation |
Tony Lindgren | a16e970 | 2008-03-18 11:56:39 +0200 | [diff] [blame] | 6 | * |
| 7 | * Contacts: |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 8 | * Richard Woodruff <r-woodruff2@ti.com> |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 9 | * Paul Walmsley |
| 10 | * |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License version 2 as |
| 13 | * published by the Free Software Foundation. |
| 14 | */ |
| 15 | #undef DEBUG |
| 16 | |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 17 | #include <linux/kernel.h> |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 18 | #include <linux/list.h> |
| 19 | #include <linux/errno.h> |
Paul Walmsley | 4d30e82 | 2010-02-22 22:09:36 -0700 | [diff] [blame] | 20 | #include <linux/err.h> |
| 21 | #include <linux/delay.h> |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 22 | #include <linux/clk.h> |
Russell King | fced80c | 2008-09-06 12:10:45 +0100 | [diff] [blame] | 23 | #include <linux/io.h> |
Russell King | fbd3bdb | 2008-09-06 12:13:59 +0100 | [diff] [blame] | 24 | #include <linux/bitops.h> |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 25 | |
Jean Pihet | 5e7c58d | 2011-03-03 11:25:43 +0100 | [diff] [blame] | 26 | #include <asm/cpu.h> |
Tony Lindgren | dbc0416 | 2012-08-31 10:59:07 -0700 | [diff] [blame] | 27 | |
Tony Lindgren | ce491cf | 2009-10-20 09:40:47 -0700 | [diff] [blame] | 28 | #include <plat/clock.h> |
Tony Lindgren | ce491cf | 2009-10-20 09:40:47 -0700 | [diff] [blame] | 29 | #include <plat/prcm.h> |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 30 | |
Tony Lindgren | dbc0416 | 2012-08-31 10:59:07 -0700 | [diff] [blame] | 31 | #include <trace/events/power.h> |
| 32 | |
| 33 | #include "soc.h" |
| 34 | #include "clockdomain.h" |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 35 | #include "clock.h" |
Paul Walmsley | 59fb659 | 2010-12-21 15:30:55 -0700 | [diff] [blame] | 36 | #include "cm2xxx_3xxx.h" |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 37 | #include "cm-regbits-24xx.h" |
| 38 | #include "cm-regbits-34xx.h" |
| 39 | |
Afzal Mohammed | 9954119 | 2011-12-13 10:46:43 -0800 | [diff] [blame] | 40 | u16 cpu_mask; |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 41 | |
Paul Walmsley | 30962d9 | 2010-02-22 22:09:38 -0700 | [diff] [blame] | 42 | /* |
Paul Walmsley | 12706c5 | 2011-07-10 05:57:06 -0600 | [diff] [blame] | 43 | * clkdm_control: if true, then when a clock is enabled in the |
| 44 | * hardware, its clockdomain will first be enabled; and when a clock |
| 45 | * is disabled in the hardware, its clockdomain will be disabled |
| 46 | * afterwards. |
| 47 | */ |
| 48 | static bool clkdm_control = true; |
| 49 | |
| 50 | /* |
Paul Walmsley | 30962d9 | 2010-02-22 22:09:38 -0700 | [diff] [blame] | 51 | * OMAP2+ specific clock functions |
| 52 | */ |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 53 | |
Paul Walmsley | 4b1f76e | 2010-01-26 20:13:04 -0700 | [diff] [blame] | 54 | /* Private functions */ |
| 55 | |
| 56 | /** |
| 57 | * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE |
| 58 | * @clk: struct clk * belonging to the module |
| 59 | * |
| 60 | * If the necessary clocks for the OMAP hardware IP block that |
| 61 | * corresponds to clock @clk are enabled, then wait for the module to |
| 62 | * indicate readiness (i.e., to leave IDLE). This code does not |
| 63 | * belong in the clock code and will be moved in the medium term to |
| 64 | * module-dependent code. No return value. |
| 65 | */ |
| 66 | static void _omap2_module_wait_ready(struct clk *clk) |
| 67 | { |
| 68 | void __iomem *companion_reg, *idlest_reg; |
Ranjith Lohithakshan | 419cc97 | 2010-02-24 12:05:54 -0700 | [diff] [blame] | 69 | u8 other_bit, idlest_bit, idlest_val; |
Paul Walmsley | 4b1f76e | 2010-01-26 20:13:04 -0700 | [diff] [blame] | 70 | |
| 71 | /* Not all modules have multiple clocks that their IDLEST depends on */ |
| 72 | if (clk->ops->find_companion) { |
| 73 | clk->ops->find_companion(clk, &companion_reg, &other_bit); |
| 74 | if (!(__raw_readl(companion_reg) & (1 << other_bit))) |
| 75 | return; |
| 76 | } |
| 77 | |
Ranjith Lohithakshan | 419cc97 | 2010-02-24 12:05:54 -0700 | [diff] [blame] | 78 | clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val); |
Paul Walmsley | 4b1f76e | 2010-01-26 20:13:04 -0700 | [diff] [blame] | 79 | |
Ranjith Lohithakshan | 419cc97 | 2010-02-24 12:05:54 -0700 | [diff] [blame] | 80 | omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), idlest_val, |
Rajendra Nayak | 5dcc3b9 | 2012-09-22 02:24:17 -0600 | [diff] [blame] | 81 | __clk_get_name(clk)); |
Paul Walmsley | 4b1f76e | 2010-01-26 20:13:04 -0700 | [diff] [blame] | 82 | } |
| 83 | |
Paul Walmsley | 4b1f76e | 2010-01-26 20:13:04 -0700 | [diff] [blame] | 84 | /* Public functions */ |
| 85 | |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 86 | /** |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 87 | * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk |
| 88 | * @clk: OMAP clock struct ptr to use |
| 89 | * |
| 90 | * Convert a clockdomain name stored in a struct clk 'clk' into a |
| 91 | * clockdomain pointer, and save it into the struct clk. Intended to be |
| 92 | * called during clk_register(). No return value. |
| 93 | */ |
| 94 | void omap2_init_clk_clkdm(struct clk *clk) |
| 95 | { |
| 96 | struct clockdomain *clkdm; |
Rajendra Nayak | 5dcc3b9 | 2012-09-22 02:24:17 -0600 | [diff] [blame] | 97 | const char *clk_name; |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 98 | |
| 99 | if (!clk->clkdm_name) |
| 100 | return; |
| 101 | |
Rajendra Nayak | 5dcc3b9 | 2012-09-22 02:24:17 -0600 | [diff] [blame] | 102 | clk_name = __clk_get_name(clk); |
| 103 | |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 104 | clkdm = clkdm_lookup(clk->clkdm_name); |
| 105 | if (clkdm) { |
| 106 | pr_debug("clock: associated clk %s to clkdm %s\n", |
Rajendra Nayak | 5dcc3b9 | 2012-09-22 02:24:17 -0600 | [diff] [blame] | 107 | clk_name, clk->clkdm_name); |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 108 | clk->clkdm = clkdm; |
| 109 | } else { |
Paul Walmsley | 7852ec0 | 2012-07-26 00:54:26 -0600 | [diff] [blame] | 110 | pr_debug("clock: could not associate clk %s to clkdm %s\n", |
Rajendra Nayak | 5dcc3b9 | 2012-09-22 02:24:17 -0600 | [diff] [blame] | 111 | clk_name, clk->clkdm_name); |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 112 | } |
| 113 | } |
| 114 | |
| 115 | /** |
Paul Walmsley | 12706c5 | 2011-07-10 05:57:06 -0600 | [diff] [blame] | 116 | * omap2_clk_disable_clkdm_control - disable clkdm control on clk enable/disable |
| 117 | * |
| 118 | * Prevent the OMAP clock code from calling into the clockdomain code |
| 119 | * when a hardware clock in that clockdomain is enabled or disabled. |
| 120 | * Intended to be called at init time from omap*_clk_init(). No |
| 121 | * return value. |
| 122 | */ |
| 123 | void __init omap2_clk_disable_clkdm_control(void) |
| 124 | { |
| 125 | clkdm_control = false; |
| 126 | } |
| 127 | |
| 128 | /** |
Paul Walmsley | 72350b2 | 2009-07-24 19:44:03 -0600 | [diff] [blame] | 129 | * omap2_clk_dflt_find_companion - find companion clock to @clk |
| 130 | * @clk: struct clk * to find the companion clock of |
| 131 | * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in |
| 132 | * @other_bit: u8 ** to return the companion clock bit shift in |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 133 | * |
Paul Walmsley | 72350b2 | 2009-07-24 19:44:03 -0600 | [diff] [blame] | 134 | * Note: We don't need special code here for INVERT_ENABLE for the |
| 135 | * time being since INVERT_ENABLE only applies to clocks enabled by |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 136 | * CM_CLKEN_PLL |
Paul Walmsley | 72350b2 | 2009-07-24 19:44:03 -0600 | [diff] [blame] | 137 | * |
| 138 | * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's |
| 139 | * just a matter of XORing the bits. |
| 140 | * |
| 141 | * Some clocks don't have companion clocks. For example, modules with |
| 142 | * only an interface clock (such as MAILBOXES) don't have a companion |
| 143 | * clock. Right now, this code relies on the hardware exporting a bit |
| 144 | * in the correct companion register that indicates that the |
| 145 | * nonexistent 'companion clock' is active. Future patches will |
| 146 | * associate this type of code with per-module data structures to |
| 147 | * avoid this issue, and remove the casts. No return value. |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 148 | */ |
Paul Walmsley | 72350b2 | 2009-07-24 19:44:03 -0600 | [diff] [blame] | 149 | void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, |
| 150 | u8 *other_bit) |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 151 | { |
Paul Walmsley | 72350b2 | 2009-07-24 19:44:03 -0600 | [diff] [blame] | 152 | u32 r; |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 153 | |
Russell King | c1168dc | 2008-11-04 21:24:00 +0000 | [diff] [blame] | 154 | /* |
| 155 | * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes |
| 156 | * it's just a matter of XORing the bits. |
| 157 | */ |
Paul Walmsley | 72350b2 | 2009-07-24 19:44:03 -0600 | [diff] [blame] | 158 | r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN)); |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 159 | |
Paul Walmsley | 72350b2 | 2009-07-24 19:44:03 -0600 | [diff] [blame] | 160 | *other_reg = (__force void __iomem *)r; |
| 161 | *other_bit = clk->enable_bit; |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 162 | } |
| 163 | |
Paul Walmsley | 72350b2 | 2009-07-24 19:44:03 -0600 | [diff] [blame] | 164 | /** |
| 165 | * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk |
| 166 | * @clk: struct clk * to find IDLEST info for |
| 167 | * @idlest_reg: void __iomem ** to return the CM_IDLEST va in |
Ranjith Lohithakshan | 419cc97 | 2010-02-24 12:05:54 -0700 | [diff] [blame] | 168 | * @idlest_bit: u8 * to return the CM_IDLEST bit shift in |
| 169 | * @idlest_val: u8 * to return the idle status indicator |
Paul Walmsley | 72350b2 | 2009-07-24 19:44:03 -0600 | [diff] [blame] | 170 | * |
| 171 | * Return the CM_IDLEST register address and bit shift corresponding |
| 172 | * to the module that "owns" this clock. This default code assumes |
| 173 | * that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that |
| 174 | * the IDLEST register address ID corresponds to the CM_*CLKEN |
| 175 | * register address ID (e.g., that CM_FCLKEN2 corresponds to |
| 176 | * CM_IDLEST2). This is not true for all modules. No return value. |
| 177 | */ |
| 178 | void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, |
Ranjith Lohithakshan | 419cc97 | 2010-02-24 12:05:54 -0700 | [diff] [blame] | 179 | u8 *idlest_bit, u8 *idlest_val) |
Paul Walmsley | 72350b2 | 2009-07-24 19:44:03 -0600 | [diff] [blame] | 180 | { |
| 181 | u32 r; |
| 182 | |
| 183 | r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); |
| 184 | *idlest_reg = (__force void __iomem *)r; |
| 185 | *idlest_bit = clk->enable_bit; |
Ranjith Lohithakshan | 419cc97 | 2010-02-24 12:05:54 -0700 | [diff] [blame] | 186 | |
| 187 | /* |
| 188 | * 24xx uses 0 to indicate not ready, and 1 to indicate ready. |
| 189 | * 34xx reverses this, just to keep us on our toes |
| 190 | * AM35xx uses both, depending on the module. |
| 191 | */ |
| 192 | if (cpu_is_omap24xx()) |
| 193 | *idlest_val = OMAP24XX_CM_IDLEST_VAL; |
| 194 | else if (cpu_is_omap34xx()) |
| 195 | *idlest_val = OMAP34XX_CM_IDLEST_VAL; |
| 196 | else |
| 197 | BUG(); |
| 198 | |
Paul Walmsley | 72350b2 | 2009-07-24 19:44:03 -0600 | [diff] [blame] | 199 | } |
| 200 | |
Paul Walmsley | 72350b2 | 2009-07-24 19:44:03 -0600 | [diff] [blame] | 201 | int omap2_dflt_clk_enable(struct clk *clk) |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 202 | { |
Paul Walmsley | ee1eec3 | 2009-01-28 12:18:19 -0700 | [diff] [blame] | 203 | u32 v; |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 204 | |
Russell King | c0fc18c5 | 2008-09-05 15:10:27 +0100 | [diff] [blame] | 205 | if (unlikely(clk->enable_reg == NULL)) { |
Paul Walmsley | 72350b2 | 2009-07-24 19:44:03 -0600 | [diff] [blame] | 206 | pr_err("clock.c: Enable for %s without enable code\n", |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 207 | clk->name); |
| 208 | return 0; /* REVISIT: -EINVAL */ |
| 209 | } |
| 210 | |
Paul Walmsley | ee1eec3 | 2009-01-28 12:18:19 -0700 | [diff] [blame] | 211 | v = __raw_readl(clk->enable_reg); |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 212 | if (clk->flags & INVERT_ENABLE) |
Paul Walmsley | ee1eec3 | 2009-01-28 12:18:19 -0700 | [diff] [blame] | 213 | v &= ~(1 << clk->enable_bit); |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 214 | else |
Paul Walmsley | ee1eec3 | 2009-01-28 12:18:19 -0700 | [diff] [blame] | 215 | v |= (1 << clk->enable_bit); |
| 216 | __raw_writel(v, clk->enable_reg); |
Paul Walmsley | f11fda6 | 2009-01-28 12:35:06 -0700 | [diff] [blame] | 217 | v = __raw_readl(clk->enable_reg); /* OCP barrier */ |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 218 | |
Paul Walmsley | 72350b2 | 2009-07-24 19:44:03 -0600 | [diff] [blame] | 219 | if (clk->ops->find_idlest) |
Paul Walmsley | 4b1f76e | 2010-01-26 20:13:04 -0700 | [diff] [blame] | 220 | _omap2_module_wait_ready(clk); |
Paul Walmsley | 72350b2 | 2009-07-24 19:44:03 -0600 | [diff] [blame] | 221 | |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 222 | return 0; |
| 223 | } |
| 224 | |
Paul Walmsley | 72350b2 | 2009-07-24 19:44:03 -0600 | [diff] [blame] | 225 | void omap2_dflt_clk_disable(struct clk *clk) |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 226 | { |
Paul Walmsley | ee1eec3 | 2009-01-28 12:18:19 -0700 | [diff] [blame] | 227 | u32 v; |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 228 | |
Paul Walmsley | fecb494 | 2009-01-27 19:12:50 -0700 | [diff] [blame] | 229 | if (!clk->enable_reg) { |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 230 | /* |
| 231 | * 'Independent' here refers to a clock which is not |
| 232 | * controlled by its parent. |
| 233 | */ |
Paul Walmsley | 7852ec0 | 2012-07-26 00:54:26 -0600 | [diff] [blame] | 234 | pr_err("clock: clk_disable called on independent clock %s which has no enable_reg\n", clk->name); |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 235 | return; |
| 236 | } |
| 237 | |
Paul Walmsley | ee1eec3 | 2009-01-28 12:18:19 -0700 | [diff] [blame] | 238 | v = __raw_readl(clk->enable_reg); |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 239 | if (clk->flags & INVERT_ENABLE) |
Paul Walmsley | ee1eec3 | 2009-01-28 12:18:19 -0700 | [diff] [blame] | 240 | v |= (1 << clk->enable_bit); |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 241 | else |
Paul Walmsley | ee1eec3 | 2009-01-28 12:18:19 -0700 | [diff] [blame] | 242 | v &= ~(1 << clk->enable_bit); |
| 243 | __raw_writel(v, clk->enable_reg); |
Paul Walmsley | de07fed | 2009-01-28 12:35:01 -0700 | [diff] [blame] | 244 | /* No OCP barrier needed here since it is a disable operation */ |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 245 | } |
| 246 | |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 247 | const struct clkops clkops_omap2_dflt_wait = { |
Paul Walmsley | 72350b2 | 2009-07-24 19:44:03 -0600 | [diff] [blame] | 248 | .enable = omap2_dflt_clk_enable, |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 249 | .disable = omap2_dflt_clk_disable, |
Paul Walmsley | 72350b2 | 2009-07-24 19:44:03 -0600 | [diff] [blame] | 250 | .find_companion = omap2_clk_dflt_find_companion, |
| 251 | .find_idlest = omap2_clk_dflt_find_idlest, |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 252 | }; |
| 253 | |
Russell King | bc51da4 | 2008-11-04 18:59:32 +0000 | [diff] [blame] | 254 | const struct clkops clkops_omap2_dflt = { |
| 255 | .enable = omap2_dflt_clk_enable, |
| 256 | .disable = omap2_dflt_clk_disable, |
| 257 | }; |
| 258 | |
Paul Walmsley | 30962d9 | 2010-02-22 22:09:38 -0700 | [diff] [blame] | 259 | /** |
| 260 | * omap2_clk_disable - disable a clock, if the system is not using it |
| 261 | * @clk: struct clk * to disable |
| 262 | * |
| 263 | * Decrements the usecount on struct clk @clk. If there are no users |
| 264 | * left, call the clkops-specific clock disable function to disable it |
| 265 | * in hardware. If the clock is part of a clockdomain (which they all |
| 266 | * should be), request that the clockdomain be disabled. (It too has |
| 267 | * a usecount, and so will not be disabled in the hardware until it no |
| 268 | * longer has any users.) If the clock has a parent clock (most of |
| 269 | * them do), then call ourselves, recursing on the parent clock. This |
| 270 | * can cause an entire branch of the clock tree to be powered off by |
| 271 | * simply disabling one clock. Intended to be called with the clockfw_lock |
| 272 | * spinlock held. No return value. |
| 273 | */ |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 274 | void omap2_clk_disable(struct clk *clk) |
| 275 | { |
Paul Walmsley | 30962d9 | 2010-02-22 22:09:38 -0700 | [diff] [blame] | 276 | if (clk->usecount == 0) { |
Paul Walmsley | 7852ec0 | 2012-07-26 00:54:26 -0600 | [diff] [blame] | 277 | WARN(1, "clock: %s: omap2_clk_disable() called, but usecount already 0?", clk->name); |
Paul Walmsley | 30962d9 | 2010-02-22 22:09:38 -0700 | [diff] [blame] | 278 | return; |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 279 | } |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 280 | |
Paul Walmsley | 30962d9 | 2010-02-22 22:09:38 -0700 | [diff] [blame] | 281 | pr_debug("clock: %s: decrementing usecount\n", clk->name); |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 282 | |
Paul Walmsley | 30962d9 | 2010-02-22 22:09:38 -0700 | [diff] [blame] | 283 | clk->usecount--; |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 284 | |
Paul Walmsley | 30962d9 | 2010-02-22 22:09:38 -0700 | [diff] [blame] | 285 | if (clk->usecount > 0) |
| 286 | return; |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 287 | |
Paul Walmsley | 30962d9 | 2010-02-22 22:09:38 -0700 | [diff] [blame] | 288 | pr_debug("clock: %s: disabling in hardware\n", clk->name); |
Russell King | a7f8c59 | 2009-01-31 11:00:17 +0000 | [diff] [blame] | 289 | |
Jean Pihet | 5e7c58d | 2011-03-03 11:25:43 +0100 | [diff] [blame] | 290 | if (clk->ops && clk->ops->disable) { |
| 291 | trace_clock_disable(clk->name, 0, smp_processor_id()); |
Rajendra Nayak | 6c52f32 | 2011-02-25 15:48:36 -0700 | [diff] [blame] | 292 | clk->ops->disable(clk); |
Jean Pihet | 5e7c58d | 2011-03-03 11:25:43 +0100 | [diff] [blame] | 293 | } |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 294 | |
Paul Walmsley | 12706c5 | 2011-07-10 05:57:06 -0600 | [diff] [blame] | 295 | if (clkdm_control && clk->clkdm) |
Rajendra Nayak | 4da71ae | 2011-02-25 16:06:48 -0700 | [diff] [blame] | 296 | clkdm_clk_disable(clk->clkdm, clk); |
Paul Walmsley | 30962d9 | 2010-02-22 22:09:38 -0700 | [diff] [blame] | 297 | |
| 298 | if (clk->parent) |
| 299 | omap2_clk_disable(clk->parent); |
| 300 | } |
| 301 | |
| 302 | /** |
| 303 | * omap2_clk_enable - request that the system enable a clock |
| 304 | * @clk: struct clk * to enable |
| 305 | * |
| 306 | * Increments the usecount on struct clk @clk. If there were no users |
| 307 | * previously, then recurse up the clock tree, enabling all of the |
| 308 | * clock's parents and all of the parent clockdomains, and finally, |
| 309 | * enabling @clk's clockdomain, and @clk itself. Intended to be |
| 310 | * called with the clockfw_lock spinlock held. Returns 0 upon success |
| 311 | * or a negative error code upon failure. |
| 312 | */ |
| 313 | int omap2_clk_enable(struct clk *clk) |
| 314 | { |
| 315 | int ret; |
| 316 | |
| 317 | pr_debug("clock: %s: incrementing usecount\n", clk->name); |
| 318 | |
| 319 | clk->usecount++; |
| 320 | |
| 321 | if (clk->usecount > 1) |
| 322 | return 0; |
| 323 | |
| 324 | pr_debug("clock: %s: enabling in hardware\n", clk->name); |
| 325 | |
| 326 | if (clk->parent) { |
| 327 | ret = omap2_clk_enable(clk->parent); |
| 328 | if (ret) { |
| 329 | WARN(1, "clock: %s: could not enable parent %s: %d\n", |
| 330 | clk->name, clk->parent->name, ret); |
| 331 | goto oce_err1; |
| 332 | } |
| 333 | } |
| 334 | |
Paul Walmsley | 12706c5 | 2011-07-10 05:57:06 -0600 | [diff] [blame] | 335 | if (clkdm_control && clk->clkdm) { |
Rajendra Nayak | 4da71ae | 2011-02-25 16:06:48 -0700 | [diff] [blame] | 336 | ret = clkdm_clk_enable(clk->clkdm, clk); |
Paul Walmsley | 30962d9 | 2010-02-22 22:09:38 -0700 | [diff] [blame] | 337 | if (ret) { |
Paul Walmsley | 7852ec0 | 2012-07-26 00:54:26 -0600 | [diff] [blame] | 338 | WARN(1, "clock: %s: could not enable clockdomain %s: %d\n", |
| 339 | clk->name, clk->clkdm->name, ret); |
Paul Walmsley | 30962d9 | 2010-02-22 22:09:38 -0700 | [diff] [blame] | 340 | goto oce_err2; |
| 341 | } |
| 342 | } |
| 343 | |
Rajendra Nayak | 6c52f32 | 2011-02-25 15:48:36 -0700 | [diff] [blame] | 344 | if (clk->ops && clk->ops->enable) { |
Jean Pihet | 5e7c58d | 2011-03-03 11:25:43 +0100 | [diff] [blame] | 345 | trace_clock_enable(clk->name, 1, smp_processor_id()); |
Rajendra Nayak | 6c52f32 | 2011-02-25 15:48:36 -0700 | [diff] [blame] | 346 | ret = clk->ops->enable(clk); |
| 347 | if (ret) { |
| 348 | WARN(1, "clock: %s: could not enable: %d\n", |
| 349 | clk->name, ret); |
| 350 | goto oce_err3; |
| 351 | } |
Paul Walmsley | 30962d9 | 2010-02-22 22:09:38 -0700 | [diff] [blame] | 352 | } |
| 353 | |
| 354 | return 0; |
| 355 | |
| 356 | oce_err3: |
Paul Walmsley | 12706c5 | 2011-07-10 05:57:06 -0600 | [diff] [blame] | 357 | if (clkdm_control && clk->clkdm) |
Rajendra Nayak | 4da71ae | 2011-02-25 16:06:48 -0700 | [diff] [blame] | 358 | clkdm_clk_disable(clk->clkdm, clk); |
Paul Walmsley | 30962d9 | 2010-02-22 22:09:38 -0700 | [diff] [blame] | 359 | oce_err2: |
| 360 | if (clk->parent) |
| 361 | omap2_clk_disable(clk->parent); |
| 362 | oce_err1: |
Russell King | a7f8c59 | 2009-01-31 11:00:17 +0000 | [diff] [blame] | 363 | clk->usecount--; |
Paul Walmsley | 30962d9 | 2010-02-22 22:09:38 -0700 | [diff] [blame] | 364 | |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 365 | return ret; |
| 366 | } |
| 367 | |
Paul Walmsley | 435699d | 2010-05-18 18:40:24 -0600 | [diff] [blame] | 368 | /* Given a clock and a rate apply a clock specific rounding function */ |
| 369 | long omap2_clk_round_rate(struct clk *clk, unsigned long rate) |
| 370 | { |
| 371 | if (clk->round_rate) |
| 372 | return clk->round_rate(clk, rate); |
| 373 | |
| 374 | return clk->rate; |
| 375 | } |
| 376 | |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 377 | /* Set the clock rate for a clock source */ |
| 378 | int omap2_clk_set_rate(struct clk *clk, unsigned long rate) |
| 379 | { |
| 380 | int ret = -EINVAL; |
| 381 | |
| 382 | pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate); |
| 383 | |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 384 | /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */ |
Jean Pihet | 5e7c58d | 2011-03-03 11:25:43 +0100 | [diff] [blame] | 385 | if (clk->set_rate) { |
| 386 | trace_clock_set_rate(clk->name, rate, smp_processor_id()); |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 387 | ret = clk->set_rate(clk, rate); |
Jean Pihet | 5e7c58d | 2011-03-03 11:25:43 +0100 | [diff] [blame] | 388 | } |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 389 | |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 390 | return ret; |
| 391 | } |
| 392 | |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 393 | int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) |
| 394 | { |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 395 | if (!clk->clksel) |
| 396 | return -EINVAL; |
| 397 | |
Paul Walmsley | 1a33771 | 2010-02-22 22:09:16 -0700 | [diff] [blame] | 398 | if (clk->parent == new_parent) |
| 399 | return 0; |
| 400 | |
Paul Walmsley | df791b3 | 2010-01-26 20:13:04 -0700 | [diff] [blame] | 401 | return omap2_clksel_set_parent(clk, new_parent); |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 402 | } |
| 403 | |
Paul Walmsley | 30962d9 | 2010-02-22 22:09:38 -0700 | [diff] [blame] | 404 | /* |
| 405 | * OMAP2+ clock reset and init functions |
| 406 | */ |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 407 | |
| 408 | #ifdef CONFIG_OMAP_RESET_CLOCKS |
| 409 | void omap2_clk_disable_unused(struct clk *clk) |
| 410 | { |
| 411 | u32 regval32, v; |
| 412 | |
| 413 | v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0; |
| 414 | |
| 415 | regval32 = __raw_readl(clk->enable_reg); |
| 416 | if ((regval32 & (1 << clk->enable_bit)) == v) |
| 417 | return; |
| 418 | |
Paul Walmsley | 6041c27 | 2010-10-08 11:40:20 -0600 | [diff] [blame] | 419 | pr_debug("Disabling unused clock \"%s\"\n", clk->name); |
Tero Kristo | 8463e20 | 2009-01-28 12:27:45 -0700 | [diff] [blame] | 420 | if (cpu_is_omap34xx()) { |
| 421 | omap2_clk_enable(clk); |
| 422 | omap2_clk_disable(clk); |
Paul Walmsley | 30962d9 | 2010-02-22 22:09:38 -0700 | [diff] [blame] | 423 | } else { |
| 424 | clk->ops->disable(clk); |
| 425 | } |
Peter 'p2' De Schrijver | fe617af | 2008-10-15 17:48:44 +0300 | [diff] [blame] | 426 | if (clk->clkdm != NULL) |
Santosh Shilimkar | 5a68a73 | 2012-05-07 23:55:38 -0600 | [diff] [blame] | 427 | pwrdm_state_switch(clk->clkdm->pwrdm.ptr); |
Paul Walmsley | 543d937 | 2008-03-18 10:22:06 +0200 | [diff] [blame] | 428 | } |
| 429 | #endif |
Paul Walmsley | 69ecefc | 2010-01-26 20:13:04 -0700 | [diff] [blame] | 430 | |
Paul Walmsley | 4d30e82 | 2010-02-22 22:09:36 -0700 | [diff] [blame] | 431 | /** |
| 432 | * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument |
| 433 | * @mpurate_ck_name: clk name of the clock to change rate |
| 434 | * |
| 435 | * Change the ARM MPU clock rate to the rate specified on the command |
| 436 | * line, if one was specified. @mpurate_ck_name should be |
| 437 | * "virt_prcm_set" on OMAP2xxx and "dpll1_ck" on OMAP34xx/OMAP36xx. |
| 438 | * XXX Does not handle voltage scaling - on OMAP2xxx this is currently |
| 439 | * handled by the virt_prcm_set clock, but this should be handled by |
| 440 | * the OPP layer. XXX This is intended to be handled by the OPP layer |
| 441 | * code in the near future and should be removed from the clock code. |
| 442 | * Returns -EINVAL if 'mpurate' is zero or if clk_set_rate() rejects |
| 443 | * the rate, -ENOENT if the struct clk referred to by @mpurate_ck_name |
| 444 | * cannot be found, or 0 upon success. |
| 445 | */ |
| 446 | int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name) |
| 447 | { |
| 448 | struct clk *mpurate_ck; |
| 449 | int r; |
| 450 | |
| 451 | if (!mpurate) |
| 452 | return -EINVAL; |
| 453 | |
| 454 | mpurate_ck = clk_get(NULL, mpurate_ck_name); |
| 455 | if (WARN(IS_ERR(mpurate_ck), "Failed to get %s.\n", mpurate_ck_name)) |
| 456 | return -ENOENT; |
| 457 | |
| 458 | r = clk_set_rate(mpurate_ck, mpurate); |
| 459 | if (IS_ERR_VALUE(r)) { |
| 460 | WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n", |
| 461 | mpurate_ck->name, mpurate, r); |
Julia Lawall | f6281f6 | 2011-07-04 04:08:10 -0700 | [diff] [blame] | 462 | clk_put(mpurate_ck); |
Paul Walmsley | 4d30e82 | 2010-02-22 22:09:36 -0700 | [diff] [blame] | 463 | return -EINVAL; |
| 464 | } |
| 465 | |
| 466 | calibrate_delay(); |
| 467 | recalculate_root_clocks(); |
| 468 | |
| 469 | clk_put(mpurate_ck); |
| 470 | |
| 471 | return 0; |
| 472 | } |
| 473 | |
| 474 | /** |
| 475 | * omap2_clk_print_new_rates - print summary of current clock tree rates |
| 476 | * @hfclkin_ck_name: clk name for the off-chip HF oscillator |
| 477 | * @core_ck_name: clk name for the on-chip CORE_CLK |
| 478 | * @mpu_ck_name: clk name for the ARM MPU clock |
| 479 | * |
| 480 | * Prints a short message to the console with the HFCLKIN oscillator |
| 481 | * rate, the rate of the CORE clock, and the rate of the ARM MPU clock. |
| 482 | * Called by the boot-time MPU rate switching code. XXX This is intended |
| 483 | * to be handled by the OPP layer code in the near future and should be |
| 484 | * removed from the clock code. No return value. |
| 485 | */ |
| 486 | void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name, |
| 487 | const char *core_ck_name, |
| 488 | const char *mpu_ck_name) |
| 489 | { |
| 490 | struct clk *hfclkin_ck, *core_ck, *mpu_ck; |
| 491 | unsigned long hfclkin_rate; |
| 492 | |
| 493 | mpu_ck = clk_get(NULL, mpu_ck_name); |
| 494 | if (WARN(IS_ERR(mpu_ck), "clock: failed to get %s.\n", mpu_ck_name)) |
| 495 | return; |
| 496 | |
| 497 | core_ck = clk_get(NULL, core_ck_name); |
| 498 | if (WARN(IS_ERR(core_ck), "clock: failed to get %s.\n", core_ck_name)) |
| 499 | return; |
| 500 | |
| 501 | hfclkin_ck = clk_get(NULL, hfclkin_ck_name); |
| 502 | if (WARN(IS_ERR(hfclkin_ck), "Failed to get %s.\n", hfclkin_ck_name)) |
| 503 | return; |
| 504 | |
| 505 | hfclkin_rate = clk_get_rate(hfclkin_ck); |
| 506 | |
Paul Walmsley | 7852ec0 | 2012-07-26 00:54:26 -0600 | [diff] [blame] | 507 | pr_info("Switched to new clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", |
| 508 | (hfclkin_rate / 1000000), ((hfclkin_rate / 100000) % 10), |
Paul Walmsley | 4d30e82 | 2010-02-22 22:09:36 -0700 | [diff] [blame] | 509 | (clk_get_rate(core_ck) / 1000000), |
| 510 | (clk_get_rate(mpu_ck) / 1000000)); |
| 511 | } |
| 512 | |
Paul Walmsley | 69ecefc | 2010-01-26 20:13:04 -0700 | [diff] [blame] | 513 | /* Common data */ |
| 514 | |
| 515 | struct clk_functions omap2_clk_functions = { |
| 516 | .clk_enable = omap2_clk_enable, |
| 517 | .clk_disable = omap2_clk_disable, |
| 518 | .clk_round_rate = omap2_clk_round_rate, |
| 519 | .clk_set_rate = omap2_clk_set_rate, |
| 520 | .clk_set_parent = omap2_clk_set_parent, |
| 521 | .clk_disable_unused = omap2_clk_disable_unused, |
Paul Walmsley | 69ecefc | 2010-01-26 20:13:04 -0700 | [diff] [blame] | 522 | }; |
| 523 | |