Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 1 | /* |
| 2 | * OMAP4 Power Management Routines |
| 3 | * |
Santosh Shilimkar | e44f9a7 | 2010-06-16 22:19:49 +0530 | [diff] [blame] | 4 | * Copyright (C) 2010-2011 Texas Instruments, Inc. |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 5 | * Rajendra Nayak <rnayak@ti.com> |
Santosh Shilimkar | e44f9a7 | 2010-06-16 22:19:49 +0530 | [diff] [blame] | 6 | * Santosh Shilimkar <santosh.shilimkar@ti.com> |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/pm.h> |
| 14 | #include <linux/suspend.h> |
| 15 | #include <linux/module.h> |
| 16 | #include <linux/list.h> |
| 17 | #include <linux/err.h> |
| 18 | #include <linux/slab.h> |
David Howells | 9f97da7 | 2012-03-28 18:30:01 +0100 | [diff] [blame] | 19 | #include <asm/system_misc.h> |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 20 | |
Tony Lindgren | 4e65331 | 2011-11-10 22:45:17 +0100 | [diff] [blame] | 21 | #include "common.h" |
Santosh Shilimkar | 3c50729 | 2011-01-05 22:03:17 +0530 | [diff] [blame] | 22 | #include "clockdomain.h" |
Paul Walmsley | 72e06d0 | 2010-12-21 21:05:16 -0700 | [diff] [blame] | 23 | #include "powerdomain.h" |
Santosh Shilimkar | e44f9a7 | 2010-06-16 22:19:49 +0530 | [diff] [blame] | 24 | #include "pm.h" |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 25 | |
| 26 | struct power_state { |
| 27 | struct powerdomain *pwrdm; |
| 28 | u32 next_state; |
| 29 | #ifdef CONFIG_SUSPEND |
| 30 | u32 saved_state; |
Santosh Shilimkar | 3ba2a73 | 2011-06-06 14:33:29 +0530 | [diff] [blame] | 31 | u32 saved_logic_state; |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 32 | #endif |
| 33 | struct list_head node; |
| 34 | }; |
| 35 | |
| 36 | static LIST_HEAD(pwrst_list); |
| 37 | |
| 38 | #ifdef CONFIG_SUSPEND |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 39 | static int omap4_pm_suspend(void) |
| 40 | { |
Santosh Shilimkar | e44f9a7 | 2010-06-16 22:19:49 +0530 | [diff] [blame] | 41 | struct power_state *pwrst; |
| 42 | int state, ret = 0; |
| 43 | u32 cpu_id = smp_processor_id(); |
| 44 | |
| 45 | /* Save current powerdomain state */ |
| 46 | list_for_each_entry(pwrst, &pwrst_list, node) { |
| 47 | pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); |
Santosh Shilimkar | 3ba2a73 | 2011-06-06 14:33:29 +0530 | [diff] [blame] | 48 | pwrst->saved_logic_state = pwrdm_read_logic_retst(pwrst->pwrdm); |
Santosh Shilimkar | e44f9a7 | 2010-06-16 22:19:49 +0530 | [diff] [blame] | 49 | } |
| 50 | |
| 51 | /* Set targeted power domain states by suspend */ |
| 52 | list_for_each_entry(pwrst, &pwrst_list, node) { |
| 53 | omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); |
Santosh Shilimkar | 3ba2a73 | 2011-06-06 14:33:29 +0530 | [diff] [blame] | 54 | pwrdm_set_logic_retst(pwrst->pwrdm, PWRDM_POWER_OFF); |
Santosh Shilimkar | e44f9a7 | 2010-06-16 22:19:49 +0530 | [diff] [blame] | 55 | } |
| 56 | |
| 57 | /* |
| 58 | * For MPUSS to hit power domain retention(CSWR or OSWR), |
| 59 | * CPU0 and CPU1 power domains need to be in OFF or DORMANT state, |
| 60 | * since CPU power domain CSWR is not supported by hardware |
| 61 | * Only master CPU follows suspend path. All other CPUs follow |
| 62 | * CPU hotplug path in system wide suspend. On OMAP4, CPU power |
| 63 | * domain CSWR is not supported by hardware. |
| 64 | * More details can be found in OMAP4430 TRM section 4.3.4.2. |
| 65 | */ |
| 66 | omap4_enter_lowpower(cpu_id, PWRDM_POWER_OFF); |
| 67 | |
| 68 | /* Restore next powerdomain state */ |
| 69 | list_for_each_entry(pwrst, &pwrst_list, node) { |
| 70 | state = pwrdm_read_prev_pwrst(pwrst->pwrdm); |
| 71 | if (state > pwrst->next_state) { |
Paul Walmsley | 7852ec0 | 2012-07-26 00:54:26 -0600 | [diff] [blame] | 72 | pr_info("Powerdomain (%s) didn't enter target state %d\n", |
| 73 | pwrst->pwrdm->name, pwrst->next_state); |
Santosh Shilimkar | e44f9a7 | 2010-06-16 22:19:49 +0530 | [diff] [blame] | 74 | ret = -1; |
| 75 | } |
| 76 | omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); |
Santosh Shilimkar | 3ba2a73 | 2011-06-06 14:33:29 +0530 | [diff] [blame] | 77 | pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->saved_logic_state); |
Santosh Shilimkar | e44f9a7 | 2010-06-16 22:19:49 +0530 | [diff] [blame] | 78 | } |
| 79 | if (ret) |
| 80 | pr_crit("Could not enter target state in pm_suspend\n"); |
| 81 | else |
| 82 | pr_info("Successfully put all powerdomains to target state\n"); |
| 83 | |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 84 | return 0; |
| 85 | } |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 86 | #endif /* CONFIG_SUSPEND */ |
| 87 | |
| 88 | static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) |
| 89 | { |
| 90 | struct power_state *pwrst; |
| 91 | |
| 92 | if (!pwrdm->pwrsts) |
| 93 | return 0; |
| 94 | |
Santosh Shilimkar | e44f9a7 | 2010-06-16 22:19:49 +0530 | [diff] [blame] | 95 | /* |
| 96 | * Skip CPU0 and CPU1 power domains. CPU1 is programmed |
| 97 | * through hotplug path and CPU0 explicitly programmed |
| 98 | * further down in the code path |
| 99 | */ |
| 100 | if (!strncmp(pwrdm->name, "cpu", 3)) |
| 101 | return 0; |
| 102 | |
| 103 | /* |
| 104 | * FIXME: Remove this check when core retention is supported |
| 105 | * Only MPUSS power domain is added in the list. |
| 106 | */ |
| 107 | if (strcmp(pwrdm->name, "mpu_pwrdm")) |
| 108 | return 0; |
| 109 | |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 110 | pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); |
| 111 | if (!pwrst) |
| 112 | return -ENOMEM; |
Santosh Shilimkar | e44f9a7 | 2010-06-16 22:19:49 +0530 | [diff] [blame] | 113 | |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 114 | pwrst->pwrdm = pwrdm; |
Santosh Shilimkar | e44f9a7 | 2010-06-16 22:19:49 +0530 | [diff] [blame] | 115 | pwrst->next_state = PWRDM_POWER_RET; |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 116 | list_add(&pwrst->node, &pwrst_list); |
| 117 | |
Santosh Shilimkar | e44f9a7 | 2010-06-16 22:19:49 +0530 | [diff] [blame] | 118 | return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 119 | } |
| 120 | |
| 121 | /** |
Santosh Shilimkar | 72826b9 | 2011-07-18 12:25:10 +0530 | [diff] [blame] | 122 | * omap_default_idle - OMAP4 default ilde routine.' |
| 123 | * |
| 124 | * Implements OMAP4 memory, IO ordering requirements which can't be addressed |
Nicolas Pitre | ae94091 | 2011-12-19 03:03:58 -0500 | [diff] [blame] | 125 | * with default cpu_do_idle() hook. Used by all CPUs with !CONFIG_CPUIDLE and |
Santosh Shilimkar | 72826b9 | 2011-07-18 12:25:10 +0530 | [diff] [blame] | 126 | * by secondary CPU with CONFIG_CPUIDLE. |
| 127 | */ |
| 128 | static void omap_default_idle(void) |
| 129 | { |
Santosh Shilimkar | 72826b9 | 2011-07-18 12:25:10 +0530 | [diff] [blame] | 130 | local_fiq_disable(); |
| 131 | |
| 132 | omap_do_wfi(); |
| 133 | |
| 134 | local_fiq_enable(); |
Santosh Shilimkar | 72826b9 | 2011-07-18 12:25:10 +0530 | [diff] [blame] | 135 | } |
| 136 | |
| 137 | /** |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 138 | * omap4_pm_init - Init routine for OMAP4 PM |
| 139 | * |
| 140 | * Initializes all powerdomain and clockdomain target states |
| 141 | * and all PRCM settings. |
| 142 | */ |
Shawn Guo | bbd707a | 2012-04-26 16:06:50 +0800 | [diff] [blame] | 143 | int __init omap4_pm_init(void) |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 144 | { |
| 145 | int ret; |
Santosh Shilimkar | 68523f4 | 2012-03-12 20:34:45 +0530 | [diff] [blame] | 146 | struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm, *l4wkup; |
Santosh Shilimkar | 12f2782 | 2011-03-08 18:24:30 +0530 | [diff] [blame] | 147 | struct clockdomain *ducati_clkdm, *l3_2_clkdm, *l4_per_clkdm; |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 148 | |
Santosh Shilimkar | 361b02f | 2011-03-11 16:13:09 +0530 | [diff] [blame] | 149 | if (omap_rev() == OMAP4430_REV_ES1_0) { |
| 150 | WARN(1, "Power Management not supported on OMAP4430 ES1.0\n"); |
| 151 | return -ENODEV; |
| 152 | } |
| 153 | |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 154 | pr_err("Power Management for TI OMAP4.\n"); |
| 155 | |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 156 | ret = pwrdm_for_each(pwrdms_setup, NULL); |
| 157 | if (ret) { |
| 158 | pr_err("Failed to setup powerdomains\n"); |
| 159 | goto err2; |
| 160 | } |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 161 | |
Santosh Shilimkar | 12f2782 | 2011-03-08 18:24:30 +0530 | [diff] [blame] | 162 | /* |
| 163 | * The dynamic dependency between MPUSS -> MEMIF and |
| 164 | * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as |
| 165 | * expected. The hardware recommendation is to enable static |
| 166 | * dependencies for these to avoid system lock ups or random crashes. |
Santosh Shilimkar | 68523f4 | 2012-03-12 20:34:45 +0530 | [diff] [blame] | 167 | * The L4 wakeup depedency is added to workaround the OCP sync hardware |
| 168 | * BUG with 32K synctimer which lead to incorrect timer value read |
| 169 | * from the 32K counter. The BUG applies for GPTIMER1 and WDT2 which |
| 170 | * are part of L4 wakeup clockdomain. |
Santosh Shilimkar | 12f2782 | 2011-03-08 18:24:30 +0530 | [diff] [blame] | 171 | */ |
| 172 | mpuss_clkdm = clkdm_lookup("mpuss_clkdm"); |
| 173 | emif_clkdm = clkdm_lookup("l3_emif_clkdm"); |
| 174 | l3_1_clkdm = clkdm_lookup("l3_1_clkdm"); |
| 175 | l3_2_clkdm = clkdm_lookup("l3_2_clkdm"); |
| 176 | l4_per_clkdm = clkdm_lookup("l4_per_clkdm"); |
Santosh Shilimkar | 68523f4 | 2012-03-12 20:34:45 +0530 | [diff] [blame] | 177 | l4wkup = clkdm_lookup("l4_wkup_clkdm"); |
Santosh Shilimkar | 12f2782 | 2011-03-08 18:24:30 +0530 | [diff] [blame] | 178 | ducati_clkdm = clkdm_lookup("ducati_clkdm"); |
Santosh Shilimkar | 68523f4 | 2012-03-12 20:34:45 +0530 | [diff] [blame] | 179 | if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) || (!l4wkup) || |
Santosh Shilimkar | 12f2782 | 2011-03-08 18:24:30 +0530 | [diff] [blame] | 180 | (!l3_2_clkdm) || (!ducati_clkdm) || (!l4_per_clkdm)) |
| 181 | goto err2; |
| 182 | |
| 183 | ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm); |
| 184 | ret |= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm); |
| 185 | ret |= clkdm_add_wkdep(mpuss_clkdm, l3_2_clkdm); |
| 186 | ret |= clkdm_add_wkdep(mpuss_clkdm, l4_per_clkdm); |
Santosh Shilimkar | 68523f4 | 2012-03-12 20:34:45 +0530 | [diff] [blame] | 187 | ret |= clkdm_add_wkdep(mpuss_clkdm, l4wkup); |
Santosh Shilimkar | 12f2782 | 2011-03-08 18:24:30 +0530 | [diff] [blame] | 188 | ret |= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm); |
| 189 | ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm); |
| 190 | if (ret) { |
Paul Walmsley | 7852ec0 | 2012-07-26 00:54:26 -0600 | [diff] [blame] | 191 | pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 wakeup dependency\n"); |
Santosh Shilimkar | 12f2782 | 2011-03-08 18:24:30 +0530 | [diff] [blame] | 192 | goto err2; |
| 193 | } |
| 194 | |
Santosh Shilimkar | b2b9762 | 2010-06-16 22:19:48 +0530 | [diff] [blame] | 195 | ret = omap4_mpuss_init(); |
| 196 | if (ret) { |
| 197 | pr_err("Failed to initialise OMAP4 MPUSS\n"); |
| 198 | goto err2; |
| 199 | } |
| 200 | |
Paul Walmsley | 92206fd | 2012-02-02 02:38:50 -0700 | [diff] [blame] | 201 | (void) clkdm_for_each(omap_pm_clkdms_setup, NULL); |
Santosh Shilimkar | 3c50729 | 2011-01-05 22:03:17 +0530 | [diff] [blame] | 202 | |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 203 | #ifdef CONFIG_SUSPEND |
Paul Walmsley | 1416408 | 2012-02-02 02:30:50 -0700 | [diff] [blame] | 204 | omap_pm_suspend = omap4_pm_suspend; |
| 205 | #endif |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 206 | |
Nicolas Pitre | ae94091 | 2011-12-19 03:03:58 -0500 | [diff] [blame] | 207 | /* Overwrite the default cpu_do_idle() */ |
Nicolas Pitre | 0bcd24b | 2012-01-04 16:27:48 -0500 | [diff] [blame] | 208 | arm_pm_idle = omap_default_idle; |
Santosh Shilimkar | 72826b9 | 2011-07-18 12:25:10 +0530 | [diff] [blame] | 209 | |
Santosh Shilimkar | 9827266 | 2011-08-16 17:31:40 +0530 | [diff] [blame] | 210 | omap4_idle_init(); |
| 211 | |
Rajendra Nayak | 5643aeb | 2010-08-02 13:18:18 +0300 | [diff] [blame] | 212 | err2: |
| 213 | return ret; |
| 214 | } |