blob: 382c60e9aa1606fa980fb6c88e1aadd286e8210f [file] [log] [blame]
John Linnb85a3ef2011-06-20 11:47:27 -06001/*
2 * This file contains common function prototypes to avoid externs
3 * in the c files.
4 *
5 * Copyright (C) 2011 Xilinx
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#ifndef __MACH_ZYNQ_COMMON_H__
18#define __MACH_ZYNQ_COMMON_H__
19
Soren Brinkmann6a37ff382013-10-31 09:10:15 -070020void zynq_secondary_startup(void);
21
Michal Simek64b889b2013-03-27 12:37:53 +010022extern int zynq_slcr_init(void);
Michal Simek016f4dc2013-11-26 15:41:31 +010023extern int zynq_early_slcr_init(void);
Michal Simek96790f02013-03-20 11:42:15 +010024extern void zynq_slcr_system_reset(void);
Michal Simekaa7eb2b2013-03-20 13:50:12 +010025extern void zynq_slcr_cpu_stop(int cpu);
26extern void zynq_slcr_cpu_start(int cpu);
Soren Brinkmann50c79602014-09-02 14:19:12 -070027extern bool zynq_slcr_cpu_state_read(int cpu);
28extern void zynq_slcr_cpu_state_write(int cpu, bool die);
Michal Simek00f7dc62013-07-31 09:19:59 +020029extern u32 zynq_slcr_get_device_id(void);
Michal Simekaa7eb2b2013-03-20 13:50:12 +010030
31#ifdef CONFIG_SMP
Michal Simekaa7eb2b2013-03-20 13:50:12 +010032extern char zynq_secondary_trampoline;
33extern char zynq_secondary_trampoline_jump;
34extern char zynq_secondary_trampoline_end;
Paul Gortmaker8bd26e32013-06-17 15:43:14 -040035extern int zynq_cpun_start(u32 address, int cpu);
Michal Simekaa7eb2b2013-03-20 13:50:12 +010036extern struct smp_operations zynq_smp_ops __initdata;
37#endif
Michal Simek64b889b2013-03-27 12:37:53 +010038
Michal Simek732078c2013-03-20 11:11:43 +010039extern void __iomem *zynq_scu_base;
40
Soren Brinkmann0beb2bd2014-09-02 14:19:09 -070041void zynq_pm_late_init(void);
42
Soren Brinkmannae88b852014-09-02 14:19:06 -070043static inline void zynq_core_pm_init(void)
44{
45 /* A9 clock gating */
46 asm volatile ("mrc p15, 0, r12, c15, c0, 0\n"
47 "orr r12, r12, #1\n"
48 "mcr p15, 0, r12, c15, c0, 0\n"
49 : /* no outputs */
50 : /* no inputs */
51 : "r12");
52}
53
John Linnb85a3ef2011-06-20 11:47:27 -060054#endif