Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the "Software"), |
| 7 | * to deal in the Software without restriction, including without limitation |
| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
| 10 | * Software is furnished to do so, subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice shall be included in |
| 13 | * all copies or substantial portions of the Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 21 | * OTHER DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: Dave Airlie |
| 24 | * Alex Deucher |
| 25 | */ |
| 26 | #include "drmP.h" |
| 27 | #include "radeon_drm.h" |
| 28 | #include "radeon.h" |
| 29 | |
| 30 | #include "atom.h" |
| 31 | #include "atom-bits.h" |
| 32 | #include "drm_dp_helper.h" |
| 33 | |
| 34 | #define DP_LINK_STATUS_SIZE 6 |
| 35 | |
Alex Deucher | f92a8b6 | 2009-11-23 18:40:40 -0500 | [diff] [blame^] | 36 | /* move these to drm_dp_helper.c/h */ |
| 37 | |
| 38 | static const int dp_clocks[] = { |
| 39 | 54000, // 1 lane, 1.62 Ghz |
| 40 | 90000, // 1 lane, 2.70 Ghz |
| 41 | 108000, // 2 lane, 1.62 Ghz |
| 42 | 180000, // 2 lane, 2.70 Ghz |
| 43 | 216000, // 4 lane, 1.62 Ghz |
| 44 | 360000, // 4 lane, 2.70 Ghz |
| 45 | }; |
| 46 | |
| 47 | static const int num_dp_clocks = sizeof(dp_clocks) / sizeof(int); |
| 48 | |
| 49 | int dp_lanes_for_mode_clock(int max_link_bw, int mode_clock) |
| 50 | { |
| 51 | int i; |
| 52 | |
| 53 | switch (max_link_bw) { |
| 54 | case DP_LINK_BW_1_62: |
| 55 | default: |
| 56 | for (i = 0; i < num_dp_clocks; i++) { |
| 57 | if (i % 2) |
| 58 | continue; |
| 59 | if (dp_clocks[i] > mode_clock) { |
| 60 | if (i < 2) |
| 61 | return 1; |
| 62 | else if (i < 4) |
| 63 | return 2; |
| 64 | else |
| 65 | return 4; |
| 66 | } |
| 67 | } |
| 68 | break; |
| 69 | case DP_LINK_BW_2_7: |
| 70 | for (i = 0; i < num_dp_clocks; i++) { |
| 71 | if (dp_clocks[i] > mode_clock) { |
| 72 | if (i < 2) |
| 73 | return 1; |
| 74 | else if (i < 4) |
| 75 | return 2; |
| 76 | else |
| 77 | return 4; |
| 78 | } |
| 79 | } |
| 80 | break; |
| 81 | } |
| 82 | |
| 83 | return 0; |
| 84 | } |
| 85 | |
| 86 | int dp_link_clock_for_mode_clock(int max_link_bw, int mode_clock) |
| 87 | { |
| 88 | int i; |
| 89 | |
| 90 | switch (max_link_bw) { |
| 91 | case DP_LINK_BW_1_62: |
| 92 | default: |
| 93 | return 162000; |
| 94 | break; |
| 95 | case DP_LINK_BW_2_7: |
| 96 | for (i = 0; i < num_dp_clocks; i++) { |
| 97 | if (dp_clocks[i] > mode_clock) |
| 98 | return (i % 2) ? 270000 : 162000; |
| 99 | } |
| 100 | } |
| 101 | |
| 102 | return 0; |
| 103 | } |
| 104 | |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 105 | bool radeon_process_aux_ch(struct radeon_i2c_chan *chan, u8 *req_bytes, |
Alex Deucher | 1a66c95 | 2009-11-20 19:40:13 -0500 | [diff] [blame] | 106 | int num_bytes, u8 *read_byte, |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 107 | u8 read_buf_len, u8 delay) |
| 108 | { |
| 109 | struct drm_device *dev = chan->dev; |
| 110 | struct radeon_device *rdev = dev->dev_private; |
| 111 | PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION args; |
| 112 | int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction); |
| 113 | unsigned char *base; |
Alex Deucher | 1a66c95 | 2009-11-20 19:40:13 -0500 | [diff] [blame] | 114 | |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 115 | memset(&args, 0, sizeof(args)); |
Alex Deucher | 1a66c95 | 2009-11-20 19:40:13 -0500 | [diff] [blame] | 116 | |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 117 | base = (unsigned char *)rdev->mode_info.atom_context->scratch; |
| 118 | |
| 119 | memcpy(base, req_bytes, num_bytes); |
| 120 | |
| 121 | args.lpAuxRequest = 0; |
| 122 | args.lpDataOut = 16; |
| 123 | args.ucDataOutLen = 0; |
Alex Deucher | 6a93cb2 | 2009-11-23 17:39:28 -0500 | [diff] [blame] | 124 | args.ucChannelID = chan->rec.i2c_id; |
Alex Deucher | 1a66c95 | 2009-11-20 19:40:13 -0500 | [diff] [blame] | 125 | args.ucDelay = delay / 10; |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 126 | |
| 127 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 128 | |
| 129 | if (args.ucReplyStatus) { |
| 130 | DRM_ERROR("failed to get auxch %02x%02x %02x %02x 0x%02x %02x\n", |
| 131 | req_bytes[1], req_bytes[0], req_bytes[2], req_bytes[3], |
Alex Deucher | 6a93cb2 | 2009-11-23 17:39:28 -0500 | [diff] [blame] | 132 | chan->rec.i2c_id, args.ucReplyStatus); |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 133 | return false; |
| 134 | } |
| 135 | |
| 136 | if (args.ucDataOutLen && read_byte && read_buf_len) { |
| 137 | if (read_buf_len < args.ucDataOutLen) { |
| 138 | DRM_ERROR("Buffer to small for return answer %d %d\n", |
| 139 | read_buf_len, args.ucDataOutLen); |
| 140 | return false; |
| 141 | } |
| 142 | { |
| 143 | int len = min(read_buf_len, args.ucDataOutLen); |
| 144 | memcpy(read_byte, base + 16, len); |
| 145 | } |
| 146 | } |
| 147 | return true; |
| 148 | } |
| 149 | |
Alex Deucher | 4143e91 | 2009-11-23 18:02:35 -0500 | [diff] [blame] | 150 | static u8 radeon_dp_encoder_service(struct radeon_device *rdev, int action, int dp_clock, |
| 151 | uint8_t ucconfig, uint8_t lane_num) |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 152 | { |
| 153 | DP_ENCODER_SERVICE_PARAMETERS args; |
| 154 | int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); |
| 155 | |
| 156 | memset(&args, 0, sizeof(args)); |
| 157 | args.ucLinkClock = dp_clock / 10; |
| 158 | args.ucConfig = ucconfig; |
| 159 | args.ucAction = action; |
| 160 | args.ucLaneNum = lane_num; |
| 161 | args.ucStatus = 0; |
| 162 | |
| 163 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 164 | return args.ucStatus; |
| 165 | } |
| 166 | |
Alex Deucher | 4143e91 | 2009-11-23 18:02:35 -0500 | [diff] [blame] | 167 | u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector) |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 168 | { |
| 169 | struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv; |
| 170 | struct drm_device *dev = radeon_connector->base.dev; |
| 171 | struct radeon_device *rdev = dev->dev_private; |
| 172 | |
| 173 | return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0, |
Alex Deucher | 6a93cb2 | 2009-11-23 17:39:28 -0500 | [diff] [blame] | 174 | radeon_dig_connector->dp_i2c_bus->rec.i2c_id, 0); |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 175 | } |
| 176 | |
| 177 | union dig_transmitter_control { |
| 178 | DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1; |
| 179 | DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; |
| 180 | }; |
| 181 | |
| 182 | bool radeon_dp_aux_native_write(struct radeon_connector *radeon_connector, uint16_t address, |
| 183 | uint8_t send_bytes, uint8_t *send) |
| 184 | { |
| 185 | struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv; |
| 186 | struct drm_device *dev = radeon_connector->base.dev; |
| 187 | struct radeon_device *rdev = dev->dev_private; |
| 188 | u8 msg[20]; |
| 189 | u8 msg_len, dp_msg_len; |
| 190 | bool ret; |
| 191 | |
| 192 | dp_msg_len = 4; |
| 193 | msg[0] = address; |
| 194 | msg[1] = address >> 8; |
| 195 | msg[2] = AUX_NATIVE_WRITE << 4; |
| 196 | dp_msg_len += send_bytes; |
| 197 | msg[3] = (dp_msg_len << 4) | (send_bytes - 1); |
| 198 | |
| 199 | if (send_bytes > 16) |
| 200 | return false; |
| 201 | |
| 202 | memcpy(&msg[4], send, send_bytes); |
| 203 | msg_len = 4 + send_bytes; |
| 204 | ret = radeon_process_aux_ch(radeon_dig_connector->dp_i2c_bus, msg, msg_len, NULL, 0, 0); |
| 205 | return ret; |
| 206 | } |
| 207 | |
| 208 | bool radeon_dp_aux_native_read(struct radeon_connector *radeon_connector, uint16_t address, |
| 209 | uint8_t delay, uint8_t expected_bytes, |
| 210 | uint8_t *read_p) |
| 211 | { |
| 212 | struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv; |
| 213 | struct drm_device *dev = radeon_connector->base.dev; |
| 214 | struct radeon_device *rdev = dev->dev_private; |
| 215 | u8 msg[20]; |
| 216 | u8 msg_len, dp_msg_len; |
| 217 | bool ret = false; |
| 218 | msg_len = 4; |
| 219 | dp_msg_len = 4; |
| 220 | msg[0] = address; |
| 221 | msg[1] = address >> 8; |
| 222 | msg[2] = AUX_NATIVE_READ << 4; |
| 223 | msg[3] = (dp_msg_len) << 4; |
| 224 | msg[3] |= expected_bytes - 1; |
| 225 | |
| 226 | ret = radeon_process_aux_ch(radeon_dig_connector->dp_i2c_bus, msg, msg_len, read_p, expected_bytes, delay); |
| 227 | return ret; |
| 228 | } |
| 229 | |
Alex Deucher | 1a66c95 | 2009-11-20 19:40:13 -0500 | [diff] [blame] | 230 | void radeon_dp_getdpcd(struct radeon_connector *radeon_connector) |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 231 | { |
| 232 | struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv; |
| 233 | u8 msg[25]; |
| 234 | int ret; |
| 235 | |
Alex Deucher | 1a66c95 | 2009-11-20 19:40:13 -0500 | [diff] [blame] | 236 | ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, 0, 8, msg); |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 237 | if (ret) { |
Alex Deucher | 1a66c95 | 2009-11-20 19:40:13 -0500 | [diff] [blame] | 238 | memcpy(radeon_dig_connector->dpcd, msg, 8); |
| 239 | { |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 240 | int i; |
Alex Deucher | 1a66c95 | 2009-11-20 19:40:13 -0500 | [diff] [blame] | 241 | printk("DPCD: "); |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 242 | for (i = 0; i < 8; i++) |
| 243 | printk("%02x ", msg[i]); |
| 244 | printk("\n"); |
| 245 | } |
| 246 | } |
Alex Deucher | 1a66c95 | 2009-11-20 19:40:13 -0500 | [diff] [blame] | 247 | radeon_dig_connector->dpcd[0] = 0; |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 248 | return; |
| 249 | } |
| 250 | |
| 251 | static bool atom_dp_get_link_status(struct radeon_connector *radeon_connector, |
| 252 | u8 link_status[DP_LINK_STATUS_SIZE]) |
| 253 | { |
| 254 | int ret; |
| 255 | ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS, 100, |
| 256 | DP_LINK_STATUS_SIZE, link_status); |
| 257 | if (!ret) { |
| 258 | DRM_ERROR("displayport link status failed\n"); |
| 259 | return false; |
| 260 | } |
| 261 | |
| 262 | DRM_INFO("link status %02x %02x %02x %02x %02x %02x\n", |
| 263 | link_status[0], link_status[1], link_status[2], |
| 264 | link_status[3], link_status[4], link_status[5]); |
| 265 | return true; |
| 266 | } |
| 267 | |
| 268 | static void dp_set_power(struct radeon_connector *radeon_connector, u8 power_state) |
| 269 | { |
| 270 | struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv; |
Alex Deucher | 1a66c95 | 2009-11-20 19:40:13 -0500 | [diff] [blame] | 271 | if (radeon_dig_connector->dpcd[0] >= 0x11) { |
| 272 | radeon_dp_aux_native_write(radeon_connector, DP_SET_POWER, 1, |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 273 | &power_state); |
| 274 | } |
| 275 | } |
| 276 | |
| 277 | static void dp_update_dpvs_emph(struct radeon_connector *radeon_connector, |
| 278 | u8 train_set[4]) |
| 279 | { |
| 280 | struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv; |
| 281 | |
| 282 | // radeon_dp_digtransmitter_setup_vsemph(); |
| 283 | radeon_dp_aux_native_write(radeon_connector, DP_TRAINING_LANE0_SET, |
| 284 | 0/* lc */, train_set); |
| 285 | } |
| 286 | |
| 287 | static void dp_set_training(struct radeon_connector *radeon_connector, |
| 288 | u8 training) |
| 289 | { |
| 290 | radeon_dp_aux_native_write(radeon_connector, DP_TRAINING_PATTERN_SET, |
| 291 | 1, &training); |
| 292 | } |
| 293 | |
| 294 | int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, |
| 295 | uint8_t write_byte, uint8_t *read_byte) |
| 296 | { |
| 297 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; |
| 298 | struct radeon_i2c_chan *auxch = (struct radeon_i2c_chan *)adapter; |
| 299 | int ret = 0; |
| 300 | uint16_t address = algo_data->address; |
| 301 | uint8_t msg[5]; |
| 302 | uint8_t reply[2]; |
| 303 | int msg_len, dp_msg_len; |
| 304 | int reply_bytes; |
| 305 | |
| 306 | /* Set up the command byte */ |
| 307 | if (mode & MODE_I2C_READ) |
| 308 | msg[2] = AUX_I2C_READ << 4; |
| 309 | else |
| 310 | msg[2] = AUX_I2C_WRITE << 4; |
| 311 | |
| 312 | if (!(mode & MODE_I2C_STOP)) |
| 313 | msg[2] |= AUX_I2C_MOT << 4; |
| 314 | |
| 315 | msg[0] = address; |
| 316 | msg[1] = address >> 8; |
| 317 | |
| 318 | reply_bytes = 1; |
| 319 | |
| 320 | msg_len = 4; |
| 321 | dp_msg_len = 3; |
| 322 | switch (mode) { |
| 323 | case MODE_I2C_WRITE: |
| 324 | msg[4] = write_byte; |
| 325 | msg_len++; |
| 326 | dp_msg_len += 2; |
| 327 | break; |
| 328 | case MODE_I2C_READ: |
| 329 | dp_msg_len += 1; |
| 330 | break; |
| 331 | default: |
| 332 | break; |
| 333 | } |
| 334 | |
| 335 | msg[3] = (dp_msg_len) << 4; |
| 336 | ret = radeon_process_aux_ch(auxch, msg, msg_len, reply, reply_bytes, 0); |
| 337 | |
| 338 | if (ret) { |
| 339 | if (read_byte) |
| 340 | *read_byte = reply[0]; |
| 341 | return reply_bytes; |
| 342 | } |
| 343 | return -EREMOTEIO; |
| 344 | } |