Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1 | /* |
| 2 | * MUSB OTG driver peripheral support |
| 3 | * |
| 4 | * Copyright 2005 Mentor Graphics Corporation |
| 5 | * Copyright (C) 2005-2006 by Texas Instruments |
| 6 | * Copyright (C) 2006-2007 Nokia Corporation |
Sergei Shtylyov | cea8324 | 2009-11-18 22:51:18 +0300 | [diff] [blame] | 7 | * Copyright (C) 2009 MontaVista Software, Inc. <source@mvista.com> |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License |
| 11 | * version 2 as published by the Free Software Foundation. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, but |
| 14 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 16 | * General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA |
| 21 | * 02110-1301 USA |
| 22 | * |
| 23 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 24 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 25 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
| 26 | * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 27 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 28 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF |
| 29 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| 30 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 31 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 32 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 33 | * |
| 34 | */ |
| 35 | |
| 36 | #include <linux/kernel.h> |
| 37 | #include <linux/list.h> |
| 38 | #include <linux/timer.h> |
| 39 | #include <linux/module.h> |
| 40 | #include <linux/smp.h> |
| 41 | #include <linux/spinlock.h> |
| 42 | #include <linux/delay.h> |
| 43 | #include <linux/moduleparam.h> |
| 44 | #include <linux/stat.h> |
| 45 | #include <linux/dma-mapping.h> |
| 46 | |
| 47 | #include "musb_core.h" |
| 48 | |
| 49 | |
| 50 | /* MUSB PERIPHERAL status 3-mar-2006: |
| 51 | * |
| 52 | * - EP0 seems solid. It passes both USBCV and usbtest control cases. |
| 53 | * Minor glitches: |
| 54 | * |
| 55 | * + remote wakeup to Linux hosts work, but saw USBCV failures; |
| 56 | * in one test run (operator error?) |
| 57 | * + endpoint halt tests -- in both usbtest and usbcv -- seem |
| 58 | * to break when dma is enabled ... is something wrongly |
| 59 | * clearing SENDSTALL? |
| 60 | * |
| 61 | * - Mass storage behaved ok when last tested. Network traffic patterns |
| 62 | * (with lots of short transfers etc) need retesting; they turn up the |
| 63 | * worst cases of the DMA, since short packets are typical but are not |
| 64 | * required. |
| 65 | * |
| 66 | * - TX/IN |
| 67 | * + both pio and dma behave in with network and g_zero tests |
| 68 | * + no cppi throughput issues other than no-hw-queueing |
| 69 | * + failed with FLAT_REG (DaVinci) |
| 70 | * + seems to behave with double buffering, PIO -and- CPPI |
| 71 | * + with gadgetfs + AIO, requests got lost? |
| 72 | * |
| 73 | * - RX/OUT |
| 74 | * + both pio and dma behave in with network and g_zero tests |
| 75 | * + dma is slow in typical case (short_not_ok is clear) |
| 76 | * + double buffering ok with PIO |
| 77 | * + double buffering *FAILS* with CPPI, wrong data bytes sometimes |
| 78 | * + request lossage observed with gadgetfs |
| 79 | * |
| 80 | * - ISO not tested ... might work, but only weakly isochronous |
| 81 | * |
| 82 | * - Gadget driver disabling of softconnect during bind() is ignored; so |
| 83 | * drivers can't hold off host requests until userspace is ready. |
| 84 | * (Workaround: they can turn it off later.) |
| 85 | * |
| 86 | * - PORTABILITY (assumes PIO works): |
| 87 | * + DaVinci, basically works with cppi dma |
| 88 | * + OMAP 2430, ditto with mentor dma |
| 89 | * + TUSB 6010, platform-specific dma in the works |
| 90 | */ |
| 91 | |
| 92 | /* ----------------------------------------------------------------------- */ |
| 93 | |
| 94 | /* |
| 95 | * Immediately complete a request. |
| 96 | * |
| 97 | * @param request the request to complete |
| 98 | * @param status the status to complete the request with |
| 99 | * Context: controller locked, IRQs blocked. |
| 100 | */ |
| 101 | void musb_g_giveback( |
| 102 | struct musb_ep *ep, |
| 103 | struct usb_request *request, |
| 104 | int status) |
| 105 | __releases(ep->musb->lock) |
| 106 | __acquires(ep->musb->lock) |
| 107 | { |
| 108 | struct musb_request *req; |
| 109 | struct musb *musb; |
| 110 | int busy = ep->busy; |
| 111 | |
| 112 | req = to_musb_request(request); |
| 113 | |
| 114 | list_del(&request->list); |
| 115 | if (req->request.status == -EINPROGRESS) |
| 116 | req->request.status = status; |
| 117 | musb = req->musb; |
| 118 | |
| 119 | ep->busy = 1; |
| 120 | spin_unlock(&musb->lock); |
| 121 | if (is_dma_capable()) { |
| 122 | if (req->mapped) { |
| 123 | dma_unmap_single(musb->controller, |
| 124 | req->request.dma, |
| 125 | req->request.length, |
| 126 | req->tx |
| 127 | ? DMA_TO_DEVICE |
| 128 | : DMA_FROM_DEVICE); |
| 129 | req->request.dma = DMA_ADDR_INVALID; |
| 130 | req->mapped = 0; |
| 131 | } else if (req->request.dma != DMA_ADDR_INVALID) |
| 132 | dma_sync_single_for_cpu(musb->controller, |
| 133 | req->request.dma, |
| 134 | req->request.length, |
| 135 | req->tx |
| 136 | ? DMA_TO_DEVICE |
| 137 | : DMA_FROM_DEVICE); |
| 138 | } |
| 139 | if (request->status == 0) |
| 140 | DBG(5, "%s done request %p, %d/%d\n", |
| 141 | ep->end_point.name, request, |
| 142 | req->request.actual, req->request.length); |
| 143 | else |
| 144 | DBG(2, "%s request %p, %d/%d fault %d\n", |
| 145 | ep->end_point.name, request, |
| 146 | req->request.actual, req->request.length, |
| 147 | request->status); |
| 148 | req->request.complete(&req->ep->end_point, &req->request); |
| 149 | spin_lock(&musb->lock); |
| 150 | ep->busy = busy; |
| 151 | } |
| 152 | |
| 153 | /* ----------------------------------------------------------------------- */ |
| 154 | |
| 155 | /* |
| 156 | * Abort requests queued to an endpoint using the status. Synchronous. |
| 157 | * caller locked controller and blocked irqs, and selected this ep. |
| 158 | */ |
| 159 | static void nuke(struct musb_ep *ep, const int status) |
| 160 | { |
| 161 | struct musb_request *req = NULL; |
| 162 | void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs; |
| 163 | |
| 164 | ep->busy = 1; |
| 165 | |
| 166 | if (is_dma_capable() && ep->dma) { |
| 167 | struct dma_controller *c = ep->musb->dma_controller; |
| 168 | int value; |
Sergei Shtylyov | b6e434a | 2009-03-26 18:27:47 -0700 | [diff] [blame] | 169 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 170 | if (ep->is_in) { |
Sergei Shtylyov | b6e434a | 2009-03-26 18:27:47 -0700 | [diff] [blame] | 171 | /* |
| 172 | * The programming guide says that we must not clear |
| 173 | * the DMAMODE bit before DMAENAB, so we only |
| 174 | * clear it in the second write... |
| 175 | */ |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 176 | musb_writew(epio, MUSB_TXCSR, |
Sergei Shtylyov | b6e434a | 2009-03-26 18:27:47 -0700 | [diff] [blame] | 177 | MUSB_TXCSR_DMAMODE | MUSB_TXCSR_FLUSHFIFO); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 178 | musb_writew(epio, MUSB_TXCSR, |
| 179 | 0 | MUSB_TXCSR_FLUSHFIFO); |
| 180 | } else { |
| 181 | musb_writew(epio, MUSB_RXCSR, |
| 182 | 0 | MUSB_RXCSR_FLUSHFIFO); |
| 183 | musb_writew(epio, MUSB_RXCSR, |
| 184 | 0 | MUSB_RXCSR_FLUSHFIFO); |
| 185 | } |
| 186 | |
| 187 | value = c->channel_abort(ep->dma); |
| 188 | DBG(value ? 1 : 6, "%s: abort DMA --> %d\n", ep->name, value); |
| 189 | c->channel_release(ep->dma); |
| 190 | ep->dma = NULL; |
| 191 | } |
| 192 | |
| 193 | while (!list_empty(&(ep->req_list))) { |
| 194 | req = container_of(ep->req_list.next, struct musb_request, |
| 195 | request.list); |
| 196 | musb_g_giveback(ep, &req->request, status); |
| 197 | } |
| 198 | } |
| 199 | |
| 200 | /* ----------------------------------------------------------------------- */ |
| 201 | |
| 202 | /* Data transfers - pure PIO, pure DMA, or mixed mode */ |
| 203 | |
| 204 | /* |
| 205 | * This assumes the separate CPPI engine is responding to DMA requests |
| 206 | * from the usb core ... sequenced a bit differently from mentor dma. |
| 207 | */ |
| 208 | |
| 209 | static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep) |
| 210 | { |
| 211 | if (can_bulk_split(musb, ep->type)) |
| 212 | return ep->hw_ep->max_packet_sz_tx; |
| 213 | else |
| 214 | return ep->packet_sz; |
| 215 | } |
| 216 | |
| 217 | |
| 218 | #ifdef CONFIG_USB_INVENTRA_DMA |
| 219 | |
| 220 | /* Peripheral tx (IN) using Mentor DMA works as follows: |
| 221 | Only mode 0 is used for transfers <= wPktSize, |
| 222 | mode 1 is used for larger transfers, |
| 223 | |
| 224 | One of the following happens: |
| 225 | - Host sends IN token which causes an endpoint interrupt |
| 226 | -> TxAvail |
| 227 | -> if DMA is currently busy, exit. |
| 228 | -> if queue is non-empty, txstate(). |
| 229 | |
| 230 | - Request is queued by the gadget driver. |
| 231 | -> if queue was previously empty, txstate() |
| 232 | |
| 233 | txstate() |
| 234 | -> start |
| 235 | /\ -> setup DMA |
| 236 | | (data is transferred to the FIFO, then sent out when |
| 237 | | IN token(s) are recd from Host. |
| 238 | | -> DMA interrupt on completion |
| 239 | | calls TxAvail. |
Sergei Shtylyov | b6e434a | 2009-03-26 18:27:47 -0700 | [diff] [blame] | 240 | | -> stop DMA, ~DMAENAB, |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 241 | | -> set TxPktRdy for last short pkt or zlp |
| 242 | | -> Complete Request |
| 243 | | -> Continue next request (call txstate) |
| 244 | |___________________________________| |
| 245 | |
| 246 | * Non-Mentor DMA engines can of course work differently, such as by |
| 247 | * upleveling from irq-per-packet to irq-per-buffer. |
| 248 | */ |
| 249 | |
| 250 | #endif |
| 251 | |
| 252 | /* |
| 253 | * An endpoint is transmitting data. This can be called either from |
| 254 | * the IRQ routine or from ep.queue() to kickstart a request on an |
| 255 | * endpoint. |
| 256 | * |
| 257 | * Context: controller locked, IRQs blocked, endpoint selected |
| 258 | */ |
| 259 | static void txstate(struct musb *musb, struct musb_request *req) |
| 260 | { |
| 261 | u8 epnum = req->epnum; |
| 262 | struct musb_ep *musb_ep; |
| 263 | void __iomem *epio = musb->endpoints[epnum].regs; |
| 264 | struct usb_request *request; |
| 265 | u16 fifo_count = 0, csr; |
| 266 | int use_dma = 0; |
| 267 | |
| 268 | musb_ep = req->ep; |
| 269 | |
| 270 | /* we shouldn't get here while DMA is active ... but we do ... */ |
| 271 | if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) { |
| 272 | DBG(4, "dma pending...\n"); |
| 273 | return; |
| 274 | } |
| 275 | |
| 276 | /* read TXCSR before */ |
| 277 | csr = musb_readw(epio, MUSB_TXCSR); |
| 278 | |
| 279 | request = &req->request; |
| 280 | fifo_count = min(max_ep_writesize(musb, musb_ep), |
| 281 | (int)(request->length - request->actual)); |
| 282 | |
| 283 | if (csr & MUSB_TXCSR_TXPKTRDY) { |
| 284 | DBG(5, "%s old packet still ready , txcsr %03x\n", |
| 285 | musb_ep->end_point.name, csr); |
| 286 | return; |
| 287 | } |
| 288 | |
| 289 | if (csr & MUSB_TXCSR_P_SENDSTALL) { |
| 290 | DBG(5, "%s stalling, txcsr %03x\n", |
| 291 | musb_ep->end_point.name, csr); |
| 292 | return; |
| 293 | } |
| 294 | |
| 295 | DBG(4, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n", |
| 296 | epnum, musb_ep->packet_sz, fifo_count, |
| 297 | csr); |
| 298 | |
| 299 | #ifndef CONFIG_MUSB_PIO_ONLY |
| 300 | if (is_dma_capable() && musb_ep->dma) { |
| 301 | struct dma_controller *c = musb->dma_controller; |
| 302 | |
| 303 | use_dma = (request->dma != DMA_ADDR_INVALID); |
| 304 | |
| 305 | /* MUSB_TXCSR_P_ISO is still set correctly */ |
| 306 | |
| 307 | #ifdef CONFIG_USB_INVENTRA_DMA |
| 308 | { |
| 309 | size_t request_size; |
| 310 | |
| 311 | /* setup DMA, then program endpoint CSR */ |
| 312 | request_size = min(request->length, |
| 313 | musb_ep->dma->max_len); |
Anand Gadiyar | d1043a2 | 2009-04-02 12:07:08 -0700 | [diff] [blame] | 314 | if (request_size < musb_ep->packet_sz) |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 315 | musb_ep->dma->desired_mode = 0; |
| 316 | else |
| 317 | musb_ep->dma->desired_mode = 1; |
| 318 | |
| 319 | use_dma = use_dma && c->channel_program( |
| 320 | musb_ep->dma, musb_ep->packet_sz, |
| 321 | musb_ep->dma->desired_mode, |
| 322 | request->dma, request_size); |
| 323 | if (use_dma) { |
| 324 | if (musb_ep->dma->desired_mode == 0) { |
Sergei Shtylyov | b6e434a | 2009-03-26 18:27:47 -0700 | [diff] [blame] | 325 | /* |
| 326 | * We must not clear the DMAMODE bit |
| 327 | * before the DMAENAB bit -- and the |
| 328 | * latter doesn't always get cleared |
| 329 | * before we get here... |
| 330 | */ |
| 331 | csr &= ~(MUSB_TXCSR_AUTOSET |
| 332 | | MUSB_TXCSR_DMAENAB); |
| 333 | musb_writew(epio, MUSB_TXCSR, csr |
| 334 | | MUSB_TXCSR_P_WZC_BITS); |
| 335 | csr &= ~MUSB_TXCSR_DMAMODE; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 336 | csr |= (MUSB_TXCSR_DMAENAB | |
| 337 | MUSB_TXCSR_MODE); |
| 338 | /* against programming guide */ |
| 339 | } else |
| 340 | csr |= (MUSB_TXCSR_AUTOSET |
| 341 | | MUSB_TXCSR_DMAENAB |
| 342 | | MUSB_TXCSR_DMAMODE |
| 343 | | MUSB_TXCSR_MODE); |
| 344 | |
| 345 | csr &= ~MUSB_TXCSR_P_UNDERRUN; |
| 346 | musb_writew(epio, MUSB_TXCSR, csr); |
| 347 | } |
| 348 | } |
| 349 | |
| 350 | #elif defined(CONFIG_USB_TI_CPPI_DMA) |
| 351 | /* program endpoint CSR first, then setup DMA */ |
Sergei Shtylyov | b6e434a | 2009-03-26 18:27:47 -0700 | [diff] [blame] | 352 | csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY); |
Sergei Shtylyov | 37e3ee9 | 2009-03-27 12:53:32 -0700 | [diff] [blame] | 353 | csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE | |
| 354 | MUSB_TXCSR_MODE; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 355 | musb_writew(epio, MUSB_TXCSR, |
| 356 | (MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN) |
| 357 | | csr); |
| 358 | |
| 359 | /* ensure writebuffer is empty */ |
| 360 | csr = musb_readw(epio, MUSB_TXCSR); |
| 361 | |
| 362 | /* NOTE host side sets DMAENAB later than this; both are |
| 363 | * OK since the transfer dma glue (between CPPI and Mentor |
| 364 | * fifos) just tells CPPI it could start. Data only moves |
| 365 | * to the USB TX fifo when both fifos are ready. |
| 366 | */ |
| 367 | |
| 368 | /* "mode" is irrelevant here; handle terminating ZLPs like |
| 369 | * PIO does, since the hardware RNDIS mode seems unreliable |
| 370 | * except for the last-packet-is-already-short case. |
| 371 | */ |
| 372 | use_dma = use_dma && c->channel_program( |
| 373 | musb_ep->dma, musb_ep->packet_sz, |
| 374 | 0, |
| 375 | request->dma, |
| 376 | request->length); |
| 377 | if (!use_dma) { |
| 378 | c->channel_release(musb_ep->dma); |
| 379 | musb_ep->dma = NULL; |
Sergei Shtylyov | b6e434a | 2009-03-26 18:27:47 -0700 | [diff] [blame] | 380 | csr &= ~MUSB_TXCSR_DMAENAB; |
| 381 | musb_writew(epio, MUSB_TXCSR, csr); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 382 | /* invariant: prequest->buf is non-null */ |
| 383 | } |
| 384 | #elif defined(CONFIG_USB_TUSB_OMAP_DMA) |
| 385 | use_dma = use_dma && c->channel_program( |
| 386 | musb_ep->dma, musb_ep->packet_sz, |
| 387 | request->zero, |
| 388 | request->dma, |
| 389 | request->length); |
| 390 | #endif |
| 391 | } |
| 392 | #endif |
| 393 | |
| 394 | if (!use_dma) { |
| 395 | musb_write_fifo(musb_ep->hw_ep, fifo_count, |
| 396 | (u8 *) (request->buf + request->actual)); |
| 397 | request->actual += fifo_count; |
| 398 | csr |= MUSB_TXCSR_TXPKTRDY; |
| 399 | csr &= ~MUSB_TXCSR_P_UNDERRUN; |
| 400 | musb_writew(epio, MUSB_TXCSR, csr); |
| 401 | } |
| 402 | |
| 403 | /* host may already have the data when this message shows... */ |
| 404 | DBG(3, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n", |
| 405 | musb_ep->end_point.name, use_dma ? "dma" : "pio", |
| 406 | request->actual, request->length, |
| 407 | musb_readw(epio, MUSB_TXCSR), |
| 408 | fifo_count, |
| 409 | musb_readw(epio, MUSB_TXMAXP)); |
| 410 | } |
| 411 | |
| 412 | /* |
| 413 | * FIFO state update (e.g. data ready). |
| 414 | * Called from IRQ, with controller locked. |
| 415 | */ |
| 416 | void musb_g_tx(struct musb *musb, u8 epnum) |
| 417 | { |
| 418 | u16 csr; |
| 419 | struct usb_request *request; |
| 420 | u8 __iomem *mbase = musb->mregs; |
| 421 | struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in; |
| 422 | void __iomem *epio = musb->endpoints[epnum].regs; |
| 423 | struct dma_channel *dma; |
| 424 | |
| 425 | musb_ep_select(mbase, epnum); |
| 426 | request = next_request(musb_ep); |
| 427 | |
| 428 | csr = musb_readw(epio, MUSB_TXCSR); |
| 429 | DBG(4, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr); |
| 430 | |
| 431 | dma = is_dma_capable() ? musb_ep->dma : NULL; |
Sergei Shtylyov | 7723de7 | 2009-11-18 22:55:28 +0300 | [diff] [blame] | 432 | |
| 433 | /* |
| 434 | * REVISIT: for high bandwidth, MUSB_TXCSR_P_INCOMPTX |
| 435 | * probably rates reporting as a host error. |
| 436 | */ |
| 437 | if (csr & MUSB_TXCSR_P_SENTSTALL) { |
| 438 | csr |= MUSB_TXCSR_P_WZC_BITS; |
| 439 | csr &= ~MUSB_TXCSR_P_SENTSTALL; |
| 440 | musb_writew(epio, MUSB_TXCSR, csr); |
| 441 | return; |
| 442 | } |
| 443 | |
| 444 | if (csr & MUSB_TXCSR_P_UNDERRUN) { |
| 445 | /* We NAKed, no big deal... little reason to care. */ |
| 446 | csr |= MUSB_TXCSR_P_WZC_BITS; |
| 447 | csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY); |
| 448 | musb_writew(epio, MUSB_TXCSR, csr); |
| 449 | DBG(20, "underrun on ep%d, req %p\n", epnum, request); |
| 450 | } |
| 451 | |
| 452 | if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { |
| 453 | /* |
| 454 | * SHOULD NOT HAPPEN... has with CPPI though, after |
| 455 | * changing SENDSTALL (and other cases); harmless? |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 456 | */ |
Sergei Shtylyov | 7723de7 | 2009-11-18 22:55:28 +0300 | [diff] [blame] | 457 | DBG(5, "%s dma still busy?\n", musb_ep->end_point.name); |
| 458 | return; |
| 459 | } |
| 460 | |
| 461 | if (request) { |
| 462 | u8 is_dma = 0; |
| 463 | |
| 464 | if (dma && (csr & MUSB_TXCSR_DMAENAB)) { |
| 465 | is_dma = 1; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 466 | csr |= MUSB_TXCSR_P_WZC_BITS; |
Sergei Shtylyov | 7723de7 | 2009-11-18 22:55:28 +0300 | [diff] [blame] | 467 | csr &= ~(MUSB_TXCSR_DMAENAB | MUSB_TXCSR_P_UNDERRUN | |
| 468 | MUSB_TXCSR_TXPKTRDY); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 469 | musb_writew(epio, MUSB_TXCSR, csr); |
Sergei Shtylyov | 7723de7 | 2009-11-18 22:55:28 +0300 | [diff] [blame] | 470 | /* Ensure writebuffer is empty. */ |
| 471 | csr = musb_readw(epio, MUSB_TXCSR); |
| 472 | request->actual += musb_ep->dma->actual_len; |
| 473 | DBG(4, "TXCSR%d %04x, DMA off, len %zu, req %p\n", |
| 474 | epnum, csr, musb_ep->dma->actual_len, request); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 475 | } |
| 476 | |
Sergei Shtylyov | 7723de7 | 2009-11-18 22:55:28 +0300 | [diff] [blame] | 477 | if (is_dma || request->actual == request->length) { |
| 478 | /* |
| 479 | * First, maybe a terminating short packet. Some DMA |
| 480 | * engines might handle this by themselves. |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 481 | */ |
Sergei Shtylyov | 7723de7 | 2009-11-18 22:55:28 +0300 | [diff] [blame] | 482 | if ((request->zero && request->length |
| 483 | && request->length % musb_ep->packet_sz == 0) |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 484 | #ifdef CONFIG_USB_INVENTRA_DMA |
Sergei Shtylyov | 7723de7 | 2009-11-18 22:55:28 +0300 | [diff] [blame] | 485 | || (is_dma && (!dma->desired_mode || |
| 486 | (request->actual & |
| 487 | (musb_ep->packet_sz - 1)))) |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 488 | #endif |
Sergei Shtylyov | 7723de7 | 2009-11-18 22:55:28 +0300 | [diff] [blame] | 489 | ) { |
| 490 | /* |
| 491 | * On DMA completion, FIFO may not be |
| 492 | * available yet... |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 493 | */ |
Sergei Shtylyov | 7723de7 | 2009-11-18 22:55:28 +0300 | [diff] [blame] | 494 | if (csr & MUSB_TXCSR_TXPKTRDY) |
| 495 | return; |
| 496 | |
| 497 | DBG(4, "sending zero pkt\n"); |
| 498 | musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE |
| 499 | | MUSB_TXCSR_TXPKTRDY); |
| 500 | request->zero = 0; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 501 | } |
| 502 | |
Sergei Shtylyov | 7723de7 | 2009-11-18 22:55:28 +0300 | [diff] [blame] | 503 | /* ... or if not, then complete it. */ |
| 504 | musb_g_giveback(musb_ep, request, 0); |
| 505 | |
| 506 | /* |
| 507 | * Kickstart next transfer if appropriate; |
| 508 | * the packet that just completed might not |
| 509 | * be transmitted for hours or days. |
| 510 | * REVISIT for double buffering... |
| 511 | * FIXME revisit for stalls too... |
| 512 | */ |
| 513 | musb_ep_select(mbase, epnum); |
| 514 | csr = musb_readw(epio, MUSB_TXCSR); |
| 515 | if (csr & MUSB_TXCSR_FIFONOTEMPTY) |
| 516 | return; |
| 517 | |
Sergei Shtylyov | 95962a7 | 2009-12-16 20:38:31 +0300 | [diff] [blame] | 518 | request = musb_ep->desc ? next_request(musb_ep) : NULL; |
| 519 | if (!request) { |
Sergei Shtylyov | 7723de7 | 2009-11-18 22:55:28 +0300 | [diff] [blame] | 520 | DBG(4, "%s idle now\n", |
| 521 | musb_ep->end_point.name); |
| 522 | return; |
Sergei Shtylyov | 95962a7 | 2009-12-16 20:38:31 +0300 | [diff] [blame] | 523 | } |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 524 | } |
| 525 | |
Sergei Shtylyov | 7723de7 | 2009-11-18 22:55:28 +0300 | [diff] [blame] | 526 | txstate(musb, to_musb_request(request)); |
| 527 | } |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 528 | } |
| 529 | |
| 530 | /* ------------------------------------------------------------ */ |
| 531 | |
| 532 | #ifdef CONFIG_USB_INVENTRA_DMA |
| 533 | |
| 534 | /* Peripheral rx (OUT) using Mentor DMA works as follows: |
| 535 | - Only mode 0 is used. |
| 536 | |
| 537 | - Request is queued by the gadget class driver. |
| 538 | -> if queue was previously empty, rxstate() |
| 539 | |
| 540 | - Host sends OUT token which causes an endpoint interrupt |
| 541 | /\ -> RxReady |
| 542 | | -> if request queued, call rxstate |
| 543 | | /\ -> setup DMA |
| 544 | | | -> DMA interrupt on completion |
| 545 | | | -> RxReady |
| 546 | | | -> stop DMA |
| 547 | | | -> ack the read |
| 548 | | | -> if data recd = max expected |
| 549 | | | by the request, or host |
| 550 | | | sent a short packet, |
| 551 | | | complete the request, |
| 552 | | | and start the next one. |
| 553 | | |_____________________________________| |
| 554 | | else just wait for the host |
| 555 | | to send the next OUT token. |
| 556 | |__________________________________________________| |
| 557 | |
| 558 | * Non-Mentor DMA engines can of course work differently. |
| 559 | */ |
| 560 | |
| 561 | #endif |
| 562 | |
| 563 | /* |
| 564 | * Context: controller locked, IRQs blocked, endpoint selected |
| 565 | */ |
| 566 | static void rxstate(struct musb *musb, struct musb_request *req) |
| 567 | { |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 568 | const u8 epnum = req->epnum; |
| 569 | struct usb_request *request = &req->request; |
| 570 | struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_out; |
| 571 | void __iomem *epio = musb->endpoints[epnum].regs; |
Felipe Balbi | c2c9632 | 2009-02-21 15:29:42 -0800 | [diff] [blame] | 572 | unsigned fifo_count = 0; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 573 | u16 len = musb_ep->packet_sz; |
Sergei Shtylyov | cea8324 | 2009-11-18 22:51:18 +0300 | [diff] [blame] | 574 | u16 csr = musb_readw(epio, MUSB_RXCSR); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 575 | |
Sergei Shtylyov | cea8324 | 2009-11-18 22:51:18 +0300 | [diff] [blame] | 576 | /* We shouldn't get here while DMA is active, but we do... */ |
| 577 | if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) { |
| 578 | DBG(4, "DMA pending...\n"); |
| 579 | return; |
| 580 | } |
| 581 | |
| 582 | if (csr & MUSB_RXCSR_P_SENDSTALL) { |
| 583 | DBG(5, "%s stalling, RXCSR %04x\n", |
| 584 | musb_ep->end_point.name, csr); |
| 585 | return; |
| 586 | } |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 587 | |
| 588 | if (is_cppi_enabled() && musb_ep->dma) { |
| 589 | struct dma_controller *c = musb->dma_controller; |
| 590 | struct dma_channel *channel = musb_ep->dma; |
| 591 | |
| 592 | /* NOTE: CPPI won't actually stop advancing the DMA |
| 593 | * queue after short packet transfers, so this is almost |
| 594 | * always going to run as IRQ-per-packet DMA so that |
| 595 | * faults will be handled correctly. |
| 596 | */ |
| 597 | if (c->channel_program(channel, |
| 598 | musb_ep->packet_sz, |
| 599 | !request->short_not_ok, |
| 600 | request->dma + request->actual, |
| 601 | request->length - request->actual)) { |
| 602 | |
| 603 | /* make sure that if an rxpkt arrived after the irq, |
| 604 | * the cppi engine will be ready to take it as soon |
| 605 | * as DMA is enabled |
| 606 | */ |
| 607 | csr &= ~(MUSB_RXCSR_AUTOCLEAR |
| 608 | | MUSB_RXCSR_DMAMODE); |
| 609 | csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS; |
| 610 | musb_writew(epio, MUSB_RXCSR, csr); |
| 611 | return; |
| 612 | } |
| 613 | } |
| 614 | |
| 615 | if (csr & MUSB_RXCSR_RXPKTRDY) { |
| 616 | len = musb_readw(epio, MUSB_RXCOUNT); |
| 617 | if (request->actual < request->length) { |
| 618 | #ifdef CONFIG_USB_INVENTRA_DMA |
| 619 | if (is_dma_capable() && musb_ep->dma) { |
| 620 | struct dma_controller *c; |
| 621 | struct dma_channel *channel; |
| 622 | int use_dma = 0; |
| 623 | |
| 624 | c = musb->dma_controller; |
| 625 | channel = musb_ep->dma; |
| 626 | |
| 627 | /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in |
| 628 | * mode 0 only. So we do not get endpoint interrupts due to DMA |
| 629 | * completion. We only get interrupts from DMA controller. |
| 630 | * |
| 631 | * We could operate in DMA mode 1 if we knew the size of the tranfer |
| 632 | * in advance. For mass storage class, request->length = what the host |
| 633 | * sends, so that'd work. But for pretty much everything else, |
| 634 | * request->length is routinely more than what the host sends. For |
| 635 | * most these gadgets, end of is signified either by a short packet, |
| 636 | * or filling the last byte of the buffer. (Sending extra data in |
| 637 | * that last pckate should trigger an overflow fault.) But in mode 1, |
| 638 | * we don't get DMA completion interrrupt for short packets. |
| 639 | * |
| 640 | * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1), |
| 641 | * to get endpoint interrupt on every DMA req, but that didn't seem |
| 642 | * to work reliably. |
| 643 | * |
| 644 | * REVISIT an updated g_file_storage can set req->short_not_ok, which |
| 645 | * then becomes usable as a runtime "use mode 1" hint... |
| 646 | */ |
| 647 | |
| 648 | csr |= MUSB_RXCSR_DMAENAB; |
| 649 | #ifdef USE_MODE1 |
| 650 | csr |= MUSB_RXCSR_AUTOCLEAR; |
| 651 | /* csr |= MUSB_RXCSR_DMAMODE; */ |
| 652 | |
| 653 | /* this special sequence (enabling and then |
| 654 | * disabling MUSB_RXCSR_DMAMODE) is required |
| 655 | * to get DMAReq to activate |
| 656 | */ |
| 657 | musb_writew(epio, MUSB_RXCSR, |
| 658 | csr | MUSB_RXCSR_DMAMODE); |
| 659 | #endif |
| 660 | musb_writew(epio, MUSB_RXCSR, csr); |
| 661 | |
| 662 | if (request->actual < request->length) { |
| 663 | int transfer_size = 0; |
| 664 | #ifdef USE_MODE1 |
| 665 | transfer_size = min(request->length, |
| 666 | channel->max_len); |
| 667 | #else |
| 668 | transfer_size = len; |
| 669 | #endif |
| 670 | if (transfer_size <= musb_ep->packet_sz) |
| 671 | musb_ep->dma->desired_mode = 0; |
| 672 | else |
| 673 | musb_ep->dma->desired_mode = 1; |
| 674 | |
| 675 | use_dma = c->channel_program( |
| 676 | channel, |
| 677 | musb_ep->packet_sz, |
| 678 | channel->desired_mode, |
| 679 | request->dma |
| 680 | + request->actual, |
| 681 | transfer_size); |
| 682 | } |
| 683 | |
| 684 | if (use_dma) |
| 685 | return; |
| 686 | } |
| 687 | #endif /* Mentor's DMA */ |
| 688 | |
| 689 | fifo_count = request->length - request->actual; |
| 690 | DBG(3, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n", |
| 691 | musb_ep->end_point.name, |
| 692 | len, fifo_count, |
| 693 | musb_ep->packet_sz); |
| 694 | |
Felipe Balbi | c2c9632 | 2009-02-21 15:29:42 -0800 | [diff] [blame] | 695 | fifo_count = min_t(unsigned, len, fifo_count); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 696 | |
| 697 | #ifdef CONFIG_USB_TUSB_OMAP_DMA |
| 698 | if (tusb_dma_omap() && musb_ep->dma) { |
| 699 | struct dma_controller *c = musb->dma_controller; |
| 700 | struct dma_channel *channel = musb_ep->dma; |
| 701 | u32 dma_addr = request->dma + request->actual; |
| 702 | int ret; |
| 703 | |
| 704 | ret = c->channel_program(channel, |
| 705 | musb_ep->packet_sz, |
| 706 | channel->desired_mode, |
| 707 | dma_addr, |
| 708 | fifo_count); |
| 709 | if (ret) |
| 710 | return; |
| 711 | } |
| 712 | #endif |
| 713 | |
| 714 | musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *) |
| 715 | (request->buf + request->actual)); |
| 716 | request->actual += fifo_count; |
| 717 | |
| 718 | /* REVISIT if we left anything in the fifo, flush |
| 719 | * it and report -EOVERFLOW |
| 720 | */ |
| 721 | |
| 722 | /* ack the read! */ |
| 723 | csr |= MUSB_RXCSR_P_WZC_BITS; |
| 724 | csr &= ~MUSB_RXCSR_RXPKTRDY; |
| 725 | musb_writew(epio, MUSB_RXCSR, csr); |
| 726 | } |
| 727 | } |
| 728 | |
| 729 | /* reach the end or short packet detected */ |
| 730 | if (request->actual == request->length || len < musb_ep->packet_sz) |
| 731 | musb_g_giveback(musb_ep, request, 0); |
| 732 | } |
| 733 | |
| 734 | /* |
| 735 | * Data ready for a request; called from IRQ |
| 736 | */ |
| 737 | void musb_g_rx(struct musb *musb, u8 epnum) |
| 738 | { |
| 739 | u16 csr; |
| 740 | struct usb_request *request; |
| 741 | void __iomem *mbase = musb->mregs; |
| 742 | struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_out; |
| 743 | void __iomem *epio = musb->endpoints[epnum].regs; |
| 744 | struct dma_channel *dma; |
| 745 | |
| 746 | musb_ep_select(mbase, epnum); |
| 747 | |
| 748 | request = next_request(musb_ep); |
| 749 | |
| 750 | csr = musb_readw(epio, MUSB_RXCSR); |
| 751 | dma = is_dma_capable() ? musb_ep->dma : NULL; |
| 752 | |
| 753 | DBG(4, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name, |
| 754 | csr, dma ? " (dma)" : "", request); |
| 755 | |
| 756 | if (csr & MUSB_RXCSR_P_SENTSTALL) { |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 757 | csr |= MUSB_RXCSR_P_WZC_BITS; |
| 758 | csr &= ~MUSB_RXCSR_P_SENTSTALL; |
| 759 | musb_writew(epio, MUSB_RXCSR, csr); |
Sergei Shtylyov | cea8324 | 2009-11-18 22:51:18 +0300 | [diff] [blame] | 760 | return; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 761 | } |
| 762 | |
| 763 | if (csr & MUSB_RXCSR_P_OVERRUN) { |
| 764 | /* csr |= MUSB_RXCSR_P_WZC_BITS; */ |
| 765 | csr &= ~MUSB_RXCSR_P_OVERRUN; |
| 766 | musb_writew(epio, MUSB_RXCSR, csr); |
| 767 | |
| 768 | DBG(3, "%s iso overrun on %p\n", musb_ep->name, request); |
| 769 | if (request && request->status == -EINPROGRESS) |
| 770 | request->status = -EOVERFLOW; |
| 771 | } |
| 772 | if (csr & MUSB_RXCSR_INCOMPRX) { |
| 773 | /* REVISIT not necessarily an error */ |
| 774 | DBG(4, "%s, incomprx\n", musb_ep->end_point.name); |
| 775 | } |
| 776 | |
| 777 | if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) { |
| 778 | /* "should not happen"; likely RXPKTRDY pending for DMA */ |
| 779 | DBG((csr & MUSB_RXCSR_DMAENAB) ? 4 : 1, |
| 780 | "%s busy, csr %04x\n", |
| 781 | musb_ep->end_point.name, csr); |
Sergei Shtylyov | cea8324 | 2009-11-18 22:51:18 +0300 | [diff] [blame] | 782 | return; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 783 | } |
| 784 | |
| 785 | if (dma && (csr & MUSB_RXCSR_DMAENAB)) { |
| 786 | csr &= ~(MUSB_RXCSR_AUTOCLEAR |
| 787 | | MUSB_RXCSR_DMAENAB |
| 788 | | MUSB_RXCSR_DMAMODE); |
| 789 | musb_writew(epio, MUSB_RXCSR, |
| 790 | MUSB_RXCSR_P_WZC_BITS | csr); |
| 791 | |
| 792 | request->actual += musb_ep->dma->actual_len; |
| 793 | |
| 794 | DBG(4, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n", |
| 795 | epnum, csr, |
| 796 | musb_readw(epio, MUSB_RXCSR), |
| 797 | musb_ep->dma->actual_len, request); |
| 798 | |
| 799 | #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) |
| 800 | /* Autoclear doesn't clear RxPktRdy for short packets */ |
| 801 | if ((dma->desired_mode == 0) |
| 802 | || (dma->actual_len |
| 803 | & (musb_ep->packet_sz - 1))) { |
| 804 | /* ack the read! */ |
| 805 | csr &= ~MUSB_RXCSR_RXPKTRDY; |
| 806 | musb_writew(epio, MUSB_RXCSR, csr); |
| 807 | } |
| 808 | |
| 809 | /* incomplete, and not short? wait for next IN packet */ |
| 810 | if ((request->actual < request->length) |
| 811 | && (musb_ep->dma->actual_len |
| 812 | == musb_ep->packet_sz)) |
Sergei Shtylyov | cea8324 | 2009-11-18 22:51:18 +0300 | [diff] [blame] | 813 | return; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 814 | #endif |
| 815 | musb_g_giveback(musb_ep, request, 0); |
| 816 | |
| 817 | request = next_request(musb_ep); |
| 818 | if (!request) |
Sergei Shtylyov | cea8324 | 2009-11-18 22:51:18 +0300 | [diff] [blame] | 819 | return; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 820 | } |
| 821 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 822 | /* analyze request if the ep is hot */ |
| 823 | if (request) |
| 824 | rxstate(musb, to_musb_request(request)); |
| 825 | else |
| 826 | DBG(3, "packet waiting for %s%s request\n", |
| 827 | musb_ep->desc ? "" : "inactive ", |
| 828 | musb_ep->end_point.name); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 829 | return; |
| 830 | } |
| 831 | |
| 832 | /* ------------------------------------------------------------ */ |
| 833 | |
| 834 | static int musb_gadget_enable(struct usb_ep *ep, |
| 835 | const struct usb_endpoint_descriptor *desc) |
| 836 | { |
| 837 | unsigned long flags; |
| 838 | struct musb_ep *musb_ep; |
| 839 | struct musb_hw_ep *hw_ep; |
| 840 | void __iomem *regs; |
| 841 | struct musb *musb; |
| 842 | void __iomem *mbase; |
| 843 | u8 epnum; |
| 844 | u16 csr; |
| 845 | unsigned tmp; |
| 846 | int status = -EINVAL; |
| 847 | |
| 848 | if (!ep || !desc) |
| 849 | return -EINVAL; |
| 850 | |
| 851 | musb_ep = to_musb_ep(ep); |
| 852 | hw_ep = musb_ep->hw_ep; |
| 853 | regs = hw_ep->regs; |
| 854 | musb = musb_ep->musb; |
| 855 | mbase = musb->mregs; |
| 856 | epnum = musb_ep->current_epnum; |
| 857 | |
| 858 | spin_lock_irqsave(&musb->lock, flags); |
| 859 | |
| 860 | if (musb_ep->desc) { |
| 861 | status = -EBUSY; |
| 862 | goto fail; |
| 863 | } |
Julia Lawall | 96bcd09 | 2009-01-24 17:57:24 -0800 | [diff] [blame] | 864 | musb_ep->type = usb_endpoint_type(desc); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 865 | |
| 866 | /* check direction and (later) maxpacket size against endpoint */ |
Julia Lawall | 96bcd09 | 2009-01-24 17:57:24 -0800 | [diff] [blame] | 867 | if (usb_endpoint_num(desc) != epnum) |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 868 | goto fail; |
| 869 | |
| 870 | /* REVISIT this rules out high bandwidth periodic transfers */ |
| 871 | tmp = le16_to_cpu(desc->wMaxPacketSize); |
| 872 | if (tmp & ~0x07ff) |
| 873 | goto fail; |
| 874 | musb_ep->packet_sz = tmp; |
| 875 | |
| 876 | /* enable the interrupts for the endpoint, set the endpoint |
| 877 | * packet size (or fail), set the mode, clear the fifo |
| 878 | */ |
| 879 | musb_ep_select(mbase, epnum); |
Julia Lawall | 96bcd09 | 2009-01-24 17:57:24 -0800 | [diff] [blame] | 880 | if (usb_endpoint_dir_in(desc)) { |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 881 | u16 int_txe = musb_readw(mbase, MUSB_INTRTXE); |
| 882 | |
| 883 | if (hw_ep->is_shared_fifo) |
| 884 | musb_ep->is_in = 1; |
| 885 | if (!musb_ep->is_in) |
| 886 | goto fail; |
| 887 | if (tmp > hw_ep->max_packet_sz_tx) |
| 888 | goto fail; |
| 889 | |
| 890 | int_txe |= (1 << epnum); |
| 891 | musb_writew(mbase, MUSB_INTRTXE, int_txe); |
| 892 | |
| 893 | /* REVISIT if can_bulk_split(), use by updating "tmp"; |
| 894 | * likewise high bandwidth periodic tx |
| 895 | */ |
| 896 | musb_writew(regs, MUSB_TXMAXP, tmp); |
| 897 | |
| 898 | csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG; |
| 899 | if (musb_readw(regs, MUSB_TXCSR) |
| 900 | & MUSB_TXCSR_FIFONOTEMPTY) |
| 901 | csr |= MUSB_TXCSR_FLUSHFIFO; |
| 902 | if (musb_ep->type == USB_ENDPOINT_XFER_ISOC) |
| 903 | csr |= MUSB_TXCSR_P_ISO; |
| 904 | |
| 905 | /* set twice in case of double buffering */ |
| 906 | musb_writew(regs, MUSB_TXCSR, csr); |
| 907 | /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */ |
| 908 | musb_writew(regs, MUSB_TXCSR, csr); |
| 909 | |
| 910 | } else { |
| 911 | u16 int_rxe = musb_readw(mbase, MUSB_INTRRXE); |
| 912 | |
| 913 | if (hw_ep->is_shared_fifo) |
| 914 | musb_ep->is_in = 0; |
| 915 | if (musb_ep->is_in) |
| 916 | goto fail; |
| 917 | if (tmp > hw_ep->max_packet_sz_rx) |
| 918 | goto fail; |
| 919 | |
| 920 | int_rxe |= (1 << epnum); |
| 921 | musb_writew(mbase, MUSB_INTRRXE, int_rxe); |
| 922 | |
| 923 | /* REVISIT if can_bulk_combine() use by updating "tmp" |
| 924 | * likewise high bandwidth periodic rx |
| 925 | */ |
| 926 | musb_writew(regs, MUSB_RXMAXP, tmp); |
| 927 | |
| 928 | /* force shared fifo to OUT-only mode */ |
| 929 | if (hw_ep->is_shared_fifo) { |
| 930 | csr = musb_readw(regs, MUSB_TXCSR); |
| 931 | csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY); |
| 932 | musb_writew(regs, MUSB_TXCSR, csr); |
| 933 | } |
| 934 | |
| 935 | csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG; |
| 936 | if (musb_ep->type == USB_ENDPOINT_XFER_ISOC) |
| 937 | csr |= MUSB_RXCSR_P_ISO; |
| 938 | else if (musb_ep->type == USB_ENDPOINT_XFER_INT) |
| 939 | csr |= MUSB_RXCSR_DISNYET; |
| 940 | |
| 941 | /* set twice in case of double buffering */ |
| 942 | musb_writew(regs, MUSB_RXCSR, csr); |
| 943 | musb_writew(regs, MUSB_RXCSR, csr); |
| 944 | } |
| 945 | |
| 946 | /* NOTE: all the I/O code _should_ work fine without DMA, in case |
| 947 | * for some reason you run out of channels here. |
| 948 | */ |
| 949 | if (is_dma_capable() && musb->dma_controller) { |
| 950 | struct dma_controller *c = musb->dma_controller; |
| 951 | |
| 952 | musb_ep->dma = c->channel_alloc(c, hw_ep, |
| 953 | (desc->bEndpointAddress & USB_DIR_IN)); |
| 954 | } else |
| 955 | musb_ep->dma = NULL; |
| 956 | |
| 957 | musb_ep->desc = desc; |
| 958 | musb_ep->busy = 0; |
Sergei Shtylyov | 47e9760 | 2009-11-18 22:51:51 +0300 | [diff] [blame] | 959 | musb_ep->wedged = 0; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 960 | status = 0; |
| 961 | |
| 962 | pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n", |
| 963 | musb_driver_name, musb_ep->end_point.name, |
| 964 | ({ char *s; switch (musb_ep->type) { |
| 965 | case USB_ENDPOINT_XFER_BULK: s = "bulk"; break; |
| 966 | case USB_ENDPOINT_XFER_INT: s = "int"; break; |
| 967 | default: s = "iso"; break; |
| 968 | }; s; }), |
| 969 | musb_ep->is_in ? "IN" : "OUT", |
| 970 | musb_ep->dma ? "dma, " : "", |
| 971 | musb_ep->packet_sz); |
| 972 | |
| 973 | schedule_work(&musb->irq_work); |
| 974 | |
| 975 | fail: |
| 976 | spin_unlock_irqrestore(&musb->lock, flags); |
| 977 | return status; |
| 978 | } |
| 979 | |
| 980 | /* |
| 981 | * Disable an endpoint flushing all requests queued. |
| 982 | */ |
| 983 | static int musb_gadget_disable(struct usb_ep *ep) |
| 984 | { |
| 985 | unsigned long flags; |
| 986 | struct musb *musb; |
| 987 | u8 epnum; |
| 988 | struct musb_ep *musb_ep; |
| 989 | void __iomem *epio; |
| 990 | int status = 0; |
| 991 | |
| 992 | musb_ep = to_musb_ep(ep); |
| 993 | musb = musb_ep->musb; |
| 994 | epnum = musb_ep->current_epnum; |
| 995 | epio = musb->endpoints[epnum].regs; |
| 996 | |
| 997 | spin_lock_irqsave(&musb->lock, flags); |
| 998 | musb_ep_select(musb->mregs, epnum); |
| 999 | |
| 1000 | /* zero the endpoint sizes */ |
| 1001 | if (musb_ep->is_in) { |
| 1002 | u16 int_txe = musb_readw(musb->mregs, MUSB_INTRTXE); |
| 1003 | int_txe &= ~(1 << epnum); |
| 1004 | musb_writew(musb->mregs, MUSB_INTRTXE, int_txe); |
| 1005 | musb_writew(epio, MUSB_TXMAXP, 0); |
| 1006 | } else { |
| 1007 | u16 int_rxe = musb_readw(musb->mregs, MUSB_INTRRXE); |
| 1008 | int_rxe &= ~(1 << epnum); |
| 1009 | musb_writew(musb->mregs, MUSB_INTRRXE, int_rxe); |
| 1010 | musb_writew(epio, MUSB_RXMAXP, 0); |
| 1011 | } |
| 1012 | |
| 1013 | musb_ep->desc = NULL; |
| 1014 | |
| 1015 | /* abort all pending DMA and requests */ |
| 1016 | nuke(musb_ep, -ESHUTDOWN); |
| 1017 | |
| 1018 | schedule_work(&musb->irq_work); |
| 1019 | |
| 1020 | spin_unlock_irqrestore(&(musb->lock), flags); |
| 1021 | |
| 1022 | DBG(2, "%s\n", musb_ep->end_point.name); |
| 1023 | |
| 1024 | return status; |
| 1025 | } |
| 1026 | |
| 1027 | /* |
| 1028 | * Allocate a request for an endpoint. |
| 1029 | * Reused by ep0 code. |
| 1030 | */ |
| 1031 | struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags) |
| 1032 | { |
| 1033 | struct musb_ep *musb_ep = to_musb_ep(ep); |
| 1034 | struct musb_request *request = NULL; |
| 1035 | |
| 1036 | request = kzalloc(sizeof *request, gfp_flags); |
| 1037 | if (request) { |
| 1038 | INIT_LIST_HEAD(&request->request.list); |
| 1039 | request->request.dma = DMA_ADDR_INVALID; |
| 1040 | request->epnum = musb_ep->current_epnum; |
| 1041 | request->ep = musb_ep; |
| 1042 | } |
| 1043 | |
| 1044 | return &request->request; |
| 1045 | } |
| 1046 | |
| 1047 | /* |
| 1048 | * Free a request |
| 1049 | * Reused by ep0 code. |
| 1050 | */ |
| 1051 | void musb_free_request(struct usb_ep *ep, struct usb_request *req) |
| 1052 | { |
| 1053 | kfree(to_musb_request(req)); |
| 1054 | } |
| 1055 | |
| 1056 | static LIST_HEAD(buffers); |
| 1057 | |
| 1058 | struct free_record { |
| 1059 | struct list_head list; |
| 1060 | struct device *dev; |
| 1061 | unsigned bytes; |
| 1062 | dma_addr_t dma; |
| 1063 | }; |
| 1064 | |
| 1065 | /* |
| 1066 | * Context: controller locked, IRQs blocked. |
| 1067 | */ |
| 1068 | static void musb_ep_restart(struct musb *musb, struct musb_request *req) |
| 1069 | { |
| 1070 | DBG(3, "<== %s request %p len %u on hw_ep%d\n", |
| 1071 | req->tx ? "TX/IN" : "RX/OUT", |
| 1072 | &req->request, req->request.length, req->epnum); |
| 1073 | |
| 1074 | musb_ep_select(musb->mregs, req->epnum); |
| 1075 | if (req->tx) |
| 1076 | txstate(musb, req); |
| 1077 | else |
| 1078 | rxstate(musb, req); |
| 1079 | } |
| 1080 | |
| 1081 | static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req, |
| 1082 | gfp_t gfp_flags) |
| 1083 | { |
| 1084 | struct musb_ep *musb_ep; |
| 1085 | struct musb_request *request; |
| 1086 | struct musb *musb; |
| 1087 | int status = 0; |
| 1088 | unsigned long lockflags; |
| 1089 | |
| 1090 | if (!ep || !req) |
| 1091 | return -EINVAL; |
| 1092 | if (!req->buf) |
| 1093 | return -ENODATA; |
| 1094 | |
| 1095 | musb_ep = to_musb_ep(ep); |
| 1096 | musb = musb_ep->musb; |
| 1097 | |
| 1098 | request = to_musb_request(req); |
| 1099 | request->musb = musb; |
| 1100 | |
| 1101 | if (request->ep != musb_ep) |
| 1102 | return -EINVAL; |
| 1103 | |
| 1104 | DBG(4, "<== to %s request=%p\n", ep->name, req); |
| 1105 | |
| 1106 | /* request is mine now... */ |
| 1107 | request->request.actual = 0; |
| 1108 | request->request.status = -EINPROGRESS; |
| 1109 | request->epnum = musb_ep->current_epnum; |
| 1110 | request->tx = musb_ep->is_in; |
| 1111 | |
| 1112 | if (is_dma_capable() && musb_ep->dma) { |
| 1113 | if (request->request.dma == DMA_ADDR_INVALID) { |
| 1114 | request->request.dma = dma_map_single( |
| 1115 | musb->controller, |
| 1116 | request->request.buf, |
| 1117 | request->request.length, |
| 1118 | request->tx |
| 1119 | ? DMA_TO_DEVICE |
| 1120 | : DMA_FROM_DEVICE); |
| 1121 | request->mapped = 1; |
| 1122 | } else { |
| 1123 | dma_sync_single_for_device(musb->controller, |
| 1124 | request->request.dma, |
| 1125 | request->request.length, |
| 1126 | request->tx |
| 1127 | ? DMA_TO_DEVICE |
| 1128 | : DMA_FROM_DEVICE); |
| 1129 | request->mapped = 0; |
| 1130 | } |
| 1131 | } else if (!req->buf) { |
| 1132 | return -ENODATA; |
| 1133 | } else |
| 1134 | request->mapped = 0; |
| 1135 | |
| 1136 | spin_lock_irqsave(&musb->lock, lockflags); |
| 1137 | |
| 1138 | /* don't queue if the ep is down */ |
| 1139 | if (!musb_ep->desc) { |
| 1140 | DBG(4, "req %p queued to %s while ep %s\n", |
| 1141 | req, ep->name, "disabled"); |
| 1142 | status = -ESHUTDOWN; |
| 1143 | goto cleanup; |
| 1144 | } |
| 1145 | |
| 1146 | /* add request to the list */ |
| 1147 | list_add_tail(&(request->request.list), &(musb_ep->req_list)); |
| 1148 | |
| 1149 | /* it this is the head of the queue, start i/o ... */ |
| 1150 | if (!musb_ep->busy && &request->request.list == musb_ep->req_list.next) |
| 1151 | musb_ep_restart(musb, request); |
| 1152 | |
| 1153 | cleanup: |
| 1154 | spin_unlock_irqrestore(&musb->lock, lockflags); |
| 1155 | return status; |
| 1156 | } |
| 1157 | |
| 1158 | static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request) |
| 1159 | { |
| 1160 | struct musb_ep *musb_ep = to_musb_ep(ep); |
| 1161 | struct usb_request *r; |
| 1162 | unsigned long flags; |
| 1163 | int status = 0; |
| 1164 | struct musb *musb = musb_ep->musb; |
| 1165 | |
| 1166 | if (!ep || !request || to_musb_request(request)->ep != musb_ep) |
| 1167 | return -EINVAL; |
| 1168 | |
| 1169 | spin_lock_irqsave(&musb->lock, flags); |
| 1170 | |
| 1171 | list_for_each_entry(r, &musb_ep->req_list, list) { |
| 1172 | if (r == request) |
| 1173 | break; |
| 1174 | } |
| 1175 | if (r != request) { |
| 1176 | DBG(3, "request %p not queued to %s\n", request, ep->name); |
| 1177 | status = -EINVAL; |
| 1178 | goto done; |
| 1179 | } |
| 1180 | |
| 1181 | /* if the hardware doesn't have the request, easy ... */ |
| 1182 | if (musb_ep->req_list.next != &request->list || musb_ep->busy) |
| 1183 | musb_g_giveback(musb_ep, request, -ECONNRESET); |
| 1184 | |
| 1185 | /* ... else abort the dma transfer ... */ |
| 1186 | else if (is_dma_capable() && musb_ep->dma) { |
| 1187 | struct dma_controller *c = musb->dma_controller; |
| 1188 | |
| 1189 | musb_ep_select(musb->mregs, musb_ep->current_epnum); |
| 1190 | if (c->channel_abort) |
| 1191 | status = c->channel_abort(musb_ep->dma); |
| 1192 | else |
| 1193 | status = -EBUSY; |
| 1194 | if (status == 0) |
| 1195 | musb_g_giveback(musb_ep, request, -ECONNRESET); |
| 1196 | } else { |
| 1197 | /* NOTE: by sticking to easily tested hardware/driver states, |
| 1198 | * we leave counting of in-flight packets imprecise. |
| 1199 | */ |
| 1200 | musb_g_giveback(musb_ep, request, -ECONNRESET); |
| 1201 | } |
| 1202 | |
| 1203 | done: |
| 1204 | spin_unlock_irqrestore(&musb->lock, flags); |
| 1205 | return status; |
| 1206 | } |
| 1207 | |
| 1208 | /* |
| 1209 | * Set or clear the halt bit of an endpoint. A halted enpoint won't tx/rx any |
| 1210 | * data but will queue requests. |
| 1211 | * |
| 1212 | * exported to ep0 code |
| 1213 | */ |
Felipe Balbi | 1b6c3b0 | 2009-12-04 15:47:46 +0200 | [diff] [blame] | 1214 | static int musb_gadget_set_halt(struct usb_ep *ep, int value) |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1215 | { |
| 1216 | struct musb_ep *musb_ep = to_musb_ep(ep); |
| 1217 | u8 epnum = musb_ep->current_epnum; |
| 1218 | struct musb *musb = musb_ep->musb; |
| 1219 | void __iomem *epio = musb->endpoints[epnum].regs; |
| 1220 | void __iomem *mbase; |
| 1221 | unsigned long flags; |
| 1222 | u16 csr; |
Sergei Shtylyov | cea8324 | 2009-11-18 22:51:18 +0300 | [diff] [blame] | 1223 | struct musb_request *request; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1224 | int status = 0; |
| 1225 | |
| 1226 | if (!ep) |
| 1227 | return -EINVAL; |
| 1228 | mbase = musb->mregs; |
| 1229 | |
| 1230 | spin_lock_irqsave(&musb->lock, flags); |
| 1231 | |
| 1232 | if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) { |
| 1233 | status = -EINVAL; |
| 1234 | goto done; |
| 1235 | } |
| 1236 | |
| 1237 | musb_ep_select(mbase, epnum); |
| 1238 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1239 | request = to_musb_request(next_request(musb_ep)); |
Sergei Shtylyov | cea8324 | 2009-11-18 22:51:18 +0300 | [diff] [blame] | 1240 | if (value) { |
| 1241 | if (request) { |
| 1242 | DBG(3, "request in progress, cannot halt %s\n", |
| 1243 | ep->name); |
| 1244 | status = -EAGAIN; |
| 1245 | goto done; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1246 | } |
Sergei Shtylyov | cea8324 | 2009-11-18 22:51:18 +0300 | [diff] [blame] | 1247 | /* Cannot portably stall with non-empty FIFO */ |
| 1248 | if (musb_ep->is_in) { |
| 1249 | csr = musb_readw(epio, MUSB_TXCSR); |
| 1250 | if (csr & MUSB_TXCSR_FIFONOTEMPTY) { |
| 1251 | DBG(3, "FIFO busy, cannot halt %s\n", ep->name); |
| 1252 | status = -EAGAIN; |
| 1253 | goto done; |
| 1254 | } |
| 1255 | } |
Sergei Shtylyov | 47e9760 | 2009-11-18 22:51:51 +0300 | [diff] [blame] | 1256 | } else |
| 1257 | musb_ep->wedged = 0; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1258 | |
| 1259 | /* set/clear the stall and toggle bits */ |
| 1260 | DBG(2, "%s: %s stall\n", ep->name, value ? "set" : "clear"); |
| 1261 | if (musb_ep->is_in) { |
| 1262 | csr = musb_readw(epio, MUSB_TXCSR); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1263 | csr |= MUSB_TXCSR_P_WZC_BITS |
| 1264 | | MUSB_TXCSR_CLRDATATOG; |
| 1265 | if (value) |
| 1266 | csr |= MUSB_TXCSR_P_SENDSTALL; |
| 1267 | else |
| 1268 | csr &= ~(MUSB_TXCSR_P_SENDSTALL |
| 1269 | | MUSB_TXCSR_P_SENTSTALL); |
| 1270 | csr &= ~MUSB_TXCSR_TXPKTRDY; |
| 1271 | musb_writew(epio, MUSB_TXCSR, csr); |
| 1272 | } else { |
| 1273 | csr = musb_readw(epio, MUSB_RXCSR); |
| 1274 | csr |= MUSB_RXCSR_P_WZC_BITS |
| 1275 | | MUSB_RXCSR_FLUSHFIFO |
| 1276 | | MUSB_RXCSR_CLRDATATOG; |
| 1277 | if (value) |
| 1278 | csr |= MUSB_RXCSR_P_SENDSTALL; |
| 1279 | else |
| 1280 | csr &= ~(MUSB_RXCSR_P_SENDSTALL |
| 1281 | | MUSB_RXCSR_P_SENTSTALL); |
| 1282 | musb_writew(epio, MUSB_RXCSR, csr); |
| 1283 | } |
| 1284 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1285 | /* maybe start the first request in the queue */ |
| 1286 | if (!musb_ep->busy && !value && request) { |
| 1287 | DBG(3, "restarting the request\n"); |
| 1288 | musb_ep_restart(musb, request); |
| 1289 | } |
| 1290 | |
Sergei Shtylyov | cea8324 | 2009-11-18 22:51:18 +0300 | [diff] [blame] | 1291 | done: |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1292 | spin_unlock_irqrestore(&musb->lock, flags); |
| 1293 | return status; |
| 1294 | } |
| 1295 | |
Sergei Shtylyov | 47e9760 | 2009-11-18 22:51:51 +0300 | [diff] [blame] | 1296 | /* |
| 1297 | * Sets the halt feature with the clear requests ignored |
| 1298 | */ |
Felipe Balbi | 1b6c3b0 | 2009-12-04 15:47:46 +0200 | [diff] [blame] | 1299 | static int musb_gadget_set_wedge(struct usb_ep *ep) |
Sergei Shtylyov | 47e9760 | 2009-11-18 22:51:51 +0300 | [diff] [blame] | 1300 | { |
| 1301 | struct musb_ep *musb_ep = to_musb_ep(ep); |
| 1302 | |
| 1303 | if (!ep) |
| 1304 | return -EINVAL; |
| 1305 | |
| 1306 | musb_ep->wedged = 1; |
| 1307 | |
| 1308 | return usb_ep_set_halt(ep); |
| 1309 | } |
| 1310 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1311 | static int musb_gadget_fifo_status(struct usb_ep *ep) |
| 1312 | { |
| 1313 | struct musb_ep *musb_ep = to_musb_ep(ep); |
| 1314 | void __iomem *epio = musb_ep->hw_ep->regs; |
| 1315 | int retval = -EINVAL; |
| 1316 | |
| 1317 | if (musb_ep->desc && !musb_ep->is_in) { |
| 1318 | struct musb *musb = musb_ep->musb; |
| 1319 | int epnum = musb_ep->current_epnum; |
| 1320 | void __iomem *mbase = musb->mregs; |
| 1321 | unsigned long flags; |
| 1322 | |
| 1323 | spin_lock_irqsave(&musb->lock, flags); |
| 1324 | |
| 1325 | musb_ep_select(mbase, epnum); |
| 1326 | /* FIXME return zero unless RXPKTRDY is set */ |
| 1327 | retval = musb_readw(epio, MUSB_RXCOUNT); |
| 1328 | |
| 1329 | spin_unlock_irqrestore(&musb->lock, flags); |
| 1330 | } |
| 1331 | return retval; |
| 1332 | } |
| 1333 | |
| 1334 | static void musb_gadget_fifo_flush(struct usb_ep *ep) |
| 1335 | { |
| 1336 | struct musb_ep *musb_ep = to_musb_ep(ep); |
| 1337 | struct musb *musb = musb_ep->musb; |
| 1338 | u8 epnum = musb_ep->current_epnum; |
| 1339 | void __iomem *epio = musb->endpoints[epnum].regs; |
| 1340 | void __iomem *mbase; |
| 1341 | unsigned long flags; |
| 1342 | u16 csr, int_txe; |
| 1343 | |
| 1344 | mbase = musb->mregs; |
| 1345 | |
| 1346 | spin_lock_irqsave(&musb->lock, flags); |
| 1347 | musb_ep_select(mbase, (u8) epnum); |
| 1348 | |
| 1349 | /* disable interrupts */ |
| 1350 | int_txe = musb_readw(mbase, MUSB_INTRTXE); |
| 1351 | musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum)); |
| 1352 | |
| 1353 | if (musb_ep->is_in) { |
| 1354 | csr = musb_readw(epio, MUSB_TXCSR); |
| 1355 | if (csr & MUSB_TXCSR_FIFONOTEMPTY) { |
| 1356 | csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS; |
| 1357 | musb_writew(epio, MUSB_TXCSR, csr); |
| 1358 | /* REVISIT may be inappropriate w/o FIFONOTEMPTY ... */ |
| 1359 | musb_writew(epio, MUSB_TXCSR, csr); |
| 1360 | } |
| 1361 | } else { |
| 1362 | csr = musb_readw(epio, MUSB_RXCSR); |
| 1363 | csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS; |
| 1364 | musb_writew(epio, MUSB_RXCSR, csr); |
| 1365 | musb_writew(epio, MUSB_RXCSR, csr); |
| 1366 | } |
| 1367 | |
| 1368 | /* re-enable interrupt */ |
| 1369 | musb_writew(mbase, MUSB_INTRTXE, int_txe); |
| 1370 | spin_unlock_irqrestore(&musb->lock, flags); |
| 1371 | } |
| 1372 | |
| 1373 | static const struct usb_ep_ops musb_ep_ops = { |
| 1374 | .enable = musb_gadget_enable, |
| 1375 | .disable = musb_gadget_disable, |
| 1376 | .alloc_request = musb_alloc_request, |
| 1377 | .free_request = musb_free_request, |
| 1378 | .queue = musb_gadget_queue, |
| 1379 | .dequeue = musb_gadget_dequeue, |
| 1380 | .set_halt = musb_gadget_set_halt, |
Sergei Shtylyov | 47e9760 | 2009-11-18 22:51:51 +0300 | [diff] [blame] | 1381 | .set_wedge = musb_gadget_set_wedge, |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1382 | .fifo_status = musb_gadget_fifo_status, |
| 1383 | .fifo_flush = musb_gadget_fifo_flush |
| 1384 | }; |
| 1385 | |
| 1386 | /* ----------------------------------------------------------------------- */ |
| 1387 | |
| 1388 | static int musb_gadget_get_frame(struct usb_gadget *gadget) |
| 1389 | { |
| 1390 | struct musb *musb = gadget_to_musb(gadget); |
| 1391 | |
| 1392 | return (int)musb_readw(musb->mregs, MUSB_FRAME); |
| 1393 | } |
| 1394 | |
| 1395 | static int musb_gadget_wakeup(struct usb_gadget *gadget) |
| 1396 | { |
| 1397 | struct musb *musb = gadget_to_musb(gadget); |
| 1398 | void __iomem *mregs = musb->mregs; |
| 1399 | unsigned long flags; |
| 1400 | int status = -EINVAL; |
| 1401 | u8 power, devctl; |
| 1402 | int retries; |
| 1403 | |
| 1404 | spin_lock_irqsave(&musb->lock, flags); |
| 1405 | |
David Brownell | 84e250f | 2009-03-31 12:30:04 -0700 | [diff] [blame] | 1406 | switch (musb->xceiv->state) { |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1407 | case OTG_STATE_B_PERIPHERAL: |
| 1408 | /* NOTE: OTG state machine doesn't include B_SUSPENDED; |
| 1409 | * that's part of the standard usb 1.1 state machine, and |
| 1410 | * doesn't affect OTG transitions. |
| 1411 | */ |
| 1412 | if (musb->may_wakeup && musb->is_suspended) |
| 1413 | break; |
| 1414 | goto done; |
| 1415 | case OTG_STATE_B_IDLE: |
| 1416 | /* Start SRP ... OTG not required. */ |
| 1417 | devctl = musb_readb(mregs, MUSB_DEVCTL); |
| 1418 | DBG(2, "Sending SRP: devctl: %02x\n", devctl); |
| 1419 | devctl |= MUSB_DEVCTL_SESSION; |
| 1420 | musb_writeb(mregs, MUSB_DEVCTL, devctl); |
| 1421 | devctl = musb_readb(mregs, MUSB_DEVCTL); |
| 1422 | retries = 100; |
| 1423 | while (!(devctl & MUSB_DEVCTL_SESSION)) { |
| 1424 | devctl = musb_readb(mregs, MUSB_DEVCTL); |
| 1425 | if (retries-- < 1) |
| 1426 | break; |
| 1427 | } |
| 1428 | retries = 10000; |
| 1429 | while (devctl & MUSB_DEVCTL_SESSION) { |
| 1430 | devctl = musb_readb(mregs, MUSB_DEVCTL); |
| 1431 | if (retries-- < 1) |
| 1432 | break; |
| 1433 | } |
| 1434 | |
| 1435 | /* Block idling for at least 1s */ |
| 1436 | musb_platform_try_idle(musb, |
| 1437 | jiffies + msecs_to_jiffies(1 * HZ)); |
| 1438 | |
| 1439 | status = 0; |
| 1440 | goto done; |
| 1441 | default: |
| 1442 | DBG(2, "Unhandled wake: %s\n", otg_state_string(musb)); |
| 1443 | goto done; |
| 1444 | } |
| 1445 | |
| 1446 | status = 0; |
| 1447 | |
| 1448 | power = musb_readb(mregs, MUSB_POWER); |
| 1449 | power |= MUSB_POWER_RESUME; |
| 1450 | musb_writeb(mregs, MUSB_POWER, power); |
| 1451 | DBG(2, "issue wakeup\n"); |
| 1452 | |
| 1453 | /* FIXME do this next chunk in a timer callback, no udelay */ |
| 1454 | mdelay(2); |
| 1455 | |
| 1456 | power = musb_readb(mregs, MUSB_POWER); |
| 1457 | power &= ~MUSB_POWER_RESUME; |
| 1458 | musb_writeb(mregs, MUSB_POWER, power); |
| 1459 | done: |
| 1460 | spin_unlock_irqrestore(&musb->lock, flags); |
| 1461 | return status; |
| 1462 | } |
| 1463 | |
| 1464 | static int |
| 1465 | musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered) |
| 1466 | { |
| 1467 | struct musb *musb = gadget_to_musb(gadget); |
| 1468 | |
| 1469 | musb->is_self_powered = !!is_selfpowered; |
| 1470 | return 0; |
| 1471 | } |
| 1472 | |
| 1473 | static void musb_pullup(struct musb *musb, int is_on) |
| 1474 | { |
| 1475 | u8 power; |
| 1476 | |
| 1477 | power = musb_readb(musb->mregs, MUSB_POWER); |
| 1478 | if (is_on) |
| 1479 | power |= MUSB_POWER_SOFTCONN; |
| 1480 | else |
| 1481 | power &= ~MUSB_POWER_SOFTCONN; |
| 1482 | |
| 1483 | /* FIXME if on, HdrcStart; if off, HdrcStop */ |
| 1484 | |
| 1485 | DBG(3, "gadget %s D+ pullup %s\n", |
| 1486 | musb->gadget_driver->function, is_on ? "on" : "off"); |
| 1487 | musb_writeb(musb->mregs, MUSB_POWER, power); |
| 1488 | } |
| 1489 | |
| 1490 | #if 0 |
| 1491 | static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active) |
| 1492 | { |
| 1493 | DBG(2, "<= %s =>\n", __func__); |
| 1494 | |
| 1495 | /* |
| 1496 | * FIXME iff driver's softconnect flag is set (as it is during probe, |
| 1497 | * though that can clear it), just musb_pullup(). |
| 1498 | */ |
| 1499 | |
| 1500 | return -EINVAL; |
| 1501 | } |
| 1502 | #endif |
| 1503 | |
| 1504 | static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA) |
| 1505 | { |
| 1506 | struct musb *musb = gadget_to_musb(gadget); |
| 1507 | |
David Brownell | 84e250f | 2009-03-31 12:30:04 -0700 | [diff] [blame] | 1508 | if (!musb->xceiv->set_power) |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1509 | return -EOPNOTSUPP; |
David Brownell | 84e250f | 2009-03-31 12:30:04 -0700 | [diff] [blame] | 1510 | return otg_set_power(musb->xceiv, mA); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1511 | } |
| 1512 | |
| 1513 | static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on) |
| 1514 | { |
| 1515 | struct musb *musb = gadget_to_musb(gadget); |
| 1516 | unsigned long flags; |
| 1517 | |
| 1518 | is_on = !!is_on; |
| 1519 | |
| 1520 | /* NOTE: this assumes we are sensing vbus; we'd rather |
| 1521 | * not pullup unless the B-session is active. |
| 1522 | */ |
| 1523 | spin_lock_irqsave(&musb->lock, flags); |
| 1524 | if (is_on != musb->softconnect) { |
| 1525 | musb->softconnect = is_on; |
| 1526 | musb_pullup(musb, is_on); |
| 1527 | } |
| 1528 | spin_unlock_irqrestore(&musb->lock, flags); |
| 1529 | return 0; |
| 1530 | } |
| 1531 | |
| 1532 | static const struct usb_gadget_ops musb_gadget_operations = { |
| 1533 | .get_frame = musb_gadget_get_frame, |
| 1534 | .wakeup = musb_gadget_wakeup, |
| 1535 | .set_selfpowered = musb_gadget_set_self_powered, |
| 1536 | /* .vbus_session = musb_gadget_vbus_session, */ |
| 1537 | .vbus_draw = musb_gadget_vbus_draw, |
| 1538 | .pullup = musb_gadget_pullup, |
| 1539 | }; |
| 1540 | |
| 1541 | /* ----------------------------------------------------------------------- */ |
| 1542 | |
| 1543 | /* Registration */ |
| 1544 | |
| 1545 | /* Only this registration code "knows" the rule (from USB standards) |
| 1546 | * about there being only one external upstream port. It assumes |
| 1547 | * all peripheral ports are external... |
| 1548 | */ |
| 1549 | static struct musb *the_gadget; |
| 1550 | |
| 1551 | static void musb_gadget_release(struct device *dev) |
| 1552 | { |
| 1553 | /* kref_put(WHAT) */ |
| 1554 | dev_dbg(dev, "%s\n", __func__); |
| 1555 | } |
| 1556 | |
| 1557 | |
| 1558 | static void __init |
| 1559 | init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in) |
| 1560 | { |
| 1561 | struct musb_hw_ep *hw_ep = musb->endpoints + epnum; |
| 1562 | |
| 1563 | memset(ep, 0, sizeof *ep); |
| 1564 | |
| 1565 | ep->current_epnum = epnum; |
| 1566 | ep->musb = musb; |
| 1567 | ep->hw_ep = hw_ep; |
| 1568 | ep->is_in = is_in; |
| 1569 | |
| 1570 | INIT_LIST_HEAD(&ep->req_list); |
| 1571 | |
| 1572 | sprintf(ep->name, "ep%d%s", epnum, |
| 1573 | (!epnum || hw_ep->is_shared_fifo) ? "" : ( |
| 1574 | is_in ? "in" : "out")); |
| 1575 | ep->end_point.name = ep->name; |
| 1576 | INIT_LIST_HEAD(&ep->end_point.ep_list); |
| 1577 | if (!epnum) { |
| 1578 | ep->end_point.maxpacket = 64; |
| 1579 | ep->end_point.ops = &musb_g_ep0_ops; |
| 1580 | musb->g.ep0 = &ep->end_point; |
| 1581 | } else { |
| 1582 | if (is_in) |
| 1583 | ep->end_point.maxpacket = hw_ep->max_packet_sz_tx; |
| 1584 | else |
| 1585 | ep->end_point.maxpacket = hw_ep->max_packet_sz_rx; |
| 1586 | ep->end_point.ops = &musb_ep_ops; |
| 1587 | list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list); |
| 1588 | } |
| 1589 | } |
| 1590 | |
| 1591 | /* |
| 1592 | * Initialize the endpoints exposed to peripheral drivers, with backlinks |
| 1593 | * to the rest of the driver state. |
| 1594 | */ |
| 1595 | static inline void __init musb_g_init_endpoints(struct musb *musb) |
| 1596 | { |
| 1597 | u8 epnum; |
| 1598 | struct musb_hw_ep *hw_ep; |
| 1599 | unsigned count = 0; |
| 1600 | |
| 1601 | /* intialize endpoint list just once */ |
| 1602 | INIT_LIST_HEAD(&(musb->g.ep_list)); |
| 1603 | |
| 1604 | for (epnum = 0, hw_ep = musb->endpoints; |
| 1605 | epnum < musb->nr_endpoints; |
| 1606 | epnum++, hw_ep++) { |
| 1607 | if (hw_ep->is_shared_fifo /* || !epnum */) { |
| 1608 | init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0); |
| 1609 | count++; |
| 1610 | } else { |
| 1611 | if (hw_ep->max_packet_sz_tx) { |
| 1612 | init_peripheral_ep(musb, &hw_ep->ep_in, |
| 1613 | epnum, 1); |
| 1614 | count++; |
| 1615 | } |
| 1616 | if (hw_ep->max_packet_sz_rx) { |
| 1617 | init_peripheral_ep(musb, &hw_ep->ep_out, |
| 1618 | epnum, 0); |
| 1619 | count++; |
| 1620 | } |
| 1621 | } |
| 1622 | } |
| 1623 | } |
| 1624 | |
| 1625 | /* called once during driver setup to initialize and link into |
| 1626 | * the driver model; memory is zeroed. |
| 1627 | */ |
| 1628 | int __init musb_gadget_setup(struct musb *musb) |
| 1629 | { |
| 1630 | int status; |
| 1631 | |
| 1632 | /* REVISIT minor race: if (erroneously) setting up two |
| 1633 | * musb peripherals at the same time, only the bus lock |
| 1634 | * is probably held. |
| 1635 | */ |
| 1636 | if (the_gadget) |
| 1637 | return -EBUSY; |
| 1638 | the_gadget = musb; |
| 1639 | |
| 1640 | musb->g.ops = &musb_gadget_operations; |
| 1641 | musb->g.is_dualspeed = 1; |
| 1642 | musb->g.speed = USB_SPEED_UNKNOWN; |
| 1643 | |
| 1644 | /* this "gadget" abstracts/virtualizes the controller */ |
Kay Sievers | 427c4f3 | 2008-11-07 01:52:53 +0100 | [diff] [blame] | 1645 | dev_set_name(&musb->g.dev, "gadget"); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1646 | musb->g.dev.parent = musb->controller; |
| 1647 | musb->g.dev.dma_mask = musb->controller->dma_mask; |
| 1648 | musb->g.dev.release = musb_gadget_release; |
| 1649 | musb->g.name = musb_driver_name; |
| 1650 | |
| 1651 | if (is_otg_enabled(musb)) |
| 1652 | musb->g.is_otg = 1; |
| 1653 | |
| 1654 | musb_g_init_endpoints(musb); |
| 1655 | |
| 1656 | musb->is_active = 0; |
| 1657 | musb_platform_try_idle(musb, 0); |
| 1658 | |
| 1659 | status = device_register(&musb->g.dev); |
| 1660 | if (status != 0) |
| 1661 | the_gadget = NULL; |
| 1662 | return status; |
| 1663 | } |
| 1664 | |
| 1665 | void musb_gadget_cleanup(struct musb *musb) |
| 1666 | { |
| 1667 | if (musb != the_gadget) |
| 1668 | return; |
| 1669 | |
| 1670 | device_unregister(&musb->g.dev); |
| 1671 | the_gadget = NULL; |
| 1672 | } |
| 1673 | |
| 1674 | /* |
| 1675 | * Register the gadget driver. Used by gadget drivers when |
| 1676 | * registering themselves with the controller. |
| 1677 | * |
| 1678 | * -EINVAL something went wrong (not driver) |
| 1679 | * -EBUSY another gadget is already using the controller |
| 1680 | * -ENOMEM no memeory to perform the operation |
| 1681 | * |
| 1682 | * @param driver the gadget driver |
| 1683 | * @return <0 if error, 0 if everything is fine |
| 1684 | */ |
| 1685 | int usb_gadget_register_driver(struct usb_gadget_driver *driver) |
| 1686 | { |
| 1687 | int retval; |
| 1688 | unsigned long flags; |
| 1689 | struct musb *musb = the_gadget; |
| 1690 | |
| 1691 | if (!driver |
| 1692 | || driver->speed != USB_SPEED_HIGH |
| 1693 | || !driver->bind |
| 1694 | || !driver->setup) |
| 1695 | return -EINVAL; |
| 1696 | |
| 1697 | /* driver must be initialized to support peripheral mode */ |
| 1698 | if (!musb || !(musb->board_mode == MUSB_OTG |
| 1699 | || musb->board_mode != MUSB_OTG)) { |
| 1700 | DBG(1, "%s, no dev??\n", __func__); |
| 1701 | return -ENODEV; |
| 1702 | } |
| 1703 | |
| 1704 | DBG(3, "registering driver %s\n", driver->function); |
| 1705 | spin_lock_irqsave(&musb->lock, flags); |
| 1706 | |
| 1707 | if (musb->gadget_driver) { |
| 1708 | DBG(1, "%s is already bound to %s\n", |
| 1709 | musb_driver_name, |
| 1710 | musb->gadget_driver->driver.name); |
| 1711 | retval = -EBUSY; |
| 1712 | } else { |
| 1713 | musb->gadget_driver = driver; |
| 1714 | musb->g.dev.driver = &driver->driver; |
| 1715 | driver->driver.bus = NULL; |
| 1716 | musb->softconnect = 1; |
| 1717 | retval = 0; |
| 1718 | } |
| 1719 | |
| 1720 | spin_unlock_irqrestore(&musb->lock, flags); |
| 1721 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1722 | if (retval == 0) { |
Felipe Balbi | f362a47 | 2008-08-04 13:53:52 +0300 | [diff] [blame] | 1723 | retval = driver->bind(&musb->g); |
| 1724 | if (retval != 0) { |
| 1725 | DBG(3, "bind to driver %s failed --> %d\n", |
| 1726 | driver->driver.name, retval); |
| 1727 | musb->gadget_driver = NULL; |
| 1728 | musb->g.dev.driver = NULL; |
| 1729 | } |
| 1730 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1731 | spin_lock_irqsave(&musb->lock, flags); |
| 1732 | |
David Brownell | 84e250f | 2009-03-31 12:30:04 -0700 | [diff] [blame] | 1733 | otg_set_peripheral(musb->xceiv, &musb->g); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1734 | musb->is_active = 1; |
| 1735 | |
| 1736 | /* FIXME this ignores the softconnect flag. Drivers are |
| 1737 | * allowed hold the peripheral inactive until for example |
| 1738 | * userspace hooks up printer hardware or DSP codecs, so |
| 1739 | * hosts only see fully functional devices. |
| 1740 | */ |
| 1741 | |
| 1742 | if (!is_otg_enabled(musb)) |
| 1743 | musb_start(musb); |
| 1744 | |
David Brownell | 84e250f | 2009-03-31 12:30:04 -0700 | [diff] [blame] | 1745 | otg_set_peripheral(musb->xceiv, &musb->g); |
| 1746 | |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1747 | spin_unlock_irqrestore(&musb->lock, flags); |
| 1748 | |
| 1749 | if (is_otg_enabled(musb)) { |
| 1750 | DBG(3, "OTG startup...\n"); |
| 1751 | |
| 1752 | /* REVISIT: funcall to other code, which also |
| 1753 | * handles power budgeting ... this way also |
| 1754 | * ensures HdrcStart is indirectly called. |
| 1755 | */ |
| 1756 | retval = usb_add_hcd(musb_to_hcd(musb), -1, 0); |
| 1757 | if (retval < 0) { |
| 1758 | DBG(1, "add_hcd failed, %d\n", retval); |
| 1759 | spin_lock_irqsave(&musb->lock, flags); |
David Brownell | 84e250f | 2009-03-31 12:30:04 -0700 | [diff] [blame] | 1760 | otg_set_peripheral(musb->xceiv, NULL); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1761 | musb->gadget_driver = NULL; |
| 1762 | musb->g.dev.driver = NULL; |
| 1763 | spin_unlock_irqrestore(&musb->lock, flags); |
| 1764 | } |
| 1765 | } |
| 1766 | } |
| 1767 | |
| 1768 | return retval; |
| 1769 | } |
| 1770 | EXPORT_SYMBOL(usb_gadget_register_driver); |
| 1771 | |
| 1772 | static void stop_activity(struct musb *musb, struct usb_gadget_driver *driver) |
| 1773 | { |
| 1774 | int i; |
| 1775 | struct musb_hw_ep *hw_ep; |
| 1776 | |
| 1777 | /* don't disconnect if it's not connected */ |
| 1778 | if (musb->g.speed == USB_SPEED_UNKNOWN) |
| 1779 | driver = NULL; |
| 1780 | else |
| 1781 | musb->g.speed = USB_SPEED_UNKNOWN; |
| 1782 | |
| 1783 | /* deactivate the hardware */ |
| 1784 | if (musb->softconnect) { |
| 1785 | musb->softconnect = 0; |
| 1786 | musb_pullup(musb, 0); |
| 1787 | } |
| 1788 | musb_stop(musb); |
| 1789 | |
| 1790 | /* killing any outstanding requests will quiesce the driver; |
| 1791 | * then report disconnect |
| 1792 | */ |
| 1793 | if (driver) { |
| 1794 | for (i = 0, hw_ep = musb->endpoints; |
| 1795 | i < musb->nr_endpoints; |
| 1796 | i++, hw_ep++) { |
| 1797 | musb_ep_select(musb->mregs, i); |
| 1798 | if (hw_ep->is_shared_fifo /* || !epnum */) { |
| 1799 | nuke(&hw_ep->ep_in, -ESHUTDOWN); |
| 1800 | } else { |
| 1801 | if (hw_ep->max_packet_sz_tx) |
| 1802 | nuke(&hw_ep->ep_in, -ESHUTDOWN); |
| 1803 | if (hw_ep->max_packet_sz_rx) |
| 1804 | nuke(&hw_ep->ep_out, -ESHUTDOWN); |
| 1805 | } |
| 1806 | } |
| 1807 | |
| 1808 | spin_unlock(&musb->lock); |
| 1809 | driver->disconnect(&musb->g); |
| 1810 | spin_lock(&musb->lock); |
| 1811 | } |
| 1812 | } |
| 1813 | |
| 1814 | /* |
| 1815 | * Unregister the gadget driver. Used by gadget drivers when |
| 1816 | * unregistering themselves from the controller. |
| 1817 | * |
| 1818 | * @param driver the gadget driver to unregister |
| 1819 | */ |
| 1820 | int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) |
| 1821 | { |
| 1822 | unsigned long flags; |
| 1823 | int retval = 0; |
| 1824 | struct musb *musb = the_gadget; |
| 1825 | |
| 1826 | if (!driver || !driver->unbind || !musb) |
| 1827 | return -EINVAL; |
| 1828 | |
| 1829 | /* REVISIT always use otg_set_peripheral() here too; |
| 1830 | * this needs to shut down the OTG engine. |
| 1831 | */ |
| 1832 | |
| 1833 | spin_lock_irqsave(&musb->lock, flags); |
| 1834 | |
| 1835 | #ifdef CONFIG_USB_MUSB_OTG |
| 1836 | musb_hnp_stop(musb); |
| 1837 | #endif |
| 1838 | |
| 1839 | if (musb->gadget_driver == driver) { |
| 1840 | |
| 1841 | (void) musb_gadget_vbus_draw(&musb->g, 0); |
| 1842 | |
David Brownell | 84e250f | 2009-03-31 12:30:04 -0700 | [diff] [blame] | 1843 | musb->xceiv->state = OTG_STATE_UNDEFINED; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1844 | stop_activity(musb, driver); |
David Brownell | 84e250f | 2009-03-31 12:30:04 -0700 | [diff] [blame] | 1845 | otg_set_peripheral(musb->xceiv, NULL); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1846 | |
| 1847 | DBG(3, "unregistering driver %s\n", driver->function); |
| 1848 | spin_unlock_irqrestore(&musb->lock, flags); |
| 1849 | driver->unbind(&musb->g); |
| 1850 | spin_lock_irqsave(&musb->lock, flags); |
| 1851 | |
| 1852 | musb->gadget_driver = NULL; |
| 1853 | musb->g.dev.driver = NULL; |
| 1854 | |
| 1855 | musb->is_active = 0; |
| 1856 | musb_platform_try_idle(musb, 0); |
| 1857 | } else |
| 1858 | retval = -EINVAL; |
| 1859 | spin_unlock_irqrestore(&musb->lock, flags); |
| 1860 | |
| 1861 | if (is_otg_enabled(musb) && retval == 0) { |
| 1862 | usb_remove_hcd(musb_to_hcd(musb)); |
| 1863 | /* FIXME we need to be able to register another |
| 1864 | * gadget driver here and have everything work; |
| 1865 | * that currently misbehaves. |
| 1866 | */ |
| 1867 | } |
| 1868 | |
| 1869 | return retval; |
| 1870 | } |
| 1871 | EXPORT_SYMBOL(usb_gadget_unregister_driver); |
| 1872 | |
| 1873 | |
| 1874 | /* ----------------------------------------------------------------------- */ |
| 1875 | |
| 1876 | /* lifecycle operations called through plat_uds.c */ |
| 1877 | |
| 1878 | void musb_g_resume(struct musb *musb) |
| 1879 | { |
| 1880 | musb->is_suspended = 0; |
David Brownell | 84e250f | 2009-03-31 12:30:04 -0700 | [diff] [blame] | 1881 | switch (musb->xceiv->state) { |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1882 | case OTG_STATE_B_IDLE: |
| 1883 | break; |
| 1884 | case OTG_STATE_B_WAIT_ACON: |
| 1885 | case OTG_STATE_B_PERIPHERAL: |
| 1886 | musb->is_active = 1; |
| 1887 | if (musb->gadget_driver && musb->gadget_driver->resume) { |
| 1888 | spin_unlock(&musb->lock); |
| 1889 | musb->gadget_driver->resume(&musb->g); |
| 1890 | spin_lock(&musb->lock); |
| 1891 | } |
| 1892 | break; |
| 1893 | default: |
| 1894 | WARNING("unhandled RESUME transition (%s)\n", |
| 1895 | otg_state_string(musb)); |
| 1896 | } |
| 1897 | } |
| 1898 | |
| 1899 | /* called when SOF packets stop for 3+ msec */ |
| 1900 | void musb_g_suspend(struct musb *musb) |
| 1901 | { |
| 1902 | u8 devctl; |
| 1903 | |
| 1904 | devctl = musb_readb(musb->mregs, MUSB_DEVCTL); |
| 1905 | DBG(3, "devctl %02x\n", devctl); |
| 1906 | |
David Brownell | 84e250f | 2009-03-31 12:30:04 -0700 | [diff] [blame] | 1907 | switch (musb->xceiv->state) { |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1908 | case OTG_STATE_B_IDLE: |
| 1909 | if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) |
David Brownell | 84e250f | 2009-03-31 12:30:04 -0700 | [diff] [blame] | 1910 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1911 | break; |
| 1912 | case OTG_STATE_B_PERIPHERAL: |
| 1913 | musb->is_suspended = 1; |
| 1914 | if (musb->gadget_driver && musb->gadget_driver->suspend) { |
| 1915 | spin_unlock(&musb->lock); |
| 1916 | musb->gadget_driver->suspend(&musb->g); |
| 1917 | spin_lock(&musb->lock); |
| 1918 | } |
| 1919 | break; |
| 1920 | default: |
| 1921 | /* REVISIT if B_HOST, clear DEVCTL.HOSTREQ; |
| 1922 | * A_PERIPHERAL may need care too |
| 1923 | */ |
| 1924 | WARNING("unhandled SUSPEND transition (%s)\n", |
| 1925 | otg_state_string(musb)); |
| 1926 | } |
| 1927 | } |
| 1928 | |
| 1929 | /* Called during SRP */ |
| 1930 | void musb_g_wakeup(struct musb *musb) |
| 1931 | { |
| 1932 | musb_gadget_wakeup(&musb->g); |
| 1933 | } |
| 1934 | |
| 1935 | /* called when VBUS drops below session threshold, and in other cases */ |
| 1936 | void musb_g_disconnect(struct musb *musb) |
| 1937 | { |
| 1938 | void __iomem *mregs = musb->mregs; |
| 1939 | u8 devctl = musb_readb(mregs, MUSB_DEVCTL); |
| 1940 | |
| 1941 | DBG(3, "devctl %02x\n", devctl); |
| 1942 | |
| 1943 | /* clear HR */ |
| 1944 | musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION); |
| 1945 | |
| 1946 | /* don't draw vbus until new b-default session */ |
| 1947 | (void) musb_gadget_vbus_draw(&musb->g, 0); |
| 1948 | |
| 1949 | musb->g.speed = USB_SPEED_UNKNOWN; |
| 1950 | if (musb->gadget_driver && musb->gadget_driver->disconnect) { |
| 1951 | spin_unlock(&musb->lock); |
| 1952 | musb->gadget_driver->disconnect(&musb->g); |
| 1953 | spin_lock(&musb->lock); |
| 1954 | } |
| 1955 | |
David Brownell | 84e250f | 2009-03-31 12:30:04 -0700 | [diff] [blame] | 1956 | switch (musb->xceiv->state) { |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1957 | default: |
| 1958 | #ifdef CONFIG_USB_MUSB_OTG |
| 1959 | DBG(2, "Unhandled disconnect %s, setting a_idle\n", |
| 1960 | otg_state_string(musb)); |
David Brownell | 84e250f | 2009-03-31 12:30:04 -0700 | [diff] [blame] | 1961 | musb->xceiv->state = OTG_STATE_A_IDLE; |
David Brownell | ab983f2a | 2009-03-31 12:35:09 -0700 | [diff] [blame] | 1962 | MUSB_HST_MODE(musb); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1963 | break; |
| 1964 | case OTG_STATE_A_PERIPHERAL: |
David Brownell | 1de00da | 2009-04-02 10:16:11 -0700 | [diff] [blame] | 1965 | musb->xceiv->state = OTG_STATE_A_WAIT_BCON; |
David Brownell | ab983f2a | 2009-03-31 12:35:09 -0700 | [diff] [blame] | 1966 | MUSB_HST_MODE(musb); |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1967 | break; |
| 1968 | case OTG_STATE_B_WAIT_ACON: |
| 1969 | case OTG_STATE_B_HOST: |
| 1970 | #endif |
| 1971 | case OTG_STATE_B_PERIPHERAL: |
| 1972 | case OTG_STATE_B_IDLE: |
David Brownell | 84e250f | 2009-03-31 12:30:04 -0700 | [diff] [blame] | 1973 | musb->xceiv->state = OTG_STATE_B_IDLE; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 1974 | break; |
| 1975 | case OTG_STATE_B_SRP_INIT: |
| 1976 | break; |
| 1977 | } |
| 1978 | |
| 1979 | musb->is_active = 0; |
| 1980 | } |
| 1981 | |
| 1982 | void musb_g_reset(struct musb *musb) |
| 1983 | __releases(musb->lock) |
| 1984 | __acquires(musb->lock) |
| 1985 | { |
| 1986 | void __iomem *mbase = musb->mregs; |
| 1987 | u8 devctl = musb_readb(mbase, MUSB_DEVCTL); |
| 1988 | u8 power; |
| 1989 | |
| 1990 | DBG(3, "<== %s addr=%x driver '%s'\n", |
| 1991 | (devctl & MUSB_DEVCTL_BDEVICE) |
| 1992 | ? "B-Device" : "A-Device", |
| 1993 | musb_readb(mbase, MUSB_FADDR), |
| 1994 | musb->gadget_driver |
| 1995 | ? musb->gadget_driver->driver.name |
| 1996 | : NULL |
| 1997 | ); |
| 1998 | |
| 1999 | /* report disconnect, if we didn't already (flushing EP state) */ |
| 2000 | if (musb->g.speed != USB_SPEED_UNKNOWN) |
| 2001 | musb_g_disconnect(musb); |
| 2002 | |
| 2003 | /* clear HR */ |
| 2004 | else if (devctl & MUSB_DEVCTL_HR) |
| 2005 | musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION); |
| 2006 | |
| 2007 | |
| 2008 | /* what speed did we negotiate? */ |
| 2009 | power = musb_readb(mbase, MUSB_POWER); |
| 2010 | musb->g.speed = (power & MUSB_POWER_HSMODE) |
| 2011 | ? USB_SPEED_HIGH : USB_SPEED_FULL; |
| 2012 | |
| 2013 | /* start in USB_STATE_DEFAULT */ |
| 2014 | musb->is_active = 1; |
| 2015 | musb->is_suspended = 0; |
| 2016 | MUSB_DEV_MODE(musb); |
| 2017 | musb->address = 0; |
| 2018 | musb->ep0_state = MUSB_EP0_STAGE_SETUP; |
| 2019 | |
| 2020 | musb->may_wakeup = 0; |
| 2021 | musb->g.b_hnp_enable = 0; |
| 2022 | musb->g.a_alt_hnp_support = 0; |
| 2023 | musb->g.a_hnp_support = 0; |
| 2024 | |
| 2025 | /* Normal reset, as B-Device; |
| 2026 | * or else after HNP, as A-Device |
| 2027 | */ |
| 2028 | if (devctl & MUSB_DEVCTL_BDEVICE) { |
David Brownell | 84e250f | 2009-03-31 12:30:04 -0700 | [diff] [blame] | 2029 | musb->xceiv->state = OTG_STATE_B_PERIPHERAL; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2030 | musb->g.is_a_peripheral = 0; |
| 2031 | } else if (is_otg_enabled(musb)) { |
David Brownell | 84e250f | 2009-03-31 12:30:04 -0700 | [diff] [blame] | 2032 | musb->xceiv->state = OTG_STATE_A_PERIPHERAL; |
Felipe Balbi | 550a737 | 2008-07-24 12:27:36 +0300 | [diff] [blame] | 2033 | musb->g.is_a_peripheral = 1; |
| 2034 | } else |
| 2035 | WARN_ON(1); |
| 2036 | |
| 2037 | /* start with default limits on VBUS power draw */ |
| 2038 | (void) musb_gadget_vbus_draw(&musb->g, |
| 2039 | is_otg_enabled(musb) ? 8 : 100); |
| 2040 | } |