Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | * Board setup routines for the Artesyn Katana cPCI boards. |
| 3 | * |
| 4 | * Author: Tim Montgomery <timm@artesyncp.com> |
| 5 | * Maintained by: Mark A. Greer <mgreer@mvista.com> |
| 6 | * |
| 7 | * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il |
| 8 | * Based on code done by - Mark A. Greer <mgreer@mvista.com> |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify it |
| 11 | * under the terms of the GNU General Public License as published by the |
| 12 | * Free Software Foundation; either version 2 of the License, or (at your |
| 13 | * option) any later version. |
| 14 | */ |
| 15 | /* |
| 16 | * Supports the Artesyn 750i, 752i, and 3750. The 752i is virtually identical |
| 17 | * to the 750i except that it has an mv64460 bridge. |
| 18 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 19 | #include <linux/kernel.h> |
| 20 | #include <linux/pci.h> |
| 21 | #include <linux/kdev_t.h> |
| 22 | #include <linux/console.h> |
| 23 | #include <linux/initrd.h> |
| 24 | #include <linux/root_dev.h> |
| 25 | #include <linux/delay.h> |
| 26 | #include <linux/seq_file.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 27 | #include <linux/mtd/physmap.h> |
| 28 | #include <linux/mv643xx.h> |
Russell King | d052d1b | 2005-10-29 19:07:23 +0100 | [diff] [blame] | 29 | #include <linux/platform_device.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 30 | #ifdef CONFIG_BOOTIMG |
| 31 | #include <linux/bootimg.h> |
| 32 | #endif |
Kumar Gala | 2ec19fa | 2005-06-25 14:54:41 -0700 | [diff] [blame] | 33 | #include <asm/io.h> |
Mark A. Greer | f4c6cc8 | 2005-09-03 15:55:57 -0700 | [diff] [blame] | 34 | #include <asm/unistd.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 35 | #include <asm/page.h> |
| 36 | #include <asm/time.h> |
| 37 | #include <asm/smp.h> |
| 38 | #include <asm/todc.h> |
| 39 | #include <asm/bootinfo.h> |
| 40 | #include <asm/ppcboot.h> |
| 41 | #include <asm/mv64x60.h> |
| 42 | #include <platforms/katana.h> |
Paul Mackerras | fd582ec | 2005-10-11 22:08:12 +1000 | [diff] [blame] | 43 | #include <asm/machdep.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 44 | |
Mark A. Greer | f4c6cc8 | 2005-09-03 15:55:57 -0700 | [diff] [blame] | 45 | static struct mv64x60_handle bh; |
| 46 | static katana_id_t katana_id; |
| 47 | static void __iomem *cpld_base; |
| 48 | static void __iomem *sram_base; |
| 49 | static u32 katana_flash_size_0; |
| 50 | static u32 katana_flash_size_1; |
| 51 | static u32 katana_bus_frequency; |
| 52 | static struct pci_controller katana_hose_a; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 53 | |
| 54 | unsigned char __res[sizeof(bd_t)]; |
| 55 | |
| 56 | /* PCI Interrupt routing */ |
| 57 | static int __init |
| 58 | katana_irq_lookup_750i(unsigned char idsel, unsigned char pin) |
| 59 | { |
| 60 | static char pci_irq_table[][4] = { |
| 61 | /* |
| 62 | * PCI IDSEL/INTPIN->INTLINE |
| 63 | * A B C D |
| 64 | */ |
| 65 | /* IDSEL 4 (PMC 1) */ |
| 66 | { KATANA_PCI_INTB_IRQ_750i, KATANA_PCI_INTC_IRQ_750i, |
| 67 | KATANA_PCI_INTD_IRQ_750i, KATANA_PCI_INTA_IRQ_750i }, |
| 68 | /* IDSEL 5 (PMC 2) */ |
| 69 | { KATANA_PCI_INTC_IRQ_750i, KATANA_PCI_INTD_IRQ_750i, |
| 70 | KATANA_PCI_INTA_IRQ_750i, KATANA_PCI_INTB_IRQ_750i }, |
| 71 | /* IDSEL 6 (T8110) */ |
| 72 | {KATANA_PCI_INTD_IRQ_750i, 0, 0, 0 }, |
Mark A. Greer | f4c6cc8 | 2005-09-03 15:55:57 -0700 | [diff] [blame] | 73 | /* IDSEL 7 (unused) */ |
| 74 | {0, 0, 0, 0 }, |
| 75 | /* IDSEL 8 (Intel 82544) (752i only but doesn't harm 750i) */ |
| 76 | {KATANA_PCI_INTD_IRQ_750i, 0, 0, 0 }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 77 | }; |
Mark A. Greer | f4c6cc8 | 2005-09-03 15:55:57 -0700 | [diff] [blame] | 78 | const long min_idsel = 4, max_idsel = 8, irqs_per_slot = 4; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 79 | |
| 80 | return PCI_IRQ_TABLE_LOOKUP; |
| 81 | } |
| 82 | |
| 83 | static int __init |
| 84 | katana_irq_lookup_3750(unsigned char idsel, unsigned char pin) |
| 85 | { |
| 86 | static char pci_irq_table[][4] = { |
| 87 | /* |
| 88 | * PCI IDSEL/INTPIN->INTLINE |
| 89 | * A B C D |
| 90 | */ |
| 91 | { KATANA_PCI_INTA_IRQ_3750, 0, 0, 0 }, /* IDSEL 3 (BCM5691) */ |
| 92 | { KATANA_PCI_INTB_IRQ_3750, 0, 0, 0 }, /* IDSEL 4 (MV64360 #2)*/ |
| 93 | { KATANA_PCI_INTC_IRQ_3750, 0, 0, 0 }, /* IDSEL 5 (MV64360 #3)*/ |
| 94 | }; |
| 95 | const long min_idsel = 3, max_idsel = 5, irqs_per_slot = 4; |
| 96 | |
| 97 | return PCI_IRQ_TABLE_LOOKUP; |
| 98 | } |
| 99 | |
| 100 | static int __init |
| 101 | katana_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) |
| 102 | { |
| 103 | switch (katana_id) { |
| 104 | case KATANA_ID_750I: |
| 105 | case KATANA_ID_752I: |
| 106 | return katana_irq_lookup_750i(idsel, pin); |
| 107 | |
| 108 | case KATANA_ID_3750: |
| 109 | return katana_irq_lookup_3750(idsel, pin); |
| 110 | |
| 111 | default: |
| 112 | printk(KERN_ERR "Bogus board ID\n"); |
| 113 | return 0; |
| 114 | } |
| 115 | } |
| 116 | |
| 117 | /* Board info retrieval routines */ |
| 118 | void __init |
| 119 | katana_get_board_id(void) |
| 120 | { |
| 121 | switch (in_8(cpld_base + KATANA_CPLD_PRODUCT_ID)) { |
| 122 | case KATANA_PRODUCT_ID_3750: |
| 123 | katana_id = KATANA_ID_3750; |
| 124 | break; |
| 125 | |
| 126 | case KATANA_PRODUCT_ID_750i: |
| 127 | katana_id = KATANA_ID_750I; |
| 128 | break; |
| 129 | |
| 130 | case KATANA_PRODUCT_ID_752i: |
| 131 | katana_id = KATANA_ID_752I; |
| 132 | break; |
| 133 | |
| 134 | default: |
| 135 | printk(KERN_ERR "Unsupported board\n"); |
| 136 | } |
| 137 | } |
| 138 | |
| 139 | int __init |
| 140 | katana_get_proc_num(void) |
| 141 | { |
| 142 | u16 val; |
| 143 | u8 save_exclude; |
| 144 | static int proc = -1; |
| 145 | static u8 first_time = 1; |
| 146 | |
| 147 | if (first_time) { |
| 148 | if (katana_id != KATANA_ID_3750) |
| 149 | proc = 0; |
| 150 | else { |
| 151 | save_exclude = mv64x60_pci_exclude_bridge; |
| 152 | mv64x60_pci_exclude_bridge = 0; |
| 153 | |
Mark A. Greer | f4c6cc8 | 2005-09-03 15:55:57 -0700 | [diff] [blame] | 154 | early_read_config_word(bh.hose_b, 0, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 155 | PCI_DEVFN(0,0), PCI_DEVICE_ID, &val); |
| 156 | |
| 157 | mv64x60_pci_exclude_bridge = save_exclude; |
| 158 | |
| 159 | switch(val) { |
| 160 | case PCI_DEVICE_ID_KATANA_3750_PROC0: |
| 161 | proc = 0; |
| 162 | break; |
| 163 | |
| 164 | case PCI_DEVICE_ID_KATANA_3750_PROC1: |
| 165 | proc = 1; |
| 166 | break; |
| 167 | |
| 168 | case PCI_DEVICE_ID_KATANA_3750_PROC2: |
| 169 | proc = 2; |
| 170 | break; |
| 171 | |
| 172 | default: |
| 173 | printk(KERN_ERR "Bogus Device ID\n"); |
| 174 | } |
| 175 | } |
| 176 | |
| 177 | first_time = 0; |
| 178 | } |
| 179 | |
| 180 | return proc; |
| 181 | } |
| 182 | |
| 183 | static inline int |
| 184 | katana_is_monarch(void) |
| 185 | { |
| 186 | return in_8(cpld_base + KATANA_CPLD_BD_CFG_3) & |
| 187 | KATANA_CPLD_BD_CFG_3_MONARCH; |
| 188 | } |
| 189 | |
| 190 | static void __init |
| 191 | katana_setup_bridge(void) |
| 192 | { |
| 193 | struct pci_controller hose; |
| 194 | struct mv64x60_setup_info si; |
| 195 | void __iomem *vaddr; |
| 196 | int i; |
Mark A. Greer | f4c6cc8 | 2005-09-03 15:55:57 -0700 | [diff] [blame] | 197 | u32 v; |
| 198 | u16 val, type; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 199 | u8 save_exclude; |
| 200 | |
| 201 | /* |
| 202 | * Some versions of the Katana firmware mistakenly change the vendor |
| 203 | * & device id fields in the bridge's pci device (visible via pci |
| 204 | * config accesses). This breaks mv64x60_init() because those values |
| 205 | * are used to identify the type of bridge that's there. Artesyn |
| 206 | * claims that the subsystem vendor/device id's will have the correct |
| 207 | * Marvell values so this code puts back the correct values from there. |
| 208 | */ |
| 209 | memset(&hose, 0, sizeof(hose)); |
| 210 | vaddr = ioremap(CONFIG_MV64X60_NEW_BASE, MV64x60_INTERNAL_SPACE_SIZE); |
| 211 | setup_indirect_pci_nomap(&hose, vaddr + MV64x60_PCI0_CONFIG_ADDR, |
| 212 | vaddr + MV64x60_PCI0_CONFIG_DATA); |
| 213 | save_exclude = mv64x60_pci_exclude_bridge; |
| 214 | mv64x60_pci_exclude_bridge = 0; |
| 215 | |
| 216 | early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID, &val); |
| 217 | |
| 218 | if (val != PCI_VENDOR_ID_MARVELL) { |
| 219 | early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), |
| 220 | PCI_SUBSYSTEM_VENDOR_ID, &val); |
| 221 | early_write_config_word(&hose, 0, PCI_DEVFN(0, 0), |
| 222 | PCI_VENDOR_ID, val); |
| 223 | early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), |
| 224 | PCI_SUBSYSTEM_ID, &val); |
| 225 | early_write_config_word(&hose, 0, PCI_DEVFN(0, 0), |
| 226 | PCI_DEVICE_ID, val); |
| 227 | } |
| 228 | |
Mark A. Greer | f4c6cc8 | 2005-09-03 15:55:57 -0700 | [diff] [blame] | 229 | /* |
| 230 | * While we're in here, set the hotswap register correctly. |
| 231 | * Turn off blue LED; mask ENUM#, clear insertion & extraction bits. |
| 232 | */ |
| 233 | early_read_config_dword(&hose, 0, PCI_DEVFN(0, 0), |
| 234 | MV64360_PCICFG_CPCI_HOTSWAP, &v); |
| 235 | v &= ~(1<<19); |
| 236 | v |= ((1<<17) | (1<<22) | (1<<23)); |
| 237 | early_write_config_dword(&hose, 0, PCI_DEVFN(0, 0), |
| 238 | MV64360_PCICFG_CPCI_HOTSWAP, v); |
| 239 | |
| 240 | /* While we're at it, grab the bridge type for later */ |
| 241 | early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_DEVICE_ID, &type); |
| 242 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 243 | mv64x60_pci_exclude_bridge = save_exclude; |
| 244 | iounmap(vaddr); |
| 245 | |
| 246 | memset(&si, 0, sizeof(si)); |
| 247 | |
| 248 | si.phys_reg_base = CONFIG_MV64X60_NEW_BASE; |
| 249 | |
| 250 | si.pci_1.enable_bus = 1; |
| 251 | si.pci_1.pci_io.cpu_base = KATANA_PCI1_IO_START_PROC_ADDR; |
| 252 | si.pci_1.pci_io.pci_base_hi = 0; |
| 253 | si.pci_1.pci_io.pci_base_lo = KATANA_PCI1_IO_START_PCI_ADDR; |
| 254 | si.pci_1.pci_io.size = KATANA_PCI1_IO_SIZE; |
| 255 | si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE; |
| 256 | si.pci_1.pci_mem[0].cpu_base = KATANA_PCI1_MEM_START_PROC_ADDR; |
| 257 | si.pci_1.pci_mem[0].pci_base_hi = KATANA_PCI1_MEM_START_PCI_HI_ADDR; |
| 258 | si.pci_1.pci_mem[0].pci_base_lo = KATANA_PCI1_MEM_START_PCI_LO_ADDR; |
| 259 | si.pci_1.pci_mem[0].size = KATANA_PCI1_MEM_SIZE; |
| 260 | si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE; |
| 261 | si.pci_1.pci_cmd_bits = 0; |
| 262 | si.pci_1.latency_timer = 0x80; |
| 263 | |
| 264 | for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) { |
| 265 | #if defined(CONFIG_NOT_COHERENT_CACHE) |
| 266 | si.cpu_prot_options[i] = 0; |
| 267 | si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; |
| 268 | si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; |
| 269 | si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; |
| 270 | |
| 271 | si.pci_1.acc_cntl_options[i] = |
Mark A. Greer | f4c6cc8 | 2005-09-03 15:55:57 -0700 | [diff] [blame] | 272 | MV64360_PCI_ACC_CNTL_SNOOP_NONE | |
| 273 | MV64360_PCI_ACC_CNTL_SWAP_NONE | |
| 274 | MV64360_PCI_ACC_CNTL_MBURST_128_BYTES | |
| 275 | MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 276 | #else |
| 277 | si.cpu_prot_options[i] = 0; |
Mark A. Greer | f4c6cc8 | 2005-09-03 15:55:57 -0700 | [diff] [blame] | 278 | si.enet_options[i] = MV64360_ENET2MEM_SNOOP_WB; |
| 279 | si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_WB; |
| 280 | si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_WB; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 281 | |
| 282 | si.pci_1.acc_cntl_options[i] = |
Mark A. Greer | f4c6cc8 | 2005-09-03 15:55:57 -0700 | [diff] [blame] | 283 | MV64360_PCI_ACC_CNTL_SNOOP_WB | |
| 284 | MV64360_PCI_ACC_CNTL_SWAP_NONE | |
| 285 | MV64360_PCI_ACC_CNTL_MBURST_32_BYTES | |
| 286 | ((type == PCI_DEVICE_ID_MARVELL_MV64360) ? |
| 287 | MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES : |
| 288 | MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 289 | #endif |
| 290 | } |
| 291 | |
| 292 | /* Lookup PCI host bridges */ |
| 293 | if (mv64x60_init(&bh, &si)) |
| 294 | printk(KERN_WARNING "Bridge initialization failed.\n"); |
| 295 | |
| 296 | pci_dram_offset = 0; /* sys mem at same addr on PCI & cpu bus */ |
| 297 | ppc_md.pci_swizzle = common_swizzle; |
| 298 | ppc_md.pci_map_irq = katana_map_irq; |
| 299 | ppc_md.pci_exclude_device = mv64x60_pci_exclude_device; |
| 300 | |
| 301 | mv64x60_set_bus(&bh, 1, 0); |
| 302 | bh.hose_b->first_busno = 0; |
| 303 | bh.hose_b->last_busno = 0xff; |
Mark A. Greer | f4c6cc8 | 2005-09-03 15:55:57 -0700 | [diff] [blame] | 304 | |
| 305 | /* |
| 306 | * Need to access hotswap reg which is in the pci config area of the |
| 307 | * bridge's hose 0. Note that pcibios_alloc_controller() can't be used |
| 308 | * to alloc hose_a b/c that would make hose 0 known to the generic |
| 309 | * pci code which we don't want. |
| 310 | */ |
| 311 | bh.hose_a = &katana_hose_a; |
| 312 | setup_indirect_pci_nomap(bh.hose_a, |
| 313 | bh.v_base + MV64x60_PCI0_CONFIG_ADDR, |
| 314 | bh.v_base + MV64x60_PCI0_CONFIG_DATA); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 315 | } |
| 316 | |
| 317 | /* Bridge & platform setup routines */ |
| 318 | void __init |
| 319 | katana_intr_setup(void) |
| 320 | { |
Mark A. Greer | f4c6cc8 | 2005-09-03 15:55:57 -0700 | [diff] [blame] | 321 | if (bh.type == MV64x60_TYPE_MV64460) /* As per instns from Marvell */ |
| 322 | mv64x60_clr_bits(&bh, MV64x60_CPU_MASTER_CNTL, 1 << 15); |
| 323 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 324 | /* MPP 8, 9, and 10 */ |
| 325 | mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1, 0xfff); |
| 326 | |
| 327 | /* MPP 14 */ |
| 328 | if ((katana_id == KATANA_ID_750I) || (katana_id == KATANA_ID_752I)) |
| 329 | mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1, 0x0f000000); |
| 330 | |
| 331 | /* |
| 332 | * Define GPP 8,9,and 10 interrupt polarity as active low |
| 333 | * input signal and level triggered |
| 334 | */ |
| 335 | mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, 0x700); |
| 336 | mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, 0x700); |
| 337 | |
| 338 | if ((katana_id == KATANA_ID_750I) || (katana_id == KATANA_ID_752I)) { |
| 339 | mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, (1<<14)); |
| 340 | mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, (1<<14)); |
| 341 | } |
| 342 | |
| 343 | /* Config GPP intr ctlr to respond to level trigger */ |
| 344 | mv64x60_set_bits(&bh, MV64x60_COMM_ARBITER_CNTL, (1<<10)); |
| 345 | |
Mark A. Greer | f4c6cc8 | 2005-09-03 15:55:57 -0700 | [diff] [blame] | 346 | if (bh.type == MV64x60_TYPE_MV64360) { |
| 347 | /* Erratum FEr PCI-#9 */ |
| 348 | mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD, |
| 349 | (1<<4) | (1<<5) | (1<<6) | (1<<7)); |
| 350 | mv64x60_set_bits(&bh, MV64x60_PCI1_CMD, (1<<8) | (1<<9)); |
| 351 | } else { |
| 352 | mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD, (1<<6) | (1<<7)); |
| 353 | mv64x60_set_bits(&bh, MV64x60_PCI1_CMD, |
| 354 | (1<<4) | (1<<5) | (1<<8) | (1<<9)); |
| 355 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 356 | |
| 357 | /* |
| 358 | * Dismiss and then enable interrupt on GPP interrupt cause |
| 359 | * for CPU #0 |
| 360 | */ |
| 361 | mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~0x700); |
| 362 | mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, 0x700); |
| 363 | |
| 364 | if ((katana_id == KATANA_ID_750I) || (katana_id == KATANA_ID_752I)) { |
| 365 | mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~(1<<14)); |
| 366 | mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, (1<<14)); |
| 367 | } |
| 368 | |
| 369 | /* |
| 370 | * Dismiss and then enable interrupt on CPU #0 high cause reg |
| 371 | * BIT25 summarizes GPP interrupts 8-15 |
| 372 | */ |
| 373 | mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, (1<<25)); |
| 374 | } |
| 375 | |
| 376 | void __init |
| 377 | katana_setup_peripherals(void) |
| 378 | { |
| 379 | u32 base; |
| 380 | |
| 381 | /* Set up windows for boot CS, soldered & socketed flash, and CPLD */ |
| 382 | mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, |
| 383 | KATANA_BOOT_WINDOW_BASE, KATANA_BOOT_WINDOW_SIZE, 0); |
| 384 | bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN); |
| 385 | |
| 386 | /* Assume firmware set up window sizes correctly for dev 0 & 1 */ |
| 387 | mv64x60_get_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, &base, |
| 388 | &katana_flash_size_0); |
| 389 | |
| 390 | if (katana_flash_size_0 > 0) { |
| 391 | mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, |
| 392 | KATANA_SOLDERED_FLASH_BASE, katana_flash_size_0, 0); |
| 393 | bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN); |
| 394 | } |
| 395 | |
| 396 | mv64x60_get_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, &base, |
| 397 | &katana_flash_size_1); |
| 398 | |
| 399 | if (katana_flash_size_1 > 0) { |
| 400 | mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, |
| 401 | (KATANA_SOLDERED_FLASH_BASE + katana_flash_size_0), |
| 402 | katana_flash_size_1, 0); |
| 403 | bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN); |
| 404 | } |
| 405 | |
| 406 | mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN, |
| 407 | KATANA_SOCKET_BASE, KATANA_SOCKETED_FLASH_SIZE, 0); |
| 408 | bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN); |
| 409 | |
| 410 | mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN, |
| 411 | KATANA_CPLD_BASE, KATANA_CPLD_SIZE, 0); |
| 412 | bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN); |
| 413 | cpld_base = ioremap(KATANA_CPLD_BASE, KATANA_CPLD_SIZE); |
| 414 | |
| 415 | mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN, |
| 416 | KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0); |
| 417 | bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN); |
| 418 | sram_base = ioremap(KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE); |
| 419 | |
| 420 | /* Set up Enet->SRAM window */ |
| 421 | mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN, |
| 422 | KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0x2); |
| 423 | bh.ci->enable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN); |
| 424 | |
| 425 | /* Give enet r/w access to memory region */ |
| 426 | mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_0, (0x3 << (4 << 1))); |
| 427 | mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_1, (0x3 << (4 << 1))); |
| 428 | mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_2, (0x3 << (4 << 1))); |
| 429 | |
| 430 | mv64x60_clr_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, (1 << 3)); |
| 431 | mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL, |
| 432 | ((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24))); |
| 433 | |
| 434 | /* Must wait until window set up before retrieving board id */ |
| 435 | katana_get_board_id(); |
| 436 | |
| 437 | /* Enumerate pci bus (must know board id before getting proc number) */ |
| 438 | if (katana_get_proc_num() == 0) |
| 439 | bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b, 0); |
| 440 | |
| 441 | #if defined(CONFIG_NOT_COHERENT_CACHE) |
| 442 | mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x00160000); |
| 443 | #else |
| 444 | mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2); |
| 445 | #endif |
| 446 | |
| 447 | /* |
| 448 | * Setting the SRAM to 0. Note that this generates parity errors on |
| 449 | * internal data path in SRAM since it's first time accessing it |
| 450 | * while after reset it's not configured. |
| 451 | */ |
| 452 | memset(sram_base, 0, MV64360_SRAM_SIZE); |
| 453 | |
| 454 | /* Only processor zero [on 3750] is an PCI interrupt controller */ |
| 455 | if (katana_get_proc_num() == 0) |
| 456 | katana_intr_setup(); |
| 457 | } |
| 458 | |
| 459 | static void __init |
| 460 | katana_enable_ipmi(void) |
| 461 | { |
| 462 | u8 reset_out; |
| 463 | |
| 464 | /* Enable access to IPMI ctlr by clearing IPMI PORTSEL bit in CPLD */ |
| 465 | reset_out = in_8(cpld_base + KATANA_CPLD_RESET_OUT); |
| 466 | reset_out &= ~KATANA_CPLD_RESET_OUT_PORTSEL; |
| 467 | out_8(cpld_base + KATANA_CPLD_RESET_OUT, reset_out); |
| 468 | } |
| 469 | |
| 470 | static void __init |
| 471 | katana_setup_arch(void) |
| 472 | { |
| 473 | if (ppc_md.progress) |
| 474 | ppc_md.progress("katana_setup_arch: enter", 0); |
| 475 | |
| 476 | set_tb(0, 0); |
| 477 | |
| 478 | #ifdef CONFIG_BLK_DEV_INITRD |
| 479 | if (initrd_start) |
| 480 | ROOT_DEV = Root_RAM0; |
| 481 | else |
| 482 | #endif |
| 483 | #ifdef CONFIG_ROOT_NFS |
| 484 | ROOT_DEV = Root_NFS; |
| 485 | #else |
| 486 | ROOT_DEV = Root_SDA2; |
| 487 | #endif |
| 488 | |
| 489 | /* |
| 490 | * Set up the L2CR register. |
| 491 | * |
| 492 | * 750FX has only L2E, L2PE (bits 2-8 are reserved) |
| 493 | * DD2.0 has bug that requires the L2 to be in WRT mode |
| 494 | * avoid dirty data in cache |
| 495 | */ |
| 496 | if (PVR_REV(mfspr(SPRN_PVR)) == 0x0200) { |
| 497 | printk(KERN_INFO "DD2.0 detected. Setting L2 cache" |
| 498 | "to Writethrough mode\n"); |
| 499 | _set_L2CR(L2CR_L2E | L2CR_L2PE | L2CR_L2WT); |
| 500 | } else |
| 501 | _set_L2CR(L2CR_L2E | L2CR_L2PE); |
| 502 | |
| 503 | if (ppc_md.progress) |
| 504 | ppc_md.progress("katana_setup_arch: calling setup_bridge", 0); |
| 505 | |
| 506 | katana_setup_bridge(); |
| 507 | katana_setup_peripherals(); |
| 508 | katana_enable_ipmi(); |
| 509 | |
| 510 | katana_bus_frequency = katana_bus_freq(cpld_base); |
| 511 | |
| 512 | printk(KERN_INFO "Artesyn Communication Products, LLC - Katana(TM)\n"); |
| 513 | if (ppc_md.progress) |
| 514 | ppc_md.progress("katana_setup_arch: exit", 0); |
| 515 | } |
| 516 | |
Mark A. Greer | f4c6cc8 | 2005-09-03 15:55:57 -0700 | [diff] [blame] | 517 | void |
| 518 | katana_fixup_resources(struct pci_dev *dev) |
| 519 | { |
| 520 | u16 v16; |
| 521 | |
Stephen Rothwell | 7dffb72 | 2005-10-17 11:50:32 +1000 | [diff] [blame] | 522 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, L1_CACHE_BYTES>>2); |
Mark A. Greer | f4c6cc8 | 2005-09-03 15:55:57 -0700 | [diff] [blame] | 523 | |
| 524 | pci_read_config_word(dev, PCI_COMMAND, &v16); |
| 525 | v16 |= PCI_COMMAND_INVALIDATE | PCI_COMMAND_FAST_BACK; |
| 526 | pci_write_config_word(dev, PCI_COMMAND, v16); |
| 527 | } |
| 528 | |
| 529 | static const unsigned int cpu_750xx[32] = { /* 750FX & 750GX */ |
| 530 | 0, 0, 2, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,/* 0-15*/ |
| 531 | 16, 17, 18, 19, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 0 /*16-31*/ |
| 532 | }; |
| 533 | |
| 534 | static int |
| 535 | katana_get_cpu_freq(void) |
| 536 | { |
| 537 | unsigned long pll_cfg; |
| 538 | |
| 539 | pll_cfg = (mfspr(SPRN_HID1) & 0xf8000000) >> 27; |
| 540 | return katana_bus_frequency * cpu_750xx[pll_cfg]/2; |
| 541 | } |
| 542 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 543 | /* Platform device data fixup routines. */ |
| 544 | #if defined(CONFIG_SERIAL_MPSC) |
| 545 | static void __init |
| 546 | katana_fixup_mpsc_pdata(struct platform_device *pdev) |
| 547 | { |
Mark A. Greer | f4c6cc8 | 2005-09-03 15:55:57 -0700 | [diff] [blame] | 548 | struct mpsc_pdata *pdata = (struct mpsc_pdata *)pdev->dev.platform_data; |
| 549 | bd_t *bdp = (bd_t *)__res; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 550 | |
Mark A. Greer | f4c6cc8 | 2005-09-03 15:55:57 -0700 | [diff] [blame] | 551 | if (bdp->bi_baudrate) |
| 552 | pdata->default_baud = bdp->bi_baudrate; |
| 553 | else |
| 554 | pdata->default_baud = KATANA_DEFAULT_BAUD; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 555 | |
| 556 | pdata->max_idle = 40; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 557 | pdata->brg_clk_src = KATANA_MPSC_CLK_SRC; |
| 558 | /* |
| 559 | * TCLK (not SysCLk) is routed to BRG, then to the MPSC. On most parts, |
| 560 | * TCLK == SysCLK but on 64460, they are separate pins. |
| 561 | * SysCLK can go up to 200 MHz but TCLK can only go up to 133 MHz. |
| 562 | */ |
| 563 | pdata->brg_clk_freq = min(katana_bus_frequency, MV64x60_TCLK_FREQ_MAX); |
| 564 | } |
| 565 | #endif |
| 566 | |
| 567 | #if defined(CONFIG_MV643XX_ETH) |
| 568 | static void __init |
| 569 | katana_fixup_eth_pdata(struct platform_device *pdev) |
| 570 | { |
| 571 | struct mv643xx_eth_platform_data *eth_pd; |
| 572 | static u16 phy_addr[] = { |
| 573 | KATANA_ETH0_PHY_ADDR, |
| 574 | KATANA_ETH1_PHY_ADDR, |
| 575 | KATANA_ETH2_PHY_ADDR, |
| 576 | }; |
| 577 | |
| 578 | eth_pd = pdev->dev.platform_data; |
| 579 | eth_pd->force_phy_addr = 1; |
| 580 | eth_pd->phy_addr = phy_addr[pdev->id]; |
| 581 | eth_pd->tx_queue_size = KATANA_ETH_TX_QUEUE_SIZE; |
| 582 | eth_pd->rx_queue_size = KATANA_ETH_RX_QUEUE_SIZE; |
| 583 | } |
| 584 | #endif |
| 585 | |
Mark A. Greer | f4c6cc8 | 2005-09-03 15:55:57 -0700 | [diff] [blame] | 586 | #if defined(CONFIG_SYSFS) |
| 587 | static void __init |
| 588 | katana_fixup_mv64xxx_pdata(struct platform_device *pdev) |
| 589 | { |
| 590 | struct mv64xxx_pdata *pdata = (struct mv64xxx_pdata *) |
| 591 | pdev->dev.platform_data; |
| 592 | |
| 593 | /* Katana supports the mv64xxx hotswap register */ |
| 594 | pdata->hs_reg_valid = 1; |
| 595 | } |
| 596 | #endif |
| 597 | |
Adrian Cox | bbbe121 | 2006-03-08 22:10:20 +0000 | [diff] [blame] | 598 | static int |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 599 | katana_platform_notify(struct device *dev) |
| 600 | { |
| 601 | static struct { |
| 602 | char *bus_id; |
| 603 | void ((*rtn)(struct platform_device *pdev)); |
| 604 | } dev_map[] = { |
| 605 | #if defined(CONFIG_SERIAL_MPSC) |
| 606 | { MPSC_CTLR_NAME ".0", katana_fixup_mpsc_pdata }, |
| 607 | { MPSC_CTLR_NAME ".1", katana_fixup_mpsc_pdata }, |
| 608 | #endif |
| 609 | #if defined(CONFIG_MV643XX_ETH) |
| 610 | { MV643XX_ETH_NAME ".0", katana_fixup_eth_pdata }, |
| 611 | { MV643XX_ETH_NAME ".1", katana_fixup_eth_pdata }, |
| 612 | { MV643XX_ETH_NAME ".2", katana_fixup_eth_pdata }, |
| 613 | #endif |
Mark A. Greer | f4c6cc8 | 2005-09-03 15:55:57 -0700 | [diff] [blame] | 614 | #if defined(CONFIG_SYSFS) |
| 615 | { MV64XXX_DEV_NAME ".0", katana_fixup_mv64xxx_pdata }, |
| 616 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 617 | }; |
| 618 | struct platform_device *pdev; |
| 619 | int i; |
| 620 | |
| 621 | if (dev && dev->bus_id) |
| 622 | for (i=0; i<ARRAY_SIZE(dev_map); i++) |
| 623 | if (!strncmp(dev->bus_id, dev_map[i].bus_id, |
Mark A. Greer | f4c6cc8 | 2005-09-03 15:55:57 -0700 | [diff] [blame] | 624 | BUS_ID_SIZE)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 625 | pdev = container_of(dev, |
| 626 | struct platform_device, dev); |
| 627 | dev_map[i].rtn(pdev); |
| 628 | } |
| 629 | |
| 630 | return 0; |
| 631 | } |
| 632 | |
| 633 | #ifdef CONFIG_MTD_PHYSMAP |
| 634 | |
| 635 | #ifndef MB |
| 636 | #define MB (1 << 20) |
| 637 | #endif |
| 638 | |
| 639 | /* |
| 640 | * MTD Layout depends on amount of soldered FLASH in system. Sizes in MB. |
| 641 | * |
| 642 | * FLASH Amount: 128 64 32 16 |
| 643 | * ------------- --- -- -- -- |
| 644 | * Monitor: 1 1 1 1 |
| 645 | * Primary Kernel: 1.5 1.5 1.5 1.5 |
| 646 | * Primary fs: 30 30 <end> <end> |
| 647 | * Secondary Kernel: 1.5 1.5 N/A N/A |
| 648 | * Secondary fs: <end> <end> N/A N/A |
| 649 | * User: <overlays entire FLASH except for "Monitor" section> |
| 650 | */ |
| 651 | static int __init |
| 652 | katana_setup_mtd(void) |
| 653 | { |
| 654 | u32 size; |
| 655 | int ptbl_entries; |
| 656 | static struct mtd_partition *ptbl; |
| 657 | |
| 658 | size = katana_flash_size_0 + katana_flash_size_1; |
| 659 | if (!size) |
| 660 | return -ENOMEM; |
| 661 | |
| 662 | ptbl_entries = (size >= (64*MB)) ? 6 : 4; |
| 663 | |
Eric Sesterhenn | d116fe5 | 2006-03-06 21:13:32 +0100 | [diff] [blame] | 664 | if ((ptbl = kcalloc(ptbl_entries, sizeof(struct mtd_partition), |
Mark A. Greer | f4c6cc8 | 2005-09-03 15:55:57 -0700 | [diff] [blame] | 665 | GFP_KERNEL)) == NULL) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 666 | printk(KERN_WARNING "Can't alloc MTD partition table\n"); |
| 667 | return -ENOMEM; |
| 668 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 669 | |
| 670 | ptbl[0].name = "Monitor"; |
| 671 | ptbl[0].size = KATANA_MTD_MONITOR_SIZE; |
| 672 | ptbl[1].name = "Primary Kernel"; |
| 673 | ptbl[1].offset = MTDPART_OFS_NXTBLK; |
| 674 | ptbl[1].size = 0x00180000; /* 1.5 MB */ |
| 675 | ptbl[2].name = "Primary Filesystem"; |
| 676 | ptbl[2].offset = MTDPART_OFS_APPEND; |
| 677 | ptbl[2].size = MTDPART_SIZ_FULL; /* Correct for 16 & 32 MB */ |
| 678 | ptbl[ptbl_entries-1].name = "User FLASH"; |
| 679 | ptbl[ptbl_entries-1].offset = KATANA_MTD_MONITOR_SIZE; |
| 680 | ptbl[ptbl_entries-1].size = MTDPART_SIZ_FULL; |
| 681 | |
| 682 | if (size >= (64*MB)) { |
| 683 | ptbl[2].size = 30*MB; |
| 684 | ptbl[3].name = "Secondary Kernel"; |
| 685 | ptbl[3].offset = MTDPART_OFS_NXTBLK; |
| 686 | ptbl[3].size = 0x00180000; /* 1.5 MB */ |
| 687 | ptbl[4].name = "Secondary Filesystem"; |
| 688 | ptbl[4].offset = MTDPART_OFS_APPEND; |
| 689 | ptbl[4].size = MTDPART_SIZ_FULL; |
| 690 | } |
| 691 | |
| 692 | physmap_map.size = size; |
| 693 | physmap_set_partitions(ptbl, ptbl_entries); |
| 694 | return 0; |
| 695 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 696 | arch_initcall(katana_setup_mtd); |
| 697 | #endif |
| 698 | |
| 699 | static void |
| 700 | katana_restart(char *cmd) |
| 701 | { |
| 702 | ulong i = 10000000; |
| 703 | |
| 704 | /* issue hard reset to the reset command register */ |
| 705 | out_8(cpld_base + KATANA_CPLD_RST_CMD, KATANA_CPLD_RST_CMD_HR); |
| 706 | |
| 707 | while (i-- > 0) ; |
| 708 | panic("restart failed\n"); |
| 709 | } |
| 710 | |
| 711 | static void |
| 712 | katana_halt(void) |
| 713 | { |
| 714 | u8 v; |
| 715 | |
Mark A. Greer | f4c6cc8 | 2005-09-03 15:55:57 -0700 | [diff] [blame] | 716 | /* Turn on blue LED to indicate its okay to remove */ |
| 717 | if (katana_id == KATANA_ID_750I) { |
| 718 | u32 v; |
| 719 | u8 save_exclude; |
| 720 | |
| 721 | /* Set LOO bit in cPCI HotSwap reg of hose 0 to turn on LED. */ |
| 722 | save_exclude = mv64x60_pci_exclude_bridge; |
| 723 | mv64x60_pci_exclude_bridge = 0; |
| 724 | early_read_config_dword(bh.hose_a, 0, PCI_DEVFN(0, 0), |
| 725 | MV64360_PCICFG_CPCI_HOTSWAP, &v); |
| 726 | v &= 0xff; |
| 727 | v |= (1 << 19); |
| 728 | early_write_config_dword(bh.hose_a, 0, PCI_DEVFN(0, 0), |
| 729 | MV64360_PCICFG_CPCI_HOTSWAP, v); |
| 730 | mv64x60_pci_exclude_bridge = save_exclude; |
| 731 | } else if (katana_id == KATANA_ID_752I) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 732 | v = in_8(cpld_base + HSL_PLD_BASE + HSL_PLD_HOT_SWAP_OFF); |
| 733 | v |= HSL_PLD_HOT_SWAP_LED_BIT; |
| 734 | out_8(cpld_base + HSL_PLD_BASE + HSL_PLD_HOT_SWAP_OFF, v); |
| 735 | } |
| 736 | |
| 737 | while (1) ; |
| 738 | /* NOTREACHED */ |
| 739 | } |
| 740 | |
| 741 | static void |
| 742 | katana_power_off(void) |
| 743 | { |
| 744 | katana_halt(); |
| 745 | /* NOTREACHED */ |
| 746 | } |
| 747 | |
| 748 | static int |
| 749 | katana_show_cpuinfo(struct seq_file *m) |
| 750 | { |
Mark A. Greer | f4c6cc8 | 2005-09-03 15:55:57 -0700 | [diff] [blame] | 751 | char *s; |
| 752 | |
| 753 | seq_printf(m, "cpu freq\t: %dMHz\n", |
| 754 | (katana_get_cpu_freq() + 500000) / 1000000); |
| 755 | seq_printf(m, "bus freq\t: %ldMHz\n", |
| 756 | ((long)katana_bus_frequency + 500000) / 1000000); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 757 | seq_printf(m, "vendor\t\t: Artesyn Communication Products, LLC\n"); |
| 758 | |
| 759 | seq_printf(m, "board\t\t: "); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 760 | switch (katana_id) { |
| 761 | case KATANA_ID_3750: |
Mark A. Greer | f4c6cc8 | 2005-09-03 15:55:57 -0700 | [diff] [blame] | 762 | seq_printf(m, "Katana 3750"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 763 | break; |
| 764 | |
| 765 | case KATANA_ID_750I: |
Mark A. Greer | f4c6cc8 | 2005-09-03 15:55:57 -0700 | [diff] [blame] | 766 | seq_printf(m, "Katana 750i"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 767 | break; |
| 768 | |
| 769 | case KATANA_ID_752I: |
Mark A. Greer | f4c6cc8 | 2005-09-03 15:55:57 -0700 | [diff] [blame] | 770 | seq_printf(m, "Katana 752i"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 771 | break; |
| 772 | |
| 773 | default: |
Mark A. Greer | f4c6cc8 | 2005-09-03 15:55:57 -0700 | [diff] [blame] | 774 | seq_printf(m, "Unknown"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 775 | break; |
| 776 | } |
Mark A. Greer | f4c6cc8 | 2005-09-03 15:55:57 -0700 | [diff] [blame] | 777 | seq_printf(m, " (product id: 0x%x)\n", |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 778 | in_8(cpld_base + KATANA_CPLD_PRODUCT_ID)); |
Mark A. Greer | f4c6cc8 | 2005-09-03 15:55:57 -0700 | [diff] [blame] | 779 | |
| 780 | seq_printf(m, "pci mode\t: %sMonarch\n", |
| 781 | katana_is_monarch()? "" : "Non-"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 782 | seq_printf(m, "hardware rev\t: 0x%x\n", |
| 783 | in_8(cpld_base+KATANA_CPLD_HARDWARE_VER)); |
Mark A. Greer | f4c6cc8 | 2005-09-03 15:55:57 -0700 | [diff] [blame] | 784 | seq_printf(m, "pld rev\t\t: 0x%x\n", |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 785 | in_8(cpld_base + KATANA_CPLD_PLD_VER)); |
Mark A. Greer | f4c6cc8 | 2005-09-03 15:55:57 -0700 | [diff] [blame] | 786 | |
| 787 | switch(bh.type) { |
| 788 | case MV64x60_TYPE_GT64260A: |
| 789 | s = "gt64260a"; |
| 790 | break; |
| 791 | case MV64x60_TYPE_GT64260B: |
| 792 | s = "gt64260b"; |
| 793 | break; |
| 794 | case MV64x60_TYPE_MV64360: |
| 795 | s = "mv64360"; |
| 796 | break; |
| 797 | case MV64x60_TYPE_MV64460: |
| 798 | s = "mv64460"; |
| 799 | break; |
| 800 | default: |
| 801 | s = "Unknown"; |
| 802 | } |
| 803 | seq_printf(m, "bridge type\t: %s\n", s); |
| 804 | seq_printf(m, "bridge rev\t: 0x%x\n", bh.rev); |
| 805 | #if defined(CONFIG_NOT_COHERENT_CACHE) |
| 806 | seq_printf(m, "coherency\t: %s\n", "off"); |
| 807 | #else |
| 808 | seq_printf(m, "coherency\t: %s\n", "on"); |
| 809 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 810 | |
| 811 | return 0; |
| 812 | } |
| 813 | |
| 814 | static void __init |
| 815 | katana_calibrate_decr(void) |
| 816 | { |
| 817 | u32 freq; |
| 818 | |
| 819 | freq = katana_bus_frequency / 4; |
| 820 | |
| 821 | printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n", |
| 822 | (long)freq / 1000000, (long)freq % 1000000); |
| 823 | |
| 824 | tb_ticks_per_jiffy = freq / HZ; |
| 825 | tb_to_us = mulhwu_scale_factor(freq, 1000000); |
| 826 | } |
| 827 | |
Mark A. Greer | f4c6cc8 | 2005-09-03 15:55:57 -0700 | [diff] [blame] | 828 | /* |
| 829 | * The katana supports both uImage and zImage. If uImage, get the mem size |
| 830 | * from the bd info. If zImage, the bootwrapper adds a BI_MEMSIZE entry in |
| 831 | * the bi_rec data which is sucked out and put into boot_mem_size by |
| 832 | * parse_bootinfo(). MMU_init() will then use the boot_mem_size for the mem |
| 833 | * size and not call this routine. The only way this will fail is when a uImage |
| 834 | * is used but the fw doesn't pass in a valid bi_memsize. This should never |
| 835 | * happen, though. |
| 836 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 837 | unsigned long __init |
| 838 | katana_find_end_of_memory(void) |
| 839 | { |
Mark A. Greer | f4c6cc8 | 2005-09-03 15:55:57 -0700 | [diff] [blame] | 840 | bd_t *bdp = (bd_t *)__res; |
| 841 | return bdp->bi_memsize; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 842 | } |
| 843 | |
| 844 | #if defined(CONFIG_I2C_MV64XXX) && defined(CONFIG_SENSORS_M41T00) |
| 845 | extern ulong m41t00_get_rtc_time(void); |
| 846 | extern int m41t00_set_rtc_time(ulong); |
| 847 | |
| 848 | static int __init |
| 849 | katana_rtc_hookup(void) |
| 850 | { |
| 851 | struct timespec tv; |
| 852 | |
| 853 | ppc_md.get_rtc_time = m41t00_get_rtc_time; |
| 854 | ppc_md.set_rtc_time = m41t00_set_rtc_time; |
| 855 | |
| 856 | tv.tv_nsec = 0; |
| 857 | tv.tv_sec = (ppc_md.get_rtc_time)(); |
| 858 | do_settimeofday(&tv); |
| 859 | |
| 860 | return 0; |
| 861 | } |
| 862 | late_initcall(katana_rtc_hookup); |
| 863 | #endif |
| 864 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 865 | #if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE) |
| 866 | static void __init |
| 867 | katana_map_io(void) |
| 868 | { |
| 869 | io_block_mapping(0xf8100000, 0xf8100000, 0x00020000, _PAGE_IO); |
| 870 | } |
| 871 | #endif |
| 872 | |
| 873 | void __init |
| 874 | platform_init(unsigned long r3, unsigned long r4, unsigned long r5, |
| 875 | unsigned long r6, unsigned long r7) |
| 876 | { |
| 877 | parse_bootinfo(find_bootinfo()); |
| 878 | |
| 879 | /* ASSUMPTION: If both r3 (bd_t pointer) and r6 (cmdline pointer) |
| 880 | * are non-zero, then we should use the board info from the bd_t |
| 881 | * structure and the cmdline pointed to by r6 instead of the |
| 882 | * information from birecs, if any. Otherwise, use the information |
Simon Arlott | a8de5ce | 2007-05-12 05:42:54 +1000 | [diff] [blame] | 883 | * from birecs as discovered by the preceding call to |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 884 | * parse_bootinfo(). This rule should work with both PPCBoot, which |
| 885 | * uses a bd_t board info structure, and the kernel boot wrapper, |
| 886 | * which uses birecs. |
| 887 | */ |
| 888 | if (r3 && r6) { |
| 889 | /* copy board info structure */ |
Mark A. Greer | f4c6cc8 | 2005-09-03 15:55:57 -0700 | [diff] [blame] | 890 | memcpy((void *)__res, (void *)(r3+KERNELBASE), sizeof(bd_t)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 891 | /* copy command line */ |
| 892 | *(char *)(r7+KERNELBASE) = 0; |
| 893 | strcpy(cmd_line, (char *)(r6+KERNELBASE)); |
| 894 | } |
| 895 | |
Mark A. Greer | f4c6cc8 | 2005-09-03 15:55:57 -0700 | [diff] [blame] | 896 | #ifdef CONFIG_BLK_DEV_INITRD |
| 897 | /* take care of initrd if we have one */ |
| 898 | if (r4) { |
| 899 | initrd_start = r4 + KERNELBASE; |
| 900 | initrd_end = r5 + KERNELBASE; |
| 901 | } |
| 902 | #endif /* CONFIG_BLK_DEV_INITRD */ |
| 903 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 904 | isa_mem_base = 0; |
| 905 | |
| 906 | ppc_md.setup_arch = katana_setup_arch; |
Mark A. Greer | f4c6cc8 | 2005-09-03 15:55:57 -0700 | [diff] [blame] | 907 | ppc_md.pcibios_fixup_resources = katana_fixup_resources; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 908 | ppc_md.show_cpuinfo = katana_show_cpuinfo; |
| 909 | ppc_md.init_IRQ = mv64360_init_irq; |
| 910 | ppc_md.get_irq = mv64360_get_irq; |
| 911 | ppc_md.restart = katana_restart; |
| 912 | ppc_md.power_off = katana_power_off; |
| 913 | ppc_md.halt = katana_halt; |
| 914 | ppc_md.find_end_of_memory = katana_find_end_of_memory; |
| 915 | ppc_md.calibrate_decr = katana_calibrate_decr; |
| 916 | |
| 917 | #if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE) |
| 918 | ppc_md.setup_io_mappings = katana_map_io; |
| 919 | ppc_md.progress = mv64x60_mpsc_progress; |
| 920 | mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE); |
| 921 | #endif |
| 922 | |
| 923 | #if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH) |
| 924 | platform_notify = katana_platform_notify; |
| 925 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 926 | } |