blob: 2365a32a595e42b8ddf43c2dc32603749cf990d7 [file] [log] [blame]
Jamie Iles1b8873a2010-02-02 20:25:44 +01001#undef DEBUG
2
3/*
4 * ARM performance counter support.
5 *
6 * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
Will Deacon43eab872010-11-13 19:04:32 +00007 * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
Jean PIHET796d1292010-01-26 18:51:05 +01008 *
Jamie Iles1b8873a2010-02-02 20:25:44 +01009 * This code is based on the sparc64 perf event code, which is in turn based
Mark Rutlandd39976f2014-09-29 17:15:32 +010010 * on the x86 code.
Jamie Iles1b8873a2010-02-02 20:25:44 +010011 */
12#define pr_fmt(fmt) "hw perfevents: " fmt
13
Mark Rutland74cf0bc2015-05-26 17:23:39 +010014#include <linux/bitmap.h>
Mark Rutlandcc881162015-05-13 17:12:25 +010015#include <linux/cpumask.h>
Mark Rutland74cf0bc2015-05-26 17:23:39 +010016#include <linux/export.h>
Jamie Iles1b8873a2010-02-02 20:25:44 +010017#include <linux/kernel.h>
Sudeep Hollabc1e3c42015-06-30 13:56:57 +010018#include <linux/of_device.h>
Mark Rutlandfa8ad782015-07-06 12:23:53 +010019#include <linux/perf/arm_pmu.h>
Will Deacon49c006b2010-04-29 17:13:24 +010020#include <linux/platform_device.h>
Mark Rutland74cf0bc2015-05-26 17:23:39 +010021#include <linux/slab.h>
22#include <linux/spinlock.h>
Stephen Boydbbd64552014-02-07 21:01:19 +000023#include <linux/irq.h>
24#include <linux/irqdesc.h>
Jamie Iles1b8873a2010-02-02 20:25:44 +010025
Mark Rutland74cf0bc2015-05-26 17:23:39 +010026#include <asm/cputype.h>
Jamie Iles1b8873a2010-02-02 20:25:44 +010027#include <asm/irq_regs.h>
Jamie Iles1b8873a2010-02-02 20:25:44 +010028
Jamie Iles1b8873a2010-02-02 20:25:44 +010029static int
Mark Rutlande1f431b2011-04-28 15:47:10 +010030armpmu_map_cache_event(const unsigned (*cache_map)
31 [PERF_COUNT_HW_CACHE_MAX]
32 [PERF_COUNT_HW_CACHE_OP_MAX]
33 [PERF_COUNT_HW_CACHE_RESULT_MAX],
34 u64 config)
Jamie Iles1b8873a2010-02-02 20:25:44 +010035{
36 unsigned int cache_type, cache_op, cache_result, ret;
37
38 cache_type = (config >> 0) & 0xff;
39 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
40 return -EINVAL;
41
42 cache_op = (config >> 8) & 0xff;
43 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
44 return -EINVAL;
45
46 cache_result = (config >> 16) & 0xff;
47 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
48 return -EINVAL;
49
Mark Rutlande1f431b2011-04-28 15:47:10 +010050 ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
Jamie Iles1b8873a2010-02-02 20:25:44 +010051
52 if (ret == CACHE_OP_UNSUPPORTED)
53 return -ENOENT;
54
55 return ret;
56}
57
58static int
Will Deacon6dbc0022012-07-29 12:36:28 +010059armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
Will Deacon84fee972010-11-13 17:13:56 +000060{
Stephen Boydd9f96632013-08-08 18:41:59 +010061 int mapping;
62
63 if (config >= PERF_COUNT_HW_MAX)
64 return -EINVAL;
65
66 mapping = (*event_map)[config];
Mark Rutlande1f431b2011-04-28 15:47:10 +010067 return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
Will Deacon84fee972010-11-13 17:13:56 +000068}
69
70static int
Mark Rutlande1f431b2011-04-28 15:47:10 +010071armpmu_map_raw_event(u32 raw_event_mask, u64 config)
Will Deacon84fee972010-11-13 17:13:56 +000072{
Mark Rutlande1f431b2011-04-28 15:47:10 +010073 return (int)(config & raw_event_mask);
74}
75
Will Deacon6dbc0022012-07-29 12:36:28 +010076int
77armpmu_map_event(struct perf_event *event,
78 const unsigned (*event_map)[PERF_COUNT_HW_MAX],
79 const unsigned (*cache_map)
80 [PERF_COUNT_HW_CACHE_MAX]
81 [PERF_COUNT_HW_CACHE_OP_MAX]
82 [PERF_COUNT_HW_CACHE_RESULT_MAX],
83 u32 raw_event_mask)
Mark Rutlande1f431b2011-04-28 15:47:10 +010084{
85 u64 config = event->attr.config;
Mark Rutland67b43052012-09-12 10:53:23 +010086 int type = event->attr.type;
Mark Rutlande1f431b2011-04-28 15:47:10 +010087
Mark Rutland67b43052012-09-12 10:53:23 +010088 if (type == event->pmu->type)
89 return armpmu_map_raw_event(raw_event_mask, config);
90
91 switch (type) {
Mark Rutlande1f431b2011-04-28 15:47:10 +010092 case PERF_TYPE_HARDWARE:
Will Deacon6dbc0022012-07-29 12:36:28 +010093 return armpmu_map_hw_event(event_map, config);
Mark Rutlande1f431b2011-04-28 15:47:10 +010094 case PERF_TYPE_HW_CACHE:
95 return armpmu_map_cache_event(cache_map, config);
96 case PERF_TYPE_RAW:
97 return armpmu_map_raw_event(raw_event_mask, config);
98 }
99
100 return -ENOENT;
Will Deacon84fee972010-11-13 17:13:56 +0000101}
102
Sudeep KarkadaNageshaed6f2a52012-07-30 12:00:02 +0100103int armpmu_event_set_period(struct perf_event *event)
Jamie Iles1b8873a2010-02-02 20:25:44 +0100104{
Mark Rutland8a16b342011-04-28 16:27:54 +0100105 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
Sudeep KarkadaNageshaed6f2a52012-07-30 12:00:02 +0100106 struct hw_perf_event *hwc = &event->hw;
Peter Zijlstrae7850592010-05-21 14:43:08 +0200107 s64 left = local64_read(&hwc->period_left);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100108 s64 period = hwc->sample_period;
109 int ret = 0;
110
111 if (unlikely(left <= -period)) {
112 left = period;
Peter Zijlstrae7850592010-05-21 14:43:08 +0200113 local64_set(&hwc->period_left, left);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100114 hwc->last_period = period;
115 ret = 1;
116 }
117
118 if (unlikely(left <= 0)) {
119 left += period;
Peter Zijlstrae7850592010-05-21 14:43:08 +0200120 local64_set(&hwc->period_left, left);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100121 hwc->last_period = period;
122 ret = 1;
123 }
124
Daniel Thompson2d9ed742015-01-05 15:58:54 +0100125 /*
126 * Limit the maximum period to prevent the counter value
127 * from overtaking the one we are about to program. In
128 * effect we are reducing max_period to account for
129 * interrupt latency (and we are being very conservative).
130 */
131 if (left > (armpmu->max_period >> 1))
132 left = armpmu->max_period >> 1;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100133
Peter Zijlstrae7850592010-05-21 14:43:08 +0200134 local64_set(&hwc->prev_count, (u64)-left);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100135
Sudeep KarkadaNageshaed6f2a52012-07-30 12:00:02 +0100136 armpmu->write_counter(event, (u64)(-left) & 0xffffffff);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100137
138 perf_event_update_userpage(event);
139
140 return ret;
141}
142
Sudeep KarkadaNageshaed6f2a52012-07-30 12:00:02 +0100143u64 armpmu_event_update(struct perf_event *event)
Jamie Iles1b8873a2010-02-02 20:25:44 +0100144{
Mark Rutland8a16b342011-04-28 16:27:54 +0100145 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
Sudeep KarkadaNageshaed6f2a52012-07-30 12:00:02 +0100146 struct hw_perf_event *hwc = &event->hw;
Will Deacona7378232011-03-25 17:12:37 +0100147 u64 delta, prev_raw_count, new_raw_count;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100148
149again:
Peter Zijlstrae7850592010-05-21 14:43:08 +0200150 prev_raw_count = local64_read(&hwc->prev_count);
Sudeep KarkadaNageshaed6f2a52012-07-30 12:00:02 +0100151 new_raw_count = armpmu->read_counter(event);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100152
Peter Zijlstrae7850592010-05-21 14:43:08 +0200153 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
Jamie Iles1b8873a2010-02-02 20:25:44 +0100154 new_raw_count) != prev_raw_count)
155 goto again;
156
Will Deacon57273472012-03-06 17:33:17 +0100157 delta = (new_raw_count - prev_raw_count) & armpmu->max_period;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100158
Peter Zijlstrae7850592010-05-21 14:43:08 +0200159 local64_add(delta, &event->count);
160 local64_sub(delta, &hwc->period_left);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100161
162 return new_raw_count;
163}
164
165static void
Jamie Iles1b8873a2010-02-02 20:25:44 +0100166armpmu_read(struct perf_event *event)
167{
Sudeep KarkadaNageshaed6f2a52012-07-30 12:00:02 +0100168 armpmu_event_update(event);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100169}
170
171static void
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200172armpmu_stop(struct perf_event *event, int flags)
Jamie Iles1b8873a2010-02-02 20:25:44 +0100173{
Mark Rutland8a16b342011-04-28 16:27:54 +0100174 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100175 struct hw_perf_event *hwc = &event->hw;
176
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200177 /*
178 * ARM pmu always has to update the counter, so ignore
179 * PERF_EF_UPDATE, see comments in armpmu_start().
180 */
181 if (!(hwc->state & PERF_HES_STOPPED)) {
Sudeep KarkadaNageshaed6f2a52012-07-30 12:00:02 +0100182 armpmu->disable(event);
183 armpmu_event_update(event);
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200184 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
185 }
186}
187
Sudeep KarkadaNageshaed6f2a52012-07-30 12:00:02 +0100188static void armpmu_start(struct perf_event *event, int flags)
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200189{
Mark Rutland8a16b342011-04-28 16:27:54 +0100190 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200191 struct hw_perf_event *hwc = &event->hw;
192
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200193 /*
194 * ARM pmu always has to reprogram the period, so ignore
195 * PERF_EF_RELOAD, see the comment below.
196 */
197 if (flags & PERF_EF_RELOAD)
198 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
199
200 hwc->state = 0;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100201 /*
202 * Set the period again. Some counters can't be stopped, so when we
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200203 * were stopped we simply disabled the IRQ source and the counter
Jamie Iles1b8873a2010-02-02 20:25:44 +0100204 * may have been left counting. If we don't do this step then we may
205 * get an interrupt too soon or *way* too late if the overflow has
206 * happened since disabling.
207 */
Sudeep KarkadaNageshaed6f2a52012-07-30 12:00:02 +0100208 armpmu_event_set_period(event);
209 armpmu->enable(event);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100210}
211
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200212static void
213armpmu_del(struct perf_event *event, int flags)
214{
Mark Rutland8a16b342011-04-28 16:27:54 +0100215 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
Mark Rutland11679252014-05-13 19:36:31 +0100216 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200217 struct hw_perf_event *hwc = &event->hw;
218 int idx = hwc->idx;
219
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200220 armpmu_stop(event, PERF_EF_UPDATE);
Mark Rutland8be3f9a2011-05-17 11:20:11 +0100221 hw_events->events[idx] = NULL;
222 clear_bit(idx, hw_events->used_mask);
Stephen Boydeab443e2014-02-07 21:01:22 +0000223 if (armpmu->clear_event_idx)
224 armpmu->clear_event_idx(hw_events, event);
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200225
226 perf_event_update_userpage(event);
227}
228
Jamie Iles1b8873a2010-02-02 20:25:44 +0100229static int
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200230armpmu_add(struct perf_event *event, int flags)
Jamie Iles1b8873a2010-02-02 20:25:44 +0100231{
Mark Rutland8a16b342011-04-28 16:27:54 +0100232 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
Mark Rutland11679252014-05-13 19:36:31 +0100233 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100234 struct hw_perf_event *hwc = &event->hw;
235 int idx;
236 int err = 0;
237
Mark Rutlandcc881162015-05-13 17:12:25 +0100238 /* An event following a process won't be stopped earlier */
239 if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
240 return -ENOENT;
241
Peter Zijlstra33696fc2010-06-14 08:49:00 +0200242 perf_pmu_disable(event->pmu);
Peter Zijlstra24cd7f52010-06-11 17:32:03 +0200243
Jamie Iles1b8873a2010-02-02 20:25:44 +0100244 /* If we don't have a space for the counter then finish early. */
Sudeep KarkadaNageshaed6f2a52012-07-30 12:00:02 +0100245 idx = armpmu->get_event_idx(hw_events, event);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100246 if (idx < 0) {
247 err = idx;
248 goto out;
249 }
250
251 /*
252 * If there is an event in the counter we are going to use then make
253 * sure it is disabled.
254 */
255 event->hw.idx = idx;
Sudeep KarkadaNageshaed6f2a52012-07-30 12:00:02 +0100256 armpmu->disable(event);
Mark Rutland8be3f9a2011-05-17 11:20:11 +0100257 hw_events->events[idx] = event;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100258
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200259 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
260 if (flags & PERF_EF_START)
261 armpmu_start(event, PERF_EF_RELOAD);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100262
263 /* Propagate our changes to the userspace mapping. */
264 perf_event_update_userpage(event);
265
266out:
Peter Zijlstra33696fc2010-06-14 08:49:00 +0200267 perf_pmu_enable(event->pmu);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100268 return err;
269}
270
Jamie Iles1b8873a2010-02-02 20:25:44 +0100271static int
Suzuki K. Poulosee4298172015-03-17 18:14:58 +0000272validate_event(struct pmu *pmu, struct pmu_hw_events *hw_events,
273 struct perf_event *event)
Jamie Iles1b8873a2010-02-02 20:25:44 +0100274{
Suzuki K. Poulosee4298172015-03-17 18:14:58 +0000275 struct arm_pmu *armpmu;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100276
Will Deaconc95eb312013-08-07 23:39:41 +0100277 if (is_software_event(event))
278 return 1;
279
Suzuki K. Poulosee4298172015-03-17 18:14:58 +0000280 /*
281 * Reject groups spanning multiple HW PMUs (e.g. CPU + CCI). The
282 * core perf code won't check that the pmu->ctx == leader->ctx
283 * until after pmu->event_init(event).
284 */
285 if (event->pmu != pmu)
286 return 0;
287
Will Deacon2dfcb802013-10-09 13:51:29 +0100288 if (event->state < PERF_EVENT_STATE_OFF)
Will Deaconcb2d8b32013-04-12 19:04:19 +0100289 return 1;
290
291 if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec)
Will Deacon65b47112010-09-02 09:32:08 +0100292 return 1;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100293
Suzuki K. Poulosee4298172015-03-17 18:14:58 +0000294 armpmu = to_arm_pmu(event->pmu);
Sudeep KarkadaNageshaed6f2a52012-07-30 12:00:02 +0100295 return armpmu->get_event_idx(hw_events, event) >= 0;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100296}
297
298static int
299validate_group(struct perf_event *event)
300{
301 struct perf_event *sibling, *leader = event->group_leader;
Mark Rutland8be3f9a2011-05-17 11:20:11 +0100302 struct pmu_hw_events fake_pmu;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100303
Will Deaconbce34d12011-11-17 15:05:14 +0000304 /*
305 * Initialise the fake PMU. We only need to populate the
306 * used_mask for the purposes of validation.
307 */
Mark Rutlanda4560842014-05-13 19:08:19 +0100308 memset(&fake_pmu.used_mask, 0, sizeof(fake_pmu.used_mask));
Jamie Iles1b8873a2010-02-02 20:25:44 +0100309
Suzuki K. Poulosee4298172015-03-17 18:14:58 +0000310 if (!validate_event(event->pmu, &fake_pmu, leader))
Peter Zijlstraaa2bc1a2011-11-09 17:56:37 +0100311 return -EINVAL;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100312
313 list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
Suzuki K. Poulosee4298172015-03-17 18:14:58 +0000314 if (!validate_event(event->pmu, &fake_pmu, sibling))
Peter Zijlstraaa2bc1a2011-11-09 17:56:37 +0100315 return -EINVAL;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100316 }
317
Suzuki K. Poulosee4298172015-03-17 18:14:58 +0000318 if (!validate_event(event->pmu, &fake_pmu, event))
Peter Zijlstraaa2bc1a2011-11-09 17:56:37 +0100319 return -EINVAL;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100320
321 return 0;
322}
323
Sudeep KarkadaNagesha051f1b12012-07-31 10:34:25 +0100324static irqreturn_t armpmu_dispatch_irq(int irq, void *dev)
Rabin Vincent0e25a5c2011-02-08 09:24:36 +0530325{
Stephen Boydbbd64552014-02-07 21:01:19 +0000326 struct arm_pmu *armpmu;
327 struct platform_device *plat_device;
328 struct arm_pmu_platdata *plat;
Will Deacon5f5092e2014-02-11 18:08:41 +0000329 int ret;
330 u64 start_clock, finish_clock;
Stephen Boydbbd64552014-02-07 21:01:19 +0000331
Mark Rutland5ebd9202014-05-13 19:46:10 +0100332 /*
333 * we request the IRQ with a (possibly percpu) struct arm_pmu**, but
334 * the handlers expect a struct arm_pmu*. The percpu_irq framework will
335 * do any necessary shifting, we just need to perform the first
336 * dereference.
337 */
338 armpmu = *(void **)dev;
Stephen Boydbbd64552014-02-07 21:01:19 +0000339 plat_device = armpmu->plat_device;
340 plat = dev_get_platdata(&plat_device->dev);
Rabin Vincent0e25a5c2011-02-08 09:24:36 +0530341
Will Deacon5f5092e2014-02-11 18:08:41 +0000342 start_clock = sched_clock();
Sudeep KarkadaNagesha051f1b12012-07-31 10:34:25 +0100343 if (plat && plat->handle_irq)
Mark Rutland5ebd9202014-05-13 19:46:10 +0100344 ret = plat->handle_irq(irq, armpmu, armpmu->handle_irq);
Sudeep KarkadaNagesha051f1b12012-07-31 10:34:25 +0100345 else
Mark Rutland5ebd9202014-05-13 19:46:10 +0100346 ret = armpmu->handle_irq(irq, armpmu);
Will Deacon5f5092e2014-02-11 18:08:41 +0000347 finish_clock = sched_clock();
348
349 perf_sample_event_took(finish_clock - start_clock);
350 return ret;
Rabin Vincent0e25a5c2011-02-08 09:24:36 +0530351}
352
Will Deacon0b390e22011-07-27 15:18:59 +0100353static void
Mark Rutland8a16b342011-04-28 16:27:54 +0100354armpmu_release_hardware(struct arm_pmu *armpmu)
Will Deacon0b390e22011-07-27 15:18:59 +0100355{
Sudeep KarkadaNageshaed6f2a52012-07-30 12:00:02 +0100356 armpmu->free_irq(armpmu);
Will Deacon0b390e22011-07-27 15:18:59 +0100357}
358
Jamie Iles1b8873a2010-02-02 20:25:44 +0100359static int
Mark Rutland8a16b342011-04-28 16:27:54 +0100360armpmu_reserve_hardware(struct arm_pmu *armpmu)
Jamie Iles1b8873a2010-02-02 20:25:44 +0100361{
Mark Rutlanded61f982015-05-26 17:23:34 +0100362 int err = armpmu->request_irq(armpmu, armpmu_dispatch_irq);
Sudeep KarkadaNagesha051f1b12012-07-31 10:34:25 +0100363 if (err) {
364 armpmu_release_hardware(armpmu);
365 return err;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100366 }
367
Will Deacon0b390e22011-07-27 15:18:59 +0100368 return 0;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100369}
370
Jamie Iles1b8873a2010-02-02 20:25:44 +0100371static void
372hw_perf_event_destroy(struct perf_event *event)
373{
Mark Rutland8a16b342011-04-28 16:27:54 +0100374 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
Mark Rutland03b78982011-04-27 11:20:11 +0100375 atomic_t *active_events = &armpmu->active_events;
376 struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex;
377
378 if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) {
Mark Rutland8a16b342011-04-28 16:27:54 +0100379 armpmu_release_hardware(armpmu);
Mark Rutland03b78982011-04-27 11:20:11 +0100380 mutex_unlock(pmu_reserve_mutex);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100381 }
382}
383
384static int
Will Deacon05d22fd2011-07-19 11:57:30 +0100385event_requires_mode_exclusion(struct perf_event_attr *attr)
386{
387 return attr->exclude_idle || attr->exclude_user ||
388 attr->exclude_kernel || attr->exclude_hv;
389}
390
391static int
Jamie Iles1b8873a2010-02-02 20:25:44 +0100392__hw_perf_event_init(struct perf_event *event)
393{
Mark Rutland8a16b342011-04-28 16:27:54 +0100394 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100395 struct hw_perf_event *hwc = &event->hw;
Mark Rutland9dcbf462013-01-18 16:10:06 +0000396 int mapping;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100397
Mark Rutlande1f431b2011-04-28 15:47:10 +0100398 mapping = armpmu->map_event(event);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100399
400 if (mapping < 0) {
401 pr_debug("event %x:%llx not supported\n", event->attr.type,
402 event->attr.config);
403 return mapping;
404 }
405
406 /*
Will Deacon05d22fd2011-07-19 11:57:30 +0100407 * We don't assign an index until we actually place the event onto
408 * hardware. Use -1 to signify that we haven't decided where to put it
409 * yet. For SMP systems, each core has it's own PMU so we can't do any
410 * clever allocation or constraints checking at this point.
Jamie Iles1b8873a2010-02-02 20:25:44 +0100411 */
Will Deacon05d22fd2011-07-19 11:57:30 +0100412 hwc->idx = -1;
413 hwc->config_base = 0;
414 hwc->config = 0;
415 hwc->event_base = 0;
416
417 /*
418 * Check whether we need to exclude the counter from certain modes.
419 */
420 if ((!armpmu->set_event_filter ||
421 armpmu->set_event_filter(hwc, &event->attr)) &&
422 event_requires_mode_exclusion(&event->attr)) {
Jamie Iles1b8873a2010-02-02 20:25:44 +0100423 pr_debug("ARM performance counters do not support "
424 "mode exclusion\n");
Will Deaconfdeb8e32012-07-04 18:15:42 +0100425 return -EOPNOTSUPP;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100426 }
427
428 /*
Will Deacon05d22fd2011-07-19 11:57:30 +0100429 * Store the event encoding into the config_base field.
Jamie Iles1b8873a2010-02-02 20:25:44 +0100430 */
Will Deacon05d22fd2011-07-19 11:57:30 +0100431 hwc->config_base |= (unsigned long)mapping;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100432
Vince Weaveredcb4d32014-05-16 17:15:49 -0400433 if (!is_sampling_event(event)) {
Will Deacon57273472012-03-06 17:33:17 +0100434 /*
435 * For non-sampling runs, limit the sample_period to half
436 * of the counter width. That way, the new counter value
437 * is far less likely to overtake the previous one unless
438 * you have some serious IRQ latency issues.
439 */
440 hwc->sample_period = armpmu->max_period >> 1;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100441 hwc->last_period = hwc->sample_period;
Peter Zijlstrae7850592010-05-21 14:43:08 +0200442 local64_set(&hwc->period_left, hwc->sample_period);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100443 }
444
Jamie Iles1b8873a2010-02-02 20:25:44 +0100445 if (event->group_leader != event) {
Chen Gange595ede2013-02-28 17:51:29 +0100446 if (validate_group(event) != 0)
Jamie Iles1b8873a2010-02-02 20:25:44 +0100447 return -EINVAL;
448 }
449
Mark Rutland9dcbf462013-01-18 16:10:06 +0000450 return 0;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100451}
452
Peter Zijlstrab0a873e2010-06-11 13:35:08 +0200453static int armpmu_event_init(struct perf_event *event)
Jamie Iles1b8873a2010-02-02 20:25:44 +0100454{
Mark Rutland8a16b342011-04-28 16:27:54 +0100455 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100456 int err = 0;
Mark Rutland03b78982011-04-27 11:20:11 +0100457 atomic_t *active_events = &armpmu->active_events;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100458
Mark Rutlandcc881162015-05-13 17:12:25 +0100459 /*
460 * Reject CPU-affine events for CPUs that are of a different class to
461 * that which this PMU handles. Process-following events (where
462 * event->cpu == -1) can be migrated between CPUs, and thus we have to
463 * reject them later (in armpmu_add) if they're scheduled on a
464 * different class of CPU.
465 */
466 if (event->cpu != -1 &&
467 !cpumask_test_cpu(event->cpu, &armpmu->supported_cpus))
468 return -ENOENT;
469
Stephane Eranian2481c5f2012-02-09 23:20:59 +0100470 /* does not support taken branch sampling */
471 if (has_branch_stack(event))
472 return -EOPNOTSUPP;
473
Mark Rutlande1f431b2011-04-28 15:47:10 +0100474 if (armpmu->map_event(event) == -ENOENT)
Peter Zijlstrab0a873e2010-06-11 13:35:08 +0200475 return -ENOENT;
Peter Zijlstrab0a873e2010-06-11 13:35:08 +0200476
Jamie Iles1b8873a2010-02-02 20:25:44 +0100477 event->destroy = hw_perf_event_destroy;
478
Mark Rutland03b78982011-04-27 11:20:11 +0100479 if (!atomic_inc_not_zero(active_events)) {
480 mutex_lock(&armpmu->reserve_mutex);
481 if (atomic_read(active_events) == 0)
Mark Rutland8a16b342011-04-28 16:27:54 +0100482 err = armpmu_reserve_hardware(armpmu);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100483
484 if (!err)
Mark Rutland03b78982011-04-27 11:20:11 +0100485 atomic_inc(active_events);
486 mutex_unlock(&armpmu->reserve_mutex);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100487 }
488
489 if (err)
Peter Zijlstrab0a873e2010-06-11 13:35:08 +0200490 return err;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100491
492 err = __hw_perf_event_init(event);
493 if (err)
494 hw_perf_event_destroy(event);
495
Peter Zijlstrab0a873e2010-06-11 13:35:08 +0200496 return err;
Jamie Iles1b8873a2010-02-02 20:25:44 +0100497}
498
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200499static void armpmu_enable(struct pmu *pmu)
Jamie Iles1b8873a2010-02-02 20:25:44 +0100500{
Mark Rutland8be3f9a2011-05-17 11:20:11 +0100501 struct arm_pmu *armpmu = to_arm_pmu(pmu);
Mark Rutland11679252014-05-13 19:36:31 +0100502 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
Mark Rutland7325eae2011-08-23 11:59:49 +0100503 int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100504
Mark Rutlandcc881162015-05-13 17:12:25 +0100505 /* For task-bound events we may be called on other CPUs */
506 if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
507 return;
508
Will Deaconf4f38432011-07-01 14:38:12 +0100509 if (enabled)
Sudeep KarkadaNageshaed6f2a52012-07-30 12:00:02 +0100510 armpmu->start(armpmu);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100511}
512
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200513static void armpmu_disable(struct pmu *pmu)
Jamie Iles1b8873a2010-02-02 20:25:44 +0100514{
Mark Rutland8a16b342011-04-28 16:27:54 +0100515 struct arm_pmu *armpmu = to_arm_pmu(pmu);
Mark Rutlandcc881162015-05-13 17:12:25 +0100516
517 /* For task-bound events we may be called on other CPUs */
518 if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
519 return;
520
Sudeep KarkadaNageshaed6f2a52012-07-30 12:00:02 +0100521 armpmu->stop(armpmu);
Jamie Iles1b8873a2010-02-02 20:25:44 +0100522}
523
Mark Rutlandc904e322015-05-13 17:12:26 +0100524/*
525 * In heterogeneous systems, events are specific to a particular
526 * microarchitecture, and aren't suitable for another. Thus, only match CPUs of
527 * the same microarchitecture.
528 */
529static int armpmu_filter_match(struct perf_event *event)
530{
531 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
532 unsigned int cpu = smp_processor_id();
533 return cpumask_test_cpu(cpu, &armpmu->supported_cpus);
534}
535
Stephen Boyd44d6b1f2013-03-05 03:54:06 +0100536static void armpmu_init(struct arm_pmu *armpmu)
Mark Rutland03b78982011-04-27 11:20:11 +0100537{
538 atomic_set(&armpmu->active_events, 0);
539 mutex_init(&armpmu->reserve_mutex);
Mark Rutland8a16b342011-04-28 16:27:54 +0100540
541 armpmu->pmu = (struct pmu) {
542 .pmu_enable = armpmu_enable,
543 .pmu_disable = armpmu_disable,
544 .event_init = armpmu_event_init,
545 .add = armpmu_add,
546 .del = armpmu_del,
547 .start = armpmu_start,
548 .stop = armpmu_stop,
549 .read = armpmu_read,
Mark Rutlandc904e322015-05-13 17:12:26 +0100550 .filter_match = armpmu_filter_match,
Mark Rutland8a16b342011-04-28 16:27:54 +0100551 };
552}
553
Will Deacon03052302012-09-21 14:23:47 +0100554int armpmu_register(struct arm_pmu *armpmu, int type)
Mark Rutland8a16b342011-04-28 16:27:54 +0100555{
556 armpmu_init(armpmu);
Will Deacon04236f92012-07-28 17:42:22 +0100557 pr_info("enabled with %s PMU driver, %d counters available\n",
558 armpmu->name, armpmu->num_events);
Will Deacon03052302012-09-21 14:23:47 +0100559 return perf_pmu_register(&armpmu->pmu, armpmu->name, type);
Mark Rutland03b78982011-04-27 11:20:11 +0100560}
561
Mark Rutland74cf0bc2015-05-26 17:23:39 +0100562/* Set at runtime when we know what CPU type we are. */
563static struct arm_pmu *__oprofile_cpu_pmu;
564
565/*
566 * Despite the names, these two functions are CPU-specific and are used
567 * by the OProfile/perf code.
568 */
569const char *perf_pmu_name(void)
570{
571 if (!__oprofile_cpu_pmu)
572 return NULL;
573
574 return __oprofile_cpu_pmu->name;
575}
576EXPORT_SYMBOL_GPL(perf_pmu_name);
577
578int perf_num_counters(void)
579{
580 int max_events = 0;
581
582 if (__oprofile_cpu_pmu != NULL)
583 max_events = __oprofile_cpu_pmu->num_events;
584
585 return max_events;
586}
587EXPORT_SYMBOL_GPL(perf_num_counters);
588
589static void cpu_pmu_enable_percpu_irq(void *data)
590{
591 int irq = *(int *)data;
592
593 enable_percpu_irq(irq, IRQ_TYPE_NONE);
594}
595
596static void cpu_pmu_disable_percpu_irq(void *data)
597{
598 int irq = *(int *)data;
599
600 disable_percpu_irq(irq);
601}
602
603static void cpu_pmu_free_irq(struct arm_pmu *cpu_pmu)
604{
605 int i, irq, irqs;
606 struct platform_device *pmu_device = cpu_pmu->plat_device;
607 struct pmu_hw_events __percpu *hw_events = cpu_pmu->hw_events;
608
609 irqs = min(pmu_device->num_resources, num_possible_cpus());
610
611 irq = platform_get_irq(pmu_device, 0);
612 if (irq >= 0 && irq_is_percpu(irq)) {
613 on_each_cpu(cpu_pmu_disable_percpu_irq, &irq, 1);
614 free_percpu_irq(irq, &hw_events->percpu_pmu);
615 } else {
616 for (i = 0; i < irqs; ++i) {
617 int cpu = i;
618
619 if (cpu_pmu->irq_affinity)
620 cpu = cpu_pmu->irq_affinity[i];
621
622 if (!cpumask_test_and_clear_cpu(cpu, &cpu_pmu->active_irqs))
623 continue;
624 irq = platform_get_irq(pmu_device, i);
625 if (irq >= 0)
626 free_irq(irq, per_cpu_ptr(&hw_events->percpu_pmu, cpu));
627 }
628 }
629}
630
631static int cpu_pmu_request_irq(struct arm_pmu *cpu_pmu, irq_handler_t handler)
632{
633 int i, err, irq, irqs;
634 struct platform_device *pmu_device = cpu_pmu->plat_device;
635 struct pmu_hw_events __percpu *hw_events = cpu_pmu->hw_events;
636
637 if (!pmu_device)
638 return -ENODEV;
639
640 irqs = min(pmu_device->num_resources, num_possible_cpus());
641 if (irqs < 1) {
642 pr_warn_once("perf/ARM: No irqs for PMU defined, sampling events not supported\n");
643 return 0;
644 }
645
646 irq = platform_get_irq(pmu_device, 0);
647 if (irq >= 0 && irq_is_percpu(irq)) {
648 err = request_percpu_irq(irq, handler, "arm-pmu",
649 &hw_events->percpu_pmu);
650 if (err) {
651 pr_err("unable to request IRQ%d for ARM PMU counters\n",
652 irq);
653 return err;
654 }
655 on_each_cpu(cpu_pmu_enable_percpu_irq, &irq, 1);
656 } else {
657 for (i = 0; i < irqs; ++i) {
658 int cpu = i;
659
660 err = 0;
661 irq = platform_get_irq(pmu_device, i);
662 if (irq < 0)
663 continue;
664
665 if (cpu_pmu->irq_affinity)
666 cpu = cpu_pmu->irq_affinity[i];
667
668 /*
669 * If we have a single PMU interrupt that we can't shift,
670 * assume that we're running on a uniprocessor machine and
671 * continue. Otherwise, continue without this interrupt.
672 */
673 if (irq_set_affinity(irq, cpumask_of(cpu)) && irqs > 1) {
674 pr_warn("unable to set irq affinity (irq=%d, cpu=%u)\n",
675 irq, cpu);
676 continue;
677 }
678
679 err = request_irq(irq, handler,
680 IRQF_NOBALANCING | IRQF_NO_THREAD, "arm-pmu",
681 per_cpu_ptr(&hw_events->percpu_pmu, cpu));
682 if (err) {
683 pr_err("unable to request IRQ%d for ARM PMU counters\n",
684 irq);
685 return err;
686 }
687
688 cpumask_set_cpu(cpu, &cpu_pmu->active_irqs);
689 }
690 }
691
692 return 0;
693}
694
695/*
696 * PMU hardware loses all context when a CPU goes offline.
697 * When a CPU is hotplugged back in, since some hardware registers are
698 * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
699 * junk values out of them.
700 */
701static int cpu_pmu_notify(struct notifier_block *b, unsigned long action,
702 void *hcpu)
703{
704 int cpu = (unsigned long)hcpu;
705 struct arm_pmu *pmu = container_of(b, struct arm_pmu, hotplug_nb);
706
707 if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
708 return NOTIFY_DONE;
709
710 if (!cpumask_test_cpu(cpu, &pmu->supported_cpus))
711 return NOTIFY_DONE;
712
713 if (pmu->reset)
714 pmu->reset(pmu);
715 else
716 return NOTIFY_DONE;
717
718 return NOTIFY_OK;
719}
720
721static int cpu_pmu_init(struct arm_pmu *cpu_pmu)
722{
723 int err;
724 int cpu;
725 struct pmu_hw_events __percpu *cpu_hw_events;
726
727 cpu_hw_events = alloc_percpu(struct pmu_hw_events);
728 if (!cpu_hw_events)
729 return -ENOMEM;
730
731 cpu_pmu->hotplug_nb.notifier_call = cpu_pmu_notify;
732 err = register_cpu_notifier(&cpu_pmu->hotplug_nb);
733 if (err)
734 goto out_hw_events;
735
736 for_each_possible_cpu(cpu) {
737 struct pmu_hw_events *events = per_cpu_ptr(cpu_hw_events, cpu);
738 raw_spin_lock_init(&events->pmu_lock);
739 events->percpu_pmu = cpu_pmu;
740 }
741
742 cpu_pmu->hw_events = cpu_hw_events;
743 cpu_pmu->request_irq = cpu_pmu_request_irq;
744 cpu_pmu->free_irq = cpu_pmu_free_irq;
745
746 /* Ensure the PMU has sane values out of reset. */
747 if (cpu_pmu->reset)
748 on_each_cpu_mask(&cpu_pmu->supported_cpus, cpu_pmu->reset,
749 cpu_pmu, 1);
750
751 /* If no interrupts available, set the corresponding capability flag */
752 if (!platform_get_irq(cpu_pmu->plat_device, 0))
753 cpu_pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
754
755 return 0;
756
757out_hw_events:
758 free_percpu(cpu_hw_events);
759 return err;
760}
761
762static void cpu_pmu_destroy(struct arm_pmu *cpu_pmu)
763{
764 unregister_cpu_notifier(&cpu_pmu->hotplug_nb);
765 free_percpu(cpu_pmu->hw_events);
766}
767
768/*
769 * CPU PMU identification and probing.
770 */
771static int probe_current_pmu(struct arm_pmu *pmu,
772 const struct pmu_probe_info *info)
773{
774 int cpu = get_cpu();
775 unsigned int cpuid = read_cpuid_id();
776 int ret = -ENODEV;
777
778 pr_info("probing PMU on CPU %d\n", cpu);
779
780 for (; info->init != NULL; info++) {
781 if ((cpuid & info->mask) != info->cpuid)
782 continue;
783 ret = info->init(pmu);
784 break;
785 }
786
787 put_cpu();
788 return ret;
789}
790
791static int of_pmu_irq_cfg(struct arm_pmu *pmu)
792{
Will Deaconb6c084d2015-06-29 13:59:01 +0100793 int *irqs, i = 0;
794 bool using_spi = false;
Mark Rutland74cf0bc2015-05-26 17:23:39 +0100795 struct platform_device *pdev = pmu->plat_device;
796
Mark Rutland74cf0bc2015-05-26 17:23:39 +0100797 irqs = kcalloc(pdev->num_resources, sizeof(*irqs), GFP_KERNEL);
798 if (!irqs)
799 return -ENOMEM;
800
Will Deaconb6c084d2015-06-29 13:59:01 +0100801 do {
Mark Rutland74cf0bc2015-05-26 17:23:39 +0100802 struct device_node *dn;
Will Deaconb6c084d2015-06-29 13:59:01 +0100803 int cpu, irq;
Mark Rutland74cf0bc2015-05-26 17:23:39 +0100804
Will Deaconb6c084d2015-06-29 13:59:01 +0100805 /* See if we have an affinity entry */
806 dn = of_parse_phandle(pdev->dev.of_node, "interrupt-affinity", i);
807 if (!dn)
Mark Rutland74cf0bc2015-05-26 17:23:39 +0100808 break;
Will Deaconb6c084d2015-06-29 13:59:01 +0100809
810 /* Check the IRQ type and prohibit a mix of PPIs and SPIs */
811 irq = platform_get_irq(pdev, i);
812 if (irq >= 0) {
813 bool spi = !irq_is_percpu(irq);
814
815 if (i > 0 && spi != using_spi) {
816 pr_err("PPI/SPI IRQ type mismatch for %s!\n",
817 dn->name);
818 kfree(irqs);
819 return -EINVAL;
820 }
821
822 using_spi = spi;
Mark Rutland74cf0bc2015-05-26 17:23:39 +0100823 }
824
Will Deaconb6c084d2015-06-29 13:59:01 +0100825 /* Now look up the logical CPU number */
Mark Rutland74cf0bc2015-05-26 17:23:39 +0100826 for_each_possible_cpu(cpu)
Sudeep Hollabc1e3c42015-06-30 13:56:57 +0100827 if (dn == of_cpu_device_node_get(cpu))
Mark Rutland74cf0bc2015-05-26 17:23:39 +0100828 break;
829
Mark Rutland74cf0bc2015-05-26 17:23:39 +0100830 if (cpu >= nr_cpu_ids) {
831 pr_warn("Failed to find logical CPU for %s\n",
832 dn->name);
Stephen Boyd8e0c34b2015-07-07 18:17:05 +0100833 of_node_put(dn);
Will Deaconb6c084d2015-06-29 13:59:01 +0100834 cpumask_setall(&pmu->supported_cpus);
Mark Rutland74cf0bc2015-05-26 17:23:39 +0100835 break;
836 }
Stephen Boyd8e0c34b2015-07-07 18:17:05 +0100837 of_node_put(dn);
Mark Rutland74cf0bc2015-05-26 17:23:39 +0100838
Will Deaconb6c084d2015-06-29 13:59:01 +0100839 /* For SPIs, we need to track the affinity per IRQ */
840 if (using_spi) {
841 if (i >= pdev->num_resources) {
842 of_node_put(dn);
843 break;
844 }
Mark Rutland74cf0bc2015-05-26 17:23:39 +0100845
Will Deaconb6c084d2015-06-29 13:59:01 +0100846 irqs[i] = cpu;
847 }
848
849 /* Keep track of the CPUs containing this PMU type */
850 cpumask_set_cpu(cpu, &pmu->supported_cpus);
851 of_node_put(dn);
852 i++;
853 } while (1);
854
855 /* If we didn't manage to parse anything, claim to support all CPUs */
856 if (cpumask_weight(&pmu->supported_cpus) == 0)
Mark Rutland74cf0bc2015-05-26 17:23:39 +0100857 cpumask_setall(&pmu->supported_cpus);
Will Deaconb6c084d2015-06-29 13:59:01 +0100858
859 /* If we matched up the IRQ affinities, use them to route the SPIs */
860 if (using_spi && i == pdev->num_resources)
861 pmu->irq_affinity = irqs;
862 else
863 kfree(irqs);
Mark Rutland74cf0bc2015-05-26 17:23:39 +0100864
865 return 0;
866}
867
868int arm_pmu_device_probe(struct platform_device *pdev,
869 const struct of_device_id *of_table,
870 const struct pmu_probe_info *probe_table)
871{
872 const struct of_device_id *of_id;
873 const int (*init_fn)(struct arm_pmu *);
874 struct device_node *node = pdev->dev.of_node;
875 struct arm_pmu *pmu;
876 int ret = -ENODEV;
877
878 pmu = kzalloc(sizeof(struct arm_pmu), GFP_KERNEL);
879 if (!pmu) {
880 pr_info("failed to allocate PMU device!\n");
881 return -ENOMEM;
882 }
883
884 if (!__oprofile_cpu_pmu)
885 __oprofile_cpu_pmu = pmu;
886
887 pmu->plat_device = pdev;
888
889 if (node && (of_id = of_match_node(of_table, pdev->dev.of_node))) {
890 init_fn = of_id->data;
891
892 ret = of_pmu_irq_cfg(pmu);
893 if (!ret)
894 ret = init_fn(pmu);
895 } else {
896 ret = probe_current_pmu(pmu, probe_table);
897 cpumask_setall(&pmu->supported_cpus);
898 }
899
900 if (ret) {
901 pr_info("failed to probe PMU!\n");
902 goto out_free;
903 }
904
905 ret = cpu_pmu_init(pmu);
906 if (ret)
907 goto out_free;
908
909 ret = armpmu_register(pmu, -1);
910 if (ret)
911 goto out_destroy;
912
913 return 0;
914
915out_destroy:
916 cpu_pmu_destroy(pmu);
917out_free:
918 pr_info("failed to register PMU devices!\n");
919 kfree(pmu);
920 return ret;
921}