blob: 6104dba380b626443512a889fd6c66629f376092 [file] [log] [blame]
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001/*
2 * Intel 7300 class Memory Controllers kernel module (Clarksboro)
3 *
4 * This file may be distributed under the terms of the
5 * GNU General Public License version 2 only.
6 *
7 * Copyright (c) 2010 by:
8 * Mauro Carvalho Chehab <mchehab@redhat.com>
9 *
10 * Red Hat Inc. http://www.redhat.com
11 *
12 * Intel 7300 Chipset Memory Controller Hub (MCH) - Datasheet
13 * http://www.intel.com/Assets/PDF/datasheet/318082.pdf
14 *
15 * TODO: The chipset allow checking for PCI Express errors also. Currently,
16 * the driver covers only memory error errors
17 *
18 * This driver uses "csrows" EDAC attribute to represent DIMM slot#
19 */
20
21#include <linux/module.h>
22#include <linux/init.h>
23#include <linux/pci.h>
24#include <linux/pci_ids.h>
25#include <linux/slab.h>
26#include <linux/edac.h>
27#include <linux/mmzone.h>
28
29#include "edac_core.h"
30
31/*
32 * Alter this version for the I7300 module when modifications are made
33 */
Michal Marek152ba392011-04-01 12:41:20 +020034#define I7300_REVISION " Ver: 1.0.0"
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -030035
36#define EDAC_MOD_STR "i7300_edac"
37
38#define i7300_printk(level, fmt, arg...) \
39 edac_printk(level, "i7300", fmt, ##arg)
40
41#define i7300_mc_printk(mci, level, fmt, arg...) \
42 edac_mc_chipset_printk(mci, level, "i7300", fmt, ##arg)
43
Mauro Carvalho Chehabb4552ac2010-08-27 16:43:01 -030044/***********************************************
45 * i7300 Limit constants Structs and static vars
46 ***********************************************/
47
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -030048/*
49 * Memory topology is organized as:
50 * Branch 0 - 2 channels: channels 0 and 1 (FDB0 PCI dev 21.0)
51 * Branch 1 - 2 channels: channels 2 and 3 (FDB1 PCI dev 22.0)
52 * Each channel can have to 8 DIMM sets (called as SLOTS)
53 * Slots should generally be filled in pairs
54 * Except on Single Channel mode of operation
55 * just slot 0/channel0 filled on this mode
56 * On normal operation mode, the two channels on a branch should be
Mauro Carvalho Chehabc3af2ea2010-08-26 19:54:51 -030057 * filled together for the same SLOT#
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -030058 * When in mirrored mode, Branch 1 replicate memory at Branch 0, so, the four
59 * channels on both branches should be filled
60 */
61
62/* Limits for i7300 */
63#define MAX_SLOTS 8
64#define MAX_BRANCHES 2
65#define MAX_CH_PER_BRANCH 2
66#define MAX_CHANNELS (MAX_CH_PER_BRANCH * MAX_BRANCHES)
67#define MAX_MIR 3
68
69#define to_channel(ch, branch) ((((branch)) << 1) | (ch))
70
71#define to_csrow(slot, ch, branch) \
72 (to_channel(ch, branch) | ((slot) << 2))
73
Mauro Carvalho Chehabb4552ac2010-08-27 16:43:01 -030074/* Device name and register DID (Device ID) */
75struct i7300_dev_info {
76 const char *ctl_name; /* name for this device */
77 u16 fsb_mapping_errors; /* DID for the branchmap,control */
78};
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -030079
Mauro Carvalho Chehabb4552ac2010-08-27 16:43:01 -030080/* Table of devices attributes supported by this driver */
81static const struct i7300_dev_info i7300_devs[] = {
82 {
83 .ctl_name = "I7300",
84 .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_I7300_MCH_ERR,
85 },
86};
87
88struct i7300_dimm_info {
89 int megabytes; /* size, 0 means not present */
90};
91
92/* driver private data structure */
93struct i7300_pvt {
94 struct pci_dev *pci_dev_16_0_fsb_ctlr; /* 16.0 */
95 struct pci_dev *pci_dev_16_1_fsb_addr_map; /* 16.1 */
96 struct pci_dev *pci_dev_16_2_fsb_err_regs; /* 16.2 */
97 struct pci_dev *pci_dev_2x_0_fbd_branch[MAX_BRANCHES]; /* 21.0 and 22.0 */
98
99 u16 tolm; /* top of low memory */
100 u64 ambase; /* AMB BAR */
101
102 u32 mc_settings; /* Report several settings */
103 u32 mc_settings_a;
104
105 u16 mir[MAX_MIR]; /* Memory Interleave Reg*/
106
Mauro Carvalho Chehab9c6f6b62010-08-27 17:43:43 -0300107 u16 mtr[MAX_SLOTS][MAX_BRANCHES]; /* Memory Technlogy Reg */
Mauro Carvalho Chehabb4552ac2010-08-27 16:43:01 -0300108 u16 ambpresent[MAX_CHANNELS]; /* AMB present regs */
109
110 /* DIMM information matrix, allocating architecture maximums */
111 struct i7300_dimm_info dimm_info[MAX_SLOTS][MAX_CHANNELS];
112
113 /* Temporary buffer for use when preparing error messages */
114 char *tmp_prt_buffer;
115};
116
117/* FIXME: Why do we need to have this static? */
118static struct edac_pci_ctl_info *i7300_pci;
119
120/***************************************************
121 * i7300 Register definitions for memory enumeration
122 ***************************************************/
123
124/*
Mauro Carvalho Chehabc3af2ea2010-08-26 19:54:51 -0300125 * Device 16,
126 * Function 0: System Address (not documented)
127 * Function 1: Memory Branch Map, Control, Errors Register
128 */
129
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300130 /* OFFSETS for Function 0 */
Mauro Carvalho Chehabaf3d8832010-08-26 20:58:45 -0300131#define AMBASE 0x48 /* AMB Mem Mapped Reg Region Base */
132#define MAXCH 0x56 /* Max Channel Number */
133#define MAXDIMMPERCH 0x57 /* Max DIMM PER Channel Number */
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300134
135 /* OFFSETS for Function 1 */
Mauro Carvalho Chehabaf3d8832010-08-26 20:58:45 -0300136#define MC_SETTINGS 0x40
Mauro Carvalho Chehabbb81a212010-08-27 09:04:11 -0300137 #define IS_MIRRORED(mc) ((mc) & (1 << 16))
138 #define IS_ECC_ENABLED(mc) ((mc) & (1 << 5))
139 #define IS_RETRY_ENABLED(mc) ((mc) & (1 << 31))
140 #define IS_SCRBALGO_ENHANCED(mc) ((mc) & (1 << 8))
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300141
Mauro Carvalho Chehabbb81a212010-08-27 09:04:11 -0300142#define MC_SETTINGS_A 0x58
143 #define IS_SINGLE_MODE(mca) ((mca) & (1 << 14))
Mauro Carvalho Chehabd7de2bd2010-08-27 08:56:48 -0300144
Mauro Carvalho Chehabaf3d8832010-08-26 20:58:45 -0300145#define TOLM 0x6C
Mauro Carvalho Chehabaf3d8832010-08-26 20:58:45 -0300146
147#define MIR0 0x80
148#define MIR1 0x84
149#define MIR2 0x88
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300150
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300151/*
152 * Note: Other Intel EDAC drivers use AMBPRESENT to identify if the available
153 * memory. From datasheet item 7.3.1 (FB-DIMM technology & organization), it
154 * seems that we cannot use this information directly for the same usage.
155 * Each memory slot may have up to 2 AMB interfaces, one for income and another
156 * for outcome interface to the next slot.
157 * For now, the driver just stores the AMB present registers, but rely only at
158 * the MTR info to detect memory.
159 * Datasheet is also not clear about how to map each AMBPRESENT registers to
160 * one of the 4 available channels.
161 */
162#define AMBPRESENT_0 0x64
163#define AMBPRESENT_1 0x66
164
Jesper Juhl42b16b32011-01-17 00:09:38 +0100165static const u16 mtr_regs[MAX_SLOTS] = {
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300166 0x80, 0x84, 0x88, 0x8c,
167 0x82, 0x86, 0x8a, 0x8e
168};
169
Mauro Carvalho Chehabb4552ac2010-08-27 16:43:01 -0300170/*
171 * Defines to extract the vaious fields from the
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300172 * MTRx - Memory Technology Registers
173 */
174#define MTR_DIMMS_PRESENT(mtr) ((mtr) & (1 << 8))
175#define MTR_DIMMS_ETHROTTLE(mtr) ((mtr) & (1 << 7))
176#define MTR_DRAM_WIDTH(mtr) (((mtr) & (1 << 6)) ? 8 : 4)
177#define MTR_DRAM_BANKS(mtr) (((mtr) & (1 << 5)) ? 8 : 4)
178#define MTR_DIMM_RANKS(mtr) (((mtr) & (1 << 4)) ? 1 : 0)
179#define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3)
180#define MTR_DRAM_BANKS_ADDR_BITS 2
181#define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13)
182#define MTR_DIMM_COLS(mtr) ((mtr) & 0x3)
183#define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10)
184
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300185#ifdef CONFIG_EDAC_DEBUG
186/* MTR NUMROW */
187static const char *numrow_toString[] = {
188 "8,192 - 13 rows",
189 "16,384 - 14 rows",
190 "32,768 - 15 rows",
191 "65,536 - 16 rows"
192};
193
194/* MTR NUMCOL */
195static const char *numcol_toString[] = {
196 "1,024 - 10 columns",
197 "2,048 - 11 columns",
198 "4,096 - 12 columns",
199 "reserved"
200};
201#endif
202
Mauro Carvalho Chehabc3af2ea2010-08-26 19:54:51 -0300203/************************************************
204 * i7300 Register definitions for error detection
205 ************************************************/
Mauro Carvalho Chehab57021912010-08-27 10:22:36 -0300206
207/*
208 * Device 16.1: FBD Error Registers
209 */
210#define FERR_FAT_FBD 0x98
211static const char *ferr_fat_fbd_name[] = {
212 [22] = "Non-Redundant Fast Reset Timeout",
213 [2] = ">Tmid Thermal event with intelligent throttling disabled",
214 [1] = "Memory or FBD configuration CRC read error",
215 [0] = "Memory Write error on non-redundant retry or "
216 "FBD configuration Write error on retry",
217};
218#define GET_FBD_FAT_IDX(fbderr) (fbderr & (3 << 28))
219#define FERR_FAT_FBD_ERR_MASK ((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3))
220
221#define FERR_NF_FBD 0xa0
222static const char *ferr_nf_fbd_name[] = {
223 [24] = "DIMM-Spare Copy Completed",
224 [23] = "DIMM-Spare Copy Initiated",
225 [22] = "Redundant Fast Reset Timeout",
226 [21] = "Memory Write error on redundant retry",
227 [18] = "SPD protocol Error",
228 [17] = "FBD Northbound parity error on FBD Sync Status",
229 [16] = "Correctable Patrol Data ECC",
230 [15] = "Correctable Resilver- or Spare-Copy Data ECC",
231 [14] = "Correctable Mirrored Demand Data ECC",
232 [13] = "Correctable Non-Mirrored Demand Data ECC",
233 [11] = "Memory or FBD configuration CRC read error",
234 [10] = "FBD Configuration Write error on first attempt",
235 [9] = "Memory Write error on first attempt",
236 [8] = "Non-Aliased Uncorrectable Patrol Data ECC",
237 [7] = "Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC",
238 [6] = "Non-Aliased Uncorrectable Mirrored Demand Data ECC",
239 [5] = "Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC",
240 [4] = "Aliased Uncorrectable Patrol Data ECC",
241 [3] = "Aliased Uncorrectable Resilver- or Spare-Copy Data ECC",
242 [2] = "Aliased Uncorrectable Mirrored Demand Data ECC",
243 [1] = "Aliased Uncorrectable Non-Mirrored Demand Data ECC",
244 [0] = "Uncorrectable Data ECC on Replay",
245};
246#define GET_FBD_NF_IDX(fbderr) (fbderr & (3 << 28))
247#define FERR_NF_FBD_ERR_MASK ((1 << 24) | (1 << 23) | (1 << 22) | (1 << 21) |\
248 (1 << 18) | (1 << 17) | (1 << 16) | (1 << 15) |\
249 (1 << 14) | (1 << 13) | (1 << 11) | (1 << 10) |\
250 (1 << 9) | (1 << 8) | (1 << 7) | (1 << 6) |\
251 (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2) |\
252 (1 << 1) | (1 << 0))
253
254#define EMASK_FBD 0xa8
255#define EMASK_FBD_ERR_MASK ((1 << 27) | (1 << 26) | (1 << 25) | (1 << 24) |\
256 (1 << 22) | (1 << 21) | (1 << 20) | (1 << 19) |\
257 (1 << 18) | (1 << 17) | (1 << 16) | (1 << 14) |\
258 (1 << 13) | (1 << 12) | (1 << 11) | (1 << 10) |\
259 (1 << 9) | (1 << 8) | (1 << 7) | (1 << 6) |\
260 (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2) |\
261 (1 << 1) | (1 << 0))
262
Mauro Carvalho Chehabc3af2ea2010-08-26 19:54:51 -0300263/*
264 * Device 16.2: Global Error Registers
265 */
266
Mauro Carvalho Chehab5de6e072010-08-27 00:16:12 -0300267#define FERR_GLOBAL_HI 0x48
268static const char *ferr_global_hi_name[] = {
269 [3] = "FSB 3 Fatal Error",
270 [2] = "FSB 2 Fatal Error",
271 [1] = "FSB 1 Fatal Error",
272 [0] = "FSB 0 Fatal Error",
273};
274#define ferr_global_hi_is_fatal(errno) 1
275
Mauro Carvalho Chehabc3af2ea2010-08-26 19:54:51 -0300276#define FERR_GLOBAL_LO 0x40
Mauro Carvalho Chehab5de6e072010-08-27 00:16:12 -0300277static const char *ferr_global_lo_name[] = {
Mauro Carvalho Chehabc3af2ea2010-08-26 19:54:51 -0300278 [31] = "Internal MCH Fatal Error",
279 [30] = "Intel QuickData Technology Device Fatal Error",
280 [29] = "FSB1 Fatal Error",
281 [28] = "FSB0 Fatal Error",
282 [27] = "FBD Channel 3 Fatal Error",
283 [26] = "FBD Channel 2 Fatal Error",
284 [25] = "FBD Channel 1 Fatal Error",
285 [24] = "FBD Channel 0 Fatal Error",
286 [23] = "PCI Express Device 7Fatal Error",
287 [22] = "PCI Express Device 6 Fatal Error",
288 [21] = "PCI Express Device 5 Fatal Error",
289 [20] = "PCI Express Device 4 Fatal Error",
290 [19] = "PCI Express Device 3 Fatal Error",
291 [18] = "PCI Express Device 2 Fatal Error",
292 [17] = "PCI Express Device 1 Fatal Error",
293 [16] = "ESI Fatal Error",
294 [15] = "Internal MCH Non-Fatal Error",
295 [14] = "Intel QuickData Technology Device Non Fatal Error",
296 [13] = "FSB1 Non-Fatal Error",
297 [12] = "FSB 0 Non-Fatal Error",
298 [11] = "FBD Channel 3 Non-Fatal Error",
299 [10] = "FBD Channel 2 Non-Fatal Error",
300 [9] = "FBD Channel 1 Non-Fatal Error",
301 [8] = "FBD Channel 0 Non-Fatal Error",
302 [7] = "PCI Express Device 7 Non-Fatal Error",
303 [6] = "PCI Express Device 6 Non-Fatal Error",
304 [5] = "PCI Express Device 5 Non-Fatal Error",
305 [4] = "PCI Express Device 4 Non-Fatal Error",
306 [3] = "PCI Express Device 3 Non-Fatal Error",
307 [2] = "PCI Express Device 2 Non-Fatal Error",
308 [1] = "PCI Express Device 1 Non-Fatal Error",
309 [0] = "ESI Non-Fatal Error",
310};
Mauro Carvalho Chehab5de6e072010-08-27 00:16:12 -0300311#define ferr_global_lo_is_fatal(errno) ((errno < 16) ? 0 : 1)
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300312
Mauro Carvalho Chehab8199d8c2010-08-27 11:51:48 -0300313#define NRECMEMA 0xbe
314 #define NRECMEMA_BANK(v) (((v) >> 12) & 7)
315 #define NRECMEMA_RANK(v) (((v) >> 8) & 15)
316
317#define NRECMEMB 0xc0
318 #define NRECMEMB_IS_WR(v) ((v) & (1 << 31))
319 #define NRECMEMB_CAS(v) (((v) >> 16) & 0x1fff)
320 #define NRECMEMB_RAS(v) ((v) & 0xffff)
321
Mauro Carvalho Chehab32f94722010-08-27 12:13:05 -0300322#define REDMEMA 0xdc
323
Mauro Carvalho Chehab37b69cf2010-08-27 15:44:43 -0300324#define REDMEMB 0x7c
325 #define IS_SECOND_CH(v) ((v) * (1 << 17))
326
Mauro Carvalho Chehab32f94722010-08-27 12:13:05 -0300327#define RECMEMA 0xe0
328 #define RECMEMA_BANK(v) (((v) >> 12) & 7)
329 #define RECMEMA_RANK(v) (((v) >> 8) & 15)
330
331#define RECMEMB 0xe4
332 #define RECMEMB_IS_WR(v) ((v) & (1 << 31))
333 #define RECMEMB_CAS(v) (((v) >> 16) & 0x1fff)
334 #define RECMEMB_RAS(v) ((v) & 0xffff)
335
Mauro Carvalho Chehab5de6e072010-08-27 00:16:12 -0300336/********************************************
337 * i7300 Functions related to error detection
338 ********************************************/
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300339
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300340/**
341 * get_err_from_table() - Gets the error message from a table
342 * @table: table name (array of char *)
343 * @size: number of elements at the table
344 * @pos: position of the element to be returned
345 *
346 * This is a small routine that gets the pos-th element of a table. If the
347 * element doesn't exist (or it is empty), it returns "reserved".
348 * Instead of calling it directly, the better is to call via the macro
349 * GET_ERR_FROM_TABLE(), that automatically checks the table size via
350 * ARRAY_SIZE() macro
351 */
352static const char *get_err_from_table(const char *table[], int size, int pos)
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300353{
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300354 if (unlikely(pos >= size))
355 return "Reserved";
356
357 if (unlikely(!table[pos]))
Mauro Carvalho Chehab5de6e072010-08-27 00:16:12 -0300358 return "Reserved";
359
360 return table[pos];
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300361}
Mauro Carvalho Chehab5de6e072010-08-27 00:16:12 -0300362
363#define GET_ERR_FROM_TABLE(table, pos) \
364 get_err_from_table(table, ARRAY_SIZE(table), pos)
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300365
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300366/**
367 * i7300_process_error_global() - Retrieve the hardware error information from
368 * the hardware global error registers and
369 * sends it to dmesg
370 * @mci: struct mem_ctl_info pointer
Mauro Carvalho Chehab5de6e072010-08-27 00:16:12 -0300371 */
Mauro Carvalho Chehabf4277422010-08-27 10:33:25 -0300372static void i7300_process_error_global(struct mem_ctl_info *mci)
Mauro Carvalho Chehab5de6e072010-08-27 00:16:12 -0300373{
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300374 struct i7300_pvt *pvt;
Mauro Carvalho Chehab5f032112011-06-13 14:09:11 -0300375 u32 errnum, error_reg;
Mauro Carvalho Chehab5de6e072010-08-27 00:16:12 -0300376 unsigned long errors;
377 const char *specific;
378 bool is_fatal;
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300379
380 pvt = mci->pvt_info;
381
382 /* read in the 1st FATAL error register */
Mauro Carvalho Chehab5de6e072010-08-27 00:16:12 -0300383 pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
Mauro Carvalho Chehab5f032112011-06-13 14:09:11 -0300384 FERR_GLOBAL_HI, &error_reg);
385 if (unlikely(error_reg)) {
386 errors = error_reg;
Mauro Carvalho Chehab5de6e072010-08-27 00:16:12 -0300387 errnum = find_first_bit(&errors,
388 ARRAY_SIZE(ferr_global_hi_name));
389 specific = GET_ERR_FROM_TABLE(ferr_global_hi_name, errnum);
390 is_fatal = ferr_global_hi_is_fatal(errnum);
Mauro Carvalho Chehab86002322010-08-27 00:46:57 -0300391
392 /* Clear the error bit */
393 pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
Mauro Carvalho Chehab5f032112011-06-13 14:09:11 -0300394 FERR_GLOBAL_HI, error_reg);
Mauro Carvalho Chehab86002322010-08-27 00:46:57 -0300395
Mauro Carvalho Chehab5de6e072010-08-27 00:16:12 -0300396 goto error_global;
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300397 }
398
Mauro Carvalho Chehab5de6e072010-08-27 00:16:12 -0300399 pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
Mauro Carvalho Chehab5f032112011-06-13 14:09:11 -0300400 FERR_GLOBAL_LO, &error_reg);
401 if (unlikely(error_reg)) {
402 errors = error_reg;
Mauro Carvalho Chehab5de6e072010-08-27 00:16:12 -0300403 errnum = find_first_bit(&errors,
404 ARRAY_SIZE(ferr_global_lo_name));
405 specific = GET_ERR_FROM_TABLE(ferr_global_lo_name, errnum);
406 is_fatal = ferr_global_lo_is_fatal(errnum);
Mauro Carvalho Chehab86002322010-08-27 00:46:57 -0300407
408 /* Clear the error bit */
409 pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
Mauro Carvalho Chehab5f032112011-06-13 14:09:11 -0300410 FERR_GLOBAL_LO, error_reg);
Mauro Carvalho Chehab86002322010-08-27 00:46:57 -0300411
Mauro Carvalho Chehab5de6e072010-08-27 00:16:12 -0300412 goto error_global;
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300413 }
Mauro Carvalho Chehab5de6e072010-08-27 00:16:12 -0300414 return;
415
416error_global:
417 i7300_mc_printk(mci, KERN_EMERG, "%s misc error: %s\n",
418 is_fatal ? "Fatal" : "NOT fatal", specific);
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300419}
420
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300421/**
422 * i7300_process_fbd_error() - Retrieve the hardware error information from
423 * the FBD error registers and sends it via
424 * EDAC error API calls
425 * @mci: struct mem_ctl_info pointer
Mauro Carvalho Chehab57021912010-08-27 10:22:36 -0300426 */
Mauro Carvalho Chehabf4277422010-08-27 10:33:25 -0300427static void i7300_process_fbd_error(struct mem_ctl_info *mci)
Mauro Carvalho Chehab57021912010-08-27 10:22:36 -0300428{
429 struct i7300_pvt *pvt;
Mauro Carvalho Chehab5f032112011-06-13 14:09:11 -0300430 u32 errnum, value, error_reg;
Mauro Carvalho Chehab8199d8c2010-08-27 11:51:48 -0300431 u16 val16;
Mauro Carvalho Chehab37b69cf2010-08-27 15:44:43 -0300432 unsigned branch, channel, bank, rank, cas, ras;
Mauro Carvalho Chehab32f94722010-08-27 12:13:05 -0300433 u32 syndrome;
434
Mauro Carvalho Chehab57021912010-08-27 10:22:36 -0300435 unsigned long errors;
436 const char *specific;
Mauro Carvalho Chehab32f94722010-08-27 12:13:05 -0300437 bool is_wr;
Mauro Carvalho Chehab57021912010-08-27 10:22:36 -0300438
439 pvt = mci->pvt_info;
440
441 /* read in the 1st FATAL error register */
442 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
Mauro Carvalho Chehab5f032112011-06-13 14:09:11 -0300443 FERR_FAT_FBD, &error_reg);
444 if (unlikely(error_reg & FERR_FAT_FBD_ERR_MASK)) {
445 errors = error_reg & FERR_FAT_FBD_ERR_MASK ;
Mauro Carvalho Chehab57021912010-08-27 10:22:36 -0300446 errnum = find_first_bit(&errors,
447 ARRAY_SIZE(ferr_fat_fbd_name));
448 specific = GET_ERR_FROM_TABLE(ferr_fat_fbd_name, errnum);
Mauro Carvalho Chehab5f032112011-06-13 14:09:11 -0300449 branch = (GET_FBD_FAT_IDX(error_reg) == 2) ? 1 : 0;
Mauro Carvalho Chehab57021912010-08-27 10:22:36 -0300450
Mauro Carvalho Chehab8199d8c2010-08-27 11:51:48 -0300451 pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map,
452 NRECMEMA, &val16);
453 bank = NRECMEMA_BANK(val16);
454 rank = NRECMEMA_RANK(val16);
Mauro Carvalho Chehab57021912010-08-27 10:22:36 -0300455
Mauro Carvalho Chehab8199d8c2010-08-27 11:51:48 -0300456 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
457 NRECMEMB, &value);
Mauro Carvalho Chehab8199d8c2010-08-27 11:51:48 -0300458 is_wr = NRECMEMB_IS_WR(value);
459 cas = NRECMEMB_CAS(value);
460 ras = NRECMEMB_RAS(value);
461
Mauro Carvalho Chehab5f032112011-06-13 14:09:11 -0300462 /* Clean the error register */
463 pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
464 FERR_FAT_FBD, error_reg);
465
Mauro Carvalho Chehab8199d8c2010-08-27 11:51:48 -0300466 snprintf(pvt->tmp_prt_buffer, PAGE_SIZE,
467 "FATAL (Branch=%d DRAM-Bank=%d %s "
468 "RAS=%d CAS=%d Err=0x%lx (%s))",
Mauro Carvalho Chehab32f94722010-08-27 12:13:05 -0300469 branch, bank,
Mauro Carvalho Chehab8199d8c2010-08-27 11:51:48 -0300470 is_wr ? "RDWR" : "RD",
471 ras, cas,
472 errors, specific);
473
474 /* Call the helper to output message */
475 edac_mc_handle_fbd_ue(mci, rank, branch << 1,
476 (branch << 1) + 1,
477 pvt->tmp_prt_buffer);
Mauro Carvalho Chehab57021912010-08-27 10:22:36 -0300478 }
479
480 /* read in the 1st NON-FATAL error register */
481 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
Mauro Carvalho Chehab5f032112011-06-13 14:09:11 -0300482 FERR_NF_FBD, &error_reg);
483 if (unlikely(error_reg & FERR_NF_FBD_ERR_MASK)) {
484 errors = error_reg & FERR_NF_FBD_ERR_MASK;
Mauro Carvalho Chehab57021912010-08-27 10:22:36 -0300485 errnum = find_first_bit(&errors,
486 ARRAY_SIZE(ferr_nf_fbd_name));
487 specific = GET_ERR_FROM_TABLE(ferr_nf_fbd_name, errnum);
Mauro Carvalho Chehab5f032112011-06-13 14:09:11 -0300488 branch = (GET_FBD_FAT_IDX(error_reg) == 2) ? 1 : 0;
Mauro Carvalho Chehab57021912010-08-27 10:22:36 -0300489
Mauro Carvalho Chehab32f94722010-08-27 12:13:05 -0300490 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
491 REDMEMA, &syndrome);
492
Mauro Carvalho Chehab32f94722010-08-27 12:13:05 -0300493 pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map,
494 RECMEMA, &val16);
495 bank = RECMEMA_BANK(val16);
496 rank = RECMEMA_RANK(val16);
497
498 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
499 RECMEMB, &value);
Mauro Carvalho Chehab32f94722010-08-27 12:13:05 -0300500 is_wr = RECMEMB_IS_WR(value);
501 cas = RECMEMB_CAS(value);
502 ras = RECMEMB_RAS(value);
503
Mauro Carvalho Chehab37b69cf2010-08-27 15:44:43 -0300504 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
505 REDMEMB, &value);
Mauro Carvalho Chehab37b69cf2010-08-27 15:44:43 -0300506 channel = (branch << 1);
507 if (IS_SECOND_CH(value))
508 channel++;
509
Mauro Carvalho Chehab5f032112011-06-13 14:09:11 -0300510 /* Clear the error bit */
511 pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
512 FERR_NF_FBD, error_reg);
513
Mauro Carvalho Chehab32f94722010-08-27 12:13:05 -0300514 /* Form out message */
515 snprintf(pvt->tmp_prt_buffer, PAGE_SIZE,
Mauro Carvalho Chehab37b69cf2010-08-27 15:44:43 -0300516 "Corrected error (Branch=%d, Channel %d), "
Mauro Carvalho Chehab32f94722010-08-27 12:13:05 -0300517 " DRAM-Bank=%d %s "
518 "RAS=%d CAS=%d, CE Err=0x%lx, Syndrome=0x%08x(%s))",
Mauro Carvalho Chehab37b69cf2010-08-27 15:44:43 -0300519 branch, channel,
Mauro Carvalho Chehab32f94722010-08-27 12:13:05 -0300520 bank,
521 is_wr ? "RDWR" : "RD",
522 ras, cas,
523 errors, syndrome, specific);
524
525 /*
526 * Call the helper to output message
527 * NOTE: Errors are reported per-branch, and not per-channel
528 * Currently, we don't know how to identify the right
529 * channel.
530 */
Mauro Carvalho Chehab37b69cf2010-08-27 15:44:43 -0300531 edac_mc_handle_fbd_ce(mci, rank, channel,
Mauro Carvalho Chehab32f94722010-08-27 12:13:05 -0300532 pvt->tmp_prt_buffer);
Mauro Carvalho Chehab57021912010-08-27 10:22:36 -0300533 }
534 return;
Mauro Carvalho Chehab57021912010-08-27 10:22:36 -0300535}
536
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300537/**
538 * i7300_check_error() - Calls the error checking subroutines
539 * @mci: struct mem_ctl_info pointer
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300540 */
Mauro Carvalho Chehabf4277422010-08-27 10:33:25 -0300541static void i7300_check_error(struct mem_ctl_info *mci)
Mauro Carvalho Chehab5de6e072010-08-27 00:16:12 -0300542{
Mauro Carvalho Chehabf4277422010-08-27 10:33:25 -0300543 i7300_process_error_global(mci);
544 i7300_process_fbd_error(mci);
Mauro Carvalho Chehab5de6e072010-08-27 00:16:12 -0300545};
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300546
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300547/**
548 * i7300_clear_error() - Clears the error registers
549 * @mci: struct mem_ctl_info pointer
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300550 */
551static void i7300_clear_error(struct mem_ctl_info *mci)
552{
Mauro Carvalho Chehabe4327602010-08-27 10:30:18 -0300553 struct i7300_pvt *pvt = mci->pvt_info;
554 u32 value;
555 /*
556 * All error values are RWC - we need to read and write 1 to the
557 * bit that we want to cleanup
558 */
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300559
Mauro Carvalho Chehabe4327602010-08-27 10:30:18 -0300560 /* Clear global error registers */
561 pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
562 FERR_GLOBAL_HI, &value);
563 pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
564 FERR_GLOBAL_HI, value);
565
566 pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
567 FERR_GLOBAL_LO, &value);
568 pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
569 FERR_GLOBAL_LO, value);
570
571 /* Clear FBD error registers */
572 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
573 FERR_FAT_FBD, &value);
574 pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
575 FERR_FAT_FBD, value);
576
577 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
578 FERR_NF_FBD, &value);
579 pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
580 FERR_NF_FBD, value);
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300581}
582
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300583/**
584 * i7300_enable_error_reporting() - Enable the memory reporting logic at the
585 * hardware
586 * @mci: struct mem_ctl_info pointer
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300587 */
588static void i7300_enable_error_reporting(struct mem_ctl_info *mci)
589{
Mauro Carvalho Chehab57021912010-08-27 10:22:36 -0300590 struct i7300_pvt *pvt = mci->pvt_info;
591 u32 fbd_error_mask;
592
593 /* Read the FBD Error Mask Register */
594 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
595 EMASK_FBD, &fbd_error_mask);
596
597 /* Enable with a '0' */
598 fbd_error_mask &= ~(EMASK_FBD_ERR_MASK);
599
600 pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
601 EMASK_FBD, fbd_error_mask);
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300602}
Mauro Carvalho Chehab5de6e072010-08-27 00:16:12 -0300603
604/************************************************
605 * i7300 Functions related to memory enumberation
606 ************************************************/
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300607
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300608/**
609 * decode_mtr() - Decodes the MTR descriptor, filling the edac structs
610 * @pvt: pointer to the private data struct used by i7300 driver
611 * @slot: DIMM slot (0 to 7)
612 * @ch: Channel number within the branch (0 or 1)
613 * @branch: Branch number (0 or 1)
614 * @dinfo: Pointer to DIMM info where dimm size is stored
615 * @p_csrow: Pointer to the struct csrow_info that corresponds to that element
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300616 */
617static int decode_mtr(struct i7300_pvt *pvt,
618 int slot, int ch, int branch,
619 struct i7300_dimm_info *dinfo,
Mauro Carvalho Chehab1aa4a7b2010-09-24 11:29:02 -0300620 struct csrow_info *p_csrow,
Mauro Carvalho Chehabe6649cc2010-09-24 11:53:52 -0300621 u32 *nr_pages)
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300622{
623 int mtr, ans, addrBits, channel;
624
625 channel = to_channel(ch, branch);
626
627 mtr = pvt->mtr[slot][branch];
628 ans = MTR_DIMMS_PRESENT(mtr) ? 1 : 0;
629
630 debugf2("\tMTR%d CH%d: DIMMs are %s (mtr)\n",
631 slot, channel,
632 ans ? "Present" : "NOT Present");
633
634 /* Determine if there is a DIMM present in this DIMM slot */
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300635 if (!ans)
636 return 0;
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300637
638 /* Start with the number of bits for a Bank
639 * on the DRAM */
640 addrBits = MTR_DRAM_BANKS_ADDR_BITS;
641 /* Add thenumber of ROW bits */
642 addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr);
643 /* add the number of COLUMN bits */
644 addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr);
645 /* add the number of RANK bits */
646 addrBits += MTR_DIMM_RANKS(mtr);
647
648 addrBits += 6; /* add 64 bits per DIMM */
649 addrBits -= 20; /* divide by 2^^20 */
650 addrBits -= 3; /* 8 bits per bytes */
651
652 dinfo->megabytes = 1 << addrBits;
Mauro Carvalho Chehabe6649cc2010-09-24 11:53:52 -0300653 *nr_pages = dinfo->megabytes << 8;
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300654
655 debugf2("\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr));
656
657 debugf2("\t\tELECTRICAL THROTTLING is %s\n",
658 MTR_DIMMS_ETHROTTLE(mtr) ? "enabled" : "disabled");
659
660 debugf2("\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr));
661 debugf2("\t\tNUMRANK: %s\n", MTR_DIMM_RANKS(mtr) ? "double" : "single");
662 debugf2("\t\tNUMROW: %s\n", numrow_toString[MTR_DIMM_ROWS(mtr)]);
663 debugf2("\t\tNUMCOL: %s\n", numcol_toString[MTR_DIMM_COLS(mtr)]);
664 debugf2("\t\tSIZE: %d MB\n", dinfo->megabytes);
665
666 p_csrow->grain = 8;
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300667 p_csrow->mtype = MEM_FB_DDR2;
Mauro Carvalho Chehab1aa4a7b2010-09-24 11:29:02 -0300668 p_csrow->csrow_idx = slot;
Mauro Carvalho Chehab1aa4a7b2010-09-24 11:29:02 -0300669 p_csrow->page_mask = 0;
Mauro Carvalho Chehab116389e2010-08-26 23:19:54 -0300670
671 /*
Mauro Carvalho Chehab15154c52010-08-27 09:16:06 -0300672 * The type of error detection actually depends of the
Mauro Carvalho Chehab116389e2010-08-26 23:19:54 -0300673 * mode of operation. When it is just one single memory chip, at
Mauro Carvalho Chehab15154c52010-08-27 09:16:06 -0300674 * socket 0, channel 0, it uses 8-byte-over-32-byte SECDED+ code.
675 * In normal or mirrored mode, it uses Lockstep mode,
Mauro Carvalho Chehab116389e2010-08-26 23:19:54 -0300676 * with the possibility of using an extended algorithm for x8 memories
677 * See datasheet Sections 7.3.6 to 7.3.8
678 */
Mauro Carvalho Chehab15154c52010-08-27 09:16:06 -0300679
680 if (IS_SINGLE_MODE(pvt->mc_settings_a)) {
681 p_csrow->edac_mode = EDAC_SECDED;
Mauro Carvalho Chehab3b330f62010-08-27 10:39:35 -0300682 debugf2("\t\tECC code is 8-byte-over-32-byte SECDED+ code\n");
Mauro Carvalho Chehab15154c52010-08-27 09:16:06 -0300683 } else {
Mauro Carvalho Chehab3b330f62010-08-27 10:39:35 -0300684 debugf2("\t\tECC code is on Lockstep mode\n");
Mauro Carvalho Chehab28c2ce72010-08-27 11:20:38 -0300685 if (MTR_DRAM_WIDTH(mtr) == 8)
Mauro Carvalho Chehab15154c52010-08-27 09:16:06 -0300686 p_csrow->edac_mode = EDAC_S8ECD8ED;
687 else
688 p_csrow->edac_mode = EDAC_S4ECD4ED;
689 }
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300690
691 /* ask what device type on this row */
Mauro Carvalho Chehab28c2ce72010-08-27 11:20:38 -0300692 if (MTR_DRAM_WIDTH(mtr) == 8) {
Mauro Carvalho Chehab3b330f62010-08-27 10:39:35 -0300693 debugf2("\t\tScrub algorithm for x8 is on %s mode\n",
Mauro Carvalho Chehabd7de2bd2010-08-27 08:56:48 -0300694 IS_SCRBALGO_ENHANCED(pvt->mc_settings) ?
695 "enhanced" : "normal");
696
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300697 p_csrow->dtype = DEV_X8;
Mauro Carvalho Chehabd7de2bd2010-08-27 08:56:48 -0300698 } else
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300699 p_csrow->dtype = DEV_X4;
700
701 return mtr;
702}
703
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300704/**
705 * print_dimm_size() - Prints dump of the memory organization
706 * @pvt: pointer to the private data struct used by i7300 driver
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300707 *
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300708 * Useful for debug. If debug is disabled, this routine do nothing
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300709 */
710static void print_dimm_size(struct i7300_pvt *pvt)
711{
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300712#ifdef CONFIG_EDAC_DEBUG
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300713 struct i7300_dimm_info *dinfo;
Mauro Carvalho Chehab85580ea2010-08-27 11:36:23 -0300714 char *p;
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300715 int space, n;
716 int channel, slot;
717
718 space = PAGE_SIZE;
Mauro Carvalho Chehab85580ea2010-08-27 11:36:23 -0300719 p = pvt->tmp_prt_buffer;
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300720
721 n = snprintf(p, space, " ");
722 p += n;
723 space -= n;
724 for (channel = 0; channel < MAX_CHANNELS; channel++) {
725 n = snprintf(p, space, "channel %d | ", channel);
726 p += n;
727 space -= n;
728 }
Mauro Carvalho Chehab85580ea2010-08-27 11:36:23 -0300729 debugf2("%s\n", pvt->tmp_prt_buffer);
730 p = pvt->tmp_prt_buffer;
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300731 space = PAGE_SIZE;
732 n = snprintf(p, space, "-------------------------------"
Mauro Carvalho Chehab9c6f6b62010-08-27 17:43:43 -0300733 "------------------------------");
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300734 p += n;
735 space -= n;
Mauro Carvalho Chehab85580ea2010-08-27 11:36:23 -0300736 debugf2("%s\n", pvt->tmp_prt_buffer);
737 p = pvt->tmp_prt_buffer;
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300738 space = PAGE_SIZE;
739
740 for (slot = 0; slot < MAX_SLOTS; slot++) {
741 n = snprintf(p, space, "csrow/SLOT %d ", slot);
742 p += n;
743 space -= n;
744
745 for (channel = 0; channel < MAX_CHANNELS; channel++) {
746 dinfo = &pvt->dimm_info[slot][channel];
747 n = snprintf(p, space, "%4d MB | ", dinfo->megabytes);
748 p += n;
749 space -= n;
750 }
751
Mauro Carvalho Chehab85580ea2010-08-27 11:36:23 -0300752 debugf2("%s\n", pvt->tmp_prt_buffer);
753 p = pvt->tmp_prt_buffer;
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300754 space = PAGE_SIZE;
755 }
756
757 n = snprintf(p, space, "-------------------------------"
Mauro Carvalho Chehab9c6f6b62010-08-27 17:43:43 -0300758 "------------------------------");
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300759 p += n;
760 space -= n;
Mauro Carvalho Chehab85580ea2010-08-27 11:36:23 -0300761 debugf2("%s\n", pvt->tmp_prt_buffer);
762 p = pvt->tmp_prt_buffer;
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300763 space = PAGE_SIZE;
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300764#endif
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300765}
766
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300767/**
768 * i7300_init_csrows() - Initialize the 'csrows' table within
769 * the mci control structure with the
770 * addressing of memory.
771 * @mci: struct mem_ctl_info pointer
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300772 */
773static int i7300_init_csrows(struct mem_ctl_info *mci)
774{
775 struct i7300_pvt *pvt;
776 struct i7300_dimm_info *dinfo;
777 struct csrow_info *p_csrow;
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300778 int rc = -ENODEV;
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300779 int mtr;
780 int ch, branch, slot, channel;
Mauro Carvalho Chehabe6649cc2010-09-24 11:53:52 -0300781 u32 last_page = 0, nr_pages;
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300782
783 pvt = mci->pvt_info;
784
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300785 debugf2("Memory Technology Registers:\n");
786
787 /* Get the AMB present registers for the four channels */
788 for (branch = 0; branch < MAX_BRANCHES; branch++) {
789 /* Read and dump branch 0's MTRs */
790 channel = to_channel(0, branch);
Mauro Carvalho Chehab9c6f6b62010-08-27 17:43:43 -0300791 pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch],
792 AMBPRESENT_0,
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300793 &pvt->ambpresent[channel]);
794 debugf2("\t\tAMB-present CH%d = 0x%x:\n",
795 channel, pvt->ambpresent[channel]);
796
797 channel = to_channel(1, branch);
Mauro Carvalho Chehab9c6f6b62010-08-27 17:43:43 -0300798 pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch],
799 AMBPRESENT_1,
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300800 &pvt->ambpresent[channel]);
801 debugf2("\t\tAMB-present CH%d = 0x%x:\n",
802 channel, pvt->ambpresent[channel]);
803 }
804
805 /* Get the set of MTR[0-7] regs by each branch */
806 for (slot = 0; slot < MAX_SLOTS; slot++) {
807 int where = mtr_regs[slot];
808 for (branch = 0; branch < MAX_BRANCHES; branch++) {
Mauro Carvalho Chehab3e57eef2010-08-26 23:38:11 -0300809 pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch],
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300810 where,
811 &pvt->mtr[slot][branch]);
812 for (ch = 0; ch < MAX_BRANCHES; ch++) {
813 int channel = to_channel(ch, branch);
814
815 dinfo = &pvt->dimm_info[slot][channel];
816 p_csrow = &mci->csrows[slot];
817
818 mtr = decode_mtr(pvt, slot, ch, branch,
Mauro Carvalho Chehabe6649cc2010-09-24 11:53:52 -0300819 dinfo, p_csrow, &nr_pages);
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300820 /* if no DIMMS on this row, continue */
821 if (!MTR_DIMMS_PRESENT(mtr))
822 continue;
823
Mauro Carvalho Chehabe6649cc2010-09-24 11:53:52 -0300824 /* Update per_csrow memory count */
825 p_csrow->nr_pages += nr_pages;
826 p_csrow->first_page = last_page;
827 last_page += nr_pages;
828 p_csrow->last_page = last_page;
829
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300830 rc = 0;
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300831 }
832 }
833 }
834
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300835 return rc;
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300836}
837
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300838/**
839 * decode_mir() - Decodes Memory Interleave Register (MIR) info
840 * @int mir_no: number of the MIR register to decode
841 * @mir: array with the MIR data cached on the driver
842 */
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300843static void decode_mir(int mir_no, u16 mir[MAX_MIR])
844{
845 if (mir[mir_no] & 3)
Mauro Carvalho Chehab9c6f6b62010-08-27 17:43:43 -0300846 debugf2("MIR%d: limit= 0x%x Branch(es) that participate:"
847 " %s %s\n",
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300848 mir_no,
849 (mir[mir_no] >> 4) & 0xfff,
850 (mir[mir_no] & 1) ? "B0" : "",
Mauro Carvalho Chehab9c6f6b62010-08-27 17:43:43 -0300851 (mir[mir_no] & 2) ? "B1" : "");
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300852}
853
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300854/**
855 * i7300_get_mc_regs() - Get the contents of the MC enumeration registers
856 * @mci: struct mem_ctl_info pointer
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300857 *
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300858 * Data read is cached internally for its usage when needed
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300859 */
860static int i7300_get_mc_regs(struct mem_ctl_info *mci)
861{
862 struct i7300_pvt *pvt;
863 u32 actual_tolm;
864 int i, rc;
865
866 pvt = mci->pvt_info;
867
Mauro Carvalho Chehab3e57eef2010-08-26 23:38:11 -0300868 pci_read_config_dword(pvt->pci_dev_16_0_fsb_ctlr, AMBASE,
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300869 (u32 *) &pvt->ambase);
870
871 debugf2("AMBASE= 0x%lx\n", (long unsigned int)pvt->ambase);
872
873 /* Get the Branch Map regs */
Mauro Carvalho Chehab3e57eef2010-08-26 23:38:11 -0300874 pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, TOLM, &pvt->tolm);
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300875 pvt->tolm >>= 12;
876 debugf2("TOLM (number of 256M regions) =%u (0x%x)\n", pvt->tolm,
877 pvt->tolm);
878
879 actual_tolm = (u32) ((1000l * pvt->tolm) >> (30 - 28));
880 debugf2("Actual TOLM byte addr=%u.%03u GB (0x%x)\n",
881 actual_tolm/1000, actual_tolm % 1000, pvt->tolm << 28);
882
Mauro Carvalho Chehabaf3d8832010-08-26 20:58:45 -0300883 /* Get memory controller settings */
Mauro Carvalho Chehab3e57eef2010-08-26 23:38:11 -0300884 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, MC_SETTINGS,
Mauro Carvalho Chehabaf3d8832010-08-26 20:58:45 -0300885 &pvt->mc_settings);
Mauro Carvalho Chehabbb81a212010-08-27 09:04:11 -0300886 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, MC_SETTINGS_A,
887 &pvt->mc_settings_a);
Mauro Carvalho Chehabd7de2bd2010-08-27 08:56:48 -0300888
Mauro Carvalho Chehabbb81a212010-08-27 09:04:11 -0300889 if (IS_SINGLE_MODE(pvt->mc_settings_a))
890 debugf0("Memory controller operating on single mode\n");
891 else
892 debugf0("Memory controller operating on %s mode\n",
Mauro Carvalho Chehabd7de2bd2010-08-27 08:56:48 -0300893 IS_MIRRORED(pvt->mc_settings) ? "mirrored" : "non-mirrored");
Mauro Carvalho Chehabbb81a212010-08-27 09:04:11 -0300894
Mauro Carvalho Chehabaf3d8832010-08-26 20:58:45 -0300895 debugf0("Error detection is %s\n",
Mauro Carvalho Chehabd7de2bd2010-08-27 08:56:48 -0300896 IS_ECC_ENABLED(pvt->mc_settings) ? "enabled" : "disabled");
897 debugf0("Retry is %s\n",
898 IS_RETRY_ENABLED(pvt->mc_settings) ? "enabled" : "disabled");
Mauro Carvalho Chehabaf3d8832010-08-26 20:58:45 -0300899
900 /* Get Memory Interleave Range registers */
Mauro Carvalho Chehab9c6f6b62010-08-27 17:43:43 -0300901 pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR0,
902 &pvt->mir[0]);
903 pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR1,
904 &pvt->mir[1]);
905 pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR2,
906 &pvt->mir[2]);
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300907
908 /* Decode the MIR regs */
909 for (i = 0; i < MAX_MIR; i++)
910 decode_mir(i, pvt->mir);
911
912 rc = i7300_init_csrows(mci);
913 if (rc < 0)
914 return rc;
915
916 /* Go and determine the size of each DIMM and place in an
917 * orderly matrix */
918 print_dimm_size(pvt);
919
920 return 0;
921}
922
Mauro Carvalho Chehab5de6e072010-08-27 00:16:12 -0300923/*************************************************
924 * i7300 Functions related to device probe/release
925 *************************************************/
926
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300927/**
928 * i7300_put_devices() - Release the PCI devices
929 * @mci: struct mem_ctl_info pointer
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300930 */
931static void i7300_put_devices(struct mem_ctl_info *mci)
932{
933 struct i7300_pvt *pvt;
934 int branch;
935
936 pvt = mci->pvt_info;
937
938 /* Decrement usage count for devices */
939 for (branch = 0; branch < MAX_CH_PER_BRANCH; branch++)
Mauro Carvalho Chehab3e57eef2010-08-26 23:38:11 -0300940 pci_dev_put(pvt->pci_dev_2x_0_fbd_branch[branch]);
941 pci_dev_put(pvt->pci_dev_16_2_fsb_err_regs);
942 pci_dev_put(pvt->pci_dev_16_1_fsb_addr_map);
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300943}
944
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300945/**
946 * i7300_get_devices() - Find and perform 'get' operation on the MCH's
947 * device/functions we want to reference for this driver
948 * @mci: struct mem_ctl_info pointer
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300949 *
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300950 * Access and prepare the several devices for usage:
951 * I7300 devices used by this driver:
952 * Device 16, functions 0,1 and 2: PCI_DEVICE_ID_INTEL_I7300_MCH_ERR
953 * Device 21 function 0: PCI_DEVICE_ID_INTEL_I7300_MCH_FB0
954 * Device 22 function 0: PCI_DEVICE_ID_INTEL_I7300_MCH_FB1
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300955 */
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -0300956static int __devinit i7300_get_devices(struct mem_ctl_info *mci)
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300957{
958 struct i7300_pvt *pvt;
959 struct pci_dev *pdev;
960
961 pvt = mci->pvt_info;
962
963 /* Attempt to 'get' the MCH register we want */
964 pdev = NULL;
Mauro Carvalho Chehab9c6f6b62010-08-27 17:43:43 -0300965 while (!pvt->pci_dev_16_1_fsb_addr_map ||
966 !pvt->pci_dev_16_2_fsb_err_regs) {
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300967 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
968 PCI_DEVICE_ID_INTEL_I7300_MCH_ERR, pdev);
969 if (!pdev) {
970 /* End of list, leave */
971 i7300_printk(KERN_ERR,
972 "'system address,Process Bus' "
973 "device not found:"
974 "vendor 0x%x device 0x%x ERR funcs "
975 "(broken BIOS?)\n",
976 PCI_VENDOR_ID_INTEL,
977 PCI_DEVICE_ID_INTEL_I7300_MCH_ERR);
978 goto error;
979 }
980
981 /* Store device 16 funcs 1 and 2 */
982 switch (PCI_FUNC(pdev->devfn)) {
983 case 1:
Mauro Carvalho Chehab3e57eef2010-08-26 23:38:11 -0300984 pvt->pci_dev_16_1_fsb_addr_map = pdev;
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300985 break;
986 case 2:
Mauro Carvalho Chehab3e57eef2010-08-26 23:38:11 -0300987 pvt->pci_dev_16_2_fsb_err_regs = pdev;
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300988 break;
989 }
990 }
991
992 debugf1("System Address, processor bus- PCI Bus ID: %s %x:%x\n",
Mauro Carvalho Chehab3e57eef2010-08-26 23:38:11 -0300993 pci_name(pvt->pci_dev_16_0_fsb_ctlr),
Mauro Carvalho Chehab9c6f6b62010-08-27 17:43:43 -0300994 pvt->pci_dev_16_0_fsb_ctlr->vendor,
995 pvt->pci_dev_16_0_fsb_ctlr->device);
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300996 debugf1("Branchmap, control and errors - PCI Bus ID: %s %x:%x\n",
Mauro Carvalho Chehab3e57eef2010-08-26 23:38:11 -0300997 pci_name(pvt->pci_dev_16_1_fsb_addr_map),
Mauro Carvalho Chehab9c6f6b62010-08-27 17:43:43 -0300998 pvt->pci_dev_16_1_fsb_addr_map->vendor,
999 pvt->pci_dev_16_1_fsb_addr_map->device);
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001000 debugf1("FSB Error Regs - PCI Bus ID: %s %x:%x\n",
Mauro Carvalho Chehab3e57eef2010-08-26 23:38:11 -03001001 pci_name(pvt->pci_dev_16_2_fsb_err_regs),
Mauro Carvalho Chehab9c6f6b62010-08-27 17:43:43 -03001002 pvt->pci_dev_16_2_fsb_err_regs->vendor,
1003 pvt->pci_dev_16_2_fsb_err_regs->device);
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001004
Mauro Carvalho Chehab3e57eef2010-08-26 23:38:11 -03001005 pvt->pci_dev_2x_0_fbd_branch[0] = pci_get_device(PCI_VENDOR_ID_INTEL,
Mauro Carvalho Chehab9c6f6b62010-08-27 17:43:43 -03001006 PCI_DEVICE_ID_INTEL_I7300_MCH_FB0,
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001007 NULL);
Mauro Carvalho Chehab3e57eef2010-08-26 23:38:11 -03001008 if (!pvt->pci_dev_2x_0_fbd_branch[0]) {
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001009 i7300_printk(KERN_ERR,
1010 "MC: 'BRANCH 0' device not found:"
1011 "vendor 0x%x device 0x%x Func 0 (broken BIOS?)\n",
1012 PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_FB0);
1013 goto error;
1014 }
1015
Mauro Carvalho Chehab3e57eef2010-08-26 23:38:11 -03001016 pvt->pci_dev_2x_0_fbd_branch[1] = pci_get_device(PCI_VENDOR_ID_INTEL,
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001017 PCI_DEVICE_ID_INTEL_I7300_MCH_FB1,
1018 NULL);
Mauro Carvalho Chehab3e57eef2010-08-26 23:38:11 -03001019 if (!pvt->pci_dev_2x_0_fbd_branch[1]) {
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001020 i7300_printk(KERN_ERR,
1021 "MC: 'BRANCH 1' device not found:"
1022 "vendor 0x%x device 0x%x Func 0 "
1023 "(broken BIOS?)\n",
1024 PCI_VENDOR_ID_INTEL,
1025 PCI_DEVICE_ID_INTEL_I7300_MCH_FB1);
1026 goto error;
1027 }
1028
1029 return 0;
1030
1031error:
1032 i7300_put_devices(mci);
1033 return -ENODEV;
1034}
1035
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -03001036/**
1037 * i7300_init_one() - Probe for one instance of the device
1038 * @pdev: struct pci_dev pointer
1039 * @id: struct pci_device_id pointer - currently unused
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001040 */
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -03001041static int __devinit i7300_init_one(struct pci_dev *pdev,
1042 const struct pci_device_id *id)
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001043{
1044 struct mem_ctl_info *mci;
1045 struct i7300_pvt *pvt;
1046 int num_channels;
1047 int num_dimms_per_channel;
1048 int num_csrows;
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -03001049 int rc;
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001050
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -03001051 /* wake up device */
1052 rc = pci_enable_device(pdev);
1053 if (rc == -EIO)
1054 return rc;
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001055
1056 debugf0("MC: " __FILE__ ": %s(), pdev bus %u dev=0x%x fn=0x%x\n",
1057 __func__,
1058 pdev->bus->number,
1059 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1060
1061 /* We only are looking for func 0 of the set */
1062 if (PCI_FUNC(pdev->devfn) != 0)
1063 return -ENODEV;
1064
1065 /* As we don't have a motherboard identification routine to determine
1066 * actual number of slots/dimms per channel, we thus utilize the
1067 * resource as specified by the chipset. Thus, we might have
1068 * have more DIMMs per channel than actually on the mobo, but this
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001069 * allows the driver to support up to the chipset max, without
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001070 * some fancy mobo determination.
1071 */
1072 num_dimms_per_channel = MAX_SLOTS;
1073 num_channels = MAX_CHANNELS;
1074 num_csrows = MAX_SLOTS * MAX_CHANNELS;
1075
1076 debugf0("MC: %s(): Number of - Channels= %d DIMMS= %d CSROWS= %d\n",
1077 __func__, num_channels, num_dimms_per_channel, num_csrows);
1078
1079 /* allocate a new MC control structure */
1080 mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels, 0);
1081
1082 if (mci == NULL)
1083 return -ENOMEM;
1084
1085 debugf0("MC: " __FILE__ ": %s(): mci = %p\n", __func__, mci);
1086
1087 mci->dev = &pdev->dev; /* record ptr to the generic device */
1088
1089 pvt = mci->pvt_info;
Mauro Carvalho Chehab3e57eef2010-08-26 23:38:11 -03001090 pvt->pci_dev_16_0_fsb_ctlr = pdev; /* Record this device in our private */
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001091
Mauro Carvalho Chehab85580ea2010-08-27 11:36:23 -03001092 pvt->tmp_prt_buffer = kmalloc(PAGE_SIZE, GFP_KERNEL);
1093 if (!pvt->tmp_prt_buffer) {
1094 edac_mc_free(mci);
1095 return -ENOMEM;
1096 }
1097
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001098 /* 'get' the pci devices we want to reserve for our use */
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -03001099 if (i7300_get_devices(mci))
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001100 goto fail0;
1101
1102 mci->mc_idx = 0;
1103 mci->mtype_cap = MEM_FLAG_FB_DDR2;
1104 mci->edac_ctl_cap = EDAC_FLAG_NONE;
1105 mci->edac_cap = EDAC_FLAG_NONE;
1106 mci->mod_name = "i7300_edac.c";
1107 mci->mod_ver = I7300_REVISION;
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -03001108 mci->ctl_name = i7300_devs[0].ctl_name;
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001109 mci->dev_name = pci_name(pdev);
1110 mci->ctl_page_to_phys = NULL;
1111
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001112 /* Set the function pointer to an actual operation function */
1113 mci->edac_check = i7300_check_error;
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001114
1115 /* initialize the MC control structure 'csrows' table
1116 * with the mapping and control information */
1117 if (i7300_get_mc_regs(mci)) {
1118 debugf0("MC: Setting mci->edac_cap to EDAC_FLAG_NONE\n"
1119 " because i7300_init_csrows() returned nonzero "
1120 "value\n");
1121 mci->edac_cap = EDAC_FLAG_NONE; /* no csrows found */
1122 } else {
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001123 debugf1("MC: Enable error reporting now\n");
1124 i7300_enable_error_reporting(mci);
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001125 }
1126
1127 /* add this new MC control structure to EDAC's list of MCs */
1128 if (edac_mc_add_mc(mci)) {
1129 debugf0("MC: " __FILE__
1130 ": %s(): failed edac_mc_add_mc()\n", __func__);
1131 /* FIXME: perhaps some code should go here that disables error
1132 * reporting if we just enabled it
1133 */
1134 goto fail1;
1135 }
1136
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001137 i7300_clear_error(mci);
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001138
1139 /* allocating generic PCI control info */
1140 i7300_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
1141 if (!i7300_pci) {
1142 printk(KERN_WARNING
1143 "%s(): Unable to create PCI control\n",
1144 __func__);
1145 printk(KERN_WARNING
1146 "%s(): PCI error report via EDAC not setup\n",
1147 __func__);
1148 }
1149
1150 return 0;
1151
1152 /* Error exit unwinding stack */
1153fail1:
1154
1155 i7300_put_devices(mci);
1156
1157fail0:
Mauro Carvalho Chehab85580ea2010-08-27 11:36:23 -03001158 kfree(pvt->tmp_prt_buffer);
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001159 edac_mc_free(mci);
1160 return -ENODEV;
1161}
1162
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -03001163/**
1164 * i7300_remove_one() - Remove the driver
1165 * @pdev: struct pci_dev pointer
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001166 */
1167static void __devexit i7300_remove_one(struct pci_dev *pdev)
1168{
1169 struct mem_ctl_info *mci;
Mauro Carvalho Chehab85580ea2010-08-27 11:36:23 -03001170 char *tmp;
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001171
1172 debugf0(__FILE__ ": %s()\n", __func__);
1173
1174 if (i7300_pci)
1175 edac_pci_release_generic_ctl(i7300_pci);
1176
1177 mci = edac_mc_del_mc(&pdev->dev);
1178 if (!mci)
1179 return;
1180
Mauro Carvalho Chehab85580ea2010-08-27 11:36:23 -03001181 tmp = ((struct i7300_pvt *)mci->pvt_info)->tmp_prt_buffer;
1182
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001183 /* retrieve references to resources, and free those resources */
1184 i7300_put_devices(mci);
1185
Mauro Carvalho Chehab85580ea2010-08-27 11:36:23 -03001186 kfree(tmp);
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001187 edac_mc_free(mci);
1188}
1189
1190/*
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -03001191 * pci_device_id: table for which devices we are looking for
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001192 *
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -03001193 * Has only 8086:360c PCI ID
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001194 */
1195static const struct pci_device_id i7300_pci_tbl[] __devinitdata = {
1196 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_ERR)},
1197 {0,} /* 0 terminated list. */
1198};
1199
1200MODULE_DEVICE_TABLE(pci, i7300_pci_tbl);
1201
1202/*
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -03001203 * i7300_driver: pci_driver structure for this module
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001204 */
1205static struct pci_driver i7300_driver = {
1206 .name = "i7300_edac",
1207 .probe = i7300_init_one,
1208 .remove = __devexit_p(i7300_remove_one),
1209 .id_table = i7300_pci_tbl,
1210};
1211
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -03001212/**
1213 * i7300_init() - Registers the driver
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001214 */
1215static int __init i7300_init(void)
1216{
1217 int pci_rc;
1218
1219 debugf2("MC: " __FILE__ ": %s()\n", __func__);
1220
1221 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
1222 opstate_init();
1223
1224 pci_rc = pci_register_driver(&i7300_driver);
1225
1226 return (pci_rc < 0) ? pci_rc : 0;
1227}
1228
Mauro Carvalho Chehabd091a6e2010-08-27 17:28:50 -03001229/**
1230 * i7300_init() - Unregisters the driver
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -03001231 */
1232static void __exit i7300_exit(void)
1233{
1234 debugf2("MC: " __FILE__ ": %s()\n", __func__);
1235 pci_unregister_driver(&i7300_driver);
1236}
1237
1238module_init(i7300_init);
1239module_exit(i7300_exit);
1240
1241MODULE_LICENSE("GPL");
1242MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
1243MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
1244MODULE_DESCRIPTION("MC Driver for Intel I7300 memory controllers - "
1245 I7300_REVISION);
1246
1247module_param(edac_op_state, int, 0444);
1248MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");