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Will Deacone1d3c0f2014-11-14 17:18:23 +00001/*
2 * CPU-agnostic ARM page table allocator.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 *
16 * Copyright (C) 2014 ARM Limited
17 *
18 * Author: Will Deacon <will.deacon@arm.com>
19 */
20
21#define pr_fmt(fmt) "arm-lpae io-pgtable: " fmt
22
23#include <linux/iommu.h>
24#include <linux/kernel.h>
25#include <linux/sizes.h>
26#include <linux/slab.h>
27#include <linux/types.h>
Lada Trimasova8f6aff92016-01-27 11:10:32 +000028#include <linux/dma-mapping.h>
Will Deacone1d3c0f2014-11-14 17:18:23 +000029
Robin Murphy87a91b12015-07-29 19:46:09 +010030#include <asm/barrier.h>
31
Will Deacone1d3c0f2014-11-14 17:18:23 +000032#include "io-pgtable.h"
33
34#define ARM_LPAE_MAX_ADDR_BITS 48
35#define ARM_LPAE_S2_MAX_CONCAT_PAGES 16
36#define ARM_LPAE_MAX_LEVELS 4
37
38/* Struct accessors */
39#define io_pgtable_to_data(x) \
40 container_of((x), struct arm_lpae_io_pgtable, iop)
41
Will Deacone1d3c0f2014-11-14 17:18:23 +000042#define io_pgtable_ops_to_data(x) \
43 io_pgtable_to_data(io_pgtable_ops_to_pgtable(x))
44
45/*
46 * For consistency with the architecture, we always consider
47 * ARM_LPAE_MAX_LEVELS levels, with the walk starting at level n >=0
48 */
49#define ARM_LPAE_START_LVL(d) (ARM_LPAE_MAX_LEVELS - (d)->levels)
50
51/*
52 * Calculate the right shift amount to get to the portion describing level l
53 * in a virtual address mapped by the pagetable in d.
54 */
55#define ARM_LPAE_LVL_SHIFT(l,d) \
56 ((((d)->levels - ((l) - ARM_LPAE_START_LVL(d) + 1)) \
57 * (d)->bits_per_level) + (d)->pg_shift)
58
Robin Murphy06c610e2015-12-07 18:18:53 +000059#define ARM_LPAE_GRANULE(d) (1UL << (d)->pg_shift)
60
Will Deacon367bd972015-02-16 18:38:20 +000061#define ARM_LPAE_PAGES_PER_PGD(d) \
Robin Murphy06c610e2015-12-07 18:18:53 +000062 DIV_ROUND_UP((d)->pgd_size, ARM_LPAE_GRANULE(d))
Will Deacone1d3c0f2014-11-14 17:18:23 +000063
64/*
65 * Calculate the index at level l used to map virtual address a using the
66 * pagetable in d.
67 */
68#define ARM_LPAE_PGD_IDX(l,d) \
69 ((l) == ARM_LPAE_START_LVL(d) ? ilog2(ARM_LPAE_PAGES_PER_PGD(d)) : 0)
70
71#define ARM_LPAE_LVL_IDX(a,l,d) \
Will Deacon367bd972015-02-16 18:38:20 +000072 (((u64)(a) >> ARM_LPAE_LVL_SHIFT(l,d)) & \
Will Deacone1d3c0f2014-11-14 17:18:23 +000073 ((1 << ((d)->bits_per_level + ARM_LPAE_PGD_IDX(l,d))) - 1))
74
75/* Calculate the block/page mapping size at level l for pagetable in d. */
76#define ARM_LPAE_BLOCK_SIZE(l,d) \
77 (1 << (ilog2(sizeof(arm_lpae_iopte)) + \
78 ((ARM_LPAE_MAX_LEVELS - (l)) * (d)->bits_per_level)))
79
80/* Page table bits */
81#define ARM_LPAE_PTE_TYPE_SHIFT 0
82#define ARM_LPAE_PTE_TYPE_MASK 0x3
83
84#define ARM_LPAE_PTE_TYPE_BLOCK 1
85#define ARM_LPAE_PTE_TYPE_TABLE 3
86#define ARM_LPAE_PTE_TYPE_PAGE 3
87
Laurent Pinchartc896c132014-12-14 23:34:50 +020088#define ARM_LPAE_PTE_NSTABLE (((arm_lpae_iopte)1) << 63)
Will Deacone1d3c0f2014-11-14 17:18:23 +000089#define ARM_LPAE_PTE_XN (((arm_lpae_iopte)3) << 53)
90#define ARM_LPAE_PTE_AF (((arm_lpae_iopte)1) << 10)
91#define ARM_LPAE_PTE_SH_NS (((arm_lpae_iopte)0) << 8)
92#define ARM_LPAE_PTE_SH_OS (((arm_lpae_iopte)2) << 8)
93#define ARM_LPAE_PTE_SH_IS (((arm_lpae_iopte)3) << 8)
Laurent Pinchartc896c132014-12-14 23:34:50 +020094#define ARM_LPAE_PTE_NS (((arm_lpae_iopte)1) << 5)
Will Deacone1d3c0f2014-11-14 17:18:23 +000095#define ARM_LPAE_PTE_VALID (((arm_lpae_iopte)1) << 0)
96
97#define ARM_LPAE_PTE_ATTR_LO_MASK (((arm_lpae_iopte)0x3ff) << 2)
98/* Ignore the contiguous bit for block splitting */
99#define ARM_LPAE_PTE_ATTR_HI_MASK (((arm_lpae_iopte)6) << 52)
100#define ARM_LPAE_PTE_ATTR_MASK (ARM_LPAE_PTE_ATTR_LO_MASK | \
101 ARM_LPAE_PTE_ATTR_HI_MASK)
102
103/* Stage-1 PTE */
104#define ARM_LPAE_PTE_AP_UNPRIV (((arm_lpae_iopte)1) << 6)
105#define ARM_LPAE_PTE_AP_RDONLY (((arm_lpae_iopte)2) << 6)
106#define ARM_LPAE_PTE_ATTRINDX_SHIFT 2
107#define ARM_LPAE_PTE_nG (((arm_lpae_iopte)1) << 11)
108
109/* Stage-2 PTE */
110#define ARM_LPAE_PTE_HAP_FAULT (((arm_lpae_iopte)0) << 6)
111#define ARM_LPAE_PTE_HAP_READ (((arm_lpae_iopte)1) << 6)
112#define ARM_LPAE_PTE_HAP_WRITE (((arm_lpae_iopte)2) << 6)
113#define ARM_LPAE_PTE_MEMATTR_OIWB (((arm_lpae_iopte)0xf) << 2)
114#define ARM_LPAE_PTE_MEMATTR_NC (((arm_lpae_iopte)0x5) << 2)
115#define ARM_LPAE_PTE_MEMATTR_DEV (((arm_lpae_iopte)0x1) << 2)
116
117/* Register bits */
118#define ARM_32_LPAE_TCR_EAE (1 << 31)
119#define ARM_64_LPAE_S2_TCR_RES1 (1 << 31)
120
Will Deacon63979b82015-03-18 10:22:18 +0000121#define ARM_LPAE_TCR_EPD1 (1 << 23)
122
Will Deacone1d3c0f2014-11-14 17:18:23 +0000123#define ARM_LPAE_TCR_TG0_4K (0 << 14)
124#define ARM_LPAE_TCR_TG0_64K (1 << 14)
125#define ARM_LPAE_TCR_TG0_16K (2 << 14)
126
127#define ARM_LPAE_TCR_SH0_SHIFT 12
128#define ARM_LPAE_TCR_SH0_MASK 0x3
129#define ARM_LPAE_TCR_SH_NS 0
130#define ARM_LPAE_TCR_SH_OS 2
131#define ARM_LPAE_TCR_SH_IS 3
132
133#define ARM_LPAE_TCR_ORGN0_SHIFT 10
134#define ARM_LPAE_TCR_IRGN0_SHIFT 8
135#define ARM_LPAE_TCR_RGN_MASK 0x3
136#define ARM_LPAE_TCR_RGN_NC 0
137#define ARM_LPAE_TCR_RGN_WBWA 1
138#define ARM_LPAE_TCR_RGN_WT 2
139#define ARM_LPAE_TCR_RGN_WB 3
140
141#define ARM_LPAE_TCR_SL0_SHIFT 6
142#define ARM_LPAE_TCR_SL0_MASK 0x3
143
144#define ARM_LPAE_TCR_T0SZ_SHIFT 0
145#define ARM_LPAE_TCR_SZ_MASK 0xf
146
147#define ARM_LPAE_TCR_PS_SHIFT 16
148#define ARM_LPAE_TCR_PS_MASK 0x7
149
150#define ARM_LPAE_TCR_IPS_SHIFT 32
151#define ARM_LPAE_TCR_IPS_MASK 0x7
152
153#define ARM_LPAE_TCR_PS_32_BIT 0x0ULL
154#define ARM_LPAE_TCR_PS_36_BIT 0x1ULL
155#define ARM_LPAE_TCR_PS_40_BIT 0x2ULL
156#define ARM_LPAE_TCR_PS_42_BIT 0x3ULL
157#define ARM_LPAE_TCR_PS_44_BIT 0x4ULL
158#define ARM_LPAE_TCR_PS_48_BIT 0x5ULL
159
160#define ARM_LPAE_MAIR_ATTR_SHIFT(n) ((n) << 3)
161#define ARM_LPAE_MAIR_ATTR_MASK 0xff
162#define ARM_LPAE_MAIR_ATTR_DEVICE 0x04
163#define ARM_LPAE_MAIR_ATTR_NC 0x44
164#define ARM_LPAE_MAIR_ATTR_WBRWA 0xff
165#define ARM_LPAE_MAIR_ATTR_IDX_NC 0
166#define ARM_LPAE_MAIR_ATTR_IDX_CACHE 1
167#define ARM_LPAE_MAIR_ATTR_IDX_DEV 2
168
169/* IOPTE accessors */
170#define iopte_deref(pte,d) \
171 (__va((pte) & ((1ULL << ARM_LPAE_MAX_ADDR_BITS) - 1) \
Robin Murphy06c610e2015-12-07 18:18:53 +0000172 & ~(ARM_LPAE_GRANULE(d) - 1ULL)))
Will Deacone1d3c0f2014-11-14 17:18:23 +0000173
174#define iopte_type(pte,l) \
175 (((pte) >> ARM_LPAE_PTE_TYPE_SHIFT) & ARM_LPAE_PTE_TYPE_MASK)
176
177#define iopte_prot(pte) ((pte) & ARM_LPAE_PTE_ATTR_MASK)
178
179#define iopte_leaf(pte,l) \
180 (l == (ARM_LPAE_MAX_LEVELS - 1) ? \
181 (iopte_type(pte,l) == ARM_LPAE_PTE_TYPE_PAGE) : \
182 (iopte_type(pte,l) == ARM_LPAE_PTE_TYPE_BLOCK))
183
184#define iopte_to_pfn(pte,d) \
185 (((pte) & ((1ULL << ARM_LPAE_MAX_ADDR_BITS) - 1)) >> (d)->pg_shift)
186
187#define pfn_to_iopte(pfn,d) \
188 (((pfn) << (d)->pg_shift) & ((1ULL << ARM_LPAE_MAX_ADDR_BITS) - 1))
189
190struct arm_lpae_io_pgtable {
191 struct io_pgtable iop;
192
193 int levels;
194 size_t pgd_size;
195 unsigned long pg_shift;
196 unsigned long bits_per_level;
197
198 void *pgd;
199};
200
201typedef u64 arm_lpae_iopte;
202
Will Deaconfe4b9912014-11-17 23:31:12 +0000203static bool selftest_running = false;
204
Robin Murphyffcb6d12015-09-17 17:42:16 +0100205static dma_addr_t __arm_lpae_dma_addr(void *pages)
Robin Murphyf8d54962015-07-29 19:46:04 +0100206{
Robin Murphyffcb6d12015-09-17 17:42:16 +0100207 return (dma_addr_t)virt_to_phys(pages);
Robin Murphyf8d54962015-07-29 19:46:04 +0100208}
209
210static void *__arm_lpae_alloc_pages(size_t size, gfp_t gfp,
211 struct io_pgtable_cfg *cfg)
212{
213 struct device *dev = cfg->iommu_dev;
214 dma_addr_t dma;
215 void *pages = alloc_pages_exact(size, gfp | __GFP_ZERO);
216
217 if (!pages)
218 return NULL;
219
Robin Murphy87a91b12015-07-29 19:46:09 +0100220 if (!selftest_running) {
Robin Murphyf8d54962015-07-29 19:46:04 +0100221 dma = dma_map_single(dev, pages, size, DMA_TO_DEVICE);
222 if (dma_mapping_error(dev, dma))
223 goto out_free;
224 /*
225 * We depend on the IOMMU being able to work with any physical
Robin Murphyffcb6d12015-09-17 17:42:16 +0100226 * address directly, so if the DMA layer suggests otherwise by
227 * translating or truncating them, that bodes very badly...
Robin Murphyf8d54962015-07-29 19:46:04 +0100228 */
Robin Murphyffcb6d12015-09-17 17:42:16 +0100229 if (dma != virt_to_phys(pages))
Robin Murphyf8d54962015-07-29 19:46:04 +0100230 goto out_unmap;
231 }
232
233 return pages;
234
235out_unmap:
236 dev_err(dev, "Cannot accommodate DMA translation for IOMMU page tables\n");
237 dma_unmap_single(dev, dma, size, DMA_TO_DEVICE);
238out_free:
239 free_pages_exact(pages, size);
240 return NULL;
241}
242
243static void __arm_lpae_free_pages(void *pages, size_t size,
244 struct io_pgtable_cfg *cfg)
245{
Robin Murphy87a91b12015-07-29 19:46:09 +0100246 if (!selftest_running)
Robin Murphyffcb6d12015-09-17 17:42:16 +0100247 dma_unmap_single(cfg->iommu_dev, __arm_lpae_dma_addr(pages),
Robin Murphyf8d54962015-07-29 19:46:04 +0100248 size, DMA_TO_DEVICE);
249 free_pages_exact(pages, size);
250}
251
252static void __arm_lpae_set_pte(arm_lpae_iopte *ptep, arm_lpae_iopte pte,
Robin Murphy87a91b12015-07-29 19:46:09 +0100253 struct io_pgtable_cfg *cfg)
Robin Murphyf8d54962015-07-29 19:46:04 +0100254{
Robin Murphyf8d54962015-07-29 19:46:04 +0100255 *ptep = pte;
256
Robin Murphy87a91b12015-07-29 19:46:09 +0100257 if (!selftest_running)
Robin Murphyffcb6d12015-09-17 17:42:16 +0100258 dma_sync_single_for_device(cfg->iommu_dev,
259 __arm_lpae_dma_addr(ptep),
Robin Murphyf8d54962015-07-29 19:46:04 +0100260 sizeof(pte), DMA_TO_DEVICE);
Robin Murphyf8d54962015-07-29 19:46:04 +0100261}
262
Will Deaconcf27ec92015-08-11 16:48:32 +0100263static int __arm_lpae_unmap(struct arm_lpae_io_pgtable *data,
264 unsigned long iova, size_t size, int lvl,
265 arm_lpae_iopte *ptep);
266
Will Deacone1d3c0f2014-11-14 17:18:23 +0000267static int arm_lpae_init_pte(struct arm_lpae_io_pgtable *data,
268 unsigned long iova, phys_addr_t paddr,
269 arm_lpae_iopte prot, int lvl,
270 arm_lpae_iopte *ptep)
271{
272 arm_lpae_iopte pte = prot;
Robin Murphyf8d54962015-07-29 19:46:04 +0100273 struct io_pgtable_cfg *cfg = &data->iop.cfg;
Will Deacone1d3c0f2014-11-14 17:18:23 +0000274
Will Deaconfe4b9912014-11-17 23:31:12 +0000275 if (iopte_leaf(*ptep, lvl)) {
Will Deaconcf27ec92015-08-11 16:48:32 +0100276 /* We require an unmap first */
Will Deaconfe4b9912014-11-17 23:31:12 +0000277 WARN_ON(!selftest_running);
Will Deacone1d3c0f2014-11-14 17:18:23 +0000278 return -EEXIST;
Will Deaconcf27ec92015-08-11 16:48:32 +0100279 } else if (iopte_type(*ptep, lvl) == ARM_LPAE_PTE_TYPE_TABLE) {
280 /*
281 * We need to unmap and free the old table before
282 * overwriting it with a block entry.
283 */
284 arm_lpae_iopte *tblp;
285 size_t sz = ARM_LPAE_BLOCK_SIZE(lvl, data);
286
287 tblp = ptep - ARM_LPAE_LVL_IDX(iova, lvl, data);
288 if (WARN_ON(__arm_lpae_unmap(data, iova, sz, lvl, tblp) != sz))
289 return -EINVAL;
Will Deaconfe4b9912014-11-17 23:31:12 +0000290 }
Will Deacone1d3c0f2014-11-14 17:18:23 +0000291
Robin Murphyf8d54962015-07-29 19:46:04 +0100292 if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS)
Laurent Pinchartc896c132014-12-14 23:34:50 +0200293 pte |= ARM_LPAE_PTE_NS;
294
Will Deacone1d3c0f2014-11-14 17:18:23 +0000295 if (lvl == ARM_LPAE_MAX_LEVELS - 1)
296 pte |= ARM_LPAE_PTE_TYPE_PAGE;
297 else
298 pte |= ARM_LPAE_PTE_TYPE_BLOCK;
299
300 pte |= ARM_LPAE_PTE_AF | ARM_LPAE_PTE_SH_IS;
301 pte |= pfn_to_iopte(paddr >> data->pg_shift, data);
302
Robin Murphy87a91b12015-07-29 19:46:09 +0100303 __arm_lpae_set_pte(ptep, pte, cfg);
Will Deacone1d3c0f2014-11-14 17:18:23 +0000304 return 0;
305}
306
307static int __arm_lpae_map(struct arm_lpae_io_pgtable *data, unsigned long iova,
308 phys_addr_t paddr, size_t size, arm_lpae_iopte prot,
309 int lvl, arm_lpae_iopte *ptep)
310{
311 arm_lpae_iopte *cptep, pte;
Will Deacone1d3c0f2014-11-14 17:18:23 +0000312 size_t block_size = ARM_LPAE_BLOCK_SIZE(lvl, data);
Robin Murphyf8d54962015-07-29 19:46:04 +0100313 struct io_pgtable_cfg *cfg = &data->iop.cfg;
Will Deacone1d3c0f2014-11-14 17:18:23 +0000314
315 /* Find our entry at the current level */
316 ptep += ARM_LPAE_LVL_IDX(iova, lvl, data);
317
318 /* If we can install a leaf entry at this level, then do so */
Robin Murphyf8d54962015-07-29 19:46:04 +0100319 if (size == block_size && (size & cfg->pgsize_bitmap))
Will Deacone1d3c0f2014-11-14 17:18:23 +0000320 return arm_lpae_init_pte(data, iova, paddr, prot, lvl, ptep);
321
322 /* We can't allocate tables at the final level */
323 if (WARN_ON(lvl >= ARM_LPAE_MAX_LEVELS - 1))
324 return -EINVAL;
325
326 /* Grab a pointer to the next level */
327 pte = *ptep;
328 if (!pte) {
Robin Murphy06c610e2015-12-07 18:18:53 +0000329 cptep = __arm_lpae_alloc_pages(ARM_LPAE_GRANULE(data),
Robin Murphyf8d54962015-07-29 19:46:04 +0100330 GFP_ATOMIC, cfg);
Will Deacone1d3c0f2014-11-14 17:18:23 +0000331 if (!cptep)
332 return -ENOMEM;
333
Will Deacone1d3c0f2014-11-14 17:18:23 +0000334 pte = __pa(cptep) | ARM_LPAE_PTE_TYPE_TABLE;
Robin Murphyf8d54962015-07-29 19:46:04 +0100335 if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS)
Laurent Pinchartc896c132014-12-14 23:34:50 +0200336 pte |= ARM_LPAE_PTE_NSTABLE;
Robin Murphy87a91b12015-07-29 19:46:09 +0100337 __arm_lpae_set_pte(ptep, pte, cfg);
Will Deacone1d3c0f2014-11-14 17:18:23 +0000338 } else {
339 cptep = iopte_deref(pte, data);
340 }
341
342 /* Rinse, repeat */
343 return __arm_lpae_map(data, iova, paddr, size, prot, lvl + 1, cptep);
344}
345
346static arm_lpae_iopte arm_lpae_prot_to_pte(struct arm_lpae_io_pgtable *data,
347 int prot)
348{
349 arm_lpae_iopte pte;
350
351 if (data->iop.fmt == ARM_64_LPAE_S1 ||
352 data->iop.fmt == ARM_32_LPAE_S1) {
353 pte = ARM_LPAE_PTE_AP_UNPRIV | ARM_LPAE_PTE_nG;
354
355 if (!(prot & IOMMU_WRITE) && (prot & IOMMU_READ))
356 pte |= ARM_LPAE_PTE_AP_RDONLY;
357
Robin Murphyfb948252016-04-05 12:39:31 +0100358 if (prot & IOMMU_MMIO)
359 pte |= (ARM_LPAE_MAIR_ATTR_IDX_DEV
360 << ARM_LPAE_PTE_ATTRINDX_SHIFT);
361 else if (prot & IOMMU_CACHE)
Will Deacone1d3c0f2014-11-14 17:18:23 +0000362 pte |= (ARM_LPAE_MAIR_ATTR_IDX_CACHE
363 << ARM_LPAE_PTE_ATTRINDX_SHIFT);
364 } else {
365 pte = ARM_LPAE_PTE_HAP_FAULT;
366 if (prot & IOMMU_READ)
367 pte |= ARM_LPAE_PTE_HAP_READ;
368 if (prot & IOMMU_WRITE)
369 pte |= ARM_LPAE_PTE_HAP_WRITE;
Robin Murphyfb948252016-04-05 12:39:31 +0100370 if (prot & IOMMU_MMIO)
371 pte |= ARM_LPAE_PTE_MEMATTR_DEV;
372 else if (prot & IOMMU_CACHE)
Will Deacone1d3c0f2014-11-14 17:18:23 +0000373 pte |= ARM_LPAE_PTE_MEMATTR_OIWB;
374 else
375 pte |= ARM_LPAE_PTE_MEMATTR_NC;
376 }
377
378 if (prot & IOMMU_NOEXEC)
379 pte |= ARM_LPAE_PTE_XN;
380
381 return pte;
382}
383
384static int arm_lpae_map(struct io_pgtable_ops *ops, unsigned long iova,
385 phys_addr_t paddr, size_t size, int iommu_prot)
386{
387 struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
388 arm_lpae_iopte *ptep = data->pgd;
Robin Murphy87a91b12015-07-29 19:46:09 +0100389 int ret, lvl = ARM_LPAE_START_LVL(data);
Will Deacone1d3c0f2014-11-14 17:18:23 +0000390 arm_lpae_iopte prot;
391
392 /* If no access, then nothing to do */
393 if (!(iommu_prot & (IOMMU_READ | IOMMU_WRITE)))
394 return 0;
395
396 prot = arm_lpae_prot_to_pte(data, iommu_prot);
Robin Murphy87a91b12015-07-29 19:46:09 +0100397 ret = __arm_lpae_map(data, iova, paddr, size, prot, lvl, ptep);
398 /*
399 * Synchronise all PTE updates for the new mapping before there's
400 * a chance for anything to kick off a table walk for the new iova.
401 */
402 wmb();
403
404 return ret;
Will Deacone1d3c0f2014-11-14 17:18:23 +0000405}
406
407static void __arm_lpae_free_pgtable(struct arm_lpae_io_pgtable *data, int lvl,
408 arm_lpae_iopte *ptep)
409{
410 arm_lpae_iopte *start, *end;
411 unsigned long table_size;
412
Will Deacone1d3c0f2014-11-14 17:18:23 +0000413 if (lvl == ARM_LPAE_START_LVL(data))
414 table_size = data->pgd_size;
415 else
Robin Murphy06c610e2015-12-07 18:18:53 +0000416 table_size = ARM_LPAE_GRANULE(data);
Will Deacone1d3c0f2014-11-14 17:18:23 +0000417
418 start = ptep;
Will Deacon12c2ab02015-12-15 16:08:12 +0000419
420 /* Only leaf entries at the last level */
421 if (lvl == ARM_LPAE_MAX_LEVELS - 1)
422 end = ptep;
423 else
424 end = (void *)ptep + table_size;
Will Deacone1d3c0f2014-11-14 17:18:23 +0000425
426 while (ptep != end) {
427 arm_lpae_iopte pte = *ptep++;
428
429 if (!pte || iopte_leaf(pte, lvl))
430 continue;
431
432 __arm_lpae_free_pgtable(data, lvl + 1, iopte_deref(pte, data));
433 }
434
Robin Murphyf8d54962015-07-29 19:46:04 +0100435 __arm_lpae_free_pages(start, table_size, &data->iop.cfg);
Will Deacone1d3c0f2014-11-14 17:18:23 +0000436}
437
438static void arm_lpae_free_pgtable(struct io_pgtable *iop)
439{
440 struct arm_lpae_io_pgtable *data = io_pgtable_to_data(iop);
441
442 __arm_lpae_free_pgtable(data, ARM_LPAE_START_LVL(data), data->pgd);
443 kfree(data);
444}
445
446static int arm_lpae_split_blk_unmap(struct arm_lpae_io_pgtable *data,
447 unsigned long iova, size_t size,
448 arm_lpae_iopte prot, int lvl,
449 arm_lpae_iopte *ptep, size_t blk_size)
450{
451 unsigned long blk_start, blk_end;
452 phys_addr_t blk_paddr;
453 arm_lpae_iopte table = 0;
Will Deacone1d3c0f2014-11-14 17:18:23 +0000454
455 blk_start = iova & ~(blk_size - 1);
456 blk_end = blk_start + blk_size;
457 blk_paddr = iopte_to_pfn(*ptep, data) << data->pg_shift;
458
459 for (; blk_start < blk_end; blk_start += size, blk_paddr += size) {
460 arm_lpae_iopte *tablep;
461
462 /* Unmap! */
463 if (blk_start == iova)
464 continue;
465
466 /* __arm_lpae_map expects a pointer to the start of the table */
467 tablep = &table - ARM_LPAE_LVL_IDX(blk_start, lvl, data);
468 if (__arm_lpae_map(data, blk_start, blk_paddr, size, prot, lvl,
469 tablep) < 0) {
470 if (table) {
471 /* Free the table we allocated */
472 tablep = iopte_deref(table, data);
473 __arm_lpae_free_pgtable(data, lvl + 1, tablep);
474 }
475 return 0; /* Bytes unmapped */
476 }
477 }
478
Robin Murphy507e4c92016-01-26 17:13:14 +0000479 __arm_lpae_set_pte(ptep, table, &data->iop.cfg);
Will Deacone1d3c0f2014-11-14 17:18:23 +0000480 iova &= ~(blk_size - 1);
Robin Murphy507e4c92016-01-26 17:13:14 +0000481 io_pgtable_tlb_add_flush(&data->iop, iova, blk_size, blk_size, true);
Will Deacone1d3c0f2014-11-14 17:18:23 +0000482 return size;
483}
484
485static int __arm_lpae_unmap(struct arm_lpae_io_pgtable *data,
486 unsigned long iova, size_t size, int lvl,
487 arm_lpae_iopte *ptep)
488{
489 arm_lpae_iopte pte;
Robin Murphy507e4c92016-01-26 17:13:14 +0000490 struct io_pgtable *iop = &data->iop;
Will Deacone1d3c0f2014-11-14 17:18:23 +0000491 size_t blk_size = ARM_LPAE_BLOCK_SIZE(lvl, data);
492
Robin Murphy2eb97c72015-12-04 17:52:58 +0000493 /* Something went horribly wrong and we ran out of page table */
494 if (WARN_ON(lvl == ARM_LPAE_MAX_LEVELS))
495 return 0;
496
Will Deacone1d3c0f2014-11-14 17:18:23 +0000497 ptep += ARM_LPAE_LVL_IDX(iova, lvl, data);
498 pte = *ptep;
Robin Murphy2eb97c72015-12-04 17:52:58 +0000499 if (WARN_ON(!pte))
Will Deacone1d3c0f2014-11-14 17:18:23 +0000500 return 0;
501
502 /* If the size matches this level, we're in the right place */
503 if (size == blk_size) {
Robin Murphy507e4c92016-01-26 17:13:14 +0000504 __arm_lpae_set_pte(ptep, 0, &iop->cfg);
Will Deacone1d3c0f2014-11-14 17:18:23 +0000505
506 if (!iopte_leaf(pte, lvl)) {
507 /* Also flush any partial walks */
Robin Murphy507e4c92016-01-26 17:13:14 +0000508 io_pgtable_tlb_add_flush(iop, iova, size,
509 ARM_LPAE_GRANULE(data), false);
510 io_pgtable_tlb_sync(iop);
Will Deacone1d3c0f2014-11-14 17:18:23 +0000511 ptep = iopte_deref(pte, data);
512 __arm_lpae_free_pgtable(data, lvl + 1, ptep);
513 } else {
Robin Murphy507e4c92016-01-26 17:13:14 +0000514 io_pgtable_tlb_add_flush(iop, iova, size, size, true);
Will Deacone1d3c0f2014-11-14 17:18:23 +0000515 }
516
517 return size;
518 } else if (iopte_leaf(pte, lvl)) {
519 /*
520 * Insert a table at the next level to map the old region,
521 * minus the part we want to unmap
522 */
523 return arm_lpae_split_blk_unmap(data, iova, size,
524 iopte_prot(pte), lvl, ptep,
525 blk_size);
526 }
527
528 /* Keep on walkin' */
529 ptep = iopte_deref(pte, data);
530 return __arm_lpae_unmap(data, iova, size, lvl + 1, ptep);
531}
532
533static int arm_lpae_unmap(struct io_pgtable_ops *ops, unsigned long iova,
534 size_t size)
535{
536 size_t unmapped;
537 struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
Will Deacone1d3c0f2014-11-14 17:18:23 +0000538 arm_lpae_iopte *ptep = data->pgd;
539 int lvl = ARM_LPAE_START_LVL(data);
540
541 unmapped = __arm_lpae_unmap(data, iova, size, lvl, ptep);
542 if (unmapped)
Robin Murphy507e4c92016-01-26 17:13:14 +0000543 io_pgtable_tlb_sync(&data->iop);
Will Deacone1d3c0f2014-11-14 17:18:23 +0000544
545 return unmapped;
546}
547
548static phys_addr_t arm_lpae_iova_to_phys(struct io_pgtable_ops *ops,
549 unsigned long iova)
550{
551 struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
552 arm_lpae_iopte pte, *ptep = data->pgd;
553 int lvl = ARM_LPAE_START_LVL(data);
554
555 do {
556 /* Valid IOPTE pointer? */
557 if (!ptep)
558 return 0;
559
560 /* Grab the IOPTE we're interested in */
561 pte = *(ptep + ARM_LPAE_LVL_IDX(iova, lvl, data));
562
563 /* Valid entry? */
564 if (!pte)
565 return 0;
566
567 /* Leaf entry? */
568 if (iopte_leaf(pte,lvl))
569 goto found_translation;
570
571 /* Take it to the next level */
572 ptep = iopte_deref(pte, data);
573 } while (++lvl < ARM_LPAE_MAX_LEVELS);
574
575 /* Ran out of page tables to walk */
576 return 0;
577
578found_translation:
Robin Murphy06c610e2015-12-07 18:18:53 +0000579 iova &= (ARM_LPAE_GRANULE(data) - 1);
Will Deacone1d3c0f2014-11-14 17:18:23 +0000580 return ((phys_addr_t)iopte_to_pfn(pte,data) << data->pg_shift) | iova;
581}
582
583static void arm_lpae_restrict_pgsizes(struct io_pgtable_cfg *cfg)
584{
585 unsigned long granule;
586
587 /*
588 * We need to restrict the supported page sizes to match the
589 * translation regime for a particular granule. Aim to match
590 * the CPU page size if possible, otherwise prefer smaller sizes.
591 * While we're at it, restrict the block sizes to match the
592 * chosen granule.
593 */
594 if (cfg->pgsize_bitmap & PAGE_SIZE)
595 granule = PAGE_SIZE;
596 else if (cfg->pgsize_bitmap & ~PAGE_MASK)
597 granule = 1UL << __fls(cfg->pgsize_bitmap & ~PAGE_MASK);
598 else if (cfg->pgsize_bitmap & PAGE_MASK)
599 granule = 1UL << __ffs(cfg->pgsize_bitmap & PAGE_MASK);
600 else
601 granule = 0;
602
603 switch (granule) {
604 case SZ_4K:
605 cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G);
606 break;
607 case SZ_16K:
608 cfg->pgsize_bitmap &= (SZ_16K | SZ_32M);
609 break;
610 case SZ_64K:
611 cfg->pgsize_bitmap &= (SZ_64K | SZ_512M);
612 break;
613 default:
614 cfg->pgsize_bitmap = 0;
615 }
616}
617
618static struct arm_lpae_io_pgtable *
619arm_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg)
620{
621 unsigned long va_bits, pgd_bits;
622 struct arm_lpae_io_pgtable *data;
623
624 arm_lpae_restrict_pgsizes(cfg);
625
626 if (!(cfg->pgsize_bitmap & (SZ_4K | SZ_16K | SZ_64K)))
627 return NULL;
628
629 if (cfg->ias > ARM_LPAE_MAX_ADDR_BITS)
630 return NULL;
631
632 if (cfg->oas > ARM_LPAE_MAX_ADDR_BITS)
633 return NULL;
634
Robin Murphyffcb6d12015-09-17 17:42:16 +0100635 if (!selftest_running && cfg->iommu_dev->dma_pfn_offset) {
636 dev_err(cfg->iommu_dev, "Cannot accommodate DMA offset for IOMMU page tables\n");
637 return NULL;
638 }
639
Will Deacone1d3c0f2014-11-14 17:18:23 +0000640 data = kmalloc(sizeof(*data), GFP_KERNEL);
641 if (!data)
642 return NULL;
643
644 data->pg_shift = __ffs(cfg->pgsize_bitmap);
645 data->bits_per_level = data->pg_shift - ilog2(sizeof(arm_lpae_iopte));
646
647 va_bits = cfg->ias - data->pg_shift;
648 data->levels = DIV_ROUND_UP(va_bits, data->bits_per_level);
649
650 /* Calculate the actual size of our pgd (without concatenation) */
651 pgd_bits = va_bits - (data->bits_per_level * (data->levels - 1));
652 data->pgd_size = 1UL << (pgd_bits + ilog2(sizeof(arm_lpae_iopte)));
653
654 data->iop.ops = (struct io_pgtable_ops) {
655 .map = arm_lpae_map,
656 .unmap = arm_lpae_unmap,
657 .iova_to_phys = arm_lpae_iova_to_phys,
658 };
659
660 return data;
661}
662
663static struct io_pgtable *
664arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie)
665{
666 u64 reg;
Robin Murphy3850db42016-02-12 17:09:46 +0000667 struct arm_lpae_io_pgtable *data;
Will Deacone1d3c0f2014-11-14 17:18:23 +0000668
Robin Murphy3850db42016-02-12 17:09:46 +0000669 if (cfg->quirks & ~IO_PGTABLE_QUIRK_ARM_NS)
670 return NULL;
671
672 data = arm_lpae_alloc_pgtable(cfg);
Will Deacone1d3c0f2014-11-14 17:18:23 +0000673 if (!data)
674 return NULL;
675
676 /* TCR */
677 reg = (ARM_LPAE_TCR_SH_IS << ARM_LPAE_TCR_SH0_SHIFT) |
678 (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_IRGN0_SHIFT) |
679 (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_ORGN0_SHIFT);
680
Robin Murphy06c610e2015-12-07 18:18:53 +0000681 switch (ARM_LPAE_GRANULE(data)) {
Will Deacone1d3c0f2014-11-14 17:18:23 +0000682 case SZ_4K:
683 reg |= ARM_LPAE_TCR_TG0_4K;
684 break;
685 case SZ_16K:
686 reg |= ARM_LPAE_TCR_TG0_16K;
687 break;
688 case SZ_64K:
689 reg |= ARM_LPAE_TCR_TG0_64K;
690 break;
691 }
692
693 switch (cfg->oas) {
694 case 32:
695 reg |= (ARM_LPAE_TCR_PS_32_BIT << ARM_LPAE_TCR_IPS_SHIFT);
696 break;
697 case 36:
698 reg |= (ARM_LPAE_TCR_PS_36_BIT << ARM_LPAE_TCR_IPS_SHIFT);
699 break;
700 case 40:
701 reg |= (ARM_LPAE_TCR_PS_40_BIT << ARM_LPAE_TCR_IPS_SHIFT);
702 break;
703 case 42:
704 reg |= (ARM_LPAE_TCR_PS_42_BIT << ARM_LPAE_TCR_IPS_SHIFT);
705 break;
706 case 44:
707 reg |= (ARM_LPAE_TCR_PS_44_BIT << ARM_LPAE_TCR_IPS_SHIFT);
708 break;
709 case 48:
710 reg |= (ARM_LPAE_TCR_PS_48_BIT << ARM_LPAE_TCR_IPS_SHIFT);
711 break;
712 default:
713 goto out_free_data;
714 }
715
716 reg |= (64ULL - cfg->ias) << ARM_LPAE_TCR_T0SZ_SHIFT;
Will Deacon63979b82015-03-18 10:22:18 +0000717
718 /* Disable speculative walks through TTBR1 */
719 reg |= ARM_LPAE_TCR_EPD1;
Will Deacone1d3c0f2014-11-14 17:18:23 +0000720 cfg->arm_lpae_s1_cfg.tcr = reg;
721
722 /* MAIRs */
723 reg = (ARM_LPAE_MAIR_ATTR_NC
724 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_NC)) |
725 (ARM_LPAE_MAIR_ATTR_WBRWA
726 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_CACHE)) |
727 (ARM_LPAE_MAIR_ATTR_DEVICE
728 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_DEV));
729
730 cfg->arm_lpae_s1_cfg.mair[0] = reg;
731 cfg->arm_lpae_s1_cfg.mair[1] = 0;
732
733 /* Looking good; allocate a pgd */
Robin Murphyf8d54962015-07-29 19:46:04 +0100734 data->pgd = __arm_lpae_alloc_pages(data->pgd_size, GFP_KERNEL, cfg);
Will Deacone1d3c0f2014-11-14 17:18:23 +0000735 if (!data->pgd)
736 goto out_free_data;
737
Robin Murphy87a91b12015-07-29 19:46:09 +0100738 /* Ensure the empty pgd is visible before any actual TTBR write */
739 wmb();
Will Deacone1d3c0f2014-11-14 17:18:23 +0000740
741 /* TTBRs */
742 cfg->arm_lpae_s1_cfg.ttbr[0] = virt_to_phys(data->pgd);
743 cfg->arm_lpae_s1_cfg.ttbr[1] = 0;
744 return &data->iop;
745
746out_free_data:
747 kfree(data);
748 return NULL;
749}
750
751static struct io_pgtable *
752arm_64_lpae_alloc_pgtable_s2(struct io_pgtable_cfg *cfg, void *cookie)
753{
754 u64 reg, sl;
Robin Murphy3850db42016-02-12 17:09:46 +0000755 struct arm_lpae_io_pgtable *data;
Will Deacone1d3c0f2014-11-14 17:18:23 +0000756
Robin Murphy3850db42016-02-12 17:09:46 +0000757 /* The NS quirk doesn't apply at stage 2 */
758 if (cfg->quirks)
759 return NULL;
760
761 data = arm_lpae_alloc_pgtable(cfg);
Will Deacone1d3c0f2014-11-14 17:18:23 +0000762 if (!data)
763 return NULL;
764
765 /*
766 * Concatenate PGDs at level 1 if possible in order to reduce
767 * the depth of the stage-2 walk.
768 */
769 if (data->levels == ARM_LPAE_MAX_LEVELS) {
770 unsigned long pgd_pages;
771
772 pgd_pages = data->pgd_size >> ilog2(sizeof(arm_lpae_iopte));
773 if (pgd_pages <= ARM_LPAE_S2_MAX_CONCAT_PAGES) {
774 data->pgd_size = pgd_pages << data->pg_shift;
775 data->levels--;
776 }
777 }
778
779 /* VTCR */
780 reg = ARM_64_LPAE_S2_TCR_RES1 |
781 (ARM_LPAE_TCR_SH_IS << ARM_LPAE_TCR_SH0_SHIFT) |
782 (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_IRGN0_SHIFT) |
783 (ARM_LPAE_TCR_RGN_WBWA << ARM_LPAE_TCR_ORGN0_SHIFT);
784
785 sl = ARM_LPAE_START_LVL(data);
786
Robin Murphy06c610e2015-12-07 18:18:53 +0000787 switch (ARM_LPAE_GRANULE(data)) {
Will Deacone1d3c0f2014-11-14 17:18:23 +0000788 case SZ_4K:
789 reg |= ARM_LPAE_TCR_TG0_4K;
790 sl++; /* SL0 format is different for 4K granule size */
791 break;
792 case SZ_16K:
793 reg |= ARM_LPAE_TCR_TG0_16K;
794 break;
795 case SZ_64K:
796 reg |= ARM_LPAE_TCR_TG0_64K;
797 break;
798 }
799
800 switch (cfg->oas) {
801 case 32:
802 reg |= (ARM_LPAE_TCR_PS_32_BIT << ARM_LPAE_TCR_PS_SHIFT);
803 break;
804 case 36:
805 reg |= (ARM_LPAE_TCR_PS_36_BIT << ARM_LPAE_TCR_PS_SHIFT);
806 break;
807 case 40:
808 reg |= (ARM_LPAE_TCR_PS_40_BIT << ARM_LPAE_TCR_PS_SHIFT);
809 break;
810 case 42:
811 reg |= (ARM_LPAE_TCR_PS_42_BIT << ARM_LPAE_TCR_PS_SHIFT);
812 break;
813 case 44:
814 reg |= (ARM_LPAE_TCR_PS_44_BIT << ARM_LPAE_TCR_PS_SHIFT);
815 break;
816 case 48:
817 reg |= (ARM_LPAE_TCR_PS_48_BIT << ARM_LPAE_TCR_PS_SHIFT);
818 break;
819 default:
820 goto out_free_data;
821 }
822
823 reg |= (64ULL - cfg->ias) << ARM_LPAE_TCR_T0SZ_SHIFT;
824 reg |= (~sl & ARM_LPAE_TCR_SL0_MASK) << ARM_LPAE_TCR_SL0_SHIFT;
825 cfg->arm_lpae_s2_cfg.vtcr = reg;
826
827 /* Allocate pgd pages */
Robin Murphyf8d54962015-07-29 19:46:04 +0100828 data->pgd = __arm_lpae_alloc_pages(data->pgd_size, GFP_KERNEL, cfg);
Will Deacone1d3c0f2014-11-14 17:18:23 +0000829 if (!data->pgd)
830 goto out_free_data;
831
Robin Murphy87a91b12015-07-29 19:46:09 +0100832 /* Ensure the empty pgd is visible before any actual TTBR write */
833 wmb();
Will Deacone1d3c0f2014-11-14 17:18:23 +0000834
835 /* VTTBR */
836 cfg->arm_lpae_s2_cfg.vttbr = virt_to_phys(data->pgd);
837 return &data->iop;
838
839out_free_data:
840 kfree(data);
841 return NULL;
842}
843
844static struct io_pgtable *
845arm_32_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie)
846{
847 struct io_pgtable *iop;
848
849 if (cfg->ias > 32 || cfg->oas > 40)
850 return NULL;
851
852 cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G);
853 iop = arm_64_lpae_alloc_pgtable_s1(cfg, cookie);
854 if (iop) {
855 cfg->arm_lpae_s1_cfg.tcr |= ARM_32_LPAE_TCR_EAE;
856 cfg->arm_lpae_s1_cfg.tcr &= 0xffffffff;
857 }
858
859 return iop;
860}
861
862static struct io_pgtable *
863arm_32_lpae_alloc_pgtable_s2(struct io_pgtable_cfg *cfg, void *cookie)
864{
865 struct io_pgtable *iop;
866
867 if (cfg->ias > 40 || cfg->oas > 40)
868 return NULL;
869
870 cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G);
871 iop = arm_64_lpae_alloc_pgtable_s2(cfg, cookie);
872 if (iop)
873 cfg->arm_lpae_s2_cfg.vtcr &= 0xffffffff;
874
875 return iop;
876}
877
878struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s1_init_fns = {
879 .alloc = arm_64_lpae_alloc_pgtable_s1,
880 .free = arm_lpae_free_pgtable,
881};
882
883struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s2_init_fns = {
884 .alloc = arm_64_lpae_alloc_pgtable_s2,
885 .free = arm_lpae_free_pgtable,
886};
887
888struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s1_init_fns = {
889 .alloc = arm_32_lpae_alloc_pgtable_s1,
890 .free = arm_lpae_free_pgtable,
891};
892
893struct io_pgtable_init_fns io_pgtable_arm_32_lpae_s2_init_fns = {
894 .alloc = arm_32_lpae_alloc_pgtable_s2,
895 .free = arm_lpae_free_pgtable,
896};
Will Deaconfe4b9912014-11-17 23:31:12 +0000897
898#ifdef CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST
899
900static struct io_pgtable_cfg *cfg_cookie;
901
902static void dummy_tlb_flush_all(void *cookie)
903{
904 WARN_ON(cookie != cfg_cookie);
905}
906
Robin Murphy06c610e2015-12-07 18:18:53 +0000907static void dummy_tlb_add_flush(unsigned long iova, size_t size,
908 size_t granule, bool leaf, void *cookie)
Will Deaconfe4b9912014-11-17 23:31:12 +0000909{
910 WARN_ON(cookie != cfg_cookie);
911 WARN_ON(!(size & cfg_cookie->pgsize_bitmap));
912}
913
914static void dummy_tlb_sync(void *cookie)
915{
916 WARN_ON(cookie != cfg_cookie);
917}
918
Will Deaconfe4b9912014-11-17 23:31:12 +0000919static struct iommu_gather_ops dummy_tlb_ops __initdata = {
920 .tlb_flush_all = dummy_tlb_flush_all,
921 .tlb_add_flush = dummy_tlb_add_flush,
922 .tlb_sync = dummy_tlb_sync,
Will Deaconfe4b9912014-11-17 23:31:12 +0000923};
924
925static void __init arm_lpae_dump_ops(struct io_pgtable_ops *ops)
926{
927 struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
928 struct io_pgtable_cfg *cfg = &data->iop.cfg;
929
930 pr_err("cfg: pgsize_bitmap 0x%lx, ias %u-bit\n",
931 cfg->pgsize_bitmap, cfg->ias);
932 pr_err("data: %d levels, 0x%zx pgd_size, %lu pg_shift, %lu bits_per_level, pgd @ %p\n",
933 data->levels, data->pgd_size, data->pg_shift,
934 data->bits_per_level, data->pgd);
935}
936
937#define __FAIL(ops, i) ({ \
938 WARN(1, "selftest: test failed for fmt idx %d\n", (i)); \
939 arm_lpae_dump_ops(ops); \
940 selftest_running = false; \
941 -EFAULT; \
942})
943
944static int __init arm_lpae_run_tests(struct io_pgtable_cfg *cfg)
945{
946 static const enum io_pgtable_fmt fmts[] = {
947 ARM_64_LPAE_S1,
948 ARM_64_LPAE_S2,
949 };
950
951 int i, j;
952 unsigned long iova;
953 size_t size;
954 struct io_pgtable_ops *ops;
955
956 selftest_running = true;
957
958 for (i = 0; i < ARRAY_SIZE(fmts); ++i) {
959 cfg_cookie = cfg;
960 ops = alloc_io_pgtable_ops(fmts[i], cfg, cfg);
961 if (!ops) {
962 pr_err("selftest: failed to allocate io pgtable ops\n");
963 return -ENOMEM;
964 }
965
966 /*
967 * Initial sanity checks.
968 * Empty page tables shouldn't provide any translations.
969 */
970 if (ops->iova_to_phys(ops, 42))
971 return __FAIL(ops, i);
972
973 if (ops->iova_to_phys(ops, SZ_1G + 42))
974 return __FAIL(ops, i);
975
976 if (ops->iova_to_phys(ops, SZ_2G + 42))
977 return __FAIL(ops, i);
978
979 /*
980 * Distinct mappings of different granule sizes.
981 */
982 iova = 0;
983 j = find_first_bit(&cfg->pgsize_bitmap, BITS_PER_LONG);
984 while (j != BITS_PER_LONG) {
985 size = 1UL << j;
986
987 if (ops->map(ops, iova, iova, size, IOMMU_READ |
988 IOMMU_WRITE |
989 IOMMU_NOEXEC |
990 IOMMU_CACHE))
991 return __FAIL(ops, i);
992
993 /* Overlapping mappings */
994 if (!ops->map(ops, iova, iova + size, size,
995 IOMMU_READ | IOMMU_NOEXEC))
996 return __FAIL(ops, i);
997
998 if (ops->iova_to_phys(ops, iova + 42) != (iova + 42))
999 return __FAIL(ops, i);
1000
1001 iova += SZ_1G;
1002 j++;
1003 j = find_next_bit(&cfg->pgsize_bitmap, BITS_PER_LONG, j);
1004 }
1005
1006 /* Partial unmap */
1007 size = 1UL << __ffs(cfg->pgsize_bitmap);
1008 if (ops->unmap(ops, SZ_1G + size, size) != size)
1009 return __FAIL(ops, i);
1010
1011 /* Remap of partial unmap */
1012 if (ops->map(ops, SZ_1G + size, size, size, IOMMU_READ))
1013 return __FAIL(ops, i);
1014
1015 if (ops->iova_to_phys(ops, SZ_1G + size + 42) != (size + 42))
1016 return __FAIL(ops, i);
1017
1018 /* Full unmap */
1019 iova = 0;
1020 j = find_first_bit(&cfg->pgsize_bitmap, BITS_PER_LONG);
1021 while (j != BITS_PER_LONG) {
1022 size = 1UL << j;
1023
1024 if (ops->unmap(ops, iova, size) != size)
1025 return __FAIL(ops, i);
1026
1027 if (ops->iova_to_phys(ops, iova + 42))
1028 return __FAIL(ops, i);
1029
1030 /* Remap full block */
1031 if (ops->map(ops, iova, iova, size, IOMMU_WRITE))
1032 return __FAIL(ops, i);
1033
1034 if (ops->iova_to_phys(ops, iova + 42) != (iova + 42))
1035 return __FAIL(ops, i);
1036
1037 iova += SZ_1G;
1038 j++;
1039 j = find_next_bit(&cfg->pgsize_bitmap, BITS_PER_LONG, j);
1040 }
1041
1042 free_io_pgtable_ops(ops);
1043 }
1044
1045 selftest_running = false;
1046 return 0;
1047}
1048
1049static int __init arm_lpae_do_selftests(void)
1050{
1051 static const unsigned long pgsize[] = {
1052 SZ_4K | SZ_2M | SZ_1G,
1053 SZ_16K | SZ_32M,
1054 SZ_64K | SZ_512M,
1055 };
1056
1057 static const unsigned int ias[] = {
1058 32, 36, 40, 42, 44, 48,
1059 };
1060
1061 int i, j, pass = 0, fail = 0;
1062 struct io_pgtable_cfg cfg = {
1063 .tlb = &dummy_tlb_ops,
1064 .oas = 48,
1065 };
1066
1067 for (i = 0; i < ARRAY_SIZE(pgsize); ++i) {
1068 for (j = 0; j < ARRAY_SIZE(ias); ++j) {
1069 cfg.pgsize_bitmap = pgsize[i];
1070 cfg.ias = ias[j];
1071 pr_info("selftest: pgsize_bitmap 0x%08lx, IAS %u\n",
1072 pgsize[i], ias[j]);
1073 if (arm_lpae_run_tests(&cfg))
1074 fail++;
1075 else
1076 pass++;
1077 }
1078 }
1079
1080 pr_info("selftest: completed with %d PASS %d FAIL\n", pass, fail);
1081 return fail ? -EFAULT : 0;
1082}
1083subsys_initcall(arm_lpae_do_selftests);
1084#endif