Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2010 Advanced Micro Devices, Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 21 | * DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Alex Deucher <alexander.deucher@amd.com> |
| 25 | */ |
| 26 | |
| 27 | #include "drmP.h" |
| 28 | #include "drm.h" |
| 29 | #include "radeon_drm.h" |
| 30 | #include "radeon.h" |
| 31 | |
| 32 | #include "evergreend.h" |
| 33 | #include "evergreen_blit_shaders.h" |
Alex Deucher | cb92d45 | 2011-05-25 16:39:00 -0400 | [diff] [blame] | 34 | #include "cayman_blit_shaders.h" |
Ilija Hadzic | 86a4d69 | 2012-02-01 11:42:38 -0500 | [diff] [blame] | 35 | #include "radeon_blit_common.h" |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 36 | |
| 37 | /* emits 17 */ |
| 38 | static void |
| 39 | set_render_target(struct radeon_device *rdev, int format, |
| 40 | int w, int h, u64 gpu_addr) |
| 41 | { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 42 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 43 | u32 cb_color_info; |
| 44 | int pitch, slice; |
| 45 | |
| 46 | h = ALIGN(h, 8); |
| 47 | if (h < 8) |
| 48 | h = 8; |
| 49 | |
Ilija Hadzic | 6018faf | 2011-10-12 23:29:36 -0400 | [diff] [blame] | 50 | cb_color_info = CB_FORMAT(format) | |
| 51 | CB_SOURCE_FORMAT(CB_SF_EXPORT_NORM) | |
| 52 | CB_ARRAY_MODE(ARRAY_1D_TILED_THIN1); |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 53 | pitch = (w / 8) - 1; |
| 54 | slice = ((w * h) / 64) - 1; |
| 55 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 56 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 15)); |
| 57 | radeon_ring_write(ring, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_START) >> 2); |
| 58 | radeon_ring_write(ring, gpu_addr >> 8); |
| 59 | radeon_ring_write(ring, pitch); |
| 60 | radeon_ring_write(ring, slice); |
| 61 | radeon_ring_write(ring, 0); |
| 62 | radeon_ring_write(ring, cb_color_info); |
| 63 | radeon_ring_write(ring, 0); |
| 64 | radeon_ring_write(ring, (w - 1) | ((h - 1) << 16)); |
| 65 | radeon_ring_write(ring, 0); |
| 66 | radeon_ring_write(ring, 0); |
| 67 | radeon_ring_write(ring, 0); |
| 68 | radeon_ring_write(ring, 0); |
| 69 | radeon_ring_write(ring, 0); |
| 70 | radeon_ring_write(ring, 0); |
| 71 | radeon_ring_write(ring, 0); |
| 72 | radeon_ring_write(ring, 0); |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 73 | } |
| 74 | |
| 75 | /* emits 5dw */ |
| 76 | static void |
| 77 | cp_set_surface_sync(struct radeon_device *rdev, |
| 78 | u32 sync_type, u32 size, |
| 79 | u64 mc_addr) |
| 80 | { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 81 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 82 | u32 cp_coher_size; |
| 83 | |
| 84 | if (size == 0xffffffff) |
| 85 | cp_coher_size = 0xffffffff; |
| 86 | else |
| 87 | cp_coher_size = ((size + 255) >> 8); |
| 88 | |
Alex Deucher | 06c9c23 | 2011-10-24 12:57:57 -0400 | [diff] [blame] | 89 | if (rdev->family >= CHIP_CAYMAN) { |
| 90 | /* CP_COHER_CNTL2 has to be set manually when submitting a surface_sync |
| 91 | * to the RB directly. For IBs, the CP programs this as part of the |
| 92 | * surface_sync packet. |
| 93 | */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 94 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
| 95 | radeon_ring_write(ring, (0x85e8 - PACKET3_SET_CONFIG_REG_START) >> 2); |
| 96 | radeon_ring_write(ring, 0); /* CP_COHER_CNTL2 */ |
Alex Deucher | 06c9c23 | 2011-10-24 12:57:57 -0400 | [diff] [blame] | 97 | } |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 98 | radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); |
| 99 | radeon_ring_write(ring, sync_type); |
| 100 | radeon_ring_write(ring, cp_coher_size); |
| 101 | radeon_ring_write(ring, mc_addr >> 8); |
| 102 | radeon_ring_write(ring, 10); /* poll interval */ |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 103 | } |
| 104 | |
| 105 | /* emits 11dw + 1 surface sync = 16dw */ |
| 106 | static void |
| 107 | set_shaders(struct radeon_device *rdev) |
| 108 | { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 109 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 110 | u64 gpu_addr; |
| 111 | |
| 112 | /* VS */ |
| 113 | gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 114 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 3)); |
| 115 | radeon_ring_write(ring, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_START) >> 2); |
| 116 | radeon_ring_write(ring, gpu_addr >> 8); |
| 117 | radeon_ring_write(ring, 2); |
| 118 | radeon_ring_write(ring, 0); |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 119 | |
| 120 | /* PS */ |
| 121 | gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset; |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 122 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 4)); |
| 123 | radeon_ring_write(ring, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_START) >> 2); |
| 124 | radeon_ring_write(ring, gpu_addr >> 8); |
| 125 | radeon_ring_write(ring, 1); |
| 126 | radeon_ring_write(ring, 0); |
| 127 | radeon_ring_write(ring, 2); |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 128 | |
| 129 | gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; |
| 130 | cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr); |
| 131 | } |
| 132 | |
| 133 | /* emits 10 + 1 sync (5) = 15 */ |
| 134 | static void |
| 135 | set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr) |
| 136 | { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 137 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 138 | u32 sq_vtx_constant_word2, sq_vtx_constant_word3; |
| 139 | |
| 140 | /* high addr, stride */ |
Ilija Hadzic | 6018faf | 2011-10-12 23:29:36 -0400 | [diff] [blame] | 141 | sq_vtx_constant_word2 = SQ_VTXC_BASE_ADDR_HI(upper_32_bits(gpu_addr) & 0xff) | |
| 142 | SQ_VTXC_STRIDE(16); |
Alex Deucher | 0f234f5f | 2011-02-13 19:06:33 -0500 | [diff] [blame] | 143 | #ifdef __BIG_ENDIAN |
Ilija Hadzic | 6018faf | 2011-10-12 23:29:36 -0400 | [diff] [blame] | 144 | sq_vtx_constant_word2 |= SQ_VTXC_ENDIAN_SWAP(SQ_ENDIAN_8IN32); |
Alex Deucher | 0f234f5f | 2011-02-13 19:06:33 -0500 | [diff] [blame] | 145 | #endif |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 146 | /* xyzw swizzles */ |
Ilija Hadzic | 6018faf | 2011-10-12 23:29:36 -0400 | [diff] [blame] | 147 | sq_vtx_constant_word3 = SQ_VTCX_SEL_X(SQ_SEL_X) | |
| 148 | SQ_VTCX_SEL_Y(SQ_SEL_Y) | |
| 149 | SQ_VTCX_SEL_Z(SQ_SEL_Z) | |
| 150 | SQ_VTCX_SEL_W(SQ_SEL_W); |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 151 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 152 | radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 8)); |
| 153 | radeon_ring_write(ring, 0x580); |
| 154 | radeon_ring_write(ring, gpu_addr & 0xffffffff); |
| 155 | radeon_ring_write(ring, 48 - 1); /* size */ |
| 156 | radeon_ring_write(ring, sq_vtx_constant_word2); |
| 157 | radeon_ring_write(ring, sq_vtx_constant_word3); |
| 158 | radeon_ring_write(ring, 0); |
| 159 | radeon_ring_write(ring, 0); |
| 160 | radeon_ring_write(ring, 0); |
| 161 | radeon_ring_write(ring, S__SQ_CONSTANT_TYPE(SQ_TEX_VTX_VALID_BUFFER)); |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 162 | |
Alex Deucher | e719ebd | 2010-11-22 17:56:33 -0500 | [diff] [blame] | 163 | if ((rdev->family == CHIP_CEDAR) || |
Alex Deucher | ff5b856 | 2011-01-06 21:19:28 -0500 | [diff] [blame] | 164 | (rdev->family == CHIP_PALM) || |
Alex Deucher | d5c5a72 | 2011-05-31 15:42:48 -0400 | [diff] [blame] | 165 | (rdev->family == CHIP_SUMO) || |
| 166 | (rdev->family == CHIP_SUMO2) || |
Alex Deucher | ff5b856 | 2011-01-06 21:19:28 -0500 | [diff] [blame] | 167 | (rdev->family == CHIP_CAICOS)) |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 168 | cp_set_surface_sync(rdev, |
| 169 | PACKET3_TC_ACTION_ENA, 48, gpu_addr); |
| 170 | else |
| 171 | cp_set_surface_sync(rdev, |
| 172 | PACKET3_VC_ACTION_ENA, 48, gpu_addr); |
| 173 | |
| 174 | } |
| 175 | |
| 176 | /* emits 10 */ |
| 177 | static void |
| 178 | set_tex_resource(struct radeon_device *rdev, |
| 179 | int format, int w, int h, int pitch, |
Alex Deucher | 9bb7703 | 2011-10-22 10:07:09 -0400 | [diff] [blame] | 180 | u64 gpu_addr, u32 size) |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 181 | { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 182 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 183 | u32 sq_tex_resource_word0, sq_tex_resource_word1; |
| 184 | u32 sq_tex_resource_word4, sq_tex_resource_word7; |
| 185 | |
| 186 | if (h < 1) |
| 187 | h = 1; |
| 188 | |
Ilija Hadzic | 6018faf | 2011-10-12 23:29:36 -0400 | [diff] [blame] | 189 | sq_tex_resource_word0 = TEX_DIM(SQ_TEX_DIM_2D); |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 190 | sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 6) | |
| 191 | ((w - 1) << 18)); |
Ilija Hadzic | 6018faf | 2011-10-12 23:29:36 -0400 | [diff] [blame] | 192 | sq_tex_resource_word1 = ((h - 1) << 0) | |
| 193 | TEX_ARRAY_MODE(ARRAY_1D_TILED_THIN1); |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 194 | /* xyzw swizzles */ |
Ilija Hadzic | 6018faf | 2011-10-12 23:29:36 -0400 | [diff] [blame] | 195 | sq_tex_resource_word4 = TEX_DST_SEL_X(SQ_SEL_X) | |
| 196 | TEX_DST_SEL_Y(SQ_SEL_Y) | |
| 197 | TEX_DST_SEL_Z(SQ_SEL_Z) | |
| 198 | TEX_DST_SEL_W(SQ_SEL_W); |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 199 | |
Ilija Hadzic | 6018faf | 2011-10-12 23:29:36 -0400 | [diff] [blame] | 200 | sq_tex_resource_word7 = format | |
| 201 | S__SQ_CONSTANT_TYPE(SQ_TEX_VTX_VALID_TEXTURE); |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 202 | |
Alex Deucher | 9bb7703 | 2011-10-22 10:07:09 -0400 | [diff] [blame] | 203 | cp_set_surface_sync(rdev, |
| 204 | PACKET3_TC_ACTION_ENA, size, gpu_addr); |
| 205 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 206 | radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 8)); |
| 207 | radeon_ring_write(ring, 0); |
| 208 | radeon_ring_write(ring, sq_tex_resource_word0); |
| 209 | radeon_ring_write(ring, sq_tex_resource_word1); |
| 210 | radeon_ring_write(ring, gpu_addr >> 8); |
| 211 | radeon_ring_write(ring, gpu_addr >> 8); |
| 212 | radeon_ring_write(ring, sq_tex_resource_word4); |
| 213 | radeon_ring_write(ring, 0); |
| 214 | radeon_ring_write(ring, 0); |
| 215 | radeon_ring_write(ring, sq_tex_resource_word7); |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 216 | } |
| 217 | |
| 218 | /* emits 12 */ |
| 219 | static void |
| 220 | set_scissors(struct radeon_device *rdev, int x1, int y1, |
| 221 | int x2, int y2) |
| 222 | { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 223 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
Alex Deucher | ac10f81 | 2011-05-25 01:00:45 -0400 | [diff] [blame] | 224 | /* workaround some hw bugs */ |
| 225 | if (x2 == 0) |
| 226 | x1 = 1; |
| 227 | if (y2 == 0) |
| 228 | y1 = 1; |
Alex Deucher | 7b76e47 | 2012-03-20 17:18:36 -0400 | [diff] [blame] | 229 | if (rdev->family >= CHIP_CAYMAN) { |
Alex Deucher | ac10f81 | 2011-05-25 01:00:45 -0400 | [diff] [blame] | 230 | if ((x2 == 1) && (y2 == 1)) |
| 231 | x2 = 2; |
| 232 | } |
| 233 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 234 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
| 235 | radeon_ring_write(ring, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2); |
| 236 | radeon_ring_write(ring, (x1 << 0) | (y1 << 16)); |
| 237 | radeon_ring_write(ring, (x2 << 0) | (y2 << 16)); |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 238 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 239 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
| 240 | radeon_ring_write(ring, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2); |
| 241 | radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31)); |
| 242 | radeon_ring_write(ring, (x2 << 0) | (y2 << 16)); |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 243 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 244 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
| 245 | radeon_ring_write(ring, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2); |
| 246 | radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31)); |
| 247 | radeon_ring_write(ring, (x2 << 0) | (y2 << 16)); |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 248 | } |
| 249 | |
| 250 | /* emits 10 */ |
| 251 | static void |
| 252 | draw_auto(struct radeon_device *rdev) |
| 253 | { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 254 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
| 255 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
| 256 | radeon_ring_write(ring, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_START) >> 2); |
| 257 | radeon_ring_write(ring, DI_PT_RECTLIST); |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 258 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 259 | radeon_ring_write(ring, PACKET3(PACKET3_INDEX_TYPE, 0)); |
| 260 | radeon_ring_write(ring, |
Alex Deucher | 0f234f5f | 2011-02-13 19:06:33 -0500 | [diff] [blame] | 261 | #ifdef __BIG_ENDIAN |
| 262 | (2 << 2) | |
| 263 | #endif |
| 264 | DI_INDEX_SIZE_16_BIT); |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 265 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 266 | radeon_ring_write(ring, PACKET3(PACKET3_NUM_INSTANCES, 0)); |
| 267 | radeon_ring_write(ring, 1); |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 268 | |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 269 | radeon_ring_write(ring, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1)); |
| 270 | radeon_ring_write(ring, 3); |
| 271 | radeon_ring_write(ring, DI_SRC_SEL_AUTO_INDEX); |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 272 | |
| 273 | } |
| 274 | |
Alex Deucher | c61d0af | 2011-07-12 11:53:23 -0400 | [diff] [blame] | 275 | /* emits 39 */ |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 276 | static void |
| 277 | set_default_state(struct radeon_device *rdev) |
| 278 | { |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 279 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 280 | u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2, sq_gpr_resource_mgmt_3; |
| 281 | u32 sq_thread_resource_mgmt, sq_thread_resource_mgmt_2; |
| 282 | u32 sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2, sq_stack_resource_mgmt_3; |
| 283 | int num_ps_gprs, num_vs_gprs, num_temp_gprs; |
| 284 | int num_gs_gprs, num_es_gprs, num_hs_gprs, num_ls_gprs; |
| 285 | int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads; |
| 286 | int num_hs_threads, num_ls_threads; |
| 287 | int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries; |
| 288 | int num_hs_stack_entries, num_ls_stack_entries; |
Alex Deucher | 1e644d6 | 2011-01-27 17:01:52 -0500 | [diff] [blame] | 289 | u64 gpu_addr; |
| 290 | int dwords; |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 291 | |
Alex Deucher | 2281a37 | 2010-10-21 13:31:38 -0400 | [diff] [blame] | 292 | /* set clear context state */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 293 | radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); |
| 294 | radeon_ring_write(ring, 0); |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 295 | |
Alex Deucher | cb92d45 | 2011-05-25 16:39:00 -0400 | [diff] [blame] | 296 | if (rdev->family < CHIP_CAYMAN) { |
| 297 | switch (rdev->family) { |
| 298 | case CHIP_CEDAR: |
| 299 | default: |
| 300 | num_ps_gprs = 93; |
| 301 | num_vs_gprs = 46; |
| 302 | num_temp_gprs = 4; |
| 303 | num_gs_gprs = 31; |
| 304 | num_es_gprs = 31; |
| 305 | num_hs_gprs = 23; |
| 306 | num_ls_gprs = 23; |
| 307 | num_ps_threads = 96; |
| 308 | num_vs_threads = 16; |
| 309 | num_gs_threads = 16; |
| 310 | num_es_threads = 16; |
| 311 | num_hs_threads = 16; |
| 312 | num_ls_threads = 16; |
| 313 | num_ps_stack_entries = 42; |
| 314 | num_vs_stack_entries = 42; |
| 315 | num_gs_stack_entries = 42; |
| 316 | num_es_stack_entries = 42; |
| 317 | num_hs_stack_entries = 42; |
| 318 | num_ls_stack_entries = 42; |
| 319 | break; |
| 320 | case CHIP_REDWOOD: |
| 321 | num_ps_gprs = 93; |
| 322 | num_vs_gprs = 46; |
| 323 | num_temp_gprs = 4; |
| 324 | num_gs_gprs = 31; |
| 325 | num_es_gprs = 31; |
| 326 | num_hs_gprs = 23; |
| 327 | num_ls_gprs = 23; |
| 328 | num_ps_threads = 128; |
| 329 | num_vs_threads = 20; |
| 330 | num_gs_threads = 20; |
| 331 | num_es_threads = 20; |
| 332 | num_hs_threads = 20; |
| 333 | num_ls_threads = 20; |
| 334 | num_ps_stack_entries = 42; |
| 335 | num_vs_stack_entries = 42; |
| 336 | num_gs_stack_entries = 42; |
| 337 | num_es_stack_entries = 42; |
| 338 | num_hs_stack_entries = 42; |
| 339 | num_ls_stack_entries = 42; |
| 340 | break; |
| 341 | case CHIP_JUNIPER: |
| 342 | num_ps_gprs = 93; |
| 343 | num_vs_gprs = 46; |
| 344 | num_temp_gprs = 4; |
| 345 | num_gs_gprs = 31; |
| 346 | num_es_gprs = 31; |
| 347 | num_hs_gprs = 23; |
| 348 | num_ls_gprs = 23; |
| 349 | num_ps_threads = 128; |
| 350 | num_vs_threads = 20; |
| 351 | num_gs_threads = 20; |
| 352 | num_es_threads = 20; |
| 353 | num_hs_threads = 20; |
| 354 | num_ls_threads = 20; |
| 355 | num_ps_stack_entries = 85; |
| 356 | num_vs_stack_entries = 85; |
| 357 | num_gs_stack_entries = 85; |
| 358 | num_es_stack_entries = 85; |
| 359 | num_hs_stack_entries = 85; |
| 360 | num_ls_stack_entries = 85; |
| 361 | break; |
| 362 | case CHIP_CYPRESS: |
| 363 | case CHIP_HEMLOCK: |
| 364 | num_ps_gprs = 93; |
| 365 | num_vs_gprs = 46; |
| 366 | num_temp_gprs = 4; |
| 367 | num_gs_gprs = 31; |
| 368 | num_es_gprs = 31; |
| 369 | num_hs_gprs = 23; |
| 370 | num_ls_gprs = 23; |
| 371 | num_ps_threads = 128; |
| 372 | num_vs_threads = 20; |
| 373 | num_gs_threads = 20; |
| 374 | num_es_threads = 20; |
| 375 | num_hs_threads = 20; |
| 376 | num_ls_threads = 20; |
| 377 | num_ps_stack_entries = 85; |
| 378 | num_vs_stack_entries = 85; |
| 379 | num_gs_stack_entries = 85; |
| 380 | num_es_stack_entries = 85; |
| 381 | num_hs_stack_entries = 85; |
| 382 | num_ls_stack_entries = 85; |
| 383 | break; |
| 384 | case CHIP_PALM: |
| 385 | num_ps_gprs = 93; |
| 386 | num_vs_gprs = 46; |
| 387 | num_temp_gprs = 4; |
| 388 | num_gs_gprs = 31; |
| 389 | num_es_gprs = 31; |
| 390 | num_hs_gprs = 23; |
| 391 | num_ls_gprs = 23; |
| 392 | num_ps_threads = 96; |
| 393 | num_vs_threads = 16; |
| 394 | num_gs_threads = 16; |
| 395 | num_es_threads = 16; |
| 396 | num_hs_threads = 16; |
| 397 | num_ls_threads = 16; |
| 398 | num_ps_stack_entries = 42; |
| 399 | num_vs_stack_entries = 42; |
| 400 | num_gs_stack_entries = 42; |
| 401 | num_es_stack_entries = 42; |
| 402 | num_hs_stack_entries = 42; |
| 403 | num_ls_stack_entries = 42; |
| 404 | break; |
Alex Deucher | d5c5a72 | 2011-05-31 15:42:48 -0400 | [diff] [blame] | 405 | case CHIP_SUMO: |
| 406 | num_ps_gprs = 93; |
| 407 | num_vs_gprs = 46; |
| 408 | num_temp_gprs = 4; |
| 409 | num_gs_gprs = 31; |
| 410 | num_es_gprs = 31; |
| 411 | num_hs_gprs = 23; |
| 412 | num_ls_gprs = 23; |
| 413 | num_ps_threads = 96; |
| 414 | num_vs_threads = 25; |
| 415 | num_gs_threads = 25; |
| 416 | num_es_threads = 25; |
| 417 | num_hs_threads = 25; |
| 418 | num_ls_threads = 25; |
| 419 | num_ps_stack_entries = 42; |
| 420 | num_vs_stack_entries = 42; |
| 421 | num_gs_stack_entries = 42; |
| 422 | num_es_stack_entries = 42; |
| 423 | num_hs_stack_entries = 42; |
| 424 | num_ls_stack_entries = 42; |
| 425 | break; |
| 426 | case CHIP_SUMO2: |
| 427 | num_ps_gprs = 93; |
| 428 | num_vs_gprs = 46; |
| 429 | num_temp_gprs = 4; |
| 430 | num_gs_gprs = 31; |
| 431 | num_es_gprs = 31; |
| 432 | num_hs_gprs = 23; |
| 433 | num_ls_gprs = 23; |
| 434 | num_ps_threads = 96; |
| 435 | num_vs_threads = 25; |
| 436 | num_gs_threads = 25; |
| 437 | num_es_threads = 25; |
| 438 | num_hs_threads = 25; |
| 439 | num_ls_threads = 25; |
| 440 | num_ps_stack_entries = 85; |
| 441 | num_vs_stack_entries = 85; |
| 442 | num_gs_stack_entries = 85; |
| 443 | num_es_stack_entries = 85; |
| 444 | num_hs_stack_entries = 85; |
| 445 | num_ls_stack_entries = 85; |
| 446 | break; |
Alex Deucher | cb92d45 | 2011-05-25 16:39:00 -0400 | [diff] [blame] | 447 | case CHIP_BARTS: |
| 448 | num_ps_gprs = 93; |
| 449 | num_vs_gprs = 46; |
| 450 | num_temp_gprs = 4; |
| 451 | num_gs_gprs = 31; |
| 452 | num_es_gprs = 31; |
| 453 | num_hs_gprs = 23; |
| 454 | num_ls_gprs = 23; |
| 455 | num_ps_threads = 128; |
| 456 | num_vs_threads = 20; |
| 457 | num_gs_threads = 20; |
| 458 | num_es_threads = 20; |
| 459 | num_hs_threads = 20; |
| 460 | num_ls_threads = 20; |
| 461 | num_ps_stack_entries = 85; |
| 462 | num_vs_stack_entries = 85; |
| 463 | num_gs_stack_entries = 85; |
| 464 | num_es_stack_entries = 85; |
| 465 | num_hs_stack_entries = 85; |
| 466 | num_ls_stack_entries = 85; |
| 467 | break; |
| 468 | case CHIP_TURKS: |
| 469 | num_ps_gprs = 93; |
| 470 | num_vs_gprs = 46; |
| 471 | num_temp_gprs = 4; |
| 472 | num_gs_gprs = 31; |
| 473 | num_es_gprs = 31; |
| 474 | num_hs_gprs = 23; |
| 475 | num_ls_gprs = 23; |
| 476 | num_ps_threads = 128; |
| 477 | num_vs_threads = 20; |
| 478 | num_gs_threads = 20; |
| 479 | num_es_threads = 20; |
| 480 | num_hs_threads = 20; |
| 481 | num_ls_threads = 20; |
| 482 | num_ps_stack_entries = 42; |
| 483 | num_vs_stack_entries = 42; |
| 484 | num_gs_stack_entries = 42; |
| 485 | num_es_stack_entries = 42; |
| 486 | num_hs_stack_entries = 42; |
| 487 | num_ls_stack_entries = 42; |
| 488 | break; |
| 489 | case CHIP_CAICOS: |
| 490 | num_ps_gprs = 93; |
| 491 | num_vs_gprs = 46; |
| 492 | num_temp_gprs = 4; |
| 493 | num_gs_gprs = 31; |
| 494 | num_es_gprs = 31; |
| 495 | num_hs_gprs = 23; |
| 496 | num_ls_gprs = 23; |
| 497 | num_ps_threads = 128; |
| 498 | num_vs_threads = 10; |
| 499 | num_gs_threads = 10; |
| 500 | num_es_threads = 10; |
| 501 | num_hs_threads = 10; |
| 502 | num_ls_threads = 10; |
| 503 | num_ps_stack_entries = 42; |
| 504 | num_vs_stack_entries = 42; |
| 505 | num_gs_stack_entries = 42; |
| 506 | num_es_stack_entries = 42; |
| 507 | num_hs_stack_entries = 42; |
| 508 | num_ls_stack_entries = 42; |
| 509 | break; |
| 510 | } |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 511 | |
Alex Deucher | cb92d45 | 2011-05-25 16:39:00 -0400 | [diff] [blame] | 512 | if ((rdev->family == CHIP_CEDAR) || |
| 513 | (rdev->family == CHIP_PALM) || |
Alex Deucher | d5c5a72 | 2011-05-31 15:42:48 -0400 | [diff] [blame] | 514 | (rdev->family == CHIP_SUMO) || |
| 515 | (rdev->family == CHIP_SUMO2) || |
Alex Deucher | cb92d45 | 2011-05-25 16:39:00 -0400 | [diff] [blame] | 516 | (rdev->family == CHIP_CAICOS)) |
| 517 | sq_config = 0; |
| 518 | else |
| 519 | sq_config = VC_ENABLE; |
| 520 | |
| 521 | sq_config |= (EXPORT_SRC_C | |
| 522 | CS_PRIO(0) | |
| 523 | LS_PRIO(0) | |
| 524 | HS_PRIO(0) | |
| 525 | PS_PRIO(0) | |
| 526 | VS_PRIO(1) | |
| 527 | GS_PRIO(2) | |
| 528 | ES_PRIO(3)); |
| 529 | |
| 530 | sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) | |
| 531 | NUM_VS_GPRS(num_vs_gprs) | |
| 532 | NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); |
| 533 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) | |
| 534 | NUM_ES_GPRS(num_es_gprs)); |
| 535 | sq_gpr_resource_mgmt_3 = (NUM_HS_GPRS(num_hs_gprs) | |
| 536 | NUM_LS_GPRS(num_ls_gprs)); |
| 537 | sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) | |
| 538 | NUM_VS_THREADS(num_vs_threads) | |
| 539 | NUM_GS_THREADS(num_gs_threads) | |
| 540 | NUM_ES_THREADS(num_es_threads)); |
| 541 | sq_thread_resource_mgmt_2 = (NUM_HS_THREADS(num_hs_threads) | |
| 542 | NUM_LS_THREADS(num_ls_threads)); |
| 543 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) | |
| 544 | NUM_VS_STACK_ENTRIES(num_vs_stack_entries)); |
| 545 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) | |
| 546 | NUM_ES_STACK_ENTRIES(num_es_stack_entries)); |
| 547 | sq_stack_resource_mgmt_3 = (NUM_HS_STACK_ENTRIES(num_hs_stack_entries) | |
| 548 | NUM_LS_STACK_ENTRIES(num_ls_stack_entries)); |
| 549 | |
| 550 | /* disable dyn gprs */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 551 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
| 552 | radeon_ring_write(ring, (SQ_DYN_GPR_CNTL_PS_FLUSH_REQ - PACKET3_SET_CONFIG_REG_START) >> 2); |
| 553 | radeon_ring_write(ring, 0); |
Alex Deucher | cb92d45 | 2011-05-25 16:39:00 -0400 | [diff] [blame] | 554 | |
Alex Deucher | c61d0af | 2011-07-12 11:53:23 -0400 | [diff] [blame] | 555 | /* setup LDS */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 556 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
| 557 | radeon_ring_write(ring, (SQ_LDS_RESOURCE_MGMT - PACKET3_SET_CONFIG_REG_START) >> 2); |
| 558 | radeon_ring_write(ring, 0x10001000); |
Alex Deucher | c61d0af | 2011-07-12 11:53:23 -0400 | [diff] [blame] | 559 | |
Alex Deucher | cb92d45 | 2011-05-25 16:39:00 -0400 | [diff] [blame] | 560 | /* SQ config */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 561 | radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 11)); |
| 562 | radeon_ring_write(ring, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_START) >> 2); |
| 563 | radeon_ring_write(ring, sq_config); |
| 564 | radeon_ring_write(ring, sq_gpr_resource_mgmt_1); |
| 565 | radeon_ring_write(ring, sq_gpr_resource_mgmt_2); |
| 566 | radeon_ring_write(ring, sq_gpr_resource_mgmt_3); |
| 567 | radeon_ring_write(ring, 0); |
| 568 | radeon_ring_write(ring, 0); |
| 569 | radeon_ring_write(ring, sq_thread_resource_mgmt); |
| 570 | radeon_ring_write(ring, sq_thread_resource_mgmt_2); |
| 571 | radeon_ring_write(ring, sq_stack_resource_mgmt_1); |
| 572 | radeon_ring_write(ring, sq_stack_resource_mgmt_2); |
| 573 | radeon_ring_write(ring, sq_stack_resource_mgmt_3); |
Alex Deucher | cb92d45 | 2011-05-25 16:39:00 -0400 | [diff] [blame] | 574 | } |
Alex Deucher | 2281a37 | 2010-10-21 13:31:38 -0400 | [diff] [blame] | 575 | |
| 576 | /* CONTEXT_CONTROL */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 577 | radeon_ring_write(ring, 0xc0012800); |
| 578 | radeon_ring_write(ring, 0x80000000); |
| 579 | radeon_ring_write(ring, 0x80000000); |
Alex Deucher | 2281a37 | 2010-10-21 13:31:38 -0400 | [diff] [blame] | 580 | |
| 581 | /* SQ_VTX_BASE_VTX_LOC */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 582 | radeon_ring_write(ring, 0xc0026f00); |
| 583 | radeon_ring_write(ring, 0x00000000); |
| 584 | radeon_ring_write(ring, 0x00000000); |
| 585 | radeon_ring_write(ring, 0x00000000); |
Alex Deucher | 2281a37 | 2010-10-21 13:31:38 -0400 | [diff] [blame] | 586 | |
| 587 | /* SET_SAMPLER */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 588 | radeon_ring_write(ring, 0xc0036e00); |
| 589 | radeon_ring_write(ring, 0x00000000); |
| 590 | radeon_ring_write(ring, 0x00000012); |
| 591 | radeon_ring_write(ring, 0x00000000); |
| 592 | radeon_ring_write(ring, 0x00000000); |
Alex Deucher | 2281a37 | 2010-10-21 13:31:38 -0400 | [diff] [blame] | 593 | |
Alex Deucher | 1292059 | 2011-02-02 12:37:40 -0500 | [diff] [blame] | 594 | /* set to DX10/11 mode */ |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 595 | radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); |
| 596 | radeon_ring_write(ring, 1); |
Alex Deucher | 1292059 | 2011-02-02 12:37:40 -0500 | [diff] [blame] | 597 | |
Alex Deucher | 1e644d6 | 2011-01-27 17:01:52 -0500 | [diff] [blame] | 598 | /* emit an IB pointing at default state */ |
| 599 | dwords = ALIGN(rdev->r600_blit.state_len, 0x10); |
| 600 | gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset; |
Christian König | e32eb50 | 2011-10-23 12:56:27 +0200 | [diff] [blame] | 601 | radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); |
| 602 | radeon_ring_write(ring, gpu_addr & 0xFFFFFFFC); |
| 603 | radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xFF); |
| 604 | radeon_ring_write(ring, dwords); |
Alex Deucher | 1e644d6 | 2011-01-27 17:01:52 -0500 | [diff] [blame] | 605 | |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 606 | } |
| 607 | |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 608 | int evergreen_blit_init(struct radeon_device *rdev) |
| 609 | { |
| 610 | u32 obj_size; |
Alex Deucher | 0f234f5f | 2011-02-13 19:06:33 -0500 | [diff] [blame] | 611 | int i, r, dwords; |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 612 | void *ptr; |
Alex Deucher | 1e644d6 | 2011-01-27 17:01:52 -0500 | [diff] [blame] | 613 | u32 packet2s[16]; |
| 614 | int num_packet2s = 0; |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 615 | |
Ilija Hadzic | fb3d9e9 | 2011-10-12 23:29:41 -0400 | [diff] [blame] | 616 | rdev->r600_blit.primitives.set_render_target = set_render_target; |
| 617 | rdev->r600_blit.primitives.cp_set_surface_sync = cp_set_surface_sync; |
| 618 | rdev->r600_blit.primitives.set_shaders = set_shaders; |
| 619 | rdev->r600_blit.primitives.set_vtx_resource = set_vtx_resource; |
| 620 | rdev->r600_blit.primitives.set_tex_resource = set_tex_resource; |
| 621 | rdev->r600_blit.primitives.set_scissors = set_scissors; |
| 622 | rdev->r600_blit.primitives.draw_auto = draw_auto; |
| 623 | rdev->r600_blit.primitives.set_default_state = set_default_state; |
| 624 | |
Christian König | 220907d | 2012-05-10 16:46:43 +0200 | [diff] [blame] | 625 | rdev->r600_blit.ring_size_common = 8; /* sync semaphore */ |
| 626 | rdev->r600_blit.ring_size_common += 55; /* shaders + def state */ |
Jerome Glisse | 77b1bad | 2011-10-26 11:41:22 -0400 | [diff] [blame] | 627 | rdev->r600_blit.ring_size_common += 16; /* fence emit for VB IB */ |
Ilija Hadzic | fb3d9e9 | 2011-10-12 23:29:41 -0400 | [diff] [blame] | 628 | rdev->r600_blit.ring_size_common += 5; /* done copy */ |
Jerome Glisse | 77b1bad | 2011-10-26 11:41:22 -0400 | [diff] [blame] | 629 | rdev->r600_blit.ring_size_common += 16; /* fence emit for done copy */ |
Ilija Hadzic | fb3d9e9 | 2011-10-12 23:29:41 -0400 | [diff] [blame] | 630 | |
| 631 | rdev->r600_blit.ring_size_per_loop = 74; |
Alex Deucher | 06c9c23 | 2011-10-24 12:57:57 -0400 | [diff] [blame] | 632 | if (rdev->family >= CHIP_CAYMAN) |
| 633 | rdev->r600_blit.ring_size_per_loop += 9; /* additional DWs for surface sync */ |
Ilija Hadzic | fb3d9e9 | 2011-10-12 23:29:41 -0400 | [diff] [blame] | 634 | |
| 635 | rdev->r600_blit.max_dim = 16384; |
| 636 | |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 637 | /* pin copy shader into vram if already initialized */ |
| 638 | if (rdev->r600_blit.shader_obj) |
| 639 | goto done; |
| 640 | |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 641 | rdev->r600_blit.state_offset = 0; |
Alex Deucher | 1e644d6 | 2011-01-27 17:01:52 -0500 | [diff] [blame] | 642 | |
Alex Deucher | cb92d45 | 2011-05-25 16:39:00 -0400 | [diff] [blame] | 643 | if (rdev->family < CHIP_CAYMAN) |
| 644 | rdev->r600_blit.state_len = evergreen_default_size; |
| 645 | else |
| 646 | rdev->r600_blit.state_len = cayman_default_size; |
Alex Deucher | 1e644d6 | 2011-01-27 17:01:52 -0500 | [diff] [blame] | 647 | |
| 648 | dwords = rdev->r600_blit.state_len; |
| 649 | while (dwords & 0xf) { |
Alex Deucher | 0f234f5f | 2011-02-13 19:06:33 -0500 | [diff] [blame] | 650 | packet2s[num_packet2s++] = cpu_to_le32(PACKET2(0)); |
Alex Deucher | 1e644d6 | 2011-01-27 17:01:52 -0500 | [diff] [blame] | 651 | dwords++; |
| 652 | } |
| 653 | |
| 654 | obj_size = dwords * 4; |
| 655 | obj_size = ALIGN(obj_size, 256); |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 656 | |
| 657 | rdev->r600_blit.vs_offset = obj_size; |
Alex Deucher | cb92d45 | 2011-05-25 16:39:00 -0400 | [diff] [blame] | 658 | if (rdev->family < CHIP_CAYMAN) |
| 659 | obj_size += evergreen_vs_size * 4; |
| 660 | else |
| 661 | obj_size += cayman_vs_size * 4; |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 662 | obj_size = ALIGN(obj_size, 256); |
| 663 | |
| 664 | rdev->r600_blit.ps_offset = obj_size; |
Alex Deucher | cb92d45 | 2011-05-25 16:39:00 -0400 | [diff] [blame] | 665 | if (rdev->family < CHIP_CAYMAN) |
| 666 | obj_size += evergreen_ps_size * 4; |
| 667 | else |
| 668 | obj_size += cayman_ps_size * 4; |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 669 | obj_size = ALIGN(obj_size, 256); |
| 670 | |
Daniel Vetter | 441921d | 2011-02-18 17:59:16 +0100 | [diff] [blame] | 671 | r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, |
Alex Deucher | 40f5cf9 | 2012-05-10 18:33:13 -0400 | [diff] [blame] | 672 | NULL, &rdev->r600_blit.shader_obj); |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 673 | if (r) { |
| 674 | DRM_ERROR("evergreen failed to allocate shader\n"); |
| 675 | return r; |
| 676 | } |
| 677 | |
| 678 | DRM_DEBUG("evergreen blit allocated bo %08x vs %08x ps %08x\n", |
| 679 | obj_size, |
| 680 | rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset); |
| 681 | |
| 682 | r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); |
| 683 | if (unlikely(r != 0)) |
| 684 | return r; |
| 685 | r = radeon_bo_kmap(rdev->r600_blit.shader_obj, &ptr); |
| 686 | if (r) { |
| 687 | DRM_ERROR("failed to map blit object %d\n", r); |
| 688 | return r; |
| 689 | } |
| 690 | |
Alex Deucher | cb92d45 | 2011-05-25 16:39:00 -0400 | [diff] [blame] | 691 | if (rdev->family < CHIP_CAYMAN) { |
| 692 | memcpy_toio(ptr + rdev->r600_blit.state_offset, |
| 693 | evergreen_default_state, rdev->r600_blit.state_len * 4); |
Alex Deucher | 1e644d6 | 2011-01-27 17:01:52 -0500 | [diff] [blame] | 694 | |
Alex Deucher | cb92d45 | 2011-05-25 16:39:00 -0400 | [diff] [blame] | 695 | if (num_packet2s) |
| 696 | memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4), |
| 697 | packet2s, num_packet2s * 4); |
| 698 | for (i = 0; i < evergreen_vs_size; i++) |
| 699 | *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(evergreen_vs[i]); |
| 700 | for (i = 0; i < evergreen_ps_size; i++) |
| 701 | *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(evergreen_ps[i]); |
| 702 | } else { |
| 703 | memcpy_toio(ptr + rdev->r600_blit.state_offset, |
| 704 | cayman_default_state, rdev->r600_blit.state_len * 4); |
| 705 | |
| 706 | if (num_packet2s) |
| 707 | memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4), |
| 708 | packet2s, num_packet2s * 4); |
| 709 | for (i = 0; i < cayman_vs_size; i++) |
| 710 | *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(cayman_vs[i]); |
| 711 | for (i = 0; i < cayman_ps_size; i++) |
| 712 | *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(cayman_ps[i]); |
| 713 | } |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 714 | radeon_bo_kunmap(rdev->r600_blit.shader_obj); |
| 715 | radeon_bo_unreserve(rdev->r600_blit.shader_obj); |
| 716 | |
| 717 | done: |
| 718 | r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); |
| 719 | if (unlikely(r != 0)) |
| 720 | return r; |
| 721 | r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM, |
| 722 | &rdev->r600_blit.shader_gpu_addr); |
| 723 | radeon_bo_unreserve(rdev->r600_blit.shader_obj); |
| 724 | if (r) { |
| 725 | dev_err(rdev->dev, "(%d) pin blit object failed\n", r); |
| 726 | return r; |
| 727 | } |
Dave Airlie | 5359533 | 2011-03-14 09:47:24 +1000 | [diff] [blame] | 728 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); |
Alex Deucher | d7ccd8f | 2010-09-09 11:33:36 -0400 | [diff] [blame] | 729 | return 0; |
| 730 | } |