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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * IPIC private definitions and structure.
3 *
Kumar Gala4c8d3d92005-11-13 16:06:30 -08004 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 *
6 * Copyright 2005 Freescale Semiconductor, Inc
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13#ifndef __IPIC_H__
14#define __IPIC_H__
15
16#include <asm/ipic.h>
17
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -050018#define NR_IPIC_INTS 128
19
20/* External IRQS */
21#define IPIC_IRQ_EXT0 48
22#define IPIC_IRQ_EXT1 17
23#define IPIC_IRQ_EXT7 23
24
25/* Default Priority Registers */
Li Yangf03ca952007-10-19 19:38:43 +080026#define IPIC_PRIORITY_DEFAULT 0x05309770
Linus Torvalds1da177e2005-04-16 15:20:36 -070027
28/* System Global Interrupt Configuration Register */
29#define SICFR_IPSA 0x00010000
Li Yangf03ca952007-10-19 19:38:43 +080030#define SICFR_IPSB 0x00020000
31#define SICFR_IPSC 0x00040000
Linus Torvalds1da177e2005-04-16 15:20:36 -070032#define SICFR_IPSD 0x00080000
33#define SICFR_MPSA 0x00200000
34#define SICFR_MPSB 0x00400000
35
36/* System External Interrupt Mask Register */
37#define SEMSR_SIRQ0 0x00008000
38
39/* System Error Control Register */
40#define SERCR_MCPR 0x00000001
41
42struct ipic {
43 volatile u32 __iomem *regs;
Kim Phillipsb9f0f1b2006-08-25 11:59:07 -050044
45 /* The remapper for this IPIC */
46 struct irq_host *irqhost;
Linus Torvalds1da177e2005-04-16 15:20:36 -070047};
48
49struct ipic_info {
Li Yang77d43092007-12-04 19:01:40 +080050 u8 ack; /* pending register offset from base if the irq
51 supports ack operation */
Linus Torvalds1da177e2005-04-16 15:20:36 -070052 u8 mask; /* mask register offset from base */
53 u8 prio; /* priority register offset from base */
54 u8 force; /* force register offset from base */
55 u8 bit; /* register bit position (as per doc)
56 bit mask = 1 << (31 - bit) */
57 u8 prio_mask; /* priority mask value */
58};
59
60#endif /* __IPIC_H__ */