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Ingo Molnar06fcb0c2006-06-29 02:24:40 -07001#ifndef _LINUX_IRQ_H
2#define _LINUX_IRQ_H
Linus Torvalds1da177e2005-04-16 15:20:36 -07003
4/*
5 * Please do not include this file in generic code. There is currently
6 * no requirement for any architecture to implement anything held
7 * within this file.
8 *
9 * Thanks. --rmk
10 */
11
Adrian Bunk23f9b312005-12-21 02:27:50 +010012#include <linux/smp.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070013#include <linux/linkage.h>
14#include <linux/cache.h>
15#include <linux/spinlock.h>
16#include <linux/cpumask.h>
Ralf Baechle503e5762009-03-29 12:59:50 +020017#include <linux/gfp.h>
Thomas Gleixner75ffc002014-11-11 21:58:34 +010018#include <linux/irqhandler.h>
Jan Beulich908dcec2006-06-23 02:06:00 -070019#include <linux/irqreturn.h>
Thomas Gleixnerdd3a1db2008-10-16 18:20:58 +020020#include <linux/irqnr.h>
David Howells77904fd2007-02-28 20:13:26 -080021#include <linux/errno.h>
Ralf Baechle503e5762009-03-29 12:59:50 +020022#include <linux/topology.h>
Thomas Gleixner3aa551c2009-03-23 18:28:15 +010023#include <linux/wait.h>
Kevin Cernekee332fd7c2014-11-06 22:44:17 -080024#include <linux/io.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070025
26#include <asm/irq.h>
27#include <asm/ptrace.h>
David Howells7d12e782006-10-05 14:55:46 +010028#include <asm/irq_regs.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
Thomas Gleixnerab7798f2011-03-25 16:48:50 +010030struct seq_file;
Paul Gortmakerec53cf22011-09-19 20:33:19 -040031struct module;
Jiang Liu515085e2014-11-06 22:20:17 +080032struct msi_msg;
Marc Zyngier1b7047e2015-03-18 11:01:22 +000033enum irqchip_irq_state;
David Howells57a58a92006-10-05 13:06:34 +010034
Linus Torvalds1da177e2005-04-16 15:20:36 -070035/*
36 * IRQ line status.
Thomas Gleixner6e213612006-07-01 19:29:03 -070037 *
Thomas Gleixner5d4d8fc2011-02-08 17:27:18 +010038 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h
Thomas Gleixner6e213612006-07-01 19:29:03 -070039 *
Thomas Gleixner5d4d8fc2011-02-08 17:27:18 +010040 * IRQ_TYPE_NONE - default, unspecified type
41 * IRQ_TYPE_EDGE_RISING - rising edge triggered
42 * IRQ_TYPE_EDGE_FALLING - falling edge triggered
43 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered
44 * IRQ_TYPE_LEVEL_HIGH - high level triggered
45 * IRQ_TYPE_LEVEL_LOW - low level triggered
46 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits
47 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits
Benjamin Herrenschmidt3fca40c2012-04-19 17:29:42 +000048 * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type
49 * to setup the HW to a sane default (used
50 * by irqdomain map() callbacks to synchronize
51 * the HW state and SW flags for a newly
52 * allocated descriptor).
53 *
Thomas Gleixner5d4d8fc2011-02-08 17:27:18 +010054 * IRQ_TYPE_PROBE - Special flag for probing in progress
55 *
56 * Bits which can be modified via irq_set/clear/modify_status_flags()
57 * IRQ_LEVEL - Interrupt is level type. Will be also
58 * updated in the code when the above trigger
Geert Uytterhoeven0911f122011-04-10 11:01:51 +020059 * bits are modified via irq_set_irq_type()
Thomas Gleixner5d4d8fc2011-02-08 17:27:18 +010060 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect
61 * it from affinity setting
62 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing
63 * IRQ_NOREQUEST - Interrupt cannot be requested via
64 * request_irq()
Paul Mundt7f1b1242011-04-07 06:01:44 +090065 * IRQ_NOTHREAD - Interrupt cannot be threaded
Thomas Gleixner5d4d8fc2011-02-08 17:27:18 +010066 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in
67 * request/setup_irq()
68 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set)
69 * IRQ_MOVE_PCNTXT - Interrupt can be migrated from process context
Mika Westerberg92068d12015-10-01 15:54:52 +030070 * IRQ_NESTED_THREAD - Interrupt nests into another thread
Marc Zyngier31d9d9b2011-09-23 17:03:06 +010071 * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable
Thomas Gleixnerb39898c2013-11-06 12:30:07 +010072 * IRQ_IS_POLLED - Always polled by another interrupt. Exclude
73 * it from the spurious interrupt detection
74 * mechanism and from core side polling.
Thomas Gleixnere9849772015-10-09 23:28:58 +020075 * IRQ_DISABLE_UNLAZY - Disable lazy irq disable
Linus Torvalds1da177e2005-04-16 15:20:36 -070076 */
Thomas Gleixner5d4d8fc2011-02-08 17:27:18 +010077enum {
78 IRQ_TYPE_NONE = 0x00000000,
79 IRQ_TYPE_EDGE_RISING = 0x00000001,
80 IRQ_TYPE_EDGE_FALLING = 0x00000002,
81 IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING),
82 IRQ_TYPE_LEVEL_HIGH = 0x00000004,
83 IRQ_TYPE_LEVEL_LOW = 0x00000008,
84 IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH),
85 IRQ_TYPE_SENSE_MASK = 0x0000000f,
Benjamin Herrenschmidt3fca40c2012-04-19 17:29:42 +000086 IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK,
Thomas Gleixner876dbd42011-02-08 17:28:12 +010087
Thomas Gleixner5d4d8fc2011-02-08 17:27:18 +010088 IRQ_TYPE_PROBE = 0x00000010,
Thomas Gleixner6e213612006-07-01 19:29:03 -070089
Thomas Gleixner5d4d8fc2011-02-08 17:27:18 +010090 IRQ_LEVEL = (1 << 8),
91 IRQ_PER_CPU = (1 << 9),
92 IRQ_NOPROBE = (1 << 10),
93 IRQ_NOREQUEST = (1 << 11),
94 IRQ_NOAUTOEN = (1 << 12),
95 IRQ_NO_BALANCING = (1 << 13),
96 IRQ_MOVE_PCNTXT = (1 << 14),
97 IRQ_NESTED_THREAD = (1 << 15),
Paul Mundt7f1b1242011-04-07 06:01:44 +090098 IRQ_NOTHREAD = (1 << 16),
Marc Zyngier31d9d9b2011-09-23 17:03:06 +010099 IRQ_PER_CPU_DEVID = (1 << 17),
Thomas Gleixnerb39898c2013-11-06 12:30:07 +0100100 IRQ_IS_POLLED = (1 << 18),
Thomas Gleixnere9849772015-10-09 23:28:58 +0200101 IRQ_DISABLE_UNLAZY = (1 << 19),
Thomas Gleixner5d4d8fc2011-02-08 17:27:18 +0100102};
Thomas Gleixner950f4422007-02-16 01:27:24 -0800103
Thomas Gleixner44247182010-09-28 10:40:18 +0200104#define IRQF_MODIFY_MASK \
105 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \
Thomas Gleixner872434d2011-02-05 16:25:25 +0100106 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \
Thomas Gleixnerb39898c2013-11-06 12:30:07 +0100107 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \
Thomas Gleixnere9849772015-10-09 23:28:58 +0200108 IRQ_IS_POLLED | IRQ_DISABLE_UNLAZY)
Thomas Gleixner44247182010-09-28 10:40:18 +0200109
Thomas Gleixner8f53f922011-02-08 16:50:00 +0100110#define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING)
111
Thomas Gleixner3b8249e2011-02-07 16:02:20 +0100112/*
113 * Return value for chip->irq_set_affinity()
114 *
Jiang Liu9df872f2015-06-03 11:47:50 +0800115 * IRQ_SET_MASK_OK - OK, core updates irq_common_data.affinity
116 * IRQ_SET_MASK_NOCPY - OK, chip did update irq_common_data.affinity
Jiang Liu2cb62542014-11-06 22:20:18 +0800117 * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to
118 * support stacked irqchips, which indicates skipping
119 * all descendent irqchips.
Thomas Gleixner3b8249e2011-02-07 16:02:20 +0100120 */
121enum {
122 IRQ_SET_MASK_OK = 0,
123 IRQ_SET_MASK_OK_NOCOPY,
Jiang Liu2cb62542014-11-06 22:20:18 +0800124 IRQ_SET_MASK_OK_DONE,
Thomas Gleixner3b8249e2011-02-07 16:02:20 +0100125};
126
Eric W. Biederman5b912c12007-01-28 12:52:03 -0700127struct msi_desc;
Grant Likely08a543a2011-07-26 03:19:06 -0600128struct irq_domain;
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700129
Ingo Molnar8fee5c32006-06-29 02:24:45 -0700130/**
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800131 * struct irq_common_data - per irq data shared by all irqchips
132 * @state_use_accessors: status information for irq chip functions.
133 * Use accessor functions to deal with it
Jiang Liu449e9ca2015-06-01 16:05:16 +0800134 * @node: node index useful for balancing
Jiang Liuaf7080e2015-06-01 16:05:21 +0800135 * @handler_data: per-IRQ data for the irq_chip methods
Qais Yousef955bfe52015-12-08 13:20:17 +0000136 * @affinity: IRQ affinity on SMP. If this is an IPI
137 * related irq, then this is the mask of the
138 * CPUs to which an IPI can be sent.
Jiang Liub2377212015-06-01 16:05:43 +0800139 * @msi_desc: MSI descriptor
Qais Youseff256c9a2015-12-08 13:20:16 +0000140 * @ipi_offset: Offset of first IPI target cpu in @affinity. Optional.
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800141 */
142struct irq_common_data {
Boqun Fengb3542862015-12-29 12:18:48 +0800143 unsigned int __private state_use_accessors;
Jiang Liu449e9ca2015-06-01 16:05:16 +0800144#ifdef CONFIG_NUMA
145 unsigned int node;
146#endif
Jiang Liuaf7080e2015-06-01 16:05:21 +0800147 void *handler_data;
Jiang Liub2377212015-06-01 16:05:43 +0800148 struct msi_desc *msi_desc;
Jiang Liu9df872f2015-06-03 11:47:50 +0800149 cpumask_var_t affinity;
Qais Youseff256c9a2015-12-08 13:20:16 +0000150#ifdef CONFIG_GENERIC_IRQ_IPI
151 unsigned int ipi_offset;
152#endif
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800153};
154
155/**
156 * struct irq_data - per irq chip data passed down to chip functions
Thomas Gleixner966dc732013-05-06 14:30:22 +0000157 * @mask: precomputed bitmask for accessing the chip registers
Thomas Gleixnerff7dcd42010-09-27 12:44:25 +0000158 * @irq: interrupt number
Grant Likely08a543a2011-07-26 03:19:06 -0600159 * @hwirq: hardware interrupt number, local to the interrupt domain
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800160 * @common: point to data shared by all irqchips
Thomas Gleixnerff7dcd42010-09-27 12:44:25 +0000161 * @chip: low level interrupt hardware access
Grant Likely08a543a2011-07-26 03:19:06 -0600162 * @domain: Interrupt translation domain; responsible for mapping
163 * between hwirq number and linux irq number.
Jiang Liuf8264e32014-11-06 22:20:14 +0800164 * @parent_data: pointer to parent struct irq_data to support hierarchy
165 * irq_domain
Thomas Gleixnerff7dcd42010-09-27 12:44:25 +0000166 * @chip_data: platform-specific per-chip private data for the chip
167 * methods, to allow shared chip implementations
Thomas Gleixnerff7dcd42010-09-27 12:44:25 +0000168 */
169struct irq_data {
Thomas Gleixner966dc732013-05-06 14:30:22 +0000170 u32 mask;
Thomas Gleixnerff7dcd42010-09-27 12:44:25 +0000171 unsigned int irq;
Grant Likely08a543a2011-07-26 03:19:06 -0600172 unsigned long hwirq;
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800173 struct irq_common_data *common;
Thomas Gleixnerff7dcd42010-09-27 12:44:25 +0000174 struct irq_chip *chip;
Grant Likely08a543a2011-07-26 03:19:06 -0600175 struct irq_domain *domain;
Jiang Liuf8264e32014-11-06 22:20:14 +0800176#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
177 struct irq_data *parent_data;
178#endif
Thomas Gleixnerff7dcd42010-09-27 12:44:25 +0000179 void *chip_data;
Thomas Gleixnerff7dcd42010-09-27 12:44:25 +0000180};
181
Thomas Gleixnerf230b6d2011-02-05 15:20:04 +0100182/*
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800183 * Bit masks for irq_common_data.state_use_accessors
Thomas Gleixnerf230b6d2011-02-05 15:20:04 +0100184 *
Thomas Gleixner876dbd42011-02-08 17:28:12 +0100185 * IRQD_TRIGGER_MASK - Mask for the trigger type bits
Thomas Gleixnerf230b6d2011-02-05 15:20:04 +0100186 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending
Thomas Gleixnera0056772011-02-08 17:11:03 +0100187 * IRQD_NO_BALANCING - Balancing disabled for this IRQ
188 * IRQD_PER_CPU - Interrupt is per cpu
Thomas Gleixner2bdd1052011-02-08 17:22:00 +0100189 * IRQD_AFFINITY_SET - Interrupt affinity was set
Thomas Gleixner876dbd42011-02-08 17:28:12 +0100190 * IRQD_LEVEL - Interrupt is level triggered
Thomas Gleixner7f942262011-02-10 19:46:26 +0100191 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup
192 * from suspend
Thomas Gleixnere1ef8242011-02-10 22:25:31 +0100193 * IRDQ_MOVE_PCNTXT - Interrupt can be moved in process
194 * context
Thomas Gleixner32f41252011-03-28 14:10:52 +0200195 * IRQD_IRQ_DISABLED - Disabled state of the interrupt
196 * IRQD_IRQ_MASKED - Masked state of the interrupt
197 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt
Thomas Gleixnerb76f1672014-08-29 13:54:09 +0200198 * IRQD_WAKEUP_ARMED - Wakeup mode armed
Thomas Gleixnerfc569712015-09-15 12:33:42 +0200199 * IRQD_FORWARDED_TO_VCPU - The interrupt is forwarded to a VCPU
Thomas Gleixner9c255582016-07-04 17:39:23 +0900200 * IRQD_AFFINITY_MANAGED - Affinity is auto-managed by the kernel
Thomas Gleixnerf230b6d2011-02-05 15:20:04 +0100201 */
202enum {
Thomas Gleixner876dbd42011-02-08 17:28:12 +0100203 IRQD_TRIGGER_MASK = 0xf,
Thomas Gleixnera0056772011-02-08 17:11:03 +0100204 IRQD_SETAFFINITY_PENDING = (1 << 8),
205 IRQD_NO_BALANCING = (1 << 10),
206 IRQD_PER_CPU = (1 << 11),
Thomas Gleixner2bdd1052011-02-08 17:22:00 +0100207 IRQD_AFFINITY_SET = (1 << 12),
Thomas Gleixner876dbd42011-02-08 17:28:12 +0100208 IRQD_LEVEL = (1 << 13),
Thomas Gleixner7f942262011-02-10 19:46:26 +0100209 IRQD_WAKEUP_STATE = (1 << 14),
Thomas Gleixnere1ef8242011-02-10 22:25:31 +0100210 IRQD_MOVE_PCNTXT = (1 << 15),
Thomas Gleixner801a0e92011-03-27 11:02:49 +0200211 IRQD_IRQ_DISABLED = (1 << 16),
Thomas Gleixner32f41252011-03-28 14:10:52 +0200212 IRQD_IRQ_MASKED = (1 << 17),
213 IRQD_IRQ_INPROGRESS = (1 << 18),
Thomas Gleixnerb76f1672014-08-29 13:54:09 +0200214 IRQD_WAKEUP_ARMED = (1 << 19),
Thomas Gleixnerfc569712015-09-15 12:33:42 +0200215 IRQD_FORWARDED_TO_VCPU = (1 << 20),
Thomas Gleixner9c255582016-07-04 17:39:23 +0900216 IRQD_AFFINITY_MANAGED = (1 << 21),
Thomas Gleixnerf230b6d2011-02-05 15:20:04 +0100217};
218
Boqun Fengb3542862015-12-29 12:18:48 +0800219#define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors)
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800220
Thomas Gleixnerf230b6d2011-02-05 15:20:04 +0100221static inline bool irqd_is_setaffinity_pending(struct irq_data *d)
222{
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800223 return __irqd_to_state(d) & IRQD_SETAFFINITY_PENDING;
Thomas Gleixnerf230b6d2011-02-05 15:20:04 +0100224}
225
Thomas Gleixnera0056772011-02-08 17:11:03 +0100226static inline bool irqd_is_per_cpu(struct irq_data *d)
227{
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800228 return __irqd_to_state(d) & IRQD_PER_CPU;
Thomas Gleixnera0056772011-02-08 17:11:03 +0100229}
230
231static inline bool irqd_can_balance(struct irq_data *d)
232{
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800233 return !(__irqd_to_state(d) & (IRQD_PER_CPU | IRQD_NO_BALANCING));
Thomas Gleixnera0056772011-02-08 17:11:03 +0100234}
235
Thomas Gleixner2bdd1052011-02-08 17:22:00 +0100236static inline bool irqd_affinity_was_set(struct irq_data *d)
237{
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800238 return __irqd_to_state(d) & IRQD_AFFINITY_SET;
Thomas Gleixner2bdd1052011-02-08 17:22:00 +0100239}
240
Thomas Gleixneree38c042011-03-28 17:11:13 +0200241static inline void irqd_mark_affinity_was_set(struct irq_data *d)
242{
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800243 __irqd_to_state(d) |= IRQD_AFFINITY_SET;
Thomas Gleixneree38c042011-03-28 17:11:13 +0200244}
245
Thomas Gleixner876dbd42011-02-08 17:28:12 +0100246static inline u32 irqd_get_trigger_type(struct irq_data *d)
247{
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800248 return __irqd_to_state(d) & IRQD_TRIGGER_MASK;
Thomas Gleixner876dbd42011-02-08 17:28:12 +0100249}
250
251/*
252 * Must only be called inside irq_chip.irq_set_type() functions.
253 */
254static inline void irqd_set_trigger_type(struct irq_data *d, u32 type)
255{
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800256 __irqd_to_state(d) &= ~IRQD_TRIGGER_MASK;
257 __irqd_to_state(d) |= type & IRQD_TRIGGER_MASK;
Thomas Gleixner876dbd42011-02-08 17:28:12 +0100258}
259
260static inline bool irqd_is_level_type(struct irq_data *d)
261{
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800262 return __irqd_to_state(d) & IRQD_LEVEL;
Thomas Gleixner876dbd42011-02-08 17:28:12 +0100263}
264
Thomas Gleixner7f942262011-02-10 19:46:26 +0100265static inline bool irqd_is_wakeup_set(struct irq_data *d)
266{
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800267 return __irqd_to_state(d) & IRQD_WAKEUP_STATE;
Thomas Gleixner7f942262011-02-10 19:46:26 +0100268}
269
Thomas Gleixnere1ef8242011-02-10 22:25:31 +0100270static inline bool irqd_can_move_in_process_context(struct irq_data *d)
271{
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800272 return __irqd_to_state(d) & IRQD_MOVE_PCNTXT;
Thomas Gleixnere1ef8242011-02-10 22:25:31 +0100273}
274
Thomas Gleixner801a0e92011-03-27 11:02:49 +0200275static inline bool irqd_irq_disabled(struct irq_data *d)
276{
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800277 return __irqd_to_state(d) & IRQD_IRQ_DISABLED;
Thomas Gleixner801a0e92011-03-27 11:02:49 +0200278}
279
Thomas Gleixner32f41252011-03-28 14:10:52 +0200280static inline bool irqd_irq_masked(struct irq_data *d)
281{
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800282 return __irqd_to_state(d) & IRQD_IRQ_MASKED;
Thomas Gleixner32f41252011-03-28 14:10:52 +0200283}
284
285static inline bool irqd_irq_inprogress(struct irq_data *d)
286{
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800287 return __irqd_to_state(d) & IRQD_IRQ_INPROGRESS;
Thomas Gleixner32f41252011-03-28 14:10:52 +0200288}
289
Thomas Gleixnerb76f1672014-08-29 13:54:09 +0200290static inline bool irqd_is_wakeup_armed(struct irq_data *d)
291{
Jiang Liu0d0b4c82015-06-01 16:05:12 +0800292 return __irqd_to_state(d) & IRQD_WAKEUP_ARMED;
Thomas Gleixnerb76f1672014-08-29 13:54:09 +0200293}
294
Thomas Gleixnerfc569712015-09-15 12:33:42 +0200295static inline bool irqd_is_forwarded_to_vcpu(struct irq_data *d)
296{
297 return __irqd_to_state(d) & IRQD_FORWARDED_TO_VCPU;
298}
299
300static inline void irqd_set_forwarded_to_vcpu(struct irq_data *d)
301{
302 __irqd_to_state(d) |= IRQD_FORWARDED_TO_VCPU;
303}
304
305static inline void irqd_clr_forwarded_to_vcpu(struct irq_data *d)
306{
307 __irqd_to_state(d) &= ~IRQD_FORWARDED_TO_VCPU;
308}
Thomas Gleixnerb76f1672014-08-29 13:54:09 +0200309
Thomas Gleixner9c255582016-07-04 17:39:23 +0900310static inline bool irqd_affinity_is_managed(struct irq_data *d)
311{
312 return __irqd_to_state(d) & IRQD_AFFINITY_MANAGED;
313}
314
Boqun Fengb3542862015-12-29 12:18:48 +0800315#undef __irqd_to_state
316
Grant Likelya699e4e2012-04-03 07:11:04 -0600317static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d)
318{
319 return d->hwirq;
320}
321
Thomas Gleixnerff7dcd42010-09-27 12:44:25 +0000322/**
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700323 * struct irq_chip - hardware interrupt chip descriptor
Ingo Molnar8fee5c32006-06-29 02:24:45 -0700324 *
Jon Hunterbe45beb2016-06-07 16:12:29 +0100325 * @parent_device: pointer to parent device for irqchip
Ingo Molnar8fee5c32006-06-29 02:24:45 -0700326 * @name: name for /proc/interrupts
Thomas Gleixnerf8822652010-09-27 12:44:32 +0000327 * @irq_startup: start up the interrupt (defaults to ->enable if NULL)
328 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL)
329 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL)
330 * @irq_disable: disable the interrupt
331 * @irq_ack: start of a new interrupt
332 * @irq_mask: mask an interrupt source
333 * @irq_mask_ack: ack and mask an interrupt source
334 * @irq_unmask: unmask an interrupt source
335 * @irq_eoi: end of interrupt
336 * @irq_set_affinity: set the CPU affinity on SMP machines
337 * @irq_retrigger: resend an IRQ to the CPU
338 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ
339 * @irq_set_wake: enable/disable power-management wake-on of an IRQ
340 * @irq_bus_lock: function to lock access to slow bus (i2c) chips
341 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips
David Daney0fdb4b22011-03-25 12:38:49 -0700342 * @irq_cpu_online: configure an interrupt source for a secondary CPU
343 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU
Brian Norrisbe9b22b2015-07-22 16:21:39 -0700344 * @irq_suspend: function called from core code on suspend once per
345 * chip, when one or more interrupts are installed
346 * @irq_resume: function called from core code on resume once per chip,
347 * when one ore more interrupts are installed
Thomas Gleixnercfefd212011-04-15 22:36:08 +0200348 * @irq_pm_shutdown: function called from core code on shutdown once per chip
Thomas Gleixnerd0051812013-05-06 14:30:24 +0000349 * @irq_calc_mask: Optional function to set irq_data.mask for special cases
Thomas Gleixnerab7798f2011-03-25 16:48:50 +0100350 * @irq_print_chip: optional to print special chip info in show_interrupts
Thomas Gleixnerc1bacba2014-03-08 08:59:58 +0100351 * @irq_request_resources: optional to request resources before calling
352 * any other callback related to this irq
353 * @irq_release_resources: optional to release resources acquired with
354 * irq_request_resources
Jiang Liu515085e2014-11-06 22:20:17 +0800355 * @irq_compose_msi_msg: optional to compose message content for MSI
Jiang Liu9dde55b2014-11-09 23:10:28 +0800356 * @irq_write_msi_msg: optional to write message content for MSI
Marc Zyngier1b7047e2015-03-18 11:01:22 +0000357 * @irq_get_irqchip_state: return the internal state of an interrupt
358 * @irq_set_irqchip_state: set the internal state of a interrupt
Jiang Liu0a4377d2015-05-19 17:07:14 +0800359 * @irq_set_vcpu_affinity: optional to target a vCPU in a virtual machine
Qais Yousef34dc1ae2015-12-08 13:20:21 +0000360 * @ipi_send_single: send a single IPI to destination cpus
361 * @ipi_send_mask: send an IPI to destination cpus in cpumask
Thomas Gleixner2bff17a2011-02-10 13:08:38 +0100362 * @flags: chip specific flags
Linus Torvalds1da177e2005-04-16 15:20:36 -0700363 */
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700364struct irq_chip {
Jon Hunterbe45beb2016-06-07 16:12:29 +0100365 struct device *parent_device;
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700366 const char *name;
Thomas Gleixnerf8822652010-09-27 12:44:32 +0000367 unsigned int (*irq_startup)(struct irq_data *data);
368 void (*irq_shutdown)(struct irq_data *data);
369 void (*irq_enable)(struct irq_data *data);
370 void (*irq_disable)(struct irq_data *data);
371
372 void (*irq_ack)(struct irq_data *data);
373 void (*irq_mask)(struct irq_data *data);
374 void (*irq_mask_ack)(struct irq_data *data);
375 void (*irq_unmask)(struct irq_data *data);
376 void (*irq_eoi)(struct irq_data *data);
377
378 int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force);
379 int (*irq_retrigger)(struct irq_data *data);
380 int (*irq_set_type)(struct irq_data *data, unsigned int flow_type);
381 int (*irq_set_wake)(struct irq_data *data, unsigned int on);
382
383 void (*irq_bus_lock)(struct irq_data *data);
384 void (*irq_bus_sync_unlock)(struct irq_data *data);
385
David Daney0fdb4b22011-03-25 12:38:49 -0700386 void (*irq_cpu_online)(struct irq_data *data);
387 void (*irq_cpu_offline)(struct irq_data *data);
388
Thomas Gleixnercfefd212011-04-15 22:36:08 +0200389 void (*irq_suspend)(struct irq_data *data);
390 void (*irq_resume)(struct irq_data *data);
391 void (*irq_pm_shutdown)(struct irq_data *data);
392
Thomas Gleixnerd0051812013-05-06 14:30:24 +0000393 void (*irq_calc_mask)(struct irq_data *data);
394
Thomas Gleixnerab7798f2011-03-25 16:48:50 +0100395 void (*irq_print_chip)(struct irq_data *data, struct seq_file *p);
Thomas Gleixnerc1bacba2014-03-08 08:59:58 +0100396 int (*irq_request_resources)(struct irq_data *data);
397 void (*irq_release_resources)(struct irq_data *data);
Thomas Gleixnerab7798f2011-03-25 16:48:50 +0100398
Jiang Liu515085e2014-11-06 22:20:17 +0800399 void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg);
Jiang Liu9dde55b2014-11-09 23:10:28 +0800400 void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg);
Jiang Liu515085e2014-11-06 22:20:17 +0800401
Marc Zyngier1b7047e2015-03-18 11:01:22 +0000402 int (*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state);
403 int (*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state);
404
Jiang Liu0a4377d2015-05-19 17:07:14 +0800405 int (*irq_set_vcpu_affinity)(struct irq_data *data, void *vcpu_info);
406
Qais Yousef34dc1ae2015-12-08 13:20:21 +0000407 void (*ipi_send_single)(struct irq_data *data, unsigned int cpu);
408 void (*ipi_send_mask)(struct irq_data *data, const struct cpumask *dest);
409
Thomas Gleixner2bff17a2011-02-10 13:08:38 +0100410 unsigned long flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700411};
412
Thomas Gleixnerd4d5e082011-02-10 13:16:14 +0100413/*
414 * irq_chip specific flags
415 *
Thomas Gleixner77694b42011-02-15 10:33:57 +0100416 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type()
417 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled
Thomas Gleixnerd209a692011-03-11 21:22:14 +0100418 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path
Thomas Gleixnerb3d42232011-03-27 16:05:36 +0200419 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks
420 * when irq enabled
Santosh Shilimkar60f96b42011-09-09 13:59:35 +0530421 * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip
Thomas Gleixner4f6e4f72014-03-13 15:32:47 +0100422 * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask
Thomas Gleixner328a4972014-03-13 19:03:51 +0100423 * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode
Thomas Gleixnerd4d5e082011-02-10 13:16:14 +0100424 */
425enum {
426 IRQCHIP_SET_TYPE_MASKED = (1 << 0),
Thomas Gleixner77694b42011-02-15 10:33:57 +0100427 IRQCHIP_EOI_IF_HANDLED = (1 << 1),
Thomas Gleixnerd209a692011-03-11 21:22:14 +0100428 IRQCHIP_MASK_ON_SUSPEND = (1 << 2),
Thomas Gleixnerb3d42232011-03-27 16:05:36 +0200429 IRQCHIP_ONOFFLINE_ENABLED = (1 << 3),
Santosh Shilimkar60f96b42011-09-09 13:59:35 +0530430 IRQCHIP_SKIP_SET_WAKE = (1 << 4),
Thomas Gleixnerdc9b2292012-07-13 19:29:45 +0200431 IRQCHIP_ONESHOT_SAFE = (1 << 5),
Thomas Gleixner328a4972014-03-13 19:03:51 +0100432 IRQCHIP_EOI_THREADED = (1 << 6),
Thomas Gleixnerd4d5e082011-02-10 13:16:14 +0100433};
434
Thomas Gleixnere1447102010-10-01 16:03:45 +0200435#include <linux/irqdesc.h>
Thomas Gleixnerc6b76742008-10-15 14:31:29 +0200436
Ingo Molnar34ffdb72006-06-29 02:24:40 -0700437/*
Ingo Molnar34ffdb72006-06-29 02:24:40 -0700438 * Pick up the arch-dependent methods:
439 */
440#include <asm/hw_irq.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -0700441
Thomas Gleixnerb683de22010-09-27 20:55:03 +0200442#ifndef NR_IRQS_LEGACY
443# define NR_IRQS_LEGACY 0
444#endif
445
Thomas Gleixner1318a482010-09-27 21:01:37 +0200446#ifndef ARCH_IRQ_INIT_FLAGS
447# define ARCH_IRQ_INIT_FLAGS 0
448#endif
449
Thomas Gleixnerc1594b72011-02-07 22:11:30 +0100450#define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS
Thomas Gleixner1318a482010-09-27 21:01:37 +0200451
Thomas Gleixnere1447102010-10-01 16:03:45 +0200452struct irqaction;
Ingo Molnar06fcb0c2006-06-29 02:24:40 -0700453extern int setup_irq(unsigned int irq, struct irqaction *new);
Magnus Dammcbf94f02009-03-12 21:05:51 +0900454extern void remove_irq(unsigned int irq, struct irqaction *act);
Marc Zyngier31d9d9b2011-09-23 17:03:06 +0100455extern int setup_percpu_irq(unsigned int irq, struct irqaction *new);
456extern void remove_percpu_irq(unsigned int irq, struct irqaction *act);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700457
David Daney0fdb4b22011-03-25 12:38:49 -0700458extern void irq_cpu_online(void);
459extern void irq_cpu_offline(void);
Thomas Gleixner01f8fa42014-04-16 14:36:44 +0000460extern int irq_set_affinity_locked(struct irq_data *data,
461 const struct cpumask *cpumask, bool force);
Jiang Liu0a4377d2015-05-19 17:07:14 +0800462extern int irq_set_vcpu_affinity(unsigned int irq, void *vcpu_info);
David Daney0fdb4b22011-03-25 12:38:49 -0700463
Yang Yingliangf1e0bb02015-09-24 17:32:13 +0800464extern void irq_migrate_all_off_this_cpu(void);
465
Thomas Gleixner3a3856d02010-10-04 13:47:12 +0200466#if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ)
Thomas Gleixnera4395202011-02-04 18:46:16 +0100467void irq_move_irq(struct irq_data *data);
468void irq_move_masked_irq(struct irq_data *data);
Thomas Gleixnere1447102010-10-01 16:03:45 +0200469#else
Thomas Gleixnera4395202011-02-04 18:46:16 +0100470static inline void irq_move_irq(struct irq_data *data) { }
471static inline void irq_move_masked_irq(struct irq_data *data) { }
Thomas Gleixnere1447102010-10-01 16:03:45 +0200472#endif
Ashok Raj54d5d422005-09-06 15:16:15 -0700473
Linus Torvalds1da177e2005-04-16 15:20:36 -0700474extern int no_irq_affinity;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700475
Thomas Gleixner293a7a02012-10-16 15:07:49 -0700476#ifdef CONFIG_HARDIRQS_SW_RESEND
477int irq_set_parent(int irq, int parent_irq);
478#else
479static inline int irq_set_parent(int irq, int parent_irq)
480{
481 return 0;
482}
483#endif
484
Ingo Molnar2e60bbb2006-06-29 02:24:39 -0700485/*
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700486 * Built-in IRQ handlers for various IRQ types,
Krzysztof Halasabebd04c2009-11-15 18:57:24 +0100487 * callable via desc->handle_irq()
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700488 */
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +0200489extern void handle_level_irq(struct irq_desc *desc);
490extern void handle_fasteoi_irq(struct irq_desc *desc);
491extern void handle_edge_irq(struct irq_desc *desc);
492extern void handle_edge_eoi_irq(struct irq_desc *desc);
493extern void handle_simple_irq(struct irq_desc *desc);
Keith Buschedd14cf2016-06-17 16:00:20 -0600494extern void handle_untracked_irq(struct irq_desc *desc);
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +0200495extern void handle_percpu_irq(struct irq_desc *desc);
496extern void handle_percpu_devid_irq(struct irq_desc *desc);
497extern void handle_bad_irq(struct irq_desc *desc);
Mark Brown31b47cf2009-08-24 20:28:04 +0100498extern void handle_nested_irq(unsigned int irq);
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700499
Jiang Liu515085e2014-11-06 22:20:17 +0800500extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg);
Jon Hunterbe45beb2016-06-07 16:12:29 +0100501extern int irq_chip_pm_get(struct irq_data *data);
502extern int irq_chip_pm_put(struct irq_data *data);
Jiang Liu85f08c12014-11-06 22:20:16 +0800503#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
Stefan Agner3cfeffc2015-05-16 11:44:14 +0200504extern void irq_chip_enable_parent(struct irq_data *data);
505extern void irq_chip_disable_parent(struct irq_data *data);
Jiang Liu85f08c12014-11-06 22:20:16 +0800506extern void irq_chip_ack_parent(struct irq_data *data);
507extern int irq_chip_retrigger_hierarchy(struct irq_data *data);
Yingjoe Chen56e8aba2014-11-13 23:37:05 +0800508extern void irq_chip_mask_parent(struct irq_data *data);
509extern void irq_chip_unmask_parent(struct irq_data *data);
510extern void irq_chip_eoi_parent(struct irq_data *data);
511extern int irq_chip_set_affinity_parent(struct irq_data *data,
512 const struct cpumask *dest,
513 bool force);
Marc Zyngier08b55e22015-03-11 15:43:43 +0000514extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on);
Jiang Liu0a4377d2015-05-19 17:07:14 +0800515extern int irq_chip_set_vcpu_affinity_parent(struct irq_data *data,
516 void *vcpu_info);
Grygorii Strashkob7560de2015-08-14 15:20:26 +0300517extern int irq_chip_set_type_parent(struct irq_data *data, unsigned int type);
Jiang Liu85f08c12014-11-06 22:20:16 +0800518#endif
519
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700520/* Handling of unhandled and spurious interrupts: */
Jiang Liu0dcdbc92015-06-04 12:13:28 +0800521extern void note_interrupt(struct irq_desc *desc, irqreturn_t action_ret);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700522
Thomas Gleixnera4633adc2006-06-29 02:24:48 -0700523
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700524/* Enable/disable irq debugging output: */
525extern int noirqdebug_setup(char *str);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700526
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700527/* Checks whether the interrupt can be requested by request_irq(): */
528extern int can_request_irq(unsigned int irq, unsigned long irqflags);
529
Thomas Gleixnerf8b54732006-07-01 22:30:08 +0100530/* Dummy irq-chip implementations: */
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700531extern struct irq_chip no_irq_chip;
Thomas Gleixnerf8b54732006-07-01 22:30:08 +0100532extern struct irq_chip dummy_irq_chip;
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700533
534extern void
Thomas Gleixner3836ca02011-02-14 20:09:19 +0100535irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
Ingo Molnara460e742006-10-17 00:10:03 -0700536 irq_flow_handler_t handle, const char *name);
537
Thomas Gleixner3836ca02011-02-14 20:09:19 +0100538static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip,
539 irq_flow_handler_t handle)
540{
541 irq_set_chip_and_handler_name(irq, chip, handle, NULL);
542}
543
Marc Zyngier31d9d9b2011-09-23 17:03:06 +0100544extern int irq_set_percpu_devid(unsigned int irq);
Marc Zyngier222df542016-04-11 09:57:52 +0100545extern int irq_set_percpu_devid_partition(unsigned int irq,
546 const struct cpumask *affinity);
547extern int irq_get_percpu_devid_partition(unsigned int irq,
548 struct cpumask *affinity);
Marc Zyngier31d9d9b2011-09-23 17:03:06 +0100549
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700550extern void
Thomas Gleixner3836ca02011-02-14 20:09:19 +0100551__irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
Ingo Molnara460e742006-10-17 00:10:03 -0700552 const char *name);
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700553
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700554static inline void
Thomas Gleixner3836ca02011-02-14 20:09:19 +0100555irq_set_handler(unsigned int irq, irq_flow_handler_t handle)
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700556{
Thomas Gleixner3836ca02011-02-14 20:09:19 +0100557 __irq_set_handler(irq, handle, 0, NULL);
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700558}
559
560/*
561 * Set a highlevel chained flow handler for a given IRQ.
562 * (a chained handler is automatically enabled and set to
Paul Mundt7f1b1242011-04-07 06:01:44 +0900563 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700564 */
565static inline void
Thomas Gleixner3836ca02011-02-14 20:09:19 +0100566irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle)
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700567{
Thomas Gleixner3836ca02011-02-14 20:09:19 +0100568 __irq_set_handler(irq, handle, 1, NULL);
Thomas Gleixner6a6de9e2006-06-29 02:24:51 -0700569}
570
Russell King3b0f95b2015-06-16 23:06:20 +0100571/*
572 * Set a highlevel chained flow handler and its data for a given IRQ.
573 * (a chained handler is automatically enabled and set to
574 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD)
575 */
576void
577irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle,
578 void *data);
579
Thomas Gleixner44247182010-09-28 10:40:18 +0200580void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set);
581
582static inline void irq_set_status_flags(unsigned int irq, unsigned long set)
583{
584 irq_modify_status(irq, 0, set);
585}
586
587static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr)
588{
589 irq_modify_status(irq, clr, 0);
590}
591
Thomas Gleixnera0cd9ca2011-02-10 11:36:33 +0100592static inline void irq_set_noprobe(unsigned int irq)
Thomas Gleixner44247182010-09-28 10:40:18 +0200593{
594 irq_modify_status(irq, 0, IRQ_NOPROBE);
595}
596
Thomas Gleixnera0cd9ca2011-02-10 11:36:33 +0100597static inline void irq_set_probe(unsigned int irq)
Thomas Gleixner44247182010-09-28 10:40:18 +0200598{
599 irq_modify_status(irq, IRQ_NOPROBE, 0);
600}
Ralf Baechle46f4f8f2008-02-08 04:22:01 -0800601
Paul Mundt7f1b1242011-04-07 06:01:44 +0900602static inline void irq_set_nothread(unsigned int irq)
603{
604 irq_modify_status(irq, 0, IRQ_NOTHREAD);
605}
606
607static inline void irq_set_thread(unsigned int irq)
608{
609 irq_modify_status(irq, IRQ_NOTHREAD, 0);
610}
611
Thomas Gleixner6f91a522011-02-14 13:33:16 +0100612static inline void irq_set_nested_thread(unsigned int irq, bool nest)
613{
614 if (nest)
615 irq_set_status_flags(irq, IRQ_NESTED_THREAD);
616 else
617 irq_clear_status_flags(irq, IRQ_NESTED_THREAD);
618}
619
Marc Zyngier31d9d9b2011-09-23 17:03:06 +0100620static inline void irq_set_percpu_devid_flags(unsigned int irq)
621{
622 irq_set_status_flags(irq,
623 IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD |
624 IRQ_NOPROBE | IRQ_PER_CPU_DEVID);
625}
626
Eric W. Biederman3a16d712006-10-04 02:16:37 -0700627/* Set/get chip/data for an IRQ: */
Thomas Gleixnera0cd9ca2011-02-10 11:36:33 +0100628extern int irq_set_chip(unsigned int irq, struct irq_chip *chip);
629extern int irq_set_handler_data(unsigned int irq, void *data);
630extern int irq_set_chip_data(unsigned int irq, void *data);
631extern int irq_set_irq_type(unsigned int irq, unsigned int type);
632extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry);
Alexander Gordeev51906e72012-11-19 16:01:29 +0100633extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset,
634 struct msi_desc *entry);
Thomas Gleixnerf303a6d2010-09-28 17:34:01 +0200635extern struct irq_data *irq_get_irq_data(unsigned int irq);
Thomas Gleixnerdd87eb32006-06-29 02:24:53 -0700636
Thomas Gleixnera0cd9ca2011-02-10 11:36:33 +0100637static inline struct irq_chip *irq_get_chip(unsigned int irq)
Thomas Gleixnerf303a6d2010-09-28 17:34:01 +0200638{
639 struct irq_data *d = irq_get_irq_data(irq);
640 return d ? d->chip : NULL;
641}
642
643static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d)
644{
645 return d->chip;
646}
647
Thomas Gleixnera0cd9ca2011-02-10 11:36:33 +0100648static inline void *irq_get_chip_data(unsigned int irq)
Thomas Gleixnerf303a6d2010-09-28 17:34:01 +0200649{
650 struct irq_data *d = irq_get_irq_data(irq);
651 return d ? d->chip_data : NULL;
652}
653
654static inline void *irq_data_get_irq_chip_data(struct irq_data *d)
655{
656 return d->chip_data;
657}
658
Thomas Gleixnera0cd9ca2011-02-10 11:36:33 +0100659static inline void *irq_get_handler_data(unsigned int irq)
Thomas Gleixnerf303a6d2010-09-28 17:34:01 +0200660{
661 struct irq_data *d = irq_get_irq_data(irq);
Jiang Liuaf7080e2015-06-01 16:05:21 +0800662 return d ? d->common->handler_data : NULL;
Thomas Gleixnerf303a6d2010-09-28 17:34:01 +0200663}
664
Thomas Gleixnera0cd9ca2011-02-10 11:36:33 +0100665static inline void *irq_data_get_irq_handler_data(struct irq_data *d)
Thomas Gleixnerf303a6d2010-09-28 17:34:01 +0200666{
Jiang Liuaf7080e2015-06-01 16:05:21 +0800667 return d->common->handler_data;
Thomas Gleixnerf303a6d2010-09-28 17:34:01 +0200668}
669
Thomas Gleixnera0cd9ca2011-02-10 11:36:33 +0100670static inline struct msi_desc *irq_get_msi_desc(unsigned int irq)
Thomas Gleixnerf303a6d2010-09-28 17:34:01 +0200671{
672 struct irq_data *d = irq_get_irq_data(irq);
Jiang Liub2377212015-06-01 16:05:43 +0800673 return d ? d->common->msi_desc : NULL;
Thomas Gleixnerf303a6d2010-09-28 17:34:01 +0200674}
675
Jiang Liuc391f262015-06-01 16:05:41 +0800676static inline struct msi_desc *irq_data_get_msi_desc(struct irq_data *d)
Thomas Gleixnerf303a6d2010-09-28 17:34:01 +0200677{
Jiang Liub2377212015-06-01 16:05:43 +0800678 return d->common->msi_desc;
Thomas Gleixnerf303a6d2010-09-28 17:34:01 +0200679}
680
Javier Martinez Canillas1f6236b2013-06-14 18:40:43 +0200681static inline u32 irq_get_trigger_type(unsigned int irq)
682{
683 struct irq_data *d = irq_get_irq_data(irq);
684 return d ? irqd_get_trigger_type(d) : 0;
685}
686
Jiang Liu449e9ca2015-06-01 16:05:16 +0800687static inline int irq_common_data_get_node(struct irq_common_data *d)
688{
689#ifdef CONFIG_NUMA
690 return d->node;
691#else
692 return 0;
693#endif
694}
695
Jiang Liu67830112015-06-01 16:05:13 +0800696static inline int irq_data_get_node(struct irq_data *d)
697{
Jiang Liu449e9ca2015-06-01 16:05:16 +0800698 return irq_common_data_get_node(d->common);
Jiang Liu67830112015-06-01 16:05:13 +0800699}
700
Jiang Liuc64301a2015-06-01 16:05:23 +0800701static inline struct cpumask *irq_get_affinity_mask(int irq)
702{
703 struct irq_data *d = irq_get_irq_data(irq);
704
Jiang Liu9df872f2015-06-03 11:47:50 +0800705 return d ? d->common->affinity : NULL;
Jiang Liuc64301a2015-06-01 16:05:23 +0800706}
707
708static inline struct cpumask *irq_data_get_affinity_mask(struct irq_data *d)
709{
Jiang Liu9df872f2015-06-03 11:47:50 +0800710 return d->common->affinity;
Jiang Liuc64301a2015-06-01 16:05:23 +0800711}
712
Thomas Gleixner62a08ae2014-04-24 09:50:53 +0200713unsigned int arch_dynirq_lower_bound(unsigned int from);
714
Sebastian Andrzej Siewiorb6873802011-07-11 12:17:31 +0200715int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node,
Thomas Gleixner06ee6d52016-07-04 17:39:24 +0900716 struct module *owner, const struct cpumask *affinity);
Sebastian Andrzej Siewiorb6873802011-07-11 12:17:31 +0200717
Paul Gortmakerec53cf22011-09-19 20:33:19 -0400718/* use macros to avoid needing export.h for THIS_MODULE */
719#define irq_alloc_descs(irq, from, cnt, node) \
Thomas Gleixner06ee6d52016-07-04 17:39:24 +0900720 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE, NULL)
Paul Gortmakerec53cf22011-09-19 20:33:19 -0400721
722#define irq_alloc_desc(node) \
723 irq_alloc_descs(-1, 0, 1, node)
724
725#define irq_alloc_desc_at(at, node) \
726 irq_alloc_descs(at, at, 1, node)
727
728#define irq_alloc_desc_from(from, node) \
729 irq_alloc_descs(-1, from, 1, node)
Sebastian Andrzej Siewiorb6873802011-07-11 12:17:31 +0200730
Alexander Gordeev51906e72012-11-19 16:01:29 +0100731#define irq_alloc_descs_from(from, cnt, node) \
732 irq_alloc_descs(-1, from, cnt, node)
733
Thomas Gleixner1f5a5b82010-09-27 17:48:26 +0200734void irq_free_descs(unsigned int irq, unsigned int cnt);
Thomas Gleixner1f5a5b82010-09-27 17:48:26 +0200735static inline void irq_free_desc(unsigned int irq)
736{
737 irq_free_descs(irq, 1);
738}
739
Thomas Gleixner7b6ef122014-05-07 15:44:05 +0000740#ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ
741unsigned int irq_alloc_hwirqs(int cnt, int node);
742static inline unsigned int irq_alloc_hwirq(int node)
743{
744 return irq_alloc_hwirqs(1, node);
745}
746void irq_free_hwirqs(unsigned int from, int cnt);
747static inline void irq_free_hwirq(unsigned int irq)
748{
749 return irq_free_hwirqs(irq, 1);
750}
751int arch_setup_hwirq(unsigned int irq, int node);
752void arch_teardown_hwirq(unsigned int irq);
753#endif
754
Thomas Gleixnerc940e012014-05-07 15:44:22 +0000755#ifdef CONFIG_GENERIC_IRQ_LEGACY
756void irq_init_desc(unsigned int irq);
757#endif
758
Thomas Gleixner7d828062011-04-03 11:42:53 +0200759/**
760 * struct irq_chip_regs - register offsets for struct irq_gci
761 * @enable: Enable register offset to reg_base
762 * @disable: Disable register offset to reg_base
763 * @mask: Mask register offset to reg_base
764 * @ack: Ack register offset to reg_base
765 * @eoi: Eoi register offset to reg_base
766 * @type: Type configuration register offset to reg_base
767 * @polarity: Polarity configuration register offset to reg_base
768 */
769struct irq_chip_regs {
770 unsigned long enable;
771 unsigned long disable;
772 unsigned long mask;
773 unsigned long ack;
774 unsigned long eoi;
775 unsigned long type;
776 unsigned long polarity;
777};
778
779/**
780 * struct irq_chip_type - Generic interrupt chip instance for a flow type
781 * @chip: The real interrupt chip which provides the callbacks
782 * @regs: Register offsets for this chip
783 * @handler: Flow handler associated with this chip
784 * @type: Chip can handle these flow types
Gerlando Falauto899f0e62013-05-06 14:30:19 +0000785 * @mask_cache_priv: Cached mask register private to the chip type
786 * @mask_cache: Pointer to cached mask register
Thomas Gleixner7d828062011-04-03 11:42:53 +0200787 *
788 * A irq_generic_chip can have several instances of irq_chip_type when
789 * it requires different functions and register offsets for different
790 * flow types.
791 */
792struct irq_chip_type {
793 struct irq_chip chip;
794 struct irq_chip_regs regs;
795 irq_flow_handler_t handler;
796 u32 type;
Gerlando Falauto899f0e62013-05-06 14:30:19 +0000797 u32 mask_cache_priv;
798 u32 *mask_cache;
Thomas Gleixner7d828062011-04-03 11:42:53 +0200799};
800
801/**
802 * struct irq_chip_generic - Generic irq chip data structure
803 * @lock: Lock to protect register and cache data access
804 * @reg_base: Register base address (virtual)
Kevin Cernekee2b280372014-11-06 22:44:18 -0800805 * @reg_readl: Alternate I/O accessor (defaults to readl if NULL)
806 * @reg_writel: Alternate I/O accessor (defaults to writel if NULL)
Brian Norrisbe9b22b2015-07-22 16:21:39 -0700807 * @suspend: Function called from core code on suspend once per
808 * chip; can be useful instead of irq_chip::suspend to
809 * handle chip details even when no interrupts are in use
810 * @resume: Function called from core code on resume once per chip;
811 * can be useful instead of irq_chip::suspend to handle
812 * chip details even when no interrupts are in use
Thomas Gleixner7d828062011-04-03 11:42:53 +0200813 * @irq_base: Interrupt base nr for this chip
814 * @irq_cnt: Number of interrupts handled by this chip
Gerlando Falauto899f0e62013-05-06 14:30:19 +0000815 * @mask_cache: Cached mask register shared between all chip types
Thomas Gleixner7d828062011-04-03 11:42:53 +0200816 * @type_cache: Cached type register
817 * @polarity_cache: Cached polarity register
818 * @wake_enabled: Interrupt can wakeup from suspend
819 * @wake_active: Interrupt is marked as an wakeup from suspend source
820 * @num_ct: Number of available irq_chip_type instances (usually 1)
821 * @private: Private data for non generic chip callbacks
Thomas Gleixner088f40b2013-05-06 14:30:27 +0000822 * @installed: bitfield to denote installed interrupts
Grant Likelye8bd8342013-05-29 03:10:52 +0100823 * @unused: bitfield to denote unused interrupts
Thomas Gleixner088f40b2013-05-06 14:30:27 +0000824 * @domain: irq domain pointer
Thomas Gleixnercfefd212011-04-15 22:36:08 +0200825 * @list: List head for keeping track of instances
Thomas Gleixner7d828062011-04-03 11:42:53 +0200826 * @chip_types: Array of interrupt irq_chip_types
827 *
828 * Note, that irq_chip_generic can have multiple irq_chip_type
829 * implementations which can be associated to a particular irq line of
830 * an irq_chip_generic instance. That allows to share and protect
831 * state in an irq_chip_generic instance when we need to implement
832 * different flow mechanisms (level/edge) for it.
833 */
834struct irq_chip_generic {
835 raw_spinlock_t lock;
836 void __iomem *reg_base;
Kevin Cernekee2b280372014-11-06 22:44:18 -0800837 u32 (*reg_readl)(void __iomem *addr);
838 void (*reg_writel)(u32 val, void __iomem *addr);
Brian Norrisbe9b22b2015-07-22 16:21:39 -0700839 void (*suspend)(struct irq_chip_generic *gc);
840 void (*resume)(struct irq_chip_generic *gc);
Thomas Gleixner7d828062011-04-03 11:42:53 +0200841 unsigned int irq_base;
842 unsigned int irq_cnt;
843 u32 mask_cache;
844 u32 type_cache;
845 u32 polarity_cache;
846 u32 wake_enabled;
847 u32 wake_active;
848 unsigned int num_ct;
849 void *private;
Thomas Gleixner088f40b2013-05-06 14:30:27 +0000850 unsigned long installed;
Grant Likelye8bd8342013-05-29 03:10:52 +0100851 unsigned long unused;
Thomas Gleixner088f40b2013-05-06 14:30:27 +0000852 struct irq_domain *domain;
Thomas Gleixnercfefd212011-04-15 22:36:08 +0200853 struct list_head list;
Thomas Gleixner7d828062011-04-03 11:42:53 +0200854 struct irq_chip_type chip_types[0];
855};
856
857/**
858 * enum irq_gc_flags - Initialization flags for generic irq chips
859 * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg
860 * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for
861 * irq chips which need to call irq_set_wake() on
862 * the parent irq. Usually GPIO implementations
Gerlando Falautoaf80b0f2013-05-06 14:30:21 +0000863 * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private
Thomas Gleixner966dc732013-05-06 14:30:22 +0000864 * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask
Kevin Cernekeeb7905592014-11-06 22:44:19 -0800865 * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE)
Thomas Gleixner7d828062011-04-03 11:42:53 +0200866 */
867enum irq_gc_flags {
868 IRQ_GC_INIT_MASK_CACHE = 1 << 0,
869 IRQ_GC_INIT_NESTED_LOCK = 1 << 1,
Gerlando Falautoaf80b0f2013-05-06 14:30:21 +0000870 IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2,
Thomas Gleixner966dc732013-05-06 14:30:22 +0000871 IRQ_GC_NO_MASK = 1 << 3,
Kevin Cernekeeb7905592014-11-06 22:44:19 -0800872 IRQ_GC_BE_IO = 1 << 4,
Thomas Gleixner7d828062011-04-03 11:42:53 +0200873};
874
Thomas Gleixner088f40b2013-05-06 14:30:27 +0000875/*
876 * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains
877 * @irqs_per_chip: Number of interrupts per chip
878 * @num_chips: Number of chips
879 * @irq_flags_to_set: IRQ* flags to set on irq setup
880 * @irq_flags_to_clear: IRQ* flags to clear on irq setup
881 * @gc_flags: Generic chip specific setup flags
882 * @gc: Array of pointers to generic interrupt chips
883 */
884struct irq_domain_chip_generic {
885 unsigned int irqs_per_chip;
886 unsigned int num_chips;
887 unsigned int irq_flags_to_clear;
888 unsigned int irq_flags_to_set;
889 enum irq_gc_flags gc_flags;
890 struct irq_chip_generic *gc[0];
891};
892
Thomas Gleixner7d828062011-04-03 11:42:53 +0200893/* Generic chip callback functions */
894void irq_gc_noop(struct irq_data *d);
895void irq_gc_mask_disable_reg(struct irq_data *d);
896void irq_gc_mask_set_bit(struct irq_data *d);
897void irq_gc_mask_clr_bit(struct irq_data *d);
898void irq_gc_unmask_enable_reg(struct irq_data *d);
Simon Guinot659fb322011-07-06 12:41:31 -0400899void irq_gc_ack_set_bit(struct irq_data *d);
900void irq_gc_ack_clr_bit(struct irq_data *d);
Thomas Gleixner7d828062011-04-03 11:42:53 +0200901void irq_gc_mask_disable_reg_and_ack(struct irq_data *d);
902void irq_gc_eoi(struct irq_data *d);
903int irq_gc_set_wake(struct irq_data *d, unsigned int on);
904
905/* Setup functions for irq_chip_generic */
Boris BREZILLONa5152c82014-07-10 19:14:16 +0200906int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
907 irq_hw_number_t hw_irq);
Thomas Gleixner7d828062011-04-03 11:42:53 +0200908struct irq_chip_generic *
909irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
910 void __iomem *reg_base, irq_flow_handler_t handler);
911void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
912 enum irq_gc_flags flags, unsigned int clr,
913 unsigned int set);
914int irq_setup_alt_chip(struct irq_data *d, unsigned int type);
Thomas Gleixnercfefd212011-04-15 22:36:08 +0200915void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
916 unsigned int clr, unsigned int set);
Thomas Gleixner7d828062011-04-03 11:42:53 +0200917
Thomas Gleixner088f40b2013-05-06 14:30:27 +0000918struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq);
919int irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
920 int num_ct, const char *name,
921 irq_flow_handler_t handler,
922 unsigned int clr, unsigned int set,
923 enum irq_gc_flags flags);
924
925
Thomas Gleixner7d828062011-04-03 11:42:53 +0200926static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d)
927{
928 return container_of(d->chip, struct irq_chip_type, chip);
929}
930
931#define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX)
932
933#ifdef CONFIG_SMP
934static inline void irq_gc_lock(struct irq_chip_generic *gc)
935{
936 raw_spin_lock(&gc->lock);
937}
938
939static inline void irq_gc_unlock(struct irq_chip_generic *gc)
940{
941 raw_spin_unlock(&gc->lock);
942}
943#else
944static inline void irq_gc_lock(struct irq_chip_generic *gc) { }
945static inline void irq_gc_unlock(struct irq_chip_generic *gc) { }
946#endif
947
Kevin Cernekee332fd7c2014-11-06 22:44:17 -0800948static inline void irq_reg_writel(struct irq_chip_generic *gc,
949 u32 val, int reg_offset)
950{
Kevin Cernekee2b280372014-11-06 22:44:18 -0800951 if (gc->reg_writel)
952 gc->reg_writel(val, gc->reg_base + reg_offset);
953 else
954 writel(val, gc->reg_base + reg_offset);
Kevin Cernekee332fd7c2014-11-06 22:44:17 -0800955}
956
957static inline u32 irq_reg_readl(struct irq_chip_generic *gc,
958 int reg_offset)
959{
Kevin Cernekee2b280372014-11-06 22:44:18 -0800960 if (gc->reg_readl)
961 return gc->reg_readl(gc->reg_base + reg_offset);
962 else
963 return readl(gc->reg_base + reg_offset);
Kevin Cernekee332fd7c2014-11-06 22:44:17 -0800964}
965
Qais Yousefd17bf242015-12-08 13:20:19 +0000966/* Contrary to Linux irqs, for hardware irqs the irq number 0 is valid */
967#define INVALID_HWIRQ (~0UL)
Qais Youseff9bce792015-12-08 13:20:20 +0000968irq_hw_number_t ipi_get_hwirq(unsigned int irq, unsigned int cpu);
Qais Yousef3b8e29a2015-12-08 13:20:22 +0000969int __ipi_send_single(struct irq_desc *desc, unsigned int cpu);
970int __ipi_send_mask(struct irq_desc *desc, const struct cpumask *dest);
971int ipi_send_single(unsigned int virq, unsigned int cpu);
972int ipi_send_mask(unsigned int virq, const struct cpumask *dest);
Qais Yousefd17bf242015-12-08 13:20:19 +0000973
Ingo Molnar06fcb0c2006-06-29 02:24:40 -0700974#endif /* _LINUX_IRQ_H */