Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* $Id: pbm.h,v 1.27 2001/08/12 13:18:23 davem Exp $ |
| 2 | * pbm.h: UltraSparc PCI controller software state. |
| 3 | * |
| 4 | * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com) |
| 5 | */ |
| 6 | |
| 7 | #ifndef __SPARC64_PBM_H |
| 8 | #define __SPARC64_PBM_H |
| 9 | |
| 10 | #include <linux/types.h> |
| 11 | #include <linux/pci.h> |
| 12 | #include <linux/ioport.h> |
| 13 | #include <linux/spinlock.h> |
David S. Miller | 35a17eb | 2007-02-10 17:41:02 -0800 | [diff] [blame] | 14 | #include <linux/msi.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15 | |
| 16 | #include <asm/io.h> |
| 17 | #include <asm/page.h> |
| 18 | #include <asm/oplib.h> |
David S. Miller | e87dc35 | 2006-06-21 18:18:47 -0700 | [diff] [blame] | 19 | #include <asm/prom.h> |
David S. Miller | 2b1e597 | 2006-06-29 15:07:37 -0700 | [diff] [blame] | 20 | #include <asm/of_device.h> |
David S. Miller | 7c963ad | 2005-05-31 16:57:59 -0700 | [diff] [blame] | 21 | #include <asm/iommu.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 22 | |
| 23 | /* The abstraction used here is that there are PCI controllers, |
| 24 | * each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules |
| 25 | * underneath. Each PCI bus module uses an IOMMU (shared by both |
| 26 | * PBMs of a controller, or per-PBM), and if a streaming buffer |
| 27 | * is present, each PCI bus module has it's own. (ie. the IOMMU |
| 28 | * might be shared between PBMs, the STC is never shared) |
| 29 | * Furthermore, each PCI bus module controls it's own autonomous |
| 30 | * PCI bus. |
| 31 | */ |
| 32 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 33 | struct pci_controller_info; |
| 34 | |
| 35 | /* This contains the software state necessary to drive a PCI |
| 36 | * controller's IOMMU. |
| 37 | */ |
David S. Miller | 688cb30 | 2005-10-13 22:15:24 -0700 | [diff] [blame] | 38 | struct pci_iommu_arena { |
| 39 | unsigned long *map; |
| 40 | unsigned int hint; |
| 41 | unsigned int limit; |
| 42 | }; |
| 43 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 44 | struct pci_iommu { |
| 45 | /* This protects the controller's IOMMU and all |
| 46 | * streaming buffers underneath. |
| 47 | */ |
| 48 | spinlock_t lock; |
| 49 | |
David S. Miller | 688cb30 | 2005-10-13 22:15:24 -0700 | [diff] [blame] | 50 | struct pci_iommu_arena arena; |
| 51 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 52 | /* IOMMU page table, a linear array of ioptes. */ |
| 53 | iopte_t *page_table; /* The page table itself. */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 54 | |
| 55 | /* Base PCI memory space address where IOMMU mappings |
| 56 | * begin. |
| 57 | */ |
| 58 | u32 page_table_map_base; |
| 59 | |
| 60 | /* IOMMU Controller Registers */ |
| 61 | unsigned long iommu_control; /* IOMMU control register */ |
| 62 | unsigned long iommu_tsbbase; /* IOMMU page table base register */ |
| 63 | unsigned long iommu_flush; /* IOMMU page flush register */ |
| 64 | unsigned long iommu_ctxflush; /* IOMMU context flush register */ |
| 65 | |
| 66 | /* This is a register in the PCI controller, which if |
| 67 | * read will have no side-effects but will guarantee |
| 68 | * completion of all previous writes into IOMMU/STC. |
| 69 | */ |
| 70 | unsigned long write_complete_reg; |
| 71 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 72 | /* In order to deal with some buggy third-party PCI bridges that |
| 73 | * do wrong prefetching, we never mark valid mappings as invalid. |
| 74 | * Instead we point them at this dummy page. |
| 75 | */ |
| 76 | unsigned long dummy_page; |
| 77 | unsigned long dummy_page_pa; |
| 78 | |
David S. Miller | 7c963ad | 2005-05-31 16:57:59 -0700 | [diff] [blame] | 79 | /* CTX allocation. */ |
| 80 | unsigned long ctx_lowest_free; |
| 81 | unsigned long ctx_bitmap[IOMMU_NUM_CTXS / (sizeof(unsigned long) * 8)]; |
| 82 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 83 | /* Here a PCI controller driver describes the areas of |
| 84 | * PCI memory space where DMA to/from physical memory |
| 85 | * are addressed. Drivers interrogate the PCI layer |
| 86 | * if their device has addressing limitations. They |
| 87 | * do so via pci_dma_supported, and pass in a mask of |
| 88 | * DMA address bits their device can actually drive. |
| 89 | * |
| 90 | * The test for being usable is: |
| 91 | * (device_mask & dma_addr_mask) == dma_addr_mask |
| 92 | */ |
| 93 | u32 dma_addr_mask; |
| 94 | }; |
| 95 | |
David S. Miller | 51e8513 | 2005-10-13 21:10:08 -0700 | [diff] [blame] | 96 | extern void pci_iommu_table_init(struct pci_iommu *iommu, int tsbsize, u32 dma_offset, u32 dma_addr_mask); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 97 | |
| 98 | /* This describes a PCI bus module's streaming buffer. */ |
| 99 | struct pci_strbuf { |
| 100 | int strbuf_enabled; /* Present and using it? */ |
| 101 | |
| 102 | /* Streaming Buffer Control Registers */ |
| 103 | unsigned long strbuf_control; /* STC control register */ |
| 104 | unsigned long strbuf_pflush; /* STC page flush register */ |
| 105 | unsigned long strbuf_fsync; /* STC flush synchronization reg */ |
| 106 | unsigned long strbuf_ctxflush; /* STC context flush register */ |
| 107 | unsigned long strbuf_ctxmatch_base; /* STC context flush match reg */ |
| 108 | unsigned long strbuf_flushflag_pa; /* Physical address of flush flag */ |
| 109 | volatile unsigned long *strbuf_flushflag; /* The flush flag itself */ |
| 110 | |
| 111 | /* And this is the actual flush flag area. |
| 112 | * We allocate extra because the chips require |
| 113 | * a 64-byte aligned area. |
| 114 | */ |
| 115 | volatile unsigned long __flushflag_buf[(64 + (64 - 1)) / sizeof(long)]; |
| 116 | }; |
| 117 | |
| 118 | #define PCI_STC_FLUSHFLAG_INIT(STC) \ |
| 119 | (*((STC)->strbuf_flushflag) = 0UL) |
| 120 | #define PCI_STC_FLUSHFLAG_SET(STC) \ |
| 121 | (*((STC)->strbuf_flushflag) != 0UL) |
| 122 | |
| 123 | /* There can be quite a few ranges and interrupt maps on a PCI |
| 124 | * segment. Thus... |
| 125 | */ |
| 126 | #define PROM_PCIRNG_MAX 64 |
| 127 | #define PROM_PCIIMAP_MAX 64 |
| 128 | |
| 129 | struct pci_pbm_info { |
| 130 | /* PCI controller we sit under. */ |
| 131 | struct pci_controller_info *parent; |
| 132 | |
| 133 | /* Physical address base of controller registers. */ |
| 134 | unsigned long controller_regs; |
| 135 | |
| 136 | /* Physical address base of PBM registers. */ |
| 137 | unsigned long pbm_regs; |
| 138 | |
David S. Miller | bb6743f4 | 2005-07-04 13:26:04 -0700 | [diff] [blame] | 139 | /* Physical address of DMA sync register, if any. */ |
| 140 | unsigned long sync_reg; |
| 141 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 142 | /* Opaque 32-bit system bus Port ID. */ |
| 143 | u32 portid; |
| 144 | |
David S. Miller | bade562 | 2006-02-09 22:05:54 -0800 | [diff] [blame] | 145 | /* Opaque 32-bit handle used for hypervisor calls. */ |
| 146 | u32 devhandle; |
| 147 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 148 | /* Chipset version information. */ |
| 149 | int chip_type; |
| 150 | #define PBM_CHIP_TYPE_SABRE 1 |
| 151 | #define PBM_CHIP_TYPE_PSYCHO 2 |
| 152 | #define PBM_CHIP_TYPE_SCHIZO 3 |
| 153 | #define PBM_CHIP_TYPE_SCHIZO_PLUS 4 |
| 154 | #define PBM_CHIP_TYPE_TOMATILLO 5 |
| 155 | int chip_version; |
| 156 | int chip_revision; |
| 157 | |
| 158 | /* Name used for top-level resources. */ |
David S. Miller | e87dc35 | 2006-06-21 18:18:47 -0700 | [diff] [blame] | 159 | char *name; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 160 | |
| 161 | /* OBP specific information. */ |
David S. Miller | e87dc35 | 2006-06-21 18:18:47 -0700 | [diff] [blame] | 162 | struct device_node *prom_node; |
| 163 | struct linux_prom_pci_ranges *pbm_ranges; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 164 | int num_pbm_ranges; |
David S. Miller | e87dc35 | 2006-06-21 18:18:47 -0700 | [diff] [blame] | 165 | struct linux_prom_pci_intmap *pbm_intmap; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 166 | int num_pbm_intmap; |
David S. Miller | e87dc35 | 2006-06-21 18:18:47 -0700 | [diff] [blame] | 167 | struct linux_prom_pci_intmask *pbm_intmask; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 168 | u64 ino_bitmap; |
| 169 | |
| 170 | /* PBM I/O and Memory space resources. */ |
| 171 | struct resource io_space; |
| 172 | struct resource mem_space; |
| 173 | |
| 174 | /* Base of PCI Config space, can be per-PBM or shared. */ |
| 175 | unsigned long config_space; |
| 176 | |
| 177 | /* State of 66MHz capabilities on this PBM. */ |
| 178 | int is_66mhz_capable; |
| 179 | int all_devs_66mhz; |
| 180 | |
David S. Miller | 35a17eb | 2007-02-10 17:41:02 -0800 | [diff] [blame] | 181 | #ifdef CONFIG_PCI_MSI |
| 182 | /* MSI info. */ |
| 183 | u32 msiq_num; |
| 184 | u32 msiq_ent_count; |
| 185 | u32 msiq_first; |
| 186 | u32 msiq_first_devino; |
| 187 | u32 msi_num; |
| 188 | u32 msi_first; |
| 189 | u32 msi_data_mask; |
| 190 | u32 msix_data_width; |
| 191 | u64 msi32_start; |
| 192 | u64 msi64_start; |
| 193 | u32 msi32_len; |
| 194 | u32 msi64_len; |
| 195 | void *msi_queues; |
| 196 | unsigned long *msi_bitmap; |
| 197 | #endif /* !(CONFIG_PCI_MSI) */ |
| 198 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 199 | /* This PBM's streaming buffer. */ |
| 200 | struct pci_strbuf stc; |
| 201 | |
| 202 | /* IOMMU state, potentially shared by both PBM segments. */ |
| 203 | struct pci_iommu *iommu; |
| 204 | |
| 205 | /* PCI slot mapping. */ |
| 206 | unsigned int pci_first_slot; |
| 207 | |
| 208 | /* Now things for the actual PCI bus probes. */ |
| 209 | unsigned int pci_first_busno; |
| 210 | unsigned int pci_last_busno; |
| 211 | struct pci_bus *pci_bus; |
| 212 | }; |
| 213 | |
| 214 | struct pci_controller_info { |
| 215 | /* List of all PCI controllers. */ |
| 216 | struct pci_controller_info *next; |
| 217 | |
| 218 | /* Each controller gets a unique index, used mostly for |
| 219 | * error logging purposes. |
| 220 | */ |
| 221 | int index; |
| 222 | |
| 223 | /* Do the PBMs both exist in the same PCI domain? */ |
| 224 | int pbms_same_domain; |
| 225 | |
| 226 | /* The PCI bus modules controlled by us. */ |
| 227 | struct pci_pbm_info pbm_A; |
| 228 | struct pci_pbm_info pbm_B; |
| 229 | |
| 230 | /* Operations which are controller specific. */ |
| 231 | void (*scan_bus)(struct pci_controller_info *); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 232 | void (*base_address_update)(struct pci_dev *, int); |
| 233 | void (*resource_adjust)(struct pci_dev *, struct resource *, struct resource *); |
| 234 | |
David S. Miller | 35a17eb | 2007-02-10 17:41:02 -0800 | [diff] [blame] | 235 | #ifdef CONFIG_PCI_MSI |
| 236 | int (*setup_msi_irq)(unsigned int *virt_irq_p, struct pci_dev *pdev, |
| 237 | struct msi_desc *entry); |
| 238 | void (*teardown_msi_irq)(unsigned int virt_irq, struct pci_dev *pdev); |
| 239 | #endif |
| 240 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 241 | /* Now things for the actual PCI bus probes. */ |
| 242 | struct pci_ops *pci_ops; |
| 243 | unsigned int pci_first_busno; |
| 244 | unsigned int pci_last_busno; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 245 | }; |
| 246 | |
| 247 | /* PCI devices which are not bridges have this placed in their pci_dev |
| 248 | * sysdata member. This makes OBP aware PCI device drivers easier to |
| 249 | * code. |
| 250 | */ |
| 251 | struct pcidev_cookie { |
| 252 | struct pci_pbm_info *pbm; |
David S. Miller | de8d28b | 2006-06-22 16:18:54 -0700 | [diff] [blame] | 253 | struct device_node *prom_node; |
David S. Miller | 2b1e597 | 2006-06-29 15:07:37 -0700 | [diff] [blame] | 254 | struct of_device *op; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 255 | struct linux_prom_pci_registers prom_regs[PROMREG_MAX]; |
| 256 | int num_prom_regs; |
| 257 | struct linux_prom_pci_registers prom_assignments[PROMREG_MAX]; |
| 258 | int num_prom_assignments; |
David S. Miller | 35a17eb | 2007-02-10 17:41:02 -0800 | [diff] [blame] | 259 | #ifdef CONFIG_PCI_MSI |
| 260 | unsigned int msi_num; |
| 261 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 262 | }; |
| 263 | |
| 264 | /* Currently these are the same across all PCI controllers |
| 265 | * we support. Someday they may not be... |
| 266 | */ |
| 267 | #define PCI_IRQ_IGN 0x000007c0 /* Interrupt Group Number */ |
| 268 | #define PCI_IRQ_INO 0x0000003f /* Interrupt Number */ |
| 269 | |
| 270 | #endif /* !(__SPARC64_PBM_H) */ |