Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1 | /* |
Daniel Vetter | be6a037 | 2015-03-18 10:46:04 +0100 | [diff] [blame] | 2 | * Copyright © 2008-2015 Intel Corporation |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * |
| 26 | */ |
| 27 | |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 28 | #include <drm/drmP.h> |
David Herrmann | 0de2397 | 2013-07-24 21:07:52 +0200 | [diff] [blame] | 29 | #include <drm/drm_vma_manager.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 30 | #include <drm/i915_drm.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 31 | #include "i915_drv.h" |
Yu Zhang | eb82289 | 2015-02-10 19:05:49 +0800 | [diff] [blame] | 32 | #include "i915_vgpu.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 33 | #include "i915_trace.h" |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 34 | #include "intel_drv.h" |
Peter Antoine | 0ccdacf | 2016-04-13 15:03:25 +0100 | [diff] [blame] | 35 | #include "intel_mocs.h" |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 36 | #include <linux/shmem_fs.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 37 | #include <linux/slab.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 38 | #include <linux/swap.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 39 | #include <linux/pci.h> |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 40 | #include <linux/dma-buf.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 41 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 42 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
Daniel Vetter | e62b59e | 2015-01-21 14:53:48 +0100 | [diff] [blame] | 43 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); |
Chris Wilson | c8725f3 | 2014-03-17 12:21:55 +0000 | [diff] [blame] | 44 | static void |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 45 | i915_gem_object_retire__write(struct drm_i915_gem_object *obj); |
| 46 | static void |
| 47 | i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring); |
Chris Wilson | 6105080 | 2012-04-17 15:31:31 +0100 | [diff] [blame] | 48 | |
Chris Wilson | c76ce03 | 2013-08-08 14:41:03 +0100 | [diff] [blame] | 49 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
| 50 | enum i915_cache_level level) |
| 51 | { |
| 52 | return HAS_LLC(dev) || level != I915_CACHE_NONE; |
| 53 | } |
| 54 | |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 55 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
| 56 | { |
| 57 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
| 58 | return true; |
| 59 | |
| 60 | return obj->pin_display; |
| 61 | } |
| 62 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 63 | /* some bookkeeping */ |
| 64 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, |
| 65 | size_t size) |
| 66 | { |
Daniel Vetter | c20e835 | 2013-07-24 22:40:23 +0200 | [diff] [blame] | 67 | spin_lock(&dev_priv->mm.object_stat_lock); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 68 | dev_priv->mm.object_count++; |
| 69 | dev_priv->mm.object_memory += size; |
Daniel Vetter | c20e835 | 2013-07-24 22:40:23 +0200 | [diff] [blame] | 70 | spin_unlock(&dev_priv->mm.object_stat_lock); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 71 | } |
| 72 | |
| 73 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, |
| 74 | size_t size) |
| 75 | { |
Daniel Vetter | c20e835 | 2013-07-24 22:40:23 +0200 | [diff] [blame] | 76 | spin_lock(&dev_priv->mm.object_stat_lock); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 77 | dev_priv->mm.object_count--; |
| 78 | dev_priv->mm.object_memory -= size; |
Daniel Vetter | c20e835 | 2013-07-24 22:40:23 +0200 | [diff] [blame] | 79 | spin_unlock(&dev_priv->mm.object_stat_lock); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 80 | } |
| 81 | |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 82 | static int |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 83 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 84 | { |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 85 | int ret; |
| 86 | |
Chris Wilson | d98c52c | 2016-04-13 17:35:05 +0100 | [diff] [blame] | 87 | if (!i915_reset_in_progress(error)) |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 88 | return 0; |
| 89 | |
Daniel Vetter | 0a6759c | 2012-07-04 22:18:41 +0200 | [diff] [blame] | 90 | /* |
| 91 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging |
| 92 | * userspace. If it takes that long something really bad is going on and |
| 93 | * we should simply try to bail out and fail as gracefully as possible. |
| 94 | */ |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 95 | ret = wait_event_interruptible_timeout(error->reset_queue, |
Chris Wilson | d98c52c | 2016-04-13 17:35:05 +0100 | [diff] [blame] | 96 | !i915_reset_in_progress(error), |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 97 | 10*HZ); |
Daniel Vetter | 0a6759c | 2012-07-04 22:18:41 +0200 | [diff] [blame] | 98 | if (ret == 0) { |
| 99 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); |
| 100 | return -EIO; |
| 101 | } else if (ret < 0) { |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 102 | return ret; |
Chris Wilson | d98c52c | 2016-04-13 17:35:05 +0100 | [diff] [blame] | 103 | } else { |
| 104 | return 0; |
Daniel Vetter | 0a6759c | 2012-07-04 22:18:41 +0200 | [diff] [blame] | 105 | } |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 106 | } |
| 107 | |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 108 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 109 | { |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 110 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 111 | int ret; |
| 112 | |
Daniel Vetter | 33196de | 2012-11-14 17:14:05 +0100 | [diff] [blame] | 113 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 114 | if (ret) |
| 115 | return ret; |
| 116 | |
| 117 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 118 | if (ret) |
| 119 | return ret; |
| 120 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 121 | WARN_ON(i915_verify_lists(dev)); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 122 | return 0; |
| 123 | } |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 124 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 125 | int |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 126 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 127 | struct drm_file *file) |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 128 | { |
Joonas Lahtinen | 72e96d6 | 2016-03-30 16:57:10 +0300 | [diff] [blame] | 129 | struct drm_i915_private *dev_priv = to_i915(dev); |
Joonas Lahtinen | 62106b4 | 2016-03-18 10:42:57 +0200 | [diff] [blame] | 130 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
Joonas Lahtinen | 72e96d6 | 2016-03-30 16:57:10 +0300 | [diff] [blame] | 131 | struct drm_i915_gem_get_aperture *args = data; |
Tvrtko Ursulin | ca1543b | 2015-07-01 11:51:10 +0100 | [diff] [blame] | 132 | struct i915_vma *vma; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 133 | size_t pinned; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 134 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 135 | pinned = 0; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 136 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 137 | list_for_each_entry(vma, &ggtt->base.active_list, vm_link) |
Tvrtko Ursulin | ca1543b | 2015-07-01 11:51:10 +0100 | [diff] [blame] | 138 | if (vma->pin_count) |
| 139 | pinned += vma->node.size; |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 140 | list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link) |
Tvrtko Ursulin | ca1543b | 2015-07-01 11:51:10 +0100 | [diff] [blame] | 141 | if (vma->pin_count) |
| 142 | pinned += vma->node.size; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 143 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 144 | |
Joonas Lahtinen | 72e96d6 | 2016-03-30 16:57:10 +0300 | [diff] [blame] | 145 | args->aper_size = ggtt->base.total; |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 146 | args->aper_available_size = args->aper_size - pinned; |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 147 | |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 148 | return 0; |
| 149 | } |
| 150 | |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 151 | static int |
| 152 | i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 153 | { |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 154 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
| 155 | char *vaddr = obj->phys_handle->vaddr; |
| 156 | struct sg_table *st; |
| 157 | struct scatterlist *sg; |
| 158 | int i; |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 159 | |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 160 | if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj))) |
| 161 | return -EINVAL; |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 162 | |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 163 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { |
| 164 | struct page *page; |
| 165 | char *src; |
| 166 | |
| 167 | page = shmem_read_mapping_page(mapping, i); |
| 168 | if (IS_ERR(page)) |
| 169 | return PTR_ERR(page); |
| 170 | |
| 171 | src = kmap_atomic(page); |
| 172 | memcpy(vaddr, src, PAGE_SIZE); |
| 173 | drm_clflush_virt_range(vaddr, PAGE_SIZE); |
| 174 | kunmap_atomic(src); |
| 175 | |
Kirill A. Shutemov | 09cbfea | 2016-04-01 15:29:47 +0300 | [diff] [blame] | 176 | put_page(page); |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 177 | vaddr += PAGE_SIZE; |
| 178 | } |
| 179 | |
| 180 | i915_gem_chipset_flush(obj->base.dev); |
| 181 | |
| 182 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
| 183 | if (st == NULL) |
| 184 | return -ENOMEM; |
| 185 | |
| 186 | if (sg_alloc_table(st, 1, GFP_KERNEL)) { |
| 187 | kfree(st); |
| 188 | return -ENOMEM; |
| 189 | } |
| 190 | |
| 191 | sg = st->sgl; |
| 192 | sg->offset = 0; |
| 193 | sg->length = obj->base.size; |
| 194 | |
| 195 | sg_dma_address(sg) = obj->phys_handle->busaddr; |
| 196 | sg_dma_len(sg) = obj->base.size; |
| 197 | |
| 198 | obj->pages = st; |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 199 | return 0; |
| 200 | } |
| 201 | |
| 202 | static void |
| 203 | i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj) |
| 204 | { |
| 205 | int ret; |
| 206 | |
| 207 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
| 208 | |
| 209 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
Chris Wilson | f4457ae | 2016-04-13 17:35:08 +0100 | [diff] [blame] | 210 | if (WARN_ON(ret)) { |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 211 | /* In the event of a disaster, abandon all caches and |
| 212 | * hope for the best. |
| 213 | */ |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 214 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 215 | } |
| 216 | |
| 217 | if (obj->madv == I915_MADV_DONTNEED) |
| 218 | obj->dirty = 0; |
| 219 | |
| 220 | if (obj->dirty) { |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 221 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 222 | char *vaddr = obj->phys_handle->vaddr; |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 223 | int i; |
| 224 | |
| 225 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 226 | struct page *page; |
| 227 | char *dst; |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 228 | |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 229 | page = shmem_read_mapping_page(mapping, i); |
| 230 | if (IS_ERR(page)) |
| 231 | continue; |
| 232 | |
| 233 | dst = kmap_atomic(page); |
| 234 | drm_clflush_virt_range(vaddr, PAGE_SIZE); |
| 235 | memcpy(dst, vaddr, PAGE_SIZE); |
| 236 | kunmap_atomic(dst); |
| 237 | |
| 238 | set_page_dirty(page); |
| 239 | if (obj->madv == I915_MADV_WILLNEED) |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 240 | mark_page_accessed(page); |
Kirill A. Shutemov | 09cbfea | 2016-04-01 15:29:47 +0300 | [diff] [blame] | 241 | put_page(page); |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 242 | vaddr += PAGE_SIZE; |
| 243 | } |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 244 | obj->dirty = 0; |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 245 | } |
| 246 | |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 247 | sg_free_table(obj->pages); |
| 248 | kfree(obj->pages); |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 249 | } |
| 250 | |
| 251 | static void |
| 252 | i915_gem_object_release_phys(struct drm_i915_gem_object *obj) |
| 253 | { |
| 254 | drm_pci_free(obj->base.dev, obj->phys_handle); |
| 255 | } |
| 256 | |
| 257 | static const struct drm_i915_gem_object_ops i915_gem_phys_ops = { |
| 258 | .get_pages = i915_gem_object_get_pages_phys, |
| 259 | .put_pages = i915_gem_object_put_pages_phys, |
| 260 | .release = i915_gem_object_release_phys, |
| 261 | }; |
| 262 | |
| 263 | static int |
| 264 | drop_pages(struct drm_i915_gem_object *obj) |
| 265 | { |
| 266 | struct i915_vma *vma, *next; |
| 267 | int ret; |
| 268 | |
| 269 | drm_gem_object_reference(&obj->base); |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 270 | list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 271 | if (i915_vma_unbind(vma)) |
| 272 | break; |
| 273 | |
| 274 | ret = i915_gem_object_put_pages(obj); |
| 275 | drm_gem_object_unreference(&obj->base); |
| 276 | |
| 277 | return ret; |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 278 | } |
| 279 | |
| 280 | int |
| 281 | i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, |
| 282 | int align) |
| 283 | { |
| 284 | drm_dma_handle_t *phys; |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 285 | int ret; |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 286 | |
| 287 | if (obj->phys_handle) { |
| 288 | if ((unsigned long)obj->phys_handle->vaddr & (align -1)) |
| 289 | return -EBUSY; |
| 290 | |
| 291 | return 0; |
| 292 | } |
| 293 | |
| 294 | if (obj->madv != I915_MADV_WILLNEED) |
| 295 | return -EFAULT; |
| 296 | |
| 297 | if (obj->base.filp == NULL) |
| 298 | return -EINVAL; |
| 299 | |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 300 | ret = drop_pages(obj); |
| 301 | if (ret) |
| 302 | return ret; |
| 303 | |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 304 | /* create a new object */ |
| 305 | phys = drm_pci_alloc(obj->base.dev, obj->base.size, align); |
| 306 | if (!phys) |
| 307 | return -ENOMEM; |
| 308 | |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 309 | obj->phys_handle = phys; |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 310 | obj->ops = &i915_gem_phys_ops; |
| 311 | |
| 312 | return i915_gem_object_get_pages(obj); |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 313 | } |
| 314 | |
| 315 | static int |
| 316 | i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, |
| 317 | struct drm_i915_gem_pwrite *args, |
| 318 | struct drm_file *file_priv) |
| 319 | { |
| 320 | struct drm_device *dev = obj->base.dev; |
| 321 | void *vaddr = obj->phys_handle->vaddr + args->offset; |
| 322 | char __user *user_data = to_user_ptr(args->data_ptr); |
Paulo Zanoni | 063e4e6 | 2015-02-13 17:23:45 -0200 | [diff] [blame] | 323 | int ret = 0; |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 324 | |
| 325 | /* We manually control the domain here and pretend that it |
| 326 | * remains coherent i.e. in the GTT domain, like shmem_pwrite. |
| 327 | */ |
| 328 | ret = i915_gem_object_wait_rendering(obj, false); |
| 329 | if (ret) |
| 330 | return ret; |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 331 | |
Rodrigo Vivi | 77a0d1c | 2015-06-18 11:43:24 -0700 | [diff] [blame] | 332 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 333 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
| 334 | unsigned long unwritten; |
| 335 | |
| 336 | /* The physical object once assigned is fixed for the lifetime |
| 337 | * of the obj, so we can safely drop the lock and continue |
| 338 | * to access vaddr. |
| 339 | */ |
| 340 | mutex_unlock(&dev->struct_mutex); |
| 341 | unwritten = copy_from_user(vaddr, user_data, args->size); |
| 342 | mutex_lock(&dev->struct_mutex); |
Paulo Zanoni | 063e4e6 | 2015-02-13 17:23:45 -0200 | [diff] [blame] | 343 | if (unwritten) { |
| 344 | ret = -EFAULT; |
| 345 | goto out; |
| 346 | } |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 347 | } |
| 348 | |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 349 | drm_clflush_virt_range(vaddr, args->size); |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 350 | i915_gem_chipset_flush(dev); |
Paulo Zanoni | 063e4e6 | 2015-02-13 17:23:45 -0200 | [diff] [blame] | 351 | |
| 352 | out: |
Rodrigo Vivi | de152b6 | 2015-07-07 16:28:51 -0700 | [diff] [blame] | 353 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
Paulo Zanoni | 063e4e6 | 2015-02-13 17:23:45 -0200 | [diff] [blame] | 354 | return ret; |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 355 | } |
| 356 | |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 357 | void *i915_gem_object_alloc(struct drm_device *dev) |
| 358 | { |
| 359 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | efab6d8 | 2015-04-07 16:20:57 +0100 | [diff] [blame] | 360 | return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL); |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 361 | } |
| 362 | |
| 363 | void i915_gem_object_free(struct drm_i915_gem_object *obj) |
| 364 | { |
| 365 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Chris Wilson | efab6d8 | 2015-04-07 16:20:57 +0100 | [diff] [blame] | 366 | kmem_cache_free(dev_priv->objects, obj); |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 367 | } |
| 368 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 369 | static int |
| 370 | i915_gem_create(struct drm_file *file, |
| 371 | struct drm_device *dev, |
| 372 | uint64_t size, |
| 373 | uint32_t *handle_p) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 374 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 375 | struct drm_i915_gem_object *obj; |
Pekka Paalanen | a1a2d1d | 2009-08-23 12:40:55 +0300 | [diff] [blame] | 376 | int ret; |
| 377 | u32 handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 378 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 379 | size = roundup(size, PAGE_SIZE); |
Chris Wilson | 8ffc024 | 2011-09-14 14:14:28 +0200 | [diff] [blame] | 380 | if (size == 0) |
| 381 | return -EINVAL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 382 | |
| 383 | /* Allocate the new object */ |
Dave Gordon | d37cd8a | 2016-04-22 19:14:32 +0100 | [diff] [blame] | 384 | obj = i915_gem_object_create(dev, size); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 385 | if (obj == NULL) |
| 386 | return -ENOMEM; |
| 387 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 388 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 389 | /* drop reference from allocate - handle holds it now */ |
Daniel Vetter | d861e33 | 2013-07-24 23:25:03 +0200 | [diff] [blame] | 390 | drm_gem_object_unreference_unlocked(&obj->base); |
| 391 | if (ret) |
| 392 | return ret; |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 393 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 394 | *handle_p = handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 395 | return 0; |
| 396 | } |
| 397 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 398 | int |
| 399 | i915_gem_dumb_create(struct drm_file *file, |
| 400 | struct drm_device *dev, |
| 401 | struct drm_mode_create_dumb *args) |
| 402 | { |
| 403 | /* have to work out size/pitch and return them */ |
Paulo Zanoni | de45eaf | 2013-10-18 18:48:24 -0300 | [diff] [blame] | 404 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 405 | args->size = args->pitch * args->height; |
| 406 | return i915_gem_create(file, dev, |
Dave Airlie | da6b51d | 2014-12-24 13:11:17 +1000 | [diff] [blame] | 407 | args->size, &args->handle); |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 408 | } |
| 409 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 410 | /** |
| 411 | * Creates a new mm object and returns a handle to it. |
| 412 | */ |
| 413 | int |
| 414 | i915_gem_create_ioctl(struct drm_device *dev, void *data, |
| 415 | struct drm_file *file) |
| 416 | { |
| 417 | struct drm_i915_gem_create *args = data; |
Daniel Vetter | 63ed2cb | 2012-04-23 16:50:50 +0200 | [diff] [blame] | 418 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 419 | return i915_gem_create(file, dev, |
Dave Airlie | da6b51d | 2014-12-24 13:11:17 +1000 | [diff] [blame] | 420 | args->size, &args->handle); |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 421 | } |
| 422 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 423 | static inline int |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 424 | __copy_to_user_swizzled(char __user *cpu_vaddr, |
| 425 | const char *gpu_vaddr, int gpu_offset, |
| 426 | int length) |
| 427 | { |
| 428 | int ret, cpu_offset = 0; |
| 429 | |
| 430 | while (length > 0) { |
| 431 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 432 | int this_length = min(cacheline_end - gpu_offset, length); |
| 433 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 434 | |
| 435 | ret = __copy_to_user(cpu_vaddr + cpu_offset, |
| 436 | gpu_vaddr + swizzled_gpu_offset, |
| 437 | this_length); |
| 438 | if (ret) |
| 439 | return ret + length; |
| 440 | |
| 441 | cpu_offset += this_length; |
| 442 | gpu_offset += this_length; |
| 443 | length -= this_length; |
| 444 | } |
| 445 | |
| 446 | return 0; |
| 447 | } |
| 448 | |
| 449 | static inline int |
Ben Widawsky | 4f0c7cf | 2012-04-16 14:07:47 -0700 | [diff] [blame] | 450 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
| 451 | const char __user *cpu_vaddr, |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 452 | int length) |
| 453 | { |
| 454 | int ret, cpu_offset = 0; |
| 455 | |
| 456 | while (length > 0) { |
| 457 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 458 | int this_length = min(cacheline_end - gpu_offset, length); |
| 459 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 460 | |
| 461 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, |
| 462 | cpu_vaddr + cpu_offset, |
| 463 | this_length); |
| 464 | if (ret) |
| 465 | return ret + length; |
| 466 | |
| 467 | cpu_offset += this_length; |
| 468 | gpu_offset += this_length; |
| 469 | length -= this_length; |
| 470 | } |
| 471 | |
| 472 | return 0; |
| 473 | } |
| 474 | |
Brad Volkin | 4c914c0 | 2014-02-18 10:15:45 -0800 | [diff] [blame] | 475 | /* |
| 476 | * Pins the specified object's pages and synchronizes the object with |
| 477 | * GPU accesses. Sets needs_clflush to non-zero if the caller should |
| 478 | * flush the object from the CPU cache. |
| 479 | */ |
| 480 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, |
| 481 | int *needs_clflush) |
| 482 | { |
| 483 | int ret; |
| 484 | |
| 485 | *needs_clflush = 0; |
| 486 | |
Ben Widawsky | 1db6e2e | 2016-02-09 11:44:12 -0800 | [diff] [blame] | 487 | if (WARN_ON((obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE) == 0)) |
Brad Volkin | 4c914c0 | 2014-02-18 10:15:45 -0800 | [diff] [blame] | 488 | return -EINVAL; |
| 489 | |
| 490 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
| 491 | /* If we're not in the cpu read domain, set ourself into the gtt |
| 492 | * read domain and manually flush cachelines (if required). This |
| 493 | * optimizes for the case when the gpu will dirty the data |
| 494 | * anyway again before the next pread happens. */ |
| 495 | *needs_clflush = !cpu_cache_is_coherent(obj->base.dev, |
| 496 | obj->cache_level); |
| 497 | ret = i915_gem_object_wait_rendering(obj, true); |
| 498 | if (ret) |
| 499 | return ret; |
| 500 | } |
| 501 | |
| 502 | ret = i915_gem_object_get_pages(obj); |
| 503 | if (ret) |
| 504 | return ret; |
| 505 | |
| 506 | i915_gem_object_pin_pages(obj); |
| 507 | |
| 508 | return ret; |
| 509 | } |
| 510 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 511 | /* Per-page copy function for the shmem pread fastpath. |
| 512 | * Flushes invalid cachelines before reading the target if |
| 513 | * needs_clflush is set. */ |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 514 | static int |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 515 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
| 516 | char __user *user_data, |
| 517 | bool page_do_bit17_swizzling, bool needs_clflush) |
| 518 | { |
| 519 | char *vaddr; |
| 520 | int ret; |
| 521 | |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 522 | if (unlikely(page_do_bit17_swizzling)) |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 523 | return -EINVAL; |
| 524 | |
| 525 | vaddr = kmap_atomic(page); |
| 526 | if (needs_clflush) |
| 527 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 528 | page_length); |
| 529 | ret = __copy_to_user_inatomic(user_data, |
| 530 | vaddr + shmem_page_offset, |
| 531 | page_length); |
| 532 | kunmap_atomic(vaddr); |
| 533 | |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 534 | return ret ? -EFAULT : 0; |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 535 | } |
| 536 | |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 537 | static void |
| 538 | shmem_clflush_swizzled_range(char *addr, unsigned long length, |
| 539 | bool swizzled) |
| 540 | { |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 541 | if (unlikely(swizzled)) { |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 542 | unsigned long start = (unsigned long) addr; |
| 543 | unsigned long end = (unsigned long) addr + length; |
| 544 | |
| 545 | /* For swizzling simply ensure that we always flush both |
| 546 | * channels. Lame, but simple and it works. Swizzled |
| 547 | * pwrite/pread is far from a hotpath - current userspace |
| 548 | * doesn't use it at all. */ |
| 549 | start = round_down(start, 128); |
| 550 | end = round_up(end, 128); |
| 551 | |
| 552 | drm_clflush_virt_range((void *)start, end - start); |
| 553 | } else { |
| 554 | drm_clflush_virt_range(addr, length); |
| 555 | } |
| 556 | |
| 557 | } |
| 558 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 559 | /* Only difference to the fast-path function is that this can handle bit17 |
| 560 | * and uses non-atomic copy and kmap functions. */ |
| 561 | static int |
| 562 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, |
| 563 | char __user *user_data, |
| 564 | bool page_do_bit17_swizzling, bool needs_clflush) |
| 565 | { |
| 566 | char *vaddr; |
| 567 | int ret; |
| 568 | |
| 569 | vaddr = kmap(page); |
| 570 | if (needs_clflush) |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 571 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 572 | page_length, |
| 573 | page_do_bit17_swizzling); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 574 | |
| 575 | if (page_do_bit17_swizzling) |
| 576 | ret = __copy_to_user_swizzled(user_data, |
| 577 | vaddr, shmem_page_offset, |
| 578 | page_length); |
| 579 | else |
| 580 | ret = __copy_to_user(user_data, |
| 581 | vaddr + shmem_page_offset, |
| 582 | page_length); |
| 583 | kunmap(page); |
| 584 | |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 585 | return ret ? - EFAULT : 0; |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 586 | } |
| 587 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 588 | static int |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 589 | i915_gem_shmem_pread(struct drm_device *dev, |
| 590 | struct drm_i915_gem_object *obj, |
| 591 | struct drm_i915_gem_pread *args, |
| 592 | struct drm_file *file) |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 593 | { |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 594 | char __user *user_data; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 595 | ssize_t remain; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 596 | loff_t offset; |
Ben Widawsky | eb2c0c8 | 2012-02-15 14:42:43 +0100 | [diff] [blame] | 597 | int shmem_page_offset, page_length, ret = 0; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 598 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
Daniel Vetter | 96d79b5 | 2012-03-25 19:47:36 +0200 | [diff] [blame] | 599 | int prefaulted = 0; |
Daniel Vetter | 8489731 | 2012-03-25 19:47:31 +0200 | [diff] [blame] | 600 | int needs_clflush = 0; |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 601 | struct sg_page_iter sg_iter; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 602 | |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 603 | user_data = to_user_ptr(args->data_ptr); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 604 | remain = args->size; |
| 605 | |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 606 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 607 | |
Brad Volkin | 4c914c0 | 2014-02-18 10:15:45 -0800 | [diff] [blame] | 608 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 609 | if (ret) |
| 610 | return ret; |
| 611 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 612 | offset = args->offset; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 613 | |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 614 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
| 615 | offset >> PAGE_SHIFT) { |
Imre Deak | 2db76d7 | 2013-03-26 15:14:18 +0200 | [diff] [blame] | 616 | struct page *page = sg_page_iter_page(&sg_iter); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 617 | |
| 618 | if (remain <= 0) |
| 619 | break; |
| 620 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 621 | /* Operation in this page |
| 622 | * |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 623 | * shmem_page_offset = offset within page in shmem file |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 624 | * page_length = bytes to copy for this page |
| 625 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 626 | shmem_page_offset = offset_in_page(offset); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 627 | page_length = remain; |
| 628 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 629 | page_length = PAGE_SIZE - shmem_page_offset; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 630 | |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 631 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
| 632 | (page_to_phys(page) & (1 << 17)) != 0; |
| 633 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 634 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
| 635 | user_data, page_do_bit17_swizzling, |
| 636 | needs_clflush); |
| 637 | if (ret == 0) |
| 638 | goto next_page; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 639 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 640 | mutex_unlock(&dev->struct_mutex); |
| 641 | |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 642 | if (likely(!i915.prefault_disable) && !prefaulted) { |
Daniel Vetter | f56f821 | 2012-03-25 19:47:41 +0200 | [diff] [blame] | 643 | ret = fault_in_multipages_writeable(user_data, remain); |
Daniel Vetter | 96d79b5 | 2012-03-25 19:47:36 +0200 | [diff] [blame] | 644 | /* Userspace is tricking us, but we've already clobbered |
| 645 | * its pages with the prefault and promised to write the |
| 646 | * data up to the first fault. Hence ignore any errors |
| 647 | * and just continue. */ |
| 648 | (void)ret; |
| 649 | prefaulted = 1; |
| 650 | } |
| 651 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 652 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
| 653 | user_data, page_do_bit17_swizzling, |
| 654 | needs_clflush); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 655 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 656 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 657 | |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 658 | if (ret) |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 659 | goto out; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 660 | |
Chris Wilson | 17793c9 | 2014-03-07 08:30:36 +0000 | [diff] [blame] | 661 | next_page: |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 662 | remain -= page_length; |
Daniel Vetter | 8461d22 | 2011-12-14 13:57:32 +0100 | [diff] [blame] | 663 | user_data += page_length; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 664 | offset += page_length; |
| 665 | } |
| 666 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 667 | out: |
Chris Wilson | f60d7f0 | 2012-09-04 21:02:56 +0100 | [diff] [blame] | 668 | i915_gem_object_unpin_pages(obj); |
| 669 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 670 | return ret; |
| 671 | } |
| 672 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 673 | /** |
| 674 | * Reads data from the object referenced by handle. |
| 675 | * |
| 676 | * On error, the contents of *data are undefined. |
| 677 | */ |
| 678 | int |
| 679 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 680 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 681 | { |
| 682 | struct drm_i915_gem_pread *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 683 | struct drm_i915_gem_object *obj; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 684 | int ret = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 685 | |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 686 | if (args->size == 0) |
| 687 | return 0; |
| 688 | |
| 689 | if (!access_ok(VERIFY_WRITE, |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 690 | to_user_ptr(args->data_ptr), |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 691 | args->size)) |
| 692 | return -EFAULT; |
| 693 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 694 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 695 | if (ret) |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 696 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 697 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 698 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 699 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 700 | ret = -ENOENT; |
| 701 | goto unlock; |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 702 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 703 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 704 | /* Bounds check source. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 705 | if (args->offset > obj->base.size || |
| 706 | args->size > obj->base.size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 707 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 708 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 709 | } |
| 710 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 711 | /* prime objects have no backing filp to GEM pread/pwrite |
| 712 | * pages from. |
| 713 | */ |
| 714 | if (!obj->base.filp) { |
| 715 | ret = -EINVAL; |
| 716 | goto out; |
| 717 | } |
| 718 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 719 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
| 720 | |
Daniel Vetter | dbf7bff | 2012-03-25 19:47:29 +0200 | [diff] [blame] | 721 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 722 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 723 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 724 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 725 | unlock: |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 726 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 727 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 728 | } |
| 729 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 730 | /* This is the fast write path which cannot handle |
| 731 | * page faults in the source data |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 732 | */ |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 733 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 734 | static inline int |
| 735 | fast_user_write(struct io_mapping *mapping, |
| 736 | loff_t page_base, int page_offset, |
| 737 | char __user *user_data, |
| 738 | int length) |
| 739 | { |
Ben Widawsky | 4f0c7cf | 2012-04-16 14:07:47 -0700 | [diff] [blame] | 740 | void __iomem *vaddr_atomic; |
| 741 | void *vaddr; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 742 | unsigned long unwritten; |
| 743 | |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 744 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
Ben Widawsky | 4f0c7cf | 2012-04-16 14:07:47 -0700 | [diff] [blame] | 745 | /* We can use the cpu mem copy function because this is X86. */ |
| 746 | vaddr = (void __force*)vaddr_atomic + page_offset; |
| 747 | unwritten = __copy_from_user_inatomic_nocache(vaddr, |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 748 | user_data, length); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 749 | io_mapping_unmap_atomic(vaddr_atomic); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 750 | return unwritten; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 751 | } |
| 752 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 753 | /** |
| 754 | * This is the fast pwrite path, where we copy the data directly from the |
| 755 | * user into the GTT, uncached. |
| 756 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 757 | static int |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 758 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
| 759 | struct drm_i915_gem_object *obj, |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 760 | struct drm_i915_gem_pwrite *args, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 761 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 762 | { |
Joonas Lahtinen | 72e96d6 | 2016-03-30 16:57:10 +0300 | [diff] [blame] | 763 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 764 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 765 | ssize_t remain; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 766 | loff_t offset, page_base; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 767 | char __user *user_data; |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 768 | int page_offset, page_length, ret; |
| 769 | |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 770 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK); |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 771 | if (ret) |
| 772 | goto out; |
| 773 | |
| 774 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
| 775 | if (ret) |
| 776 | goto out_unpin; |
| 777 | |
| 778 | ret = i915_gem_object_put_fence(obj); |
| 779 | if (ret) |
| 780 | goto out_unpin; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 781 | |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 782 | user_data = to_user_ptr(args->data_ptr); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 783 | remain = args->size; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 784 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 785 | offset = i915_gem_obj_ggtt_offset(obj) + args->offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 786 | |
Rodrigo Vivi | 77a0d1c | 2015-06-18 11:43:24 -0700 | [diff] [blame] | 787 | intel_fb_obj_invalidate(obj, ORIGIN_GTT); |
Paulo Zanoni | 063e4e6 | 2015-02-13 17:23:45 -0200 | [diff] [blame] | 788 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 789 | while (remain > 0) { |
| 790 | /* Operation in this page |
| 791 | * |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 792 | * page_base = page offset within aperture |
| 793 | * page_offset = offset within page |
| 794 | * page_length = bytes to copy for this page |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 795 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 796 | page_base = offset & PAGE_MASK; |
| 797 | page_offset = offset_in_page(offset); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 798 | page_length = remain; |
| 799 | if ((page_offset + remain) > PAGE_SIZE) |
| 800 | page_length = PAGE_SIZE - page_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 801 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 802 | /* If we get a fault while copying data, then (presumably) our |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 803 | * source page isn't available. Return the error and we'll |
| 804 | * retry in the slow path. |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 805 | */ |
Joonas Lahtinen | 72e96d6 | 2016-03-30 16:57:10 +0300 | [diff] [blame] | 806 | if (fast_user_write(ggtt->mappable, page_base, |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 807 | page_offset, user_data, page_length)) { |
| 808 | ret = -EFAULT; |
Paulo Zanoni | 063e4e6 | 2015-02-13 17:23:45 -0200 | [diff] [blame] | 809 | goto out_flush; |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 810 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 811 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 812 | remain -= page_length; |
| 813 | user_data += page_length; |
| 814 | offset += page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 815 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 816 | |
Paulo Zanoni | 063e4e6 | 2015-02-13 17:23:45 -0200 | [diff] [blame] | 817 | out_flush: |
Rodrigo Vivi | de152b6 | 2015-07-07 16:28:51 -0700 | [diff] [blame] | 818 | intel_fb_obj_flush(obj, false, ORIGIN_GTT); |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 819 | out_unpin: |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 820 | i915_gem_object_ggtt_unpin(obj); |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 821 | out: |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 822 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 823 | } |
| 824 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 825 | /* Per-page copy function for the shmem pwrite fastpath. |
| 826 | * Flushes invalid cachelines before writing to the target if |
| 827 | * needs_clflush_before is set and flushes out any written cachelines after |
| 828 | * writing if needs_clflush is set. */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 829 | static int |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 830 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
| 831 | char __user *user_data, |
| 832 | bool page_do_bit17_swizzling, |
| 833 | bool needs_clflush_before, |
| 834 | bool needs_clflush_after) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 835 | { |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 836 | char *vaddr; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 837 | int ret; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 838 | |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 839 | if (unlikely(page_do_bit17_swizzling)) |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 840 | return -EINVAL; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 841 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 842 | vaddr = kmap_atomic(page); |
| 843 | if (needs_clflush_before) |
| 844 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 845 | page_length); |
Chris Wilson | c2831a9 | 2014-03-07 08:30:37 +0000 | [diff] [blame] | 846 | ret = __copy_from_user_inatomic(vaddr + shmem_page_offset, |
| 847 | user_data, page_length); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 848 | if (needs_clflush_after) |
| 849 | drm_clflush_virt_range(vaddr + shmem_page_offset, |
| 850 | page_length); |
| 851 | kunmap_atomic(vaddr); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 852 | |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 853 | return ret ? -EFAULT : 0; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 854 | } |
| 855 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 856 | /* Only difference to the fast-path function is that this can handle bit17 |
| 857 | * and uses non-atomic copy and kmap functions. */ |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 858 | static int |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 859 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
| 860 | char __user *user_data, |
| 861 | bool page_do_bit17_swizzling, |
| 862 | bool needs_clflush_before, |
| 863 | bool needs_clflush_after) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 864 | { |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 865 | char *vaddr; |
| 866 | int ret; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 867 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 868 | vaddr = kmap(page); |
Daniel Vetter | e7e58eb | 2012-03-25 19:47:43 +0200 | [diff] [blame] | 869 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 870 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 871 | page_length, |
| 872 | page_do_bit17_swizzling); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 873 | if (page_do_bit17_swizzling) |
| 874 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 875 | user_data, |
| 876 | page_length); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 877 | else |
| 878 | ret = __copy_from_user(vaddr + shmem_page_offset, |
| 879 | user_data, |
| 880 | page_length); |
| 881 | if (needs_clflush_after) |
Daniel Vetter | 23c18c7 | 2012-03-25 19:47:42 +0200 | [diff] [blame] | 882 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
| 883 | page_length, |
| 884 | page_do_bit17_swizzling); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 885 | kunmap(page); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 886 | |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 887 | return ret ? -EFAULT : 0; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 888 | } |
| 889 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 890 | static int |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 891 | i915_gem_shmem_pwrite(struct drm_device *dev, |
| 892 | struct drm_i915_gem_object *obj, |
| 893 | struct drm_i915_gem_pwrite *args, |
| 894 | struct drm_file *file) |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 895 | { |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 896 | ssize_t remain; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 897 | loff_t offset; |
| 898 | char __user *user_data; |
Ben Widawsky | eb2c0c8 | 2012-02-15 14:42:43 +0100 | [diff] [blame] | 899 | int shmem_page_offset, page_length, ret = 0; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 900 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 901 | int hit_slowpath = 0; |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 902 | int needs_clflush_after = 0; |
| 903 | int needs_clflush_before = 0; |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 904 | struct sg_page_iter sg_iter; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 905 | |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 906 | user_data = to_user_ptr(args->data_ptr); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 907 | remain = args->size; |
| 908 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 909 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 910 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 911 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
| 912 | /* If we're not in the cpu write domain, set ourself into the gtt |
| 913 | * write domain and manually flush cachelines (if required). This |
| 914 | * optimizes for the case when the gpu will use the data |
| 915 | * right away and we therefore have to clflush anyway. */ |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 916 | needs_clflush_after = cpu_write_needs_clflush(obj); |
Ben Widawsky | 23f5448 | 2013-09-11 14:57:48 -0700 | [diff] [blame] | 917 | ret = i915_gem_object_wait_rendering(obj, false); |
| 918 | if (ret) |
| 919 | return ret; |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 920 | } |
Chris Wilson | c76ce03 | 2013-08-08 14:41:03 +0100 | [diff] [blame] | 921 | /* Same trick applies to invalidate partially written cachelines read |
| 922 | * before writing. */ |
| 923 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) |
| 924 | needs_clflush_before = |
| 925 | !cpu_cache_is_coherent(dev, obj->cache_level); |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 926 | |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 927 | ret = i915_gem_object_get_pages(obj); |
| 928 | if (ret) |
| 929 | return ret; |
| 930 | |
Rodrigo Vivi | 77a0d1c | 2015-06-18 11:43:24 -0700 | [diff] [blame] | 931 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
Paulo Zanoni | 063e4e6 | 2015-02-13 17:23:45 -0200 | [diff] [blame] | 932 | |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 933 | i915_gem_object_pin_pages(obj); |
| 934 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 935 | offset = args->offset; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 936 | obj->dirty = 1; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 937 | |
Imre Deak | 67d5a50 | 2013-02-18 19:28:02 +0200 | [diff] [blame] | 938 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
| 939 | offset >> PAGE_SHIFT) { |
Imre Deak | 2db76d7 | 2013-03-26 15:14:18 +0200 | [diff] [blame] | 940 | struct page *page = sg_page_iter_page(&sg_iter); |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 941 | int partial_cacheline_write; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 942 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 943 | if (remain <= 0) |
| 944 | break; |
| 945 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 946 | /* Operation in this page |
| 947 | * |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 948 | * shmem_page_offset = offset within page in shmem file |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 949 | * page_length = bytes to copy for this page |
| 950 | */ |
Chris Wilson | c8cbbb8 | 2011-05-12 22:17:11 +0100 | [diff] [blame] | 951 | shmem_page_offset = offset_in_page(offset); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 952 | |
| 953 | page_length = remain; |
| 954 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 955 | page_length = PAGE_SIZE - shmem_page_offset; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 956 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 957 | /* If we don't overwrite a cacheline completely we need to be |
| 958 | * careful to have up-to-date data by first clflushing. Don't |
| 959 | * overcomplicate things and flush the entire patch. */ |
| 960 | partial_cacheline_write = needs_clflush_before && |
| 961 | ((shmem_page_offset | page_length) |
| 962 | & (boot_cpu_data.x86_clflush_size - 1)); |
| 963 | |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 964 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
| 965 | (page_to_phys(page) & (1 << 17)) != 0; |
| 966 | |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 967 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
| 968 | user_data, page_do_bit17_swizzling, |
| 969 | partial_cacheline_write, |
| 970 | needs_clflush_after); |
| 971 | if (ret == 0) |
| 972 | goto next_page; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 973 | |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 974 | hit_slowpath = 1; |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 975 | mutex_unlock(&dev->struct_mutex); |
Daniel Vetter | d174bd6 | 2012-03-25 19:47:40 +0200 | [diff] [blame] | 976 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
| 977 | user_data, page_do_bit17_swizzling, |
| 978 | partial_cacheline_write, |
| 979 | needs_clflush_after); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 980 | |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 981 | mutex_lock(&dev->struct_mutex); |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 982 | |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 983 | if (ret) |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 984 | goto out; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 985 | |
Chris Wilson | 17793c9 | 2014-03-07 08:30:36 +0000 | [diff] [blame] | 986 | next_page: |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 987 | remain -= page_length; |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 988 | user_data += page_length; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 989 | offset += page_length; |
| 990 | } |
| 991 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 992 | out: |
Chris Wilson | 755d221 | 2012-09-04 21:02:55 +0100 | [diff] [blame] | 993 | i915_gem_object_unpin_pages(obj); |
| 994 | |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 995 | if (hit_slowpath) { |
Daniel Vetter | 8dcf015 | 2012-11-15 16:53:58 +0100 | [diff] [blame] | 996 | /* |
| 997 | * Fixup: Flush cpu caches in case we didn't flush the dirty |
| 998 | * cachelines in-line while writing and the object moved |
| 999 | * out of the cpu write domain while we've dropped the lock. |
| 1000 | */ |
| 1001 | if (!needs_clflush_after && |
| 1002 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 1003 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
Ville Syrjälä | ed75a55 | 2015-08-11 19:47:10 +0300 | [diff] [blame] | 1004 | needs_clflush_after = true; |
Daniel Vetter | e244a44 | 2012-03-25 19:47:28 +0200 | [diff] [blame] | 1005 | } |
Daniel Vetter | 8c59967 | 2011-12-14 13:57:31 +0100 | [diff] [blame] | 1006 | } |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1007 | |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 1008 | if (needs_clflush_after) |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1009 | i915_gem_chipset_flush(dev); |
Ville Syrjälä | ed75a55 | 2015-08-11 19:47:10 +0300 | [diff] [blame] | 1010 | else |
| 1011 | obj->cache_dirty = true; |
Daniel Vetter | 5864288 | 2012-03-25 19:47:37 +0200 | [diff] [blame] | 1012 | |
Rodrigo Vivi | de152b6 | 2015-07-07 16:28:51 -0700 | [diff] [blame] | 1013 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1014 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1015 | } |
| 1016 | |
| 1017 | /** |
| 1018 | * Writes data to the object referenced by handle. |
| 1019 | * |
| 1020 | * On error, the contents of the buffer that were to be modified are undefined. |
| 1021 | */ |
| 1022 | int |
| 1023 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1024 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1025 | { |
Imre Deak | 5d77d9c | 2014-11-12 16:40:35 +0200 | [diff] [blame] | 1026 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1027 | struct drm_i915_gem_pwrite *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1028 | struct drm_i915_gem_object *obj; |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 1029 | int ret; |
| 1030 | |
| 1031 | if (args->size == 0) |
| 1032 | return 0; |
| 1033 | |
| 1034 | if (!access_ok(VERIFY_READ, |
Ville Syrjälä | 2bb4629 | 2013-02-22 16:12:51 +0200 | [diff] [blame] | 1035 | to_user_ptr(args->data_ptr), |
Chris Wilson | 51311d0 | 2010-11-17 09:10:42 +0000 | [diff] [blame] | 1036 | args->size)) |
| 1037 | return -EFAULT; |
| 1038 | |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 1039 | if (likely(!i915.prefault_disable)) { |
Xiong Zhang | 0b74b50 | 2013-07-19 13:51:24 +0800 | [diff] [blame] | 1040 | ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr), |
| 1041 | args->size); |
| 1042 | if (ret) |
| 1043 | return -EFAULT; |
| 1044 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1045 | |
Imre Deak | 5d77d9c | 2014-11-12 16:40:35 +0200 | [diff] [blame] | 1046 | intel_runtime_pm_get(dev_priv); |
| 1047 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1048 | ret = i915_mutex_lock_interruptible(dev); |
| 1049 | if (ret) |
Imre Deak | 5d77d9c | 2014-11-12 16:40:35 +0200 | [diff] [blame] | 1050 | goto put_rpm; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1051 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1052 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 1053 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1054 | ret = -ENOENT; |
| 1055 | goto unlock; |
| 1056 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1057 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 1058 | /* Bounds check destination. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1059 | if (args->offset > obj->base.size || |
| 1060 | args->size > obj->base.size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 1061 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 1062 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 1063 | } |
| 1064 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 1065 | /* prime objects have no backing filp to GEM pread/pwrite |
| 1066 | * pages from. |
| 1067 | */ |
| 1068 | if (!obj->base.filp) { |
| 1069 | ret = -EINVAL; |
| 1070 | goto out; |
| 1071 | } |
| 1072 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1073 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
| 1074 | |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 1075 | ret = -EFAULT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1076 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
| 1077 | * it would end up going through the fenced access, and we'll get |
| 1078 | * different detiling behavior between reading and writing. |
| 1079 | * pread/pwrite currently are reading and writing from the CPU |
| 1080 | * perspective, requiring manual detiling by the client. |
| 1081 | */ |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 1082 | if (obj->tiling_mode == I915_TILING_NONE && |
| 1083 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && |
| 1084 | cpu_write_needs_clflush(obj)) { |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1085 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
Daniel Vetter | 935aaa6 | 2012-03-25 19:47:35 +0200 | [diff] [blame] | 1086 | /* Note that the gtt paths might fail with non-page-backed user |
| 1087 | * pointers (e.g. gtt mappings when moving data between |
| 1088 | * textures). Fallback to the shmem path in that case. */ |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1089 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1090 | |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 1091 | if (ret == -EFAULT || ret == -ENOSPC) { |
| 1092 | if (obj->phys_handle) |
| 1093 | ret = i915_gem_phys_pwrite(obj, args, file); |
| 1094 | else |
| 1095 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
| 1096 | } |
Daniel Vetter | 5c0480f | 2011-12-14 13:57:30 +0100 | [diff] [blame] | 1097 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 1098 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1099 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1100 | unlock: |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1101 | mutex_unlock(&dev->struct_mutex); |
Imre Deak | 5d77d9c | 2014-11-12 16:40:35 +0200 | [diff] [blame] | 1102 | put_rpm: |
| 1103 | intel_runtime_pm_put(dev_priv); |
| 1104 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1105 | return ret; |
| 1106 | } |
| 1107 | |
Chris Wilson | f4457ae | 2016-04-13 17:35:08 +0100 | [diff] [blame] | 1108 | static int |
| 1109 | i915_gem_check_wedge(unsigned reset_counter, bool interruptible) |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1110 | { |
Chris Wilson | f4457ae | 2016-04-13 17:35:08 +0100 | [diff] [blame] | 1111 | if (__i915_terminally_wedged(reset_counter)) |
| 1112 | return -EIO; |
Chris Wilson | d98c52c | 2016-04-13 17:35:05 +0100 | [diff] [blame] | 1113 | |
Chris Wilson | f4457ae | 2016-04-13 17:35:08 +0100 | [diff] [blame] | 1114 | if (__i915_reset_in_progress(reset_counter)) { |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1115 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
| 1116 | * -EIO unconditionally for these. */ |
| 1117 | if (!interruptible) |
| 1118 | return -EIO; |
| 1119 | |
Chris Wilson | d98c52c | 2016-04-13 17:35:05 +0100 | [diff] [blame] | 1120 | return -EAGAIN; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1121 | } |
| 1122 | |
| 1123 | return 0; |
| 1124 | } |
| 1125 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1126 | static void fake_irq(unsigned long data) |
| 1127 | { |
| 1128 | wake_up_process((struct task_struct *)data); |
| 1129 | } |
| 1130 | |
| 1131 | static bool missed_irq(struct drm_i915_private *dev_priv, |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1132 | struct intel_engine_cs *engine) |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1133 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 1134 | return test_bit(engine->id, &dev_priv->gpu_error.missed_irq_rings); |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1135 | } |
| 1136 | |
Chris Wilson | ca5b721 | 2015-12-11 11:32:58 +0000 | [diff] [blame] | 1137 | static unsigned long local_clock_us(unsigned *cpu) |
| 1138 | { |
| 1139 | unsigned long t; |
| 1140 | |
| 1141 | /* Cheaply and approximately convert from nanoseconds to microseconds. |
| 1142 | * The result and subsequent calculations are also defined in the same |
| 1143 | * approximate microseconds units. The principal source of timing |
| 1144 | * error here is from the simple truncation. |
| 1145 | * |
| 1146 | * Note that local_clock() is only defined wrt to the current CPU; |
| 1147 | * the comparisons are no longer valid if we switch CPUs. Instead of |
| 1148 | * blocking preemption for the entire busywait, we can detect the CPU |
| 1149 | * switch and use that as indicator of system load and a reason to |
| 1150 | * stop busywaiting, see busywait_stop(). |
| 1151 | */ |
| 1152 | *cpu = get_cpu(); |
| 1153 | t = local_clock() >> 10; |
| 1154 | put_cpu(); |
| 1155 | |
| 1156 | return t; |
| 1157 | } |
| 1158 | |
| 1159 | static bool busywait_stop(unsigned long timeout, unsigned cpu) |
| 1160 | { |
| 1161 | unsigned this_cpu; |
| 1162 | |
| 1163 | if (time_after(local_clock_us(&this_cpu), timeout)) |
| 1164 | return true; |
| 1165 | |
| 1166 | return this_cpu != cpu; |
| 1167 | } |
| 1168 | |
Chris Wilson | 91b0c35 | 2015-12-11 11:32:57 +0000 | [diff] [blame] | 1169 | static int __i915_spin_request(struct drm_i915_gem_request *req, int state) |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 1170 | { |
Chris Wilson | 2def4ad9 | 2015-04-07 16:20:41 +0100 | [diff] [blame] | 1171 | unsigned long timeout; |
Chris Wilson | ca5b721 | 2015-12-11 11:32:58 +0000 | [diff] [blame] | 1172 | unsigned cpu; |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 1173 | |
Chris Wilson | ca5b721 | 2015-12-11 11:32:58 +0000 | [diff] [blame] | 1174 | /* When waiting for high frequency requests, e.g. during synchronous |
| 1175 | * rendering split between the CPU and GPU, the finite amount of time |
| 1176 | * required to set up the irq and wait upon it limits the response |
| 1177 | * rate. By busywaiting on the request completion for a short while we |
| 1178 | * can service the high frequency waits as quick as possible. However, |
| 1179 | * if it is a slow request, we want to sleep as quickly as possible. |
| 1180 | * The tradeoff between waiting and sleeping is roughly the time it |
| 1181 | * takes to sleep on a request, on the order of a microsecond. |
| 1182 | */ |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 1183 | |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 1184 | if (req->engine->irq_refcount) |
Chris Wilson | 2def4ad9 | 2015-04-07 16:20:41 +0100 | [diff] [blame] | 1185 | return -EBUSY; |
| 1186 | |
Chris Wilson | 821485d | 2015-12-11 11:32:59 +0000 | [diff] [blame] | 1187 | /* Only spin if we know the GPU is processing this request */ |
| 1188 | if (!i915_gem_request_started(req, true)) |
| 1189 | return -EAGAIN; |
| 1190 | |
Chris Wilson | ca5b721 | 2015-12-11 11:32:58 +0000 | [diff] [blame] | 1191 | timeout = local_clock_us(&cpu) + 5; |
Chris Wilson | 2def4ad9 | 2015-04-07 16:20:41 +0100 | [diff] [blame] | 1192 | while (!need_resched()) { |
Daniel Vetter | eed29a5 | 2015-05-21 14:21:25 +0200 | [diff] [blame] | 1193 | if (i915_gem_request_completed(req, true)) |
Chris Wilson | 2def4ad9 | 2015-04-07 16:20:41 +0100 | [diff] [blame] | 1194 | return 0; |
| 1195 | |
Chris Wilson | 91b0c35 | 2015-12-11 11:32:57 +0000 | [diff] [blame] | 1196 | if (signal_pending_state(state, current)) |
| 1197 | break; |
| 1198 | |
Chris Wilson | ca5b721 | 2015-12-11 11:32:58 +0000 | [diff] [blame] | 1199 | if (busywait_stop(timeout, cpu)) |
Chris Wilson | 2def4ad9 | 2015-04-07 16:20:41 +0100 | [diff] [blame] | 1200 | break; |
| 1201 | |
| 1202 | cpu_relax_lowlatency(); |
| 1203 | } |
Chris Wilson | 821485d | 2015-12-11 11:32:59 +0000 | [diff] [blame] | 1204 | |
Daniel Vetter | eed29a5 | 2015-05-21 14:21:25 +0200 | [diff] [blame] | 1205 | if (i915_gem_request_completed(req, false)) |
Chris Wilson | 2def4ad9 | 2015-04-07 16:20:41 +0100 | [diff] [blame] | 1206 | return 0; |
| 1207 | |
| 1208 | return -EAGAIN; |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 1209 | } |
| 1210 | |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1211 | /** |
John Harrison | 9c65481 | 2014-11-24 18:49:35 +0000 | [diff] [blame] | 1212 | * __i915_wait_request - wait until execution of request has finished |
| 1213 | * @req: duh! |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1214 | * @interruptible: do an interruptible wait (normally yes) |
| 1215 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining |
| 1216 | * |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1217 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
| 1218 | * values have been read by the caller in an smp safe manner. Where read-side |
| 1219 | * locks are involved, it is sufficient to read the reset_counter before |
| 1220 | * unlocking the lock that protects the seqno. For lockless tricks, the |
| 1221 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be |
| 1222 | * inserted. |
| 1223 | * |
John Harrison | 9c65481 | 2014-11-24 18:49:35 +0000 | [diff] [blame] | 1224 | * Returns 0 if the request was found within the alloted time. Else returns the |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1225 | * errno with remaining time filled in timeout argument. |
| 1226 | */ |
John Harrison | 9c65481 | 2014-11-24 18:49:35 +0000 | [diff] [blame] | 1227 | int __i915_wait_request(struct drm_i915_gem_request *req, |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 1228 | bool interruptible, |
Thomas Gleixner | 5ed0bdf | 2014-07-16 21:05:06 +0000 | [diff] [blame] | 1229 | s64 *timeout, |
Chris Wilson | 2e1b873 | 2015-04-27 13:41:22 +0100 | [diff] [blame] | 1230 | struct intel_rps_client *rps) |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1231 | { |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 1232 | struct intel_engine_cs *engine = i915_gem_request_get_engine(req); |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1233 | struct drm_device *dev = engine->dev; |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 1234 | struct drm_i915_private *dev_priv = dev->dev_private; |
Mika Kuoppala | 168c3f2 | 2013-12-12 17:54:42 +0200 | [diff] [blame] | 1235 | const bool irq_test_in_progress = |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 1236 | ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_engine_flag(engine); |
Chris Wilson | 91b0c35 | 2015-12-11 11:32:57 +0000 | [diff] [blame] | 1237 | int state = interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE; |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1238 | DEFINE_WAIT(wait); |
Mika Kuoppala | 47e9766d | 2013-12-10 17:02:43 +0200 | [diff] [blame] | 1239 | unsigned long timeout_expire; |
Tvrtko Ursulin | e0313db | 2016-01-15 15:11:12 +0000 | [diff] [blame] | 1240 | s64 before = 0; /* Only to silence a compiler warning. */ |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1241 | int ret; |
| 1242 | |
Jesse Barnes | 9df7575f | 2014-06-20 09:29:20 -0700 | [diff] [blame] | 1243 | WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled"); |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 1244 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1245 | if (list_empty(&req->list)) |
| 1246 | return 0; |
| 1247 | |
John Harrison | 1b5a433 | 2014-11-24 18:49:42 +0000 | [diff] [blame] | 1248 | if (i915_gem_request_completed(req, true)) |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1249 | return 0; |
| 1250 | |
Chris Wilson | bb6d198 | 2015-11-26 13:31:42 +0000 | [diff] [blame] | 1251 | timeout_expire = 0; |
| 1252 | if (timeout) { |
| 1253 | if (WARN_ON(*timeout < 0)) |
| 1254 | return -EINVAL; |
| 1255 | |
| 1256 | if (*timeout == 0) |
| 1257 | return -ETIME; |
| 1258 | |
| 1259 | timeout_expire = jiffies + nsecs_to_jiffies_timeout(*timeout); |
Tvrtko Ursulin | e0313db | 2016-01-15 15:11:12 +0000 | [diff] [blame] | 1260 | |
| 1261 | /* |
| 1262 | * Record current time in case interrupted by signal, or wedged. |
| 1263 | */ |
| 1264 | before = ktime_get_raw_ns(); |
Chris Wilson | bb6d198 | 2015-11-26 13:31:42 +0000 | [diff] [blame] | 1265 | } |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1266 | |
Chris Wilson | 2e1b873 | 2015-04-27 13:41:22 +0100 | [diff] [blame] | 1267 | if (INTEL_INFO(dev_priv)->gen >= 6) |
Chris Wilson | e61b995 | 2015-04-27 13:41:24 +0100 | [diff] [blame] | 1268 | gen6_rps_boost(dev_priv, rps, req->emitted_jiffies); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1269 | |
John Harrison | 74328ee | 2014-11-24 18:49:38 +0000 | [diff] [blame] | 1270 | trace_i915_gem_request_wait_begin(req); |
Chris Wilson | 2def4ad9 | 2015-04-07 16:20:41 +0100 | [diff] [blame] | 1271 | |
| 1272 | /* Optimistic spin for the next jiffie before touching IRQs */ |
Chris Wilson | 91b0c35 | 2015-12-11 11:32:57 +0000 | [diff] [blame] | 1273 | ret = __i915_spin_request(req, state); |
Chris Wilson | 2def4ad9 | 2015-04-07 16:20:41 +0100 | [diff] [blame] | 1274 | if (ret == 0) |
| 1275 | goto out; |
| 1276 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1277 | if (!irq_test_in_progress && WARN_ON(!engine->irq_get(engine))) { |
Chris Wilson | 2def4ad9 | 2015-04-07 16:20:41 +0100 | [diff] [blame] | 1278 | ret = -ENODEV; |
| 1279 | goto out; |
| 1280 | } |
| 1281 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1282 | for (;;) { |
| 1283 | struct timer_list timer; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1284 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1285 | prepare_to_wait(&engine->irq_queue, &wait, state); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1286 | |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1287 | /* We need to check whether any gpu reset happened in between |
Chris Wilson | f4457ae | 2016-04-13 17:35:08 +0100 | [diff] [blame] | 1288 | * the request being submitted and now. If a reset has occurred, |
| 1289 | * the request is effectively complete (we either are in the |
| 1290 | * process of or have discarded the rendering and completely |
| 1291 | * reset the GPU. The results of the request are lost and we |
| 1292 | * are free to continue on with the original operation. |
| 1293 | */ |
Chris Wilson | 299259a | 2016-04-13 17:35:06 +0100 | [diff] [blame] | 1294 | if (req->reset_counter != i915_reset_counter(&dev_priv->gpu_error)) { |
Chris Wilson | f4457ae | 2016-04-13 17:35:08 +0100 | [diff] [blame] | 1295 | ret = 0; |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1296 | break; |
| 1297 | } |
Daniel Vetter | f69061b | 2012-12-06 09:01:42 +0100 | [diff] [blame] | 1298 | |
John Harrison | 1b5a433 | 2014-11-24 18:49:42 +0000 | [diff] [blame] | 1299 | if (i915_gem_request_completed(req, false)) { |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1300 | ret = 0; |
| 1301 | break; |
| 1302 | } |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1303 | |
Chris Wilson | 91b0c35 | 2015-12-11 11:32:57 +0000 | [diff] [blame] | 1304 | if (signal_pending_state(state, current)) { |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1305 | ret = -ERESTARTSYS; |
| 1306 | break; |
| 1307 | } |
| 1308 | |
Mika Kuoppala | 47e9766d | 2013-12-10 17:02:43 +0200 | [diff] [blame] | 1309 | if (timeout && time_after_eq(jiffies, timeout_expire)) { |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1310 | ret = -ETIME; |
| 1311 | break; |
| 1312 | } |
| 1313 | |
| 1314 | timer.function = NULL; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1315 | if (timeout || missed_irq(dev_priv, engine)) { |
Mika Kuoppala | 47e9766d | 2013-12-10 17:02:43 +0200 | [diff] [blame] | 1316 | unsigned long expire; |
| 1317 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1318 | setup_timer_on_stack(&timer, fake_irq, (unsigned long)current); |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1319 | expire = missed_irq(dev_priv, engine) ? jiffies + 1 : timeout_expire; |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1320 | mod_timer(&timer, expire); |
| 1321 | } |
| 1322 | |
Chris Wilson | 5035c27 | 2013-10-04 09:58:46 +0100 | [diff] [blame] | 1323 | io_schedule(); |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1324 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1325 | if (timer.function) { |
| 1326 | del_singleshot_timer_sync(&timer); |
| 1327 | destroy_timer_on_stack(&timer); |
| 1328 | } |
| 1329 | } |
Mika Kuoppala | 168c3f2 | 2013-12-12 17:54:42 +0200 | [diff] [blame] | 1330 | if (!irq_test_in_progress) |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1331 | engine->irq_put(engine); |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1332 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 1333 | finish_wait(&engine->irq_queue, &wait); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1334 | |
Chris Wilson | 2def4ad9 | 2015-04-07 16:20:41 +0100 | [diff] [blame] | 1335 | out: |
Chris Wilson | 2def4ad9 | 2015-04-07 16:20:41 +0100 | [diff] [blame] | 1336 | trace_i915_gem_request_wait_end(req); |
| 1337 | |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1338 | if (timeout) { |
Tvrtko Ursulin | e0313db | 2016-01-15 15:11:12 +0000 | [diff] [blame] | 1339 | s64 tres = *timeout - (ktime_get_raw_ns() - before); |
Thomas Gleixner | 5ed0bdf | 2014-07-16 21:05:06 +0000 | [diff] [blame] | 1340 | |
| 1341 | *timeout = tres < 0 ? 0 : tres; |
Daniel Vetter | 9cca306 | 2014-11-28 10:29:55 +0100 | [diff] [blame] | 1342 | |
| 1343 | /* |
| 1344 | * Apparently ktime isn't accurate enough and occasionally has a |
| 1345 | * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch |
| 1346 | * things up to make the test happy. We allow up to 1 jiffy. |
| 1347 | * |
| 1348 | * This is a regrssion from the timespec->ktime conversion. |
| 1349 | */ |
| 1350 | if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000) |
| 1351 | *timeout = 0; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1352 | } |
| 1353 | |
Chris Wilson | 094f9a5 | 2013-09-25 17:34:55 +0100 | [diff] [blame] | 1354 | return ret; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1355 | } |
| 1356 | |
John Harrison | fcfa423c | 2015-05-29 17:44:12 +0100 | [diff] [blame] | 1357 | int i915_gem_request_add_to_client(struct drm_i915_gem_request *req, |
| 1358 | struct drm_file *file) |
| 1359 | { |
John Harrison | fcfa423c | 2015-05-29 17:44:12 +0100 | [diff] [blame] | 1360 | struct drm_i915_file_private *file_priv; |
| 1361 | |
| 1362 | WARN_ON(!req || !file || req->file_priv); |
| 1363 | |
| 1364 | if (!req || !file) |
| 1365 | return -EINVAL; |
| 1366 | |
| 1367 | if (req->file_priv) |
| 1368 | return -EINVAL; |
| 1369 | |
John Harrison | fcfa423c | 2015-05-29 17:44:12 +0100 | [diff] [blame] | 1370 | file_priv = file->driver_priv; |
| 1371 | |
| 1372 | spin_lock(&file_priv->mm.lock); |
| 1373 | req->file_priv = file_priv; |
| 1374 | list_add_tail(&req->client_list, &file_priv->mm.request_list); |
| 1375 | spin_unlock(&file_priv->mm.lock); |
| 1376 | |
| 1377 | req->pid = get_pid(task_pid(current)); |
| 1378 | |
| 1379 | return 0; |
| 1380 | } |
| 1381 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1382 | static inline void |
| 1383 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) |
| 1384 | { |
| 1385 | struct drm_i915_file_private *file_priv = request->file_priv; |
| 1386 | |
| 1387 | if (!file_priv) |
| 1388 | return; |
| 1389 | |
| 1390 | spin_lock(&file_priv->mm.lock); |
| 1391 | list_del(&request->client_list); |
| 1392 | request->file_priv = NULL; |
| 1393 | spin_unlock(&file_priv->mm.lock); |
John Harrison | fcfa423c | 2015-05-29 17:44:12 +0100 | [diff] [blame] | 1394 | |
| 1395 | put_pid(request->pid); |
| 1396 | request->pid = NULL; |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1397 | } |
| 1398 | |
| 1399 | static void i915_gem_request_retire(struct drm_i915_gem_request *request) |
| 1400 | { |
| 1401 | trace_i915_gem_request_retire(request); |
| 1402 | |
| 1403 | /* We know the GPU must have read the request to have |
| 1404 | * sent us the seqno + interrupt, so use the position |
| 1405 | * of tail of the request to update the last known position |
| 1406 | * of the GPU head. |
| 1407 | * |
| 1408 | * Note this requires that we are always called in request |
| 1409 | * completion order. |
| 1410 | */ |
| 1411 | request->ringbuf->last_retired_head = request->postfix; |
| 1412 | |
| 1413 | list_del_init(&request->list); |
| 1414 | i915_gem_request_remove_from_client(request); |
| 1415 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1416 | i915_gem_request_unreference(request); |
| 1417 | } |
| 1418 | |
| 1419 | static void |
| 1420 | __i915_gem_request_retire__upto(struct drm_i915_gem_request *req) |
| 1421 | { |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 1422 | struct intel_engine_cs *engine = req->engine; |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1423 | struct drm_i915_gem_request *tmp; |
| 1424 | |
| 1425 | lockdep_assert_held(&engine->dev->struct_mutex); |
| 1426 | |
| 1427 | if (list_empty(&req->list)) |
| 1428 | return; |
| 1429 | |
| 1430 | do { |
| 1431 | tmp = list_first_entry(&engine->request_list, |
| 1432 | typeof(*tmp), list); |
| 1433 | |
| 1434 | i915_gem_request_retire(tmp); |
| 1435 | } while (tmp != req); |
| 1436 | |
| 1437 | WARN_ON(i915_verify_lists(engine->dev)); |
| 1438 | } |
| 1439 | |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1440 | /** |
Daniel Vetter | a4b3a57 | 2014-11-26 14:17:05 +0100 | [diff] [blame] | 1441 | * Waits for a request to be signaled, and cleans up the |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1442 | * request and object lists appropriately for that event. |
| 1443 | */ |
| 1444 | int |
Daniel Vetter | a4b3a57 | 2014-11-26 14:17:05 +0100 | [diff] [blame] | 1445 | i915_wait_request(struct drm_i915_gem_request *req) |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1446 | { |
Tvrtko Ursulin | 791bee1 | 2016-04-19 16:46:09 +0100 | [diff] [blame] | 1447 | struct drm_i915_private *dev_priv = req->i915; |
Daniel Vetter | a4b3a57 | 2014-11-26 14:17:05 +0100 | [diff] [blame] | 1448 | bool interruptible; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1449 | int ret; |
| 1450 | |
Daniel Vetter | a4b3a57 | 2014-11-26 14:17:05 +0100 | [diff] [blame] | 1451 | interruptible = dev_priv->mm.interruptible; |
| 1452 | |
Tvrtko Ursulin | 791bee1 | 2016-04-19 16:46:09 +0100 | [diff] [blame] | 1453 | BUG_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex)); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1454 | |
Chris Wilson | 299259a | 2016-04-13 17:35:06 +0100 | [diff] [blame] | 1455 | ret = __i915_wait_request(req, interruptible, NULL, NULL); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1456 | if (ret) |
| 1457 | return ret; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1458 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1459 | __i915_gem_request_retire__upto(req); |
Chris Wilson | d26e3af | 2013-06-29 22:05:26 +0100 | [diff] [blame] | 1460 | return 0; |
| 1461 | } |
| 1462 | |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1463 | /** |
| 1464 | * Ensures that all rendering to the object has completed and the object is |
| 1465 | * safe to unbind from the GTT or access from the CPU. |
| 1466 | */ |
Chris Wilson | 2e2f351 | 2015-04-27 13:41:14 +0100 | [diff] [blame] | 1467 | int |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1468 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
| 1469 | bool readonly) |
| 1470 | { |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1471 | int ret, i; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1472 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1473 | if (!obj->active) |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1474 | return 0; |
| 1475 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1476 | if (readonly) { |
| 1477 | if (obj->last_write_req != NULL) { |
| 1478 | ret = i915_wait_request(obj->last_write_req); |
| 1479 | if (ret) |
| 1480 | return ret; |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1481 | |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 1482 | i = obj->last_write_req->engine->id; |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1483 | if (obj->last_read_req[i] == obj->last_write_req) |
| 1484 | i915_gem_object_retire__read(obj, i); |
| 1485 | else |
| 1486 | i915_gem_object_retire__write(obj); |
| 1487 | } |
| 1488 | } else { |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 1489 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1490 | if (obj->last_read_req[i] == NULL) |
| 1491 | continue; |
| 1492 | |
| 1493 | ret = i915_wait_request(obj->last_read_req[i]); |
| 1494 | if (ret) |
| 1495 | return ret; |
| 1496 | |
| 1497 | i915_gem_object_retire__read(obj, i); |
| 1498 | } |
Chris Wilson | d501b1d | 2016-04-13 17:35:02 +0100 | [diff] [blame] | 1499 | GEM_BUG_ON(obj->active); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1500 | } |
| 1501 | |
| 1502 | return 0; |
| 1503 | } |
| 1504 | |
| 1505 | static void |
| 1506 | i915_gem_object_retire_request(struct drm_i915_gem_object *obj, |
| 1507 | struct drm_i915_gem_request *req) |
| 1508 | { |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 1509 | int ring = req->engine->id; |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1510 | |
| 1511 | if (obj->last_read_req[ring] == req) |
| 1512 | i915_gem_object_retire__read(obj, ring); |
| 1513 | else if (obj->last_write_req == req) |
| 1514 | i915_gem_object_retire__write(obj); |
| 1515 | |
| 1516 | __i915_gem_request_retire__upto(req); |
Chris Wilson | b361237 | 2012-08-24 09:35:08 +0100 | [diff] [blame] | 1517 | } |
| 1518 | |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1519 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
| 1520 | * as the object state may change during this call. |
| 1521 | */ |
| 1522 | static __must_check int |
| 1523 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, |
Chris Wilson | 2e1b873 | 2015-04-27 13:41:22 +0100 | [diff] [blame] | 1524 | struct intel_rps_client *rps, |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1525 | bool readonly) |
| 1526 | { |
| 1527 | struct drm_device *dev = obj->base.dev; |
| 1528 | struct drm_i915_private *dev_priv = dev->dev_private; |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 1529 | struct drm_i915_gem_request *requests[I915_NUM_ENGINES]; |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1530 | int ret, i, n = 0; |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1531 | |
| 1532 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 1533 | BUG_ON(!dev_priv->mm.interruptible); |
| 1534 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1535 | if (!obj->active) |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1536 | return 0; |
| 1537 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1538 | if (readonly) { |
| 1539 | struct drm_i915_gem_request *req; |
| 1540 | |
| 1541 | req = obj->last_write_req; |
| 1542 | if (req == NULL) |
| 1543 | return 0; |
| 1544 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1545 | requests[n++] = i915_gem_request_reference(req); |
| 1546 | } else { |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 1547 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1548 | struct drm_i915_gem_request *req; |
| 1549 | |
| 1550 | req = obj->last_read_req[i]; |
| 1551 | if (req == NULL) |
| 1552 | continue; |
| 1553 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1554 | requests[n++] = i915_gem_request_reference(req); |
| 1555 | } |
| 1556 | } |
| 1557 | |
| 1558 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 299259a | 2016-04-13 17:35:06 +0100 | [diff] [blame] | 1559 | ret = 0; |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1560 | for (i = 0; ret == 0 && i < n; i++) |
Chris Wilson | 299259a | 2016-04-13 17:35:06 +0100 | [diff] [blame] | 1561 | ret = __i915_wait_request(requests[i], true, NULL, rps); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1562 | mutex_lock(&dev->struct_mutex); |
| 1563 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 1564 | for (i = 0; i < n; i++) { |
| 1565 | if (ret == 0) |
| 1566 | i915_gem_object_retire_request(obj, requests[i]); |
| 1567 | i915_gem_request_unreference(requests[i]); |
| 1568 | } |
| 1569 | |
| 1570 | return ret; |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1571 | } |
| 1572 | |
Chris Wilson | 2e1b873 | 2015-04-27 13:41:22 +0100 | [diff] [blame] | 1573 | static struct intel_rps_client *to_rps_client(struct drm_file *file) |
| 1574 | { |
| 1575 | struct drm_i915_file_private *fpriv = file->driver_priv; |
| 1576 | return &fpriv->rps; |
| 1577 | } |
| 1578 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1579 | /** |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1580 | * Called when user space prepares to use an object with the CPU, either |
| 1581 | * through the mmap ioctl's mapping or a GTT mapping. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1582 | */ |
| 1583 | int |
| 1584 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1585 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1586 | { |
| 1587 | struct drm_i915_gem_set_domain *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1588 | struct drm_i915_gem_object *obj; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1589 | uint32_t read_domains = args->read_domains; |
| 1590 | uint32_t write_domain = args->write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1591 | int ret; |
| 1592 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1593 | /* Only handle setting domains to types used by the CPU. */ |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1594 | if (write_domain & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1595 | return -EINVAL; |
| 1596 | |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1597 | if (read_domains & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1598 | return -EINVAL; |
| 1599 | |
| 1600 | /* Having something in the write domain implies it's in the read |
| 1601 | * domain, and only that read domain. Enforce that in the request. |
| 1602 | */ |
| 1603 | if (write_domain != 0 && read_domains != write_domain) |
| 1604 | return -EINVAL; |
| 1605 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1606 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1607 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1608 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1609 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1610 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 1611 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1612 | ret = -ENOENT; |
| 1613 | goto unlock; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1614 | } |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1615 | |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1616 | /* Try to flush the object off the GPU without holding the lock. |
| 1617 | * We will repeat the flush holding the lock in the normal manner |
| 1618 | * to catch cases where we are gazumped. |
| 1619 | */ |
Chris Wilson | 6e4930f | 2014-02-07 18:37:06 -0200 | [diff] [blame] | 1620 | ret = i915_gem_object_wait_rendering__nonblocking(obj, |
Chris Wilson | 2e1b873 | 2015-04-27 13:41:22 +0100 | [diff] [blame] | 1621 | to_rps_client(file), |
Chris Wilson | 6e4930f | 2014-02-07 18:37:06 -0200 | [diff] [blame] | 1622 | !write_domain); |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1623 | if (ret) |
| 1624 | goto unref; |
| 1625 | |
Chris Wilson | 43566de | 2015-01-02 16:29:29 +0530 | [diff] [blame] | 1626 | if (read_domains & I915_GEM_DOMAIN_GTT) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1627 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
Chris Wilson | 43566de | 2015-01-02 16:29:29 +0530 | [diff] [blame] | 1628 | else |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1629 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1630 | |
Daniel Vetter | 031b698 | 2015-06-26 19:35:16 +0200 | [diff] [blame] | 1631 | if (write_domain != 0) |
| 1632 | intel_fb_obj_invalidate(obj, |
| 1633 | write_domain == I915_GEM_DOMAIN_GTT ? |
| 1634 | ORIGIN_GTT : ORIGIN_CPU); |
| 1635 | |
Chris Wilson | 3236f57 | 2012-08-24 09:35:09 +0100 | [diff] [blame] | 1636 | unref: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1637 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1638 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1639 | mutex_unlock(&dev->struct_mutex); |
| 1640 | return ret; |
| 1641 | } |
| 1642 | |
| 1643 | /** |
| 1644 | * Called when user space has done writes to this buffer |
| 1645 | */ |
| 1646 | int |
| 1647 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1648 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1649 | { |
| 1650 | struct drm_i915_gem_sw_finish *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1651 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1652 | int ret = 0; |
| 1653 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1654 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1655 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1656 | return ret; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1657 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1658 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 1659 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1660 | ret = -ENOENT; |
| 1661 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1662 | } |
| 1663 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1664 | /* Pinned buffers may be scanout, so flush the cache */ |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 1665 | if (obj->pin_display) |
Daniel Vetter | e62b59e | 2015-01-21 14:53:48 +0100 | [diff] [blame] | 1666 | i915_gem_object_flush_cpu_write_domain(obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1667 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1668 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1669 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1670 | mutex_unlock(&dev->struct_mutex); |
| 1671 | return ret; |
| 1672 | } |
| 1673 | |
| 1674 | /** |
| 1675 | * Maps the contents of an object, returning the address it is mapped |
| 1676 | * into. |
| 1677 | * |
| 1678 | * While the mapping holds a reference on the contents of the object, it doesn't |
| 1679 | * imply a ref on the object itself. |
Daniel Vetter | 3436738 | 2014-10-16 12:28:18 +0200 | [diff] [blame] | 1680 | * |
| 1681 | * IMPORTANT: |
| 1682 | * |
| 1683 | * DRM driver writers who look a this function as an example for how to do GEM |
| 1684 | * mmap support, please don't implement mmap support like here. The modern way |
| 1685 | * to implement DRM mmap support is with an mmap offset ioctl (like |
| 1686 | * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly. |
| 1687 | * That way debug tooling like valgrind will understand what's going on, hiding |
| 1688 | * the mmap call in a driver private ioctl will break that. The i915 driver only |
| 1689 | * does cpu mmaps this way because we didn't know better. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1690 | */ |
| 1691 | int |
| 1692 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1693 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1694 | { |
| 1695 | struct drm_i915_gem_mmap *args = data; |
| 1696 | struct drm_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1697 | unsigned long addr; |
| 1698 | |
Akash Goel | 1816f92 | 2015-01-02 16:29:30 +0530 | [diff] [blame] | 1699 | if (args->flags & ~(I915_MMAP_WC)) |
| 1700 | return -EINVAL; |
| 1701 | |
| 1702 | if (args->flags & I915_MMAP_WC && !cpu_has_pat) |
| 1703 | return -ENODEV; |
| 1704 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1705 | obj = drm_gem_object_lookup(dev, file, args->handle); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1706 | if (obj == NULL) |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 1707 | return -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1708 | |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 1709 | /* prime objects have no backing filp to GEM mmap |
| 1710 | * pages from. |
| 1711 | */ |
| 1712 | if (!obj->filp) { |
| 1713 | drm_gem_object_unreference_unlocked(obj); |
| 1714 | return -EINVAL; |
| 1715 | } |
| 1716 | |
Linus Torvalds | 6be5ceb | 2012-04-20 17:13:58 -0700 | [diff] [blame] | 1717 | addr = vm_mmap(obj->filp, 0, args->size, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1718 | PROT_READ | PROT_WRITE, MAP_SHARED, |
| 1719 | args->offset); |
Akash Goel | 1816f92 | 2015-01-02 16:29:30 +0530 | [diff] [blame] | 1720 | if (args->flags & I915_MMAP_WC) { |
| 1721 | struct mm_struct *mm = current->mm; |
| 1722 | struct vm_area_struct *vma; |
| 1723 | |
| 1724 | down_write(&mm->mmap_sem); |
| 1725 | vma = find_vma(mm, addr); |
| 1726 | if (vma) |
| 1727 | vma->vm_page_prot = |
| 1728 | pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); |
| 1729 | else |
| 1730 | addr = -ENOMEM; |
| 1731 | up_write(&mm->mmap_sem); |
| 1732 | } |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 1733 | drm_gem_object_unreference_unlocked(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1734 | if (IS_ERR((void *)addr)) |
| 1735 | return addr; |
| 1736 | |
| 1737 | args->addr_ptr = (uint64_t) addr; |
| 1738 | |
| 1739 | return 0; |
| 1740 | } |
| 1741 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1742 | /** |
| 1743 | * i915_gem_fault - fault a page into the GTT |
Geliang Tang | d9072a3 | 2015-09-15 05:58:44 -0700 | [diff] [blame] | 1744 | * @vma: VMA in question |
| 1745 | * @vmf: fault info |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1746 | * |
| 1747 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped |
| 1748 | * from userspace. The fault handler takes care of binding the object to |
| 1749 | * the GTT (if needed), allocating and programming a fence register (again, |
| 1750 | * only if needed based on whether the old reg is still valid or the object |
| 1751 | * is tiled) and inserting a new PTE into the faulting process. |
| 1752 | * |
| 1753 | * Note that the faulting process may involve evicting existing objects |
| 1754 | * from the GTT and/or fence registers to make room. So performance may |
| 1755 | * suffer if the GTT working set is large or there are few fence registers |
| 1756 | * left. |
| 1757 | */ |
| 1758 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) |
| 1759 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1760 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
| 1761 | struct drm_device *dev = obj->base.dev; |
Joonas Lahtinen | 72e96d6 | 2016-03-30 16:57:10 +0300 | [diff] [blame] | 1762 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 1763 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
Joonas Lahtinen | c5ad54c | 2015-05-06 14:36:09 +0300 | [diff] [blame] | 1764 | struct i915_ggtt_view view = i915_ggtt_view_normal; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1765 | pgoff_t page_offset; |
| 1766 | unsigned long pfn; |
| 1767 | int ret = 0; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 1768 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1769 | |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 1770 | intel_runtime_pm_get(dev_priv); |
| 1771 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1772 | /* We don't use vmf->pgoff since that has the fake offset */ |
| 1773 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> |
| 1774 | PAGE_SHIFT; |
| 1775 | |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1776 | ret = i915_mutex_lock_interruptible(dev); |
| 1777 | if (ret) |
| 1778 | goto out; |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 1779 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1780 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
| 1781 | |
Chris Wilson | 6e4930f | 2014-02-07 18:37:06 -0200 | [diff] [blame] | 1782 | /* Try to flush the object off the GPU first without holding the lock. |
| 1783 | * Upon reacquiring the lock, we will perform our sanity checks and then |
| 1784 | * repeat the flush holding the lock in the normal manner to catch cases |
| 1785 | * where we are gazumped. |
| 1786 | */ |
| 1787 | ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write); |
| 1788 | if (ret) |
| 1789 | goto unlock; |
| 1790 | |
Chris Wilson | eb119bd | 2012-12-16 12:43:36 +0000 | [diff] [blame] | 1791 | /* Access to snoopable pages through the GTT is incoherent. */ |
| 1792 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { |
Chris Wilson | ddeff6e | 2014-05-28 16:16:41 +0100 | [diff] [blame] | 1793 | ret = -EFAULT; |
Chris Wilson | eb119bd | 2012-12-16 12:43:36 +0000 | [diff] [blame] | 1794 | goto unlock; |
| 1795 | } |
| 1796 | |
Joonas Lahtinen | c5ad54c | 2015-05-06 14:36:09 +0300 | [diff] [blame] | 1797 | /* Use a partial view if the object is bigger than the aperture. */ |
Joonas Lahtinen | 72e96d6 | 2016-03-30 16:57:10 +0300 | [diff] [blame] | 1798 | if (obj->base.size >= ggtt->mappable_end && |
Joonas Lahtinen | e7ded2d | 2015-05-08 14:37:39 +0300 | [diff] [blame] | 1799 | obj->tiling_mode == I915_TILING_NONE) { |
Joonas Lahtinen | c5ad54c | 2015-05-06 14:36:09 +0300 | [diff] [blame] | 1800 | static const unsigned int chunk_size = 256; // 1 MiB |
Joonas Lahtinen | e7ded2d | 2015-05-08 14:37:39 +0300 | [diff] [blame] | 1801 | |
Joonas Lahtinen | c5ad54c | 2015-05-06 14:36:09 +0300 | [diff] [blame] | 1802 | memset(&view, 0, sizeof(view)); |
| 1803 | view.type = I915_GGTT_VIEW_PARTIAL; |
| 1804 | view.params.partial.offset = rounddown(page_offset, chunk_size); |
| 1805 | view.params.partial.size = |
| 1806 | min_t(unsigned int, |
| 1807 | chunk_size, |
| 1808 | (vma->vm_end - vma->vm_start)/PAGE_SIZE - |
| 1809 | view.params.partial.offset); |
| 1810 | } |
| 1811 | |
| 1812 | /* Now pin it into the GTT if needed */ |
| 1813 | ret = i915_gem_object_ggtt_pin(obj, &view, 0, PIN_MAPPABLE); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 1814 | if (ret) |
| 1815 | goto unlock; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1816 | |
Chris Wilson | c983930 | 2012-11-20 10:45:17 +0000 | [diff] [blame] | 1817 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
| 1818 | if (ret) |
| 1819 | goto unpin; |
| 1820 | |
| 1821 | ret = i915_gem_object_get_fence(obj); |
| 1822 | if (ret) |
| 1823 | goto unpin; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1824 | |
Chris Wilson | b90b91d | 2014-06-10 12:14:40 +0100 | [diff] [blame] | 1825 | /* Finally, remap it using the new GTT offset */ |
Joonas Lahtinen | 72e96d6 | 2016-03-30 16:57:10 +0300 | [diff] [blame] | 1826 | pfn = ggtt->mappable_base + |
Joonas Lahtinen | c5ad54c | 2015-05-06 14:36:09 +0300 | [diff] [blame] | 1827 | i915_gem_obj_ggtt_offset_view(obj, &view); |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 1828 | pfn >>= PAGE_SHIFT; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1829 | |
Joonas Lahtinen | c5ad54c | 2015-05-06 14:36:09 +0300 | [diff] [blame] | 1830 | if (unlikely(view.type == I915_GGTT_VIEW_PARTIAL)) { |
| 1831 | /* Overriding existing pages in partial view does not cause |
| 1832 | * us any trouble as TLBs are still valid because the fault |
| 1833 | * is due to userspace losing part of the mapping or never |
| 1834 | * having accessed it before (at this partials' range). |
| 1835 | */ |
| 1836 | unsigned long base = vma->vm_start + |
| 1837 | (view.params.partial.offset << PAGE_SHIFT); |
| 1838 | unsigned int i; |
Chris Wilson | b90b91d | 2014-06-10 12:14:40 +0100 | [diff] [blame] | 1839 | |
Joonas Lahtinen | c5ad54c | 2015-05-06 14:36:09 +0300 | [diff] [blame] | 1840 | for (i = 0; i < view.params.partial.size; i++) { |
| 1841 | ret = vm_insert_pfn(vma, base + i * PAGE_SIZE, pfn + i); |
Chris Wilson | b90b91d | 2014-06-10 12:14:40 +0100 | [diff] [blame] | 1842 | if (ret) |
| 1843 | break; |
| 1844 | } |
| 1845 | |
| 1846 | obj->fault_mappable = true; |
Joonas Lahtinen | c5ad54c | 2015-05-06 14:36:09 +0300 | [diff] [blame] | 1847 | } else { |
| 1848 | if (!obj->fault_mappable) { |
| 1849 | unsigned long size = min_t(unsigned long, |
| 1850 | vma->vm_end - vma->vm_start, |
| 1851 | obj->base.size); |
| 1852 | int i; |
| 1853 | |
| 1854 | for (i = 0; i < size >> PAGE_SHIFT; i++) { |
| 1855 | ret = vm_insert_pfn(vma, |
| 1856 | (unsigned long)vma->vm_start + i * PAGE_SIZE, |
| 1857 | pfn + i); |
| 1858 | if (ret) |
| 1859 | break; |
| 1860 | } |
| 1861 | |
| 1862 | obj->fault_mappable = true; |
| 1863 | } else |
| 1864 | ret = vm_insert_pfn(vma, |
| 1865 | (unsigned long)vmf->virtual_address, |
| 1866 | pfn + page_offset); |
| 1867 | } |
Chris Wilson | c983930 | 2012-11-20 10:45:17 +0000 | [diff] [blame] | 1868 | unpin: |
Joonas Lahtinen | c5ad54c | 2015-05-06 14:36:09 +0300 | [diff] [blame] | 1869 | i915_gem_object_ggtt_unpin_view(obj, &view); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1870 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1871 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1872 | out: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1873 | switch (ret) { |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1874 | case -EIO: |
Daniel Vetter | 2232f03 | 2014-09-04 09:36:18 +0200 | [diff] [blame] | 1875 | /* |
| 1876 | * We eat errors when the gpu is terminally wedged to avoid |
| 1877 | * userspace unduly crashing (gl has no provisions for mmaps to |
| 1878 | * fail). But any other -EIO isn't ours (e.g. swap in failure) |
| 1879 | * and so needs to be reported. |
| 1880 | */ |
| 1881 | if (!i915_terminally_wedged(&dev_priv->gpu_error)) { |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 1882 | ret = VM_FAULT_SIGBUS; |
| 1883 | break; |
| 1884 | } |
Chris Wilson | 045e769 | 2010-11-07 09:18:22 +0000 | [diff] [blame] | 1885 | case -EAGAIN: |
Daniel Vetter | 571c608 | 2013-09-12 17:57:28 +0200 | [diff] [blame] | 1886 | /* |
| 1887 | * EAGAIN means the gpu is hung and we'll wait for the error |
| 1888 | * handler to reset everything when re-faulting in |
| 1889 | * i915_mutex_lock_interruptible. |
Chris Wilson | d9bc7e9 | 2011-02-07 13:09:31 +0000 | [diff] [blame] | 1890 | */ |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1891 | case 0: |
| 1892 | case -ERESTARTSYS: |
Chris Wilson | bed636a | 2011-02-11 20:31:19 +0000 | [diff] [blame] | 1893 | case -EINTR: |
Dmitry Rogozhkin | e79e0fe | 2012-10-03 17:15:26 +0300 | [diff] [blame] | 1894 | case -EBUSY: |
| 1895 | /* |
| 1896 | * EBUSY is ok: this just means that another thread |
| 1897 | * already did the job. |
| 1898 | */ |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 1899 | ret = VM_FAULT_NOPAGE; |
| 1900 | break; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1901 | case -ENOMEM: |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 1902 | ret = VM_FAULT_OOM; |
| 1903 | break; |
Daniel Vetter | a7c2e1a | 2012-10-17 11:17:16 +0200 | [diff] [blame] | 1904 | case -ENOSPC: |
Chris Wilson | 45d6781 | 2014-01-31 11:34:57 +0000 | [diff] [blame] | 1905 | case -EFAULT: |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 1906 | ret = VM_FAULT_SIGBUS; |
| 1907 | break; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1908 | default: |
Daniel Vetter | a7c2e1a | 2012-10-17 11:17:16 +0200 | [diff] [blame] | 1909 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 1910 | ret = VM_FAULT_SIGBUS; |
| 1911 | break; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1912 | } |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 1913 | |
| 1914 | intel_runtime_pm_put(dev_priv); |
| 1915 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1916 | } |
| 1917 | |
| 1918 | /** |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1919 | * i915_gem_release_mmap - remove physical page mappings |
| 1920 | * @obj: obj in question |
| 1921 | * |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 1922 | * Preserve the reservation of the mmapping with the DRM core code, but |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1923 | * relinquish ownership of the pages back to the system. |
| 1924 | * |
| 1925 | * It is vital that we remove the page mapping if we have mapped a tiled |
| 1926 | * object through the GTT and then lose the fence register due to |
| 1927 | * resource pressure. Similarly if the object has been moved out of the |
| 1928 | * aperture, than pages mapped into userspace must be revoked. Removing the |
| 1929 | * mapping will then trigger a page fault on the next user access, allowing |
| 1930 | * fixup by i915_gem_fault(). |
| 1931 | */ |
Eric Anholt | d05ca30 | 2009-07-10 13:02:26 -0700 | [diff] [blame] | 1932 | void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1933 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1934 | { |
Chris Wilson | 349f2cc | 2016-04-13 17:35:12 +0100 | [diff] [blame] | 1935 | /* Serialisation between user GTT access and our code depends upon |
| 1936 | * revoking the CPU's PTE whilst the mutex is held. The next user |
| 1937 | * pagefault then has to wait until we release the mutex. |
| 1938 | */ |
| 1939 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
| 1940 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1941 | if (!obj->fault_mappable) |
| 1942 | return; |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1943 | |
David Herrmann | 6796cb1 | 2014-01-03 14:24:19 +0100 | [diff] [blame] | 1944 | drm_vma_node_unmap(&obj->base.vma_node, |
| 1945 | obj->base.dev->anon_inode->i_mapping); |
Chris Wilson | 349f2cc | 2016-04-13 17:35:12 +0100 | [diff] [blame] | 1946 | |
| 1947 | /* Ensure that the CPU's PTE are revoked and there are not outstanding |
| 1948 | * memory transactions from userspace before we return. The TLB |
| 1949 | * flushing implied above by changing the PTE above *should* be |
| 1950 | * sufficient, an extra barrier here just provides us with a bit |
| 1951 | * of paranoid documentation about our requirement to serialise |
| 1952 | * memory writes before touching registers / GSM. |
| 1953 | */ |
| 1954 | wmb(); |
| 1955 | |
Chris Wilson | 6299f99 | 2010-11-24 12:23:44 +0000 | [diff] [blame] | 1956 | obj->fault_mappable = false; |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1957 | } |
| 1958 | |
Chris Wilson | eedd10f | 2014-06-16 08:57:44 +0100 | [diff] [blame] | 1959 | void |
| 1960 | i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv) |
| 1961 | { |
| 1962 | struct drm_i915_gem_object *obj; |
| 1963 | |
| 1964 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
| 1965 | i915_gem_release_mmap(obj); |
| 1966 | } |
| 1967 | |
Imre Deak | 0fa8779 | 2013-01-07 21:47:35 +0200 | [diff] [blame] | 1968 | uint32_t |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1969 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1970 | { |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1971 | uint32_t gtt_size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1972 | |
| 1973 | if (INTEL_INFO(dev)->gen >= 4 || |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1974 | tiling_mode == I915_TILING_NONE) |
| 1975 | return size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1976 | |
| 1977 | /* Previous chips need a power-of-two fence region when tiling */ |
| 1978 | if (INTEL_INFO(dev)->gen == 3) |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1979 | gtt_size = 1024*1024; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1980 | else |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1981 | gtt_size = 512*1024; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1982 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1983 | while (gtt_size < size) |
| 1984 | gtt_size <<= 1; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1985 | |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 1986 | return gtt_size; |
Chris Wilson | 92b88ae | 2010-11-09 11:47:32 +0000 | [diff] [blame] | 1987 | } |
| 1988 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1989 | /** |
| 1990 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object |
| 1991 | * @obj: object to check |
| 1992 | * |
| 1993 | * Return the required GTT alignment for an object, taking into account |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 1994 | * potential fence register mapping. |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1995 | */ |
Imre Deak | d865110 | 2013-01-07 21:47:33 +0200 | [diff] [blame] | 1996 | uint32_t |
| 1997 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
| 1998 | int tiling_mode, bool fenced) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1999 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2000 | /* |
| 2001 | * Minimum alignment is 4k (GTT page size), but might be greater |
| 2002 | * if a fence register is needed for the object. |
| 2003 | */ |
Imre Deak | d865110 | 2013-01-07 21:47:33 +0200 | [diff] [blame] | 2004 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 2005 | tiling_mode == I915_TILING_NONE) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2006 | return 4096; |
| 2007 | |
| 2008 | /* |
| 2009 | * Previous chips need to be aligned to the size of the smallest |
| 2010 | * fence register that can contain the object. |
| 2011 | */ |
Chris Wilson | e28f871 | 2011-07-18 13:11:49 -0700 | [diff] [blame] | 2012 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 2013 | } |
| 2014 | |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 2015 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
| 2016 | { |
| 2017 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 2018 | int ret; |
| 2019 | |
David Herrmann | 0de2397 | 2013-07-24 21:07:52 +0200 | [diff] [blame] | 2020 | if (drm_vma_node_has_offset(&obj->base.vma_node)) |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 2021 | return 0; |
| 2022 | |
Daniel Vetter | da494d7 | 2012-12-20 15:11:16 +0100 | [diff] [blame] | 2023 | dev_priv->mm.shrinker_no_lock_stealing = true; |
| 2024 | |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 2025 | ret = drm_gem_create_mmap_offset(&obj->base); |
| 2026 | if (ret != -ENOSPC) |
Daniel Vetter | da494d7 | 2012-12-20 15:11:16 +0100 | [diff] [blame] | 2027 | goto out; |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 2028 | |
| 2029 | /* Badly fragmented mmap space? The only way we can recover |
| 2030 | * space is by destroying unwanted objects. We can't randomly release |
| 2031 | * mmap_offsets as userspace expects them to be persistent for the |
| 2032 | * lifetime of the objects. The closest we can is to release the |
| 2033 | * offsets on purgeable objects by truncating it and marking it purged, |
| 2034 | * which prevents userspace from ever using that object again. |
| 2035 | */ |
Chris Wilson | 21ab4e7 | 2014-09-09 11:16:08 +0100 | [diff] [blame] | 2036 | i915_gem_shrink(dev_priv, |
| 2037 | obj->base.size >> PAGE_SHIFT, |
| 2038 | I915_SHRINK_BOUND | |
| 2039 | I915_SHRINK_UNBOUND | |
| 2040 | I915_SHRINK_PURGEABLE); |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 2041 | ret = drm_gem_create_mmap_offset(&obj->base); |
| 2042 | if (ret != -ENOSPC) |
Daniel Vetter | da494d7 | 2012-12-20 15:11:16 +0100 | [diff] [blame] | 2043 | goto out; |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 2044 | |
| 2045 | i915_gem_shrink_all(dev_priv); |
Daniel Vetter | da494d7 | 2012-12-20 15:11:16 +0100 | [diff] [blame] | 2046 | ret = drm_gem_create_mmap_offset(&obj->base); |
| 2047 | out: |
| 2048 | dev_priv->mm.shrinker_no_lock_stealing = false; |
| 2049 | |
| 2050 | return ret; |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 2051 | } |
| 2052 | |
| 2053 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) |
| 2054 | { |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 2055 | drm_gem_free_mmap_offset(&obj->base); |
| 2056 | } |
| 2057 | |
Dave Airlie | da6b51d | 2014-12-24 13:11:17 +1000 | [diff] [blame] | 2058 | int |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 2059 | i915_gem_mmap_gtt(struct drm_file *file, |
| 2060 | struct drm_device *dev, |
Dave Airlie | da6b51d | 2014-12-24 13:11:17 +1000 | [diff] [blame] | 2061 | uint32_t handle, |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 2062 | uint64_t *offset) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2063 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2064 | struct drm_i915_gem_object *obj; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2065 | int ret; |
| 2066 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 2067 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 2068 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 2069 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2070 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 2071 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 2072 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 2073 | ret = -ENOENT; |
| 2074 | goto unlock; |
| 2075 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2076 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2077 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | bd9b6a4 | 2014-02-10 09:03:50 +0000 | [diff] [blame] | 2078 | DRM_DEBUG("Attempting to mmap a purgeable buffer\n"); |
Chris Wilson | 8c99e57 | 2014-01-31 11:34:58 +0000 | [diff] [blame] | 2079 | ret = -EFAULT; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 2080 | goto out; |
Chris Wilson | ab18282 | 2009-09-22 18:46:17 +0100 | [diff] [blame] | 2081 | } |
| 2082 | |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 2083 | ret = i915_gem_object_create_mmap_offset(obj); |
| 2084 | if (ret) |
| 2085 | goto out; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2086 | |
David Herrmann | 0de2397 | 2013-07-24 21:07:52 +0200 | [diff] [blame] | 2087 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2088 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 2089 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2090 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 2091 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2092 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 2093 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2094 | } |
| 2095 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 2096 | /** |
| 2097 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing |
| 2098 | * @dev: DRM device |
| 2099 | * @data: GTT mapping ioctl data |
| 2100 | * @file: GEM object info |
| 2101 | * |
| 2102 | * Simply returns the fake offset to userspace so it can mmap it. |
| 2103 | * The mmap call will end up in drm_gem_mmap(), which will set things |
| 2104 | * up so we can get faults in the handler above. |
| 2105 | * |
| 2106 | * The fault handler will take care of binding the object into the GTT |
| 2107 | * (since it may have been evicted to make room for something), allocating |
| 2108 | * a fence register, and mapping the appropriate aperture address into |
| 2109 | * userspace. |
| 2110 | */ |
| 2111 | int |
| 2112 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
| 2113 | struct drm_file *file) |
| 2114 | { |
| 2115 | struct drm_i915_gem_mmap_gtt *args = data; |
| 2116 | |
Dave Airlie | da6b51d | 2014-12-24 13:11:17 +1000 | [diff] [blame] | 2117 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 2118 | } |
| 2119 | |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 2120 | /* Immediately discard the backing storage */ |
| 2121 | static void |
| 2122 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2123 | { |
Chris Wilson | 4d6294bf | 2012-08-11 15:41:05 +0100 | [diff] [blame] | 2124 | i915_gem_object_free_mmap_offset(obj); |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 2125 | |
Chris Wilson | 4d6294bf | 2012-08-11 15:41:05 +0100 | [diff] [blame] | 2126 | if (obj->base.filp == NULL) |
| 2127 | return; |
| 2128 | |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 2129 | /* Our goal here is to return as much of the memory as |
| 2130 | * is possible back to the system as we are called from OOM. |
| 2131 | * To do this we must instruct the shmfs to drop all of its |
| 2132 | * backing pages, *now*. |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2133 | */ |
Chris Wilson | 5537252 | 2014-03-25 13:23:06 +0000 | [diff] [blame] | 2134 | shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 2135 | obj->madv = __I915_MADV_PURGED; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2136 | } |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2137 | |
Chris Wilson | 5537252 | 2014-03-25 13:23:06 +0000 | [diff] [blame] | 2138 | /* Try to discard unwanted pages */ |
| 2139 | static void |
| 2140 | i915_gem_object_invalidate(struct drm_i915_gem_object *obj) |
Daniel Vetter | 225067e | 2012-08-20 10:23:20 +0200 | [diff] [blame] | 2141 | { |
Chris Wilson | 5537252 | 2014-03-25 13:23:06 +0000 | [diff] [blame] | 2142 | struct address_space *mapping; |
| 2143 | |
| 2144 | switch (obj->madv) { |
| 2145 | case I915_MADV_DONTNEED: |
| 2146 | i915_gem_object_truncate(obj); |
| 2147 | case __I915_MADV_PURGED: |
| 2148 | return; |
| 2149 | } |
| 2150 | |
| 2151 | if (obj->base.filp == NULL) |
| 2152 | return; |
| 2153 | |
| 2154 | mapping = file_inode(obj->base.filp)->i_mapping, |
| 2155 | invalidate_mapping_pages(mapping, 0, (loff_t)-1); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2156 | } |
| 2157 | |
Chris Wilson | 5cdf588 | 2010-09-27 15:51:07 +0100 | [diff] [blame] | 2158 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2159 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2160 | { |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 2161 | struct sg_page_iter sg_iter; |
| 2162 | int ret; |
Daniel Vetter | 1286ff7 | 2012-05-10 15:25:09 +0200 | [diff] [blame] | 2163 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2164 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2165 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2166 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
Chris Wilson | f4457ae | 2016-04-13 17:35:08 +0100 | [diff] [blame] | 2167 | if (WARN_ON(ret)) { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2168 | /* In the event of a disaster, abandon all caches and |
| 2169 | * hope for the best. |
| 2170 | */ |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 2171 | i915_gem_clflush_object(obj, true); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2172 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 2173 | } |
| 2174 | |
Imre Deak | e227330 | 2015-07-09 12:59:05 +0300 | [diff] [blame] | 2175 | i915_gem_gtt_finish_object(obj); |
| 2176 | |
Daniel Vetter | 6dacfd2 | 2011-09-12 21:30:02 +0200 | [diff] [blame] | 2177 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 2178 | i915_gem_object_save_bit_17_swizzle(obj); |
| 2179 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2180 | if (obj->madv == I915_MADV_DONTNEED) |
| 2181 | obj->dirty = 0; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 2182 | |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 2183 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
Imre Deak | 2db76d7 | 2013-03-26 15:14:18 +0200 | [diff] [blame] | 2184 | struct page *page = sg_page_iter_page(&sg_iter); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2185 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2186 | if (obj->dirty) |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2187 | set_page_dirty(page); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 2188 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2189 | if (obj->madv == I915_MADV_WILLNEED) |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2190 | mark_page_accessed(page); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 2191 | |
Kirill A. Shutemov | 09cbfea | 2016-04-01 15:29:47 +0300 | [diff] [blame] | 2192 | put_page(page); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 2193 | } |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2194 | obj->dirty = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2195 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2196 | sg_free_table(obj->pages); |
| 2197 | kfree(obj->pages); |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2198 | } |
| 2199 | |
Chris Wilson | dd624af | 2013-01-15 12:39:35 +0000 | [diff] [blame] | 2200 | int |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2201 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
| 2202 | { |
| 2203 | const struct drm_i915_gem_object_ops *ops = obj->ops; |
| 2204 | |
Chris Wilson | 2f745ad | 2012-09-04 21:02:58 +0100 | [diff] [blame] | 2205 | if (obj->pages == NULL) |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2206 | return 0; |
| 2207 | |
Chris Wilson | a557017 | 2012-09-04 21:02:54 +0100 | [diff] [blame] | 2208 | if (obj->pages_pin_count) |
| 2209 | return -EBUSY; |
| 2210 | |
Ben Widawsky | 9843877 | 2013-07-31 17:00:12 -0700 | [diff] [blame] | 2211 | BUG_ON(i915_gem_obj_bound_any(obj)); |
Ben Widawsky | 3e12302 | 2013-07-31 17:00:04 -0700 | [diff] [blame] | 2212 | |
Chris Wilson | a2165e3 | 2012-12-03 11:49:00 +0000 | [diff] [blame] | 2213 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
| 2214 | * array, hence protect them from being reaped by removing them from gtt |
| 2215 | * lists early. */ |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 2216 | list_del(&obj->global_list); |
Chris Wilson | a2165e3 | 2012-12-03 11:49:00 +0000 | [diff] [blame] | 2217 | |
Chris Wilson | 0a798eb | 2016-04-08 12:11:11 +0100 | [diff] [blame] | 2218 | if (obj->mapping) { |
Chris Wilson | fb8621d | 2016-04-08 12:11:14 +0100 | [diff] [blame] | 2219 | if (is_vmalloc_addr(obj->mapping)) |
| 2220 | vunmap(obj->mapping); |
| 2221 | else |
| 2222 | kunmap(kmap_to_page(obj->mapping)); |
Chris Wilson | 0a798eb | 2016-04-08 12:11:11 +0100 | [diff] [blame] | 2223 | obj->mapping = NULL; |
| 2224 | } |
| 2225 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2226 | ops->put_pages(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2227 | obj->pages = NULL; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2228 | |
Chris Wilson | 5537252 | 2014-03-25 13:23:06 +0000 | [diff] [blame] | 2229 | i915_gem_object_invalidate(obj); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2230 | |
| 2231 | return 0; |
| 2232 | } |
| 2233 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2234 | static int |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2235 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2236 | { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2237 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2238 | int page_count, i; |
| 2239 | struct address_space *mapping; |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2240 | struct sg_table *st; |
| 2241 | struct scatterlist *sg; |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 2242 | struct sg_page_iter sg_iter; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2243 | struct page *page; |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 2244 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
Imre Deak | e227330 | 2015-07-09 12:59:05 +0300 | [diff] [blame] | 2245 | int ret; |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2246 | gfp_t gfp; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2247 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2248 | /* Assert that the object is not currently in any GPU domain. As it |
| 2249 | * wasn't in the GTT, there shouldn't be any way it could have been in |
| 2250 | * a GPU cache |
| 2251 | */ |
| 2252 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
| 2253 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); |
| 2254 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2255 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
| 2256 | if (st == NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2257 | return -ENOMEM; |
| 2258 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2259 | page_count = obj->base.size / PAGE_SIZE; |
| 2260 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2261 | kfree(st); |
| 2262 | return -ENOMEM; |
| 2263 | } |
| 2264 | |
| 2265 | /* Get the list of pages out of our struct file. They'll be pinned |
| 2266 | * at this point until we release them. |
| 2267 | * |
| 2268 | * Fail silently without starting the shrinker |
| 2269 | */ |
Al Viro | 496ad9a | 2013-01-23 17:07:38 -0500 | [diff] [blame] | 2270 | mapping = file_inode(obj->base.filp)->i_mapping; |
Michal Hocko | c62d255 | 2015-11-06 16:28:49 -0800 | [diff] [blame] | 2271 | gfp = mapping_gfp_constraint(mapping, ~(__GFP_IO | __GFP_RECLAIM)); |
Mel Gorman | d0164ad | 2015-11-06 16:28:21 -0800 | [diff] [blame] | 2272 | gfp |= __GFP_NORETRY | __GFP_NOWARN; |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 2273 | sg = st->sgl; |
| 2274 | st->nents = 0; |
| 2275 | for (i = 0; i < page_count; i++) { |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2276 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
| 2277 | if (IS_ERR(page)) { |
Chris Wilson | 21ab4e7 | 2014-09-09 11:16:08 +0100 | [diff] [blame] | 2278 | i915_gem_shrink(dev_priv, |
| 2279 | page_count, |
| 2280 | I915_SHRINK_BOUND | |
| 2281 | I915_SHRINK_UNBOUND | |
| 2282 | I915_SHRINK_PURGEABLE); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2283 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
| 2284 | } |
| 2285 | if (IS_ERR(page)) { |
| 2286 | /* We've tried hard to allocate the memory by reaping |
| 2287 | * our own buffer, now let the real VM do its job and |
| 2288 | * go down in flames if truly OOM. |
| 2289 | */ |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2290 | i915_gem_shrink_all(dev_priv); |
David Herrmann | f461d1b | 2014-05-25 14:34:10 +0200 | [diff] [blame] | 2291 | page = shmem_read_mapping_page(mapping, i); |
Imre Deak | e227330 | 2015-07-09 12:59:05 +0300 | [diff] [blame] | 2292 | if (IS_ERR(page)) { |
| 2293 | ret = PTR_ERR(page); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2294 | goto err_pages; |
Imre Deak | e227330 | 2015-07-09 12:59:05 +0300 | [diff] [blame] | 2295 | } |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 2296 | } |
Konrad Rzeszutek Wilk | 426729d | 2013-06-24 11:47:48 -0400 | [diff] [blame] | 2297 | #ifdef CONFIG_SWIOTLB |
| 2298 | if (swiotlb_nr_tbl()) { |
| 2299 | st->nents++; |
| 2300 | sg_set_page(sg, page, PAGE_SIZE, 0); |
| 2301 | sg = sg_next(sg); |
| 2302 | continue; |
| 2303 | } |
| 2304 | #endif |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 2305 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
| 2306 | if (i) |
| 2307 | sg = sg_next(sg); |
| 2308 | st->nents++; |
| 2309 | sg_set_page(sg, page, PAGE_SIZE, 0); |
| 2310 | } else { |
| 2311 | sg->length += PAGE_SIZE; |
| 2312 | } |
| 2313 | last_pfn = page_to_pfn(page); |
Daniel Vetter | 3bbbe70 | 2013-10-07 17:15:45 -0300 | [diff] [blame] | 2314 | |
| 2315 | /* Check that the i965g/gm workaround works. */ |
| 2316 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2317 | } |
Konrad Rzeszutek Wilk | 426729d | 2013-06-24 11:47:48 -0400 | [diff] [blame] | 2318 | #ifdef CONFIG_SWIOTLB |
| 2319 | if (!swiotlb_nr_tbl()) |
| 2320 | #endif |
| 2321 | sg_mark_end(sg); |
Chris Wilson | 74ce6b6 | 2012-10-19 15:51:06 +0100 | [diff] [blame] | 2322 | obj->pages = st; |
| 2323 | |
Imre Deak | e227330 | 2015-07-09 12:59:05 +0300 | [diff] [blame] | 2324 | ret = i915_gem_gtt_prepare_object(obj); |
| 2325 | if (ret) |
| 2326 | goto err_pages; |
| 2327 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2328 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
| 2329 | i915_gem_object_do_bit_17_swizzle(obj); |
| 2330 | |
Daniel Vetter | 656bfa3 | 2014-11-20 09:26:30 +0100 | [diff] [blame] | 2331 | if (obj->tiling_mode != I915_TILING_NONE && |
| 2332 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) |
| 2333 | i915_gem_object_pin_pages(obj); |
| 2334 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2335 | return 0; |
| 2336 | |
| 2337 | err_pages: |
Imre Deak | 90797e6 | 2013-02-18 19:28:03 +0200 | [diff] [blame] | 2338 | sg_mark_end(sg); |
| 2339 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) |
Kirill A. Shutemov | 09cbfea | 2016-04-01 15:29:47 +0300 | [diff] [blame] | 2340 | put_page(sg_page_iter_page(&sg_iter)); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2341 | sg_free_table(st); |
| 2342 | kfree(st); |
Chris Wilson | 0820baf | 2014-03-25 13:23:03 +0000 | [diff] [blame] | 2343 | |
| 2344 | /* shmemfs first checks if there is enough memory to allocate the page |
| 2345 | * and reports ENOSPC should there be insufficient, along with the usual |
| 2346 | * ENOMEM for a genuine allocation failure. |
| 2347 | * |
| 2348 | * We use ENOSPC in our driver to mean that we have run out of aperture |
| 2349 | * space and so want to translate the error from shmemfs back to our |
| 2350 | * usual understanding of ENOMEM. |
| 2351 | */ |
Imre Deak | e227330 | 2015-07-09 12:59:05 +0300 | [diff] [blame] | 2352 | if (ret == -ENOSPC) |
| 2353 | ret = -ENOMEM; |
| 2354 | |
| 2355 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2356 | } |
| 2357 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2358 | /* Ensure that the associated pages are gathered from the backing storage |
| 2359 | * and pinned into our object. i915_gem_object_get_pages() may be called |
| 2360 | * multiple times before they are released by a single call to |
| 2361 | * i915_gem_object_put_pages() - once the pages are no longer referenced |
| 2362 | * either as a result of memory pressure (reaping pages under the shrinker) |
| 2363 | * or as the object is itself released. |
| 2364 | */ |
| 2365 | int |
| 2366 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) |
| 2367 | { |
| 2368 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
| 2369 | const struct drm_i915_gem_object_ops *ops = obj->ops; |
| 2370 | int ret; |
| 2371 | |
Chris Wilson | 2f745ad | 2012-09-04 21:02:58 +0100 | [diff] [blame] | 2372 | if (obj->pages) |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2373 | return 0; |
| 2374 | |
Chris Wilson | 43e28f0 | 2013-01-08 10:53:09 +0000 | [diff] [blame] | 2375 | if (obj->madv != I915_MADV_WILLNEED) { |
Chris Wilson | bd9b6a4 | 2014-02-10 09:03:50 +0000 | [diff] [blame] | 2376 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); |
Chris Wilson | 8c99e57 | 2014-01-31 11:34:58 +0000 | [diff] [blame] | 2377 | return -EFAULT; |
Chris Wilson | 43e28f0 | 2013-01-08 10:53:09 +0000 | [diff] [blame] | 2378 | } |
| 2379 | |
Chris Wilson | a557017 | 2012-09-04 21:02:54 +0100 | [diff] [blame] | 2380 | BUG_ON(obj->pages_pin_count); |
| 2381 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2382 | ret = ops->get_pages(obj); |
| 2383 | if (ret) |
| 2384 | return ret; |
| 2385 | |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 2386 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
Chris Wilson | ee28637 | 2015-04-07 16:20:25 +0100 | [diff] [blame] | 2387 | |
| 2388 | obj->get_page.sg = obj->pages->sgl; |
| 2389 | obj->get_page.last = 0; |
| 2390 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 2391 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2392 | } |
| 2393 | |
Chris Wilson | 0a798eb | 2016-04-08 12:11:11 +0100 | [diff] [blame] | 2394 | void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj) |
| 2395 | { |
| 2396 | int ret; |
| 2397 | |
| 2398 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
| 2399 | |
| 2400 | ret = i915_gem_object_get_pages(obj); |
| 2401 | if (ret) |
| 2402 | return ERR_PTR(ret); |
| 2403 | |
| 2404 | i915_gem_object_pin_pages(obj); |
| 2405 | |
| 2406 | if (obj->mapping == NULL) { |
Chris Wilson | 0a798eb | 2016-04-08 12:11:11 +0100 | [diff] [blame] | 2407 | struct page **pages; |
Chris Wilson | 0a798eb | 2016-04-08 12:11:11 +0100 | [diff] [blame] | 2408 | |
Chris Wilson | fb8621d | 2016-04-08 12:11:14 +0100 | [diff] [blame] | 2409 | pages = NULL; |
| 2410 | if (obj->base.size == PAGE_SIZE) |
| 2411 | obj->mapping = kmap(sg_page(obj->pages->sgl)); |
| 2412 | else |
| 2413 | pages = drm_malloc_gfp(obj->base.size >> PAGE_SHIFT, |
| 2414 | sizeof(*pages), |
| 2415 | GFP_TEMPORARY); |
Chris Wilson | 0a798eb | 2016-04-08 12:11:11 +0100 | [diff] [blame] | 2416 | if (pages != NULL) { |
Chris Wilson | fb8621d | 2016-04-08 12:11:14 +0100 | [diff] [blame] | 2417 | struct sg_page_iter sg_iter; |
| 2418 | int n; |
| 2419 | |
Chris Wilson | 0a798eb | 2016-04-08 12:11:11 +0100 | [diff] [blame] | 2420 | n = 0; |
| 2421 | for_each_sg_page(obj->pages->sgl, &sg_iter, |
| 2422 | obj->pages->nents, 0) |
| 2423 | pages[n++] = sg_page_iter_page(&sg_iter); |
| 2424 | |
| 2425 | obj->mapping = vmap(pages, n, 0, PAGE_KERNEL); |
| 2426 | drm_free_large(pages); |
| 2427 | } |
| 2428 | if (obj->mapping == NULL) { |
| 2429 | i915_gem_object_unpin_pages(obj); |
| 2430 | return ERR_PTR(-ENOMEM); |
| 2431 | } |
| 2432 | } |
| 2433 | |
| 2434 | return obj->mapping; |
| 2435 | } |
| 2436 | |
Ben Widawsky | e2d05a8 | 2013-09-24 09:57:58 -0700 | [diff] [blame] | 2437 | void i915_vma_move_to_active(struct i915_vma *vma, |
John Harrison | b2af037 | 2015-05-29 17:43:50 +0100 | [diff] [blame] | 2438 | struct drm_i915_gem_request *req) |
Ben Widawsky | e2d05a8 | 2013-09-24 09:57:58 -0700 | [diff] [blame] | 2439 | { |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2440 | struct drm_i915_gem_object *obj = vma->obj; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2441 | struct intel_engine_cs *engine; |
John Harrison | b2af037 | 2015-05-29 17:43:50 +0100 | [diff] [blame] | 2442 | |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 2443 | engine = i915_gem_request_get_engine(req); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2444 | |
| 2445 | /* Add a reference if we're newly entering the active list. */ |
| 2446 | if (obj->active == 0) |
| 2447 | drm_gem_object_reference(&obj->base); |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 2448 | obj->active |= intel_engine_flag(engine); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2449 | |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 2450 | list_move_tail(&obj->engine_list[engine->id], &engine->active_list); |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2451 | i915_gem_request_assign(&obj->last_read_req[engine->id], req); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2452 | |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 2453 | list_move_tail(&vma->vm_link, &vma->vm->active_list); |
Ben Widawsky | e2d05a8 | 2013-09-24 09:57:58 -0700 | [diff] [blame] | 2454 | } |
| 2455 | |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2456 | static void |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2457 | i915_gem_object_retire__write(struct drm_i915_gem_object *obj) |
| 2458 | { |
Chris Wilson | d501b1d | 2016-04-13 17:35:02 +0100 | [diff] [blame] | 2459 | GEM_BUG_ON(obj->last_write_req == NULL); |
| 2460 | GEM_BUG_ON(!(obj->active & intel_engine_flag(obj->last_write_req->engine))); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2461 | |
| 2462 | i915_gem_request_assign(&obj->last_write_req, NULL); |
Rodrigo Vivi | de152b6 | 2015-07-07 16:28:51 -0700 | [diff] [blame] | 2463 | intel_fb_obj_flush(obj, true, ORIGIN_CS); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2464 | } |
| 2465 | |
| 2466 | static void |
| 2467 | i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring) |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2468 | { |
Ben Widawsky | feb822c | 2013-12-06 14:10:51 -0800 | [diff] [blame] | 2469 | struct i915_vma *vma; |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2470 | |
Chris Wilson | d501b1d | 2016-04-13 17:35:02 +0100 | [diff] [blame] | 2471 | GEM_BUG_ON(obj->last_read_req[ring] == NULL); |
| 2472 | GEM_BUG_ON(!(obj->active & (1 << ring))); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2473 | |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 2474 | list_del_init(&obj->engine_list[ring]); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2475 | i915_gem_request_assign(&obj->last_read_req[ring], NULL); |
| 2476 | |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 2477 | if (obj->last_write_req && obj->last_write_req->engine->id == ring) |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2478 | i915_gem_object_retire__write(obj); |
| 2479 | |
| 2480 | obj->active &= ~(1 << ring); |
| 2481 | if (obj->active) |
| 2482 | return; |
Chris Wilson | 65ce302 | 2012-07-20 12:41:02 +0100 | [diff] [blame] | 2483 | |
Chris Wilson | 6c24695 | 2015-07-27 10:26:26 +0100 | [diff] [blame] | 2484 | /* Bump our place on the bound list to keep it roughly in LRU order |
| 2485 | * so that we don't steal from recently used but inactive objects |
| 2486 | * (unless we are forced to ofc!) |
| 2487 | */ |
| 2488 | list_move_tail(&obj->global_list, |
| 2489 | &to_i915(obj->base.dev)->mm.bound_list); |
| 2490 | |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 2491 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
| 2492 | if (!list_empty(&vma->vm_link)) |
| 2493 | list_move_tail(&vma->vm_link, &vma->vm->inactive_list); |
Ben Widawsky | feb822c | 2013-12-06 14:10:51 -0800 | [diff] [blame] | 2494 | } |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2495 | |
John Harrison | 97b2a6a | 2014-11-24 18:49:26 +0000 | [diff] [blame] | 2496 | i915_gem_request_assign(&obj->last_fenced_req, NULL); |
Chris Wilson | caea747 | 2010-11-12 13:53:37 +0000 | [diff] [blame] | 2497 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | c8725f3 | 2014-03-17 12:21:55 +0000 | [diff] [blame] | 2498 | } |
| 2499 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2500 | static int |
Mika Kuoppala | fca26bb | 2012-12-19 11:13:08 +0200 | [diff] [blame] | 2501 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 2502 | { |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2503 | struct drm_i915_private *dev_priv = dev->dev_private; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2504 | struct intel_engine_cs *engine; |
Chris Wilson | 29dcb57 | 2016-04-07 07:29:13 +0100 | [diff] [blame] | 2505 | int ret; |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 2506 | |
Chris Wilson | 107f27a5 | 2012-12-10 13:56:17 +0200 | [diff] [blame] | 2507 | /* Carefully retire all requests without writing to the rings */ |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 2508 | for_each_engine(engine, dev_priv) { |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 2509 | ret = intel_engine_idle(engine); |
Chris Wilson | 107f27a5 | 2012-12-10 13:56:17 +0200 | [diff] [blame] | 2510 | if (ret) |
| 2511 | return ret; |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2512 | } |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2513 | i915_gem_retire_requests(dev); |
Chris Wilson | 107f27a5 | 2012-12-10 13:56:17 +0200 | [diff] [blame] | 2514 | |
| 2515 | /* Finally reset hw state */ |
Chris Wilson | 29dcb57 | 2016-04-07 07:29:13 +0100 | [diff] [blame] | 2516 | for_each_engine(engine, dev_priv) |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2517 | intel_ring_init_seqno(engine, seqno); |
Mika Kuoppala | 498d2ac | 2012-12-04 15:12:04 +0200 | [diff] [blame] | 2518 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2519 | return 0; |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 2520 | } |
| 2521 | |
Mika Kuoppala | fca26bb | 2012-12-19 11:13:08 +0200 | [diff] [blame] | 2522 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
| 2523 | { |
| 2524 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2525 | int ret; |
| 2526 | |
| 2527 | if (seqno == 0) |
| 2528 | return -EINVAL; |
| 2529 | |
| 2530 | /* HWS page needs to be set less than what we |
| 2531 | * will inject to ring |
| 2532 | */ |
| 2533 | ret = i915_gem_init_seqno(dev, seqno - 1); |
| 2534 | if (ret) |
| 2535 | return ret; |
| 2536 | |
| 2537 | /* Carefully set the last_seqno value so that wrap |
| 2538 | * detection still works |
| 2539 | */ |
| 2540 | dev_priv->next_seqno = seqno; |
| 2541 | dev_priv->last_seqno = seqno - 1; |
| 2542 | if (dev_priv->last_seqno == 0) |
| 2543 | dev_priv->last_seqno--; |
| 2544 | |
| 2545 | return 0; |
| 2546 | } |
| 2547 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2548 | int |
| 2549 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 2550 | { |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2551 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 2552 | |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2553 | /* reserve 0 for non-seqno */ |
| 2554 | if (dev_priv->next_seqno == 0) { |
Mika Kuoppala | fca26bb | 2012-12-19 11:13:08 +0200 | [diff] [blame] | 2555 | int ret = i915_gem_init_seqno(dev, 0); |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2556 | if (ret) |
| 2557 | return ret; |
| 2558 | |
| 2559 | dev_priv->next_seqno = 1; |
| 2560 | } |
| 2561 | |
Mika Kuoppala | f72b343 | 2012-12-10 15:41:48 +0200 | [diff] [blame] | 2562 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
Chris Wilson | 9d773091 | 2012-11-27 16:22:52 +0000 | [diff] [blame] | 2563 | return 0; |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 2564 | } |
| 2565 | |
John Harrison | bf7dc5b | 2015-05-29 17:43:24 +0100 | [diff] [blame] | 2566 | /* |
| 2567 | * NB: This function is not allowed to fail. Doing so would mean the the |
| 2568 | * request is not being tracked for completion but the work itself is |
| 2569 | * going to happen on the hardware. This would be a Bad Thing(tm). |
| 2570 | */ |
John Harrison | 7528987 | 2015-05-29 17:43:49 +0100 | [diff] [blame] | 2571 | void __i915_add_request(struct drm_i915_gem_request *request, |
John Harrison | 5b4a60c | 2015-05-29 17:43:34 +0100 | [diff] [blame] | 2572 | struct drm_i915_gem_object *obj, |
| 2573 | bool flush_caches) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2574 | { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2575 | struct intel_engine_cs *engine; |
John Harrison | 7528987 | 2015-05-29 17:43:49 +0100 | [diff] [blame] | 2576 | struct drm_i915_private *dev_priv; |
Oscar Mateo | 48e29f5 | 2014-07-24 17:04:29 +0100 | [diff] [blame] | 2577 | struct intel_ringbuffer *ringbuf; |
Nick Hoath | 6d3d827 | 2015-01-15 13:10:39 +0000 | [diff] [blame] | 2578 | u32 request_start; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 2579 | int ret; |
| 2580 | |
Oscar Mateo | 48e29f5 | 2014-07-24 17:04:29 +0100 | [diff] [blame] | 2581 | if (WARN_ON(request == NULL)) |
John Harrison | bf7dc5b | 2015-05-29 17:43:24 +0100 | [diff] [blame] | 2582 | return; |
Oscar Mateo | 48e29f5 | 2014-07-24 17:04:29 +0100 | [diff] [blame] | 2583 | |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 2584 | engine = request->engine; |
Tvrtko Ursulin | 39dabec | 2016-03-17 13:04:10 +0000 | [diff] [blame] | 2585 | dev_priv = request->i915; |
John Harrison | 7528987 | 2015-05-29 17:43:49 +0100 | [diff] [blame] | 2586 | ringbuf = request->ringbuf; |
| 2587 | |
John Harrison | 29b1b41 | 2015-06-18 13:10:09 +0100 | [diff] [blame] | 2588 | /* |
| 2589 | * To ensure that this call will not fail, space for its emissions |
| 2590 | * should already have been reserved in the ring buffer. Let the ring |
| 2591 | * know that it is time to use that space up. |
| 2592 | */ |
| 2593 | intel_ring_reserved_space_use(ringbuf); |
| 2594 | |
Oscar Mateo | 48e29f5 | 2014-07-24 17:04:29 +0100 | [diff] [blame] | 2595 | request_start = intel_ring_get_tail(ringbuf); |
Daniel Vetter | cc889e0 | 2012-06-13 20:45:19 +0200 | [diff] [blame] | 2596 | /* |
| 2597 | * Emit any outstanding flushes - execbuf can fail to emit the flush |
| 2598 | * after having emitted the batchbuffer command. Hence we need to fix |
| 2599 | * things up similar to emitting the lazy request. The difference here |
| 2600 | * is that the flush _must_ happen before the next request, no matter |
| 2601 | * what. |
| 2602 | */ |
John Harrison | 5b4a60c | 2015-05-29 17:43:34 +0100 | [diff] [blame] | 2603 | if (flush_caches) { |
| 2604 | if (i915.enable_execlists) |
John Harrison | 4866d72 | 2015-05-29 17:43:55 +0100 | [diff] [blame] | 2605 | ret = logical_ring_flush_all_caches(request); |
John Harrison | 5b4a60c | 2015-05-29 17:43:34 +0100 | [diff] [blame] | 2606 | else |
John Harrison | 4866d72 | 2015-05-29 17:43:55 +0100 | [diff] [blame] | 2607 | ret = intel_ring_flush_all_caches(request); |
John Harrison | 5b4a60c | 2015-05-29 17:43:34 +0100 | [diff] [blame] | 2608 | /* Not allowed to fail! */ |
| 2609 | WARN(ret, "*_ring_flush_all_caches failed: %d!\n", ret); |
| 2610 | } |
Daniel Vetter | cc889e0 | 2012-06-13 20:45:19 +0200 | [diff] [blame] | 2611 | |
Chris Wilson | 7c90b7d | 2016-04-07 07:29:17 +0100 | [diff] [blame] | 2612 | trace_i915_gem_request_add(request); |
| 2613 | |
| 2614 | request->head = request_start; |
| 2615 | |
| 2616 | /* Whilst this request exists, batch_obj will be on the |
| 2617 | * active_list, and so will hold the active reference. Only when this |
| 2618 | * request is retired will the the batch_obj be moved onto the |
| 2619 | * inactive_list and lose its active reference. Hence we do not need |
| 2620 | * to explicitly hold another reference here. |
| 2621 | */ |
| 2622 | request->batch_obj = obj; |
| 2623 | |
| 2624 | /* Seal the request and mark it as pending execution. Note that |
| 2625 | * we may inspect this state, without holding any locks, during |
| 2626 | * hangcheck. Hence we apply the barrier to ensure that we do not |
| 2627 | * see a more recent value in the hws than we are tracking. |
| 2628 | */ |
| 2629 | request->emitted_jiffies = jiffies; |
| 2630 | request->previous_seqno = engine->last_submitted_seqno; |
| 2631 | smp_store_mb(engine->last_submitted_seqno, request->seqno); |
| 2632 | list_add_tail(&request->list, &engine->request_list); |
| 2633 | |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2634 | /* Record the position of the start of the request so that |
| 2635 | * should we detect the updated seqno part-way through the |
| 2636 | * GPU processing the request, we never over-estimate the |
| 2637 | * position of the head. |
| 2638 | */ |
Nick Hoath | 6d3d827 | 2015-01-15 13:10:39 +0000 | [diff] [blame] | 2639 | request->postfix = intel_ring_get_tail(ringbuf); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 2640 | |
John Harrison | bf7dc5b | 2015-05-29 17:43:24 +0100 | [diff] [blame] | 2641 | if (i915.enable_execlists) |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2642 | ret = engine->emit_request(request); |
John Harrison | bf7dc5b | 2015-05-29 17:43:24 +0100 | [diff] [blame] | 2643 | else { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2644 | ret = engine->add_request(request); |
Michel Thierry | 53292cd | 2015-04-15 18:11:33 +0100 | [diff] [blame] | 2645 | |
| 2646 | request->tail = intel_ring_get_tail(ringbuf); |
Oscar Mateo | 48e29f5 | 2014-07-24 17:04:29 +0100 | [diff] [blame] | 2647 | } |
John Harrison | bf7dc5b | 2015-05-29 17:43:24 +0100 | [diff] [blame] | 2648 | /* Not allowed to fail! */ |
| 2649 | WARN(ret, "emit|add_request failed: %d!\n", ret); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2650 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2651 | i915_queue_hangcheck(engine->dev); |
Mika Kuoppala | 10cd45b | 2013-07-03 17:22:08 +0300 | [diff] [blame] | 2652 | |
Daniel Vetter | 8725548 | 2014-11-19 20:36:48 +0100 | [diff] [blame] | 2653 | queue_delayed_work(dev_priv->wq, |
| 2654 | &dev_priv->mm.retire_work, |
| 2655 | round_jiffies_up_relative(HZ)); |
| 2656 | intel_mark_busy(dev_priv->dev); |
Daniel Vetter | cc889e0 | 2012-06-13 20:45:19 +0200 | [diff] [blame] | 2657 | |
John Harrison | 29b1b41 | 2015-06-18 13:10:09 +0100 | [diff] [blame] | 2658 | /* Sanity check that the reserved size was large enough. */ |
| 2659 | intel_ring_reserved_space_end(ringbuf); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2660 | } |
| 2661 | |
Mika Kuoppala | 939fd76 | 2014-01-30 19:04:44 +0200 | [diff] [blame] | 2662 | static bool i915_context_is_banned(struct drm_i915_private *dev_priv, |
Oscar Mateo | 273497e | 2014-05-22 14:13:37 +0100 | [diff] [blame] | 2663 | const struct intel_context *ctx) |
Mika Kuoppala | be62acb | 2013-08-30 16:19:28 +0300 | [diff] [blame] | 2664 | { |
Mika Kuoppala | 44e2c07 | 2014-01-30 16:01:15 +0200 | [diff] [blame] | 2665 | unsigned long elapsed; |
Mika Kuoppala | be62acb | 2013-08-30 16:19:28 +0300 | [diff] [blame] | 2666 | |
Mika Kuoppala | 44e2c07 | 2014-01-30 16:01:15 +0200 | [diff] [blame] | 2667 | elapsed = get_seconds() - ctx->hang_stats.guilty_ts; |
| 2668 | |
| 2669 | if (ctx->hang_stats.banned) |
Mika Kuoppala | be62acb | 2013-08-30 16:19:28 +0300 | [diff] [blame] | 2670 | return true; |
| 2671 | |
Chris Wilson | 676fa57 | 2014-12-24 08:13:39 -0800 | [diff] [blame] | 2672 | if (ctx->hang_stats.ban_period_seconds && |
| 2673 | elapsed <= ctx->hang_stats.ban_period_seconds) { |
Ville Syrjälä | ccc7bed | 2014-02-21 16:26:47 +0200 | [diff] [blame] | 2674 | if (!i915_gem_context_is_default(ctx)) { |
Mika Kuoppala | 3fac897 | 2014-01-30 16:05:48 +0200 | [diff] [blame] | 2675 | DRM_DEBUG("context hanging too fast, banning!\n"); |
Ville Syrjälä | ccc7bed | 2014-02-21 16:26:47 +0200 | [diff] [blame] | 2676 | return true; |
Mika Kuoppala | 88b4aa8 | 2014-03-28 18:18:18 +0200 | [diff] [blame] | 2677 | } else if (i915_stop_ring_allow_ban(dev_priv)) { |
| 2678 | if (i915_stop_ring_allow_warn(dev_priv)) |
| 2679 | DRM_ERROR("gpu hanging too fast, banning!\n"); |
Ville Syrjälä | ccc7bed | 2014-02-21 16:26:47 +0200 | [diff] [blame] | 2680 | return true; |
Mika Kuoppala | 3fac897 | 2014-01-30 16:05:48 +0200 | [diff] [blame] | 2681 | } |
Mika Kuoppala | be62acb | 2013-08-30 16:19:28 +0300 | [diff] [blame] | 2682 | } |
| 2683 | |
| 2684 | return false; |
| 2685 | } |
| 2686 | |
Mika Kuoppala | 939fd76 | 2014-01-30 19:04:44 +0200 | [diff] [blame] | 2687 | static void i915_set_reset_status(struct drm_i915_private *dev_priv, |
Oscar Mateo | 273497e | 2014-05-22 14:13:37 +0100 | [diff] [blame] | 2688 | struct intel_context *ctx, |
Mika Kuoppala | b6b0fac | 2014-01-30 19:04:43 +0200 | [diff] [blame] | 2689 | const bool guilty) |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2690 | { |
Mika Kuoppala | 44e2c07 | 2014-01-30 16:01:15 +0200 | [diff] [blame] | 2691 | struct i915_ctx_hang_stats *hs; |
| 2692 | |
| 2693 | if (WARN_ON(!ctx)) |
| 2694 | return; |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2695 | |
Mika Kuoppala | 44e2c07 | 2014-01-30 16:01:15 +0200 | [diff] [blame] | 2696 | hs = &ctx->hang_stats; |
| 2697 | |
| 2698 | if (guilty) { |
Mika Kuoppala | 939fd76 | 2014-01-30 19:04:44 +0200 | [diff] [blame] | 2699 | hs->banned = i915_context_is_banned(dev_priv, ctx); |
Mika Kuoppala | 44e2c07 | 2014-01-30 16:01:15 +0200 | [diff] [blame] | 2700 | hs->batch_active++; |
| 2701 | hs->guilty_ts = get_seconds(); |
| 2702 | } else { |
| 2703 | hs->batch_pending++; |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2704 | } |
| 2705 | } |
| 2706 | |
John Harrison | abfe262 | 2014-11-24 18:49:24 +0000 | [diff] [blame] | 2707 | void i915_gem_request_free(struct kref *req_ref) |
| 2708 | { |
| 2709 | struct drm_i915_gem_request *req = container_of(req_ref, |
| 2710 | typeof(*req), ref); |
| 2711 | struct intel_context *ctx = req->ctx; |
| 2712 | |
John Harrison | fcfa423c | 2015-05-29 17:44:12 +0100 | [diff] [blame] | 2713 | if (req->file_priv) |
| 2714 | i915_gem_request_remove_from_client(req); |
| 2715 | |
Thomas Daniel | 0794aed | 2014-11-25 10:39:25 +0000 | [diff] [blame] | 2716 | if (ctx) { |
Dave Gordon | e28e404 | 2016-01-19 19:02:55 +0000 | [diff] [blame] | 2717 | if (i915.enable_execlists && ctx != req->i915->kernel_context) |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 2718 | intel_lr_context_unpin(ctx, req->engine); |
John Harrison | abfe262 | 2014-11-24 18:49:24 +0000 | [diff] [blame] | 2719 | |
Oscar Mateo | dcb4c12 | 2014-11-13 10:28:10 +0000 | [diff] [blame] | 2720 | i915_gem_context_unreference(ctx); |
| 2721 | } |
John Harrison | abfe262 | 2014-11-24 18:49:24 +0000 | [diff] [blame] | 2722 | |
Chris Wilson | efab6d8 | 2015-04-07 16:20:57 +0100 | [diff] [blame] | 2723 | kmem_cache_free(req->i915->requests, req); |
Mika Kuoppala | 0e50e96 | 2013-05-02 16:48:08 +0300 | [diff] [blame] | 2724 | } |
| 2725 | |
Dave Gordon | 2682708 | 2016-01-19 19:02:53 +0000 | [diff] [blame] | 2726 | static inline int |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2727 | __i915_gem_request_alloc(struct intel_engine_cs *engine, |
Dave Gordon | 2682708 | 2016-01-19 19:02:53 +0000 | [diff] [blame] | 2728 | struct intel_context *ctx, |
| 2729 | struct drm_i915_gem_request **req_out) |
John Harrison | 6689cb2 | 2015-03-19 12:30:08 +0000 | [diff] [blame] | 2730 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2731 | struct drm_i915_private *dev_priv = to_i915(engine->dev); |
Chris Wilson | 299259a | 2016-04-13 17:35:06 +0100 | [diff] [blame] | 2732 | unsigned reset_counter = i915_reset_counter(&dev_priv->gpu_error); |
Daniel Vetter | eed29a5 | 2015-05-21 14:21:25 +0200 | [diff] [blame] | 2733 | struct drm_i915_gem_request *req; |
John Harrison | 6689cb2 | 2015-03-19 12:30:08 +0000 | [diff] [blame] | 2734 | int ret; |
John Harrison | 6689cb2 | 2015-03-19 12:30:08 +0000 | [diff] [blame] | 2735 | |
John Harrison | 217e46b | 2015-05-29 17:43:29 +0100 | [diff] [blame] | 2736 | if (!req_out) |
| 2737 | return -EINVAL; |
| 2738 | |
John Harrison | bccca49 | 2015-05-29 17:44:11 +0100 | [diff] [blame] | 2739 | *req_out = NULL; |
John Harrison | 6689cb2 | 2015-03-19 12:30:08 +0000 | [diff] [blame] | 2740 | |
Chris Wilson | f4457ae | 2016-04-13 17:35:08 +0100 | [diff] [blame] | 2741 | /* ABI: Before userspace accesses the GPU (e.g. execbuffer), report |
| 2742 | * EIO if the GPU is already wedged, or EAGAIN to drop the struct_mutex |
| 2743 | * and restart. |
| 2744 | */ |
| 2745 | ret = i915_gem_check_wedge(reset_counter, dev_priv->mm.interruptible); |
Chris Wilson | 299259a | 2016-04-13 17:35:06 +0100 | [diff] [blame] | 2746 | if (ret) |
| 2747 | return ret; |
| 2748 | |
Daniel Vetter | eed29a5 | 2015-05-21 14:21:25 +0200 | [diff] [blame] | 2749 | req = kmem_cache_zalloc(dev_priv->requests, GFP_KERNEL); |
| 2750 | if (req == NULL) |
John Harrison | 6689cb2 | 2015-03-19 12:30:08 +0000 | [diff] [blame] | 2751 | return -ENOMEM; |
| 2752 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2753 | ret = i915_gem_get_seqno(engine->dev, &req->seqno); |
Chris Wilson | 9a0c1e2 | 2015-05-21 21:01:45 +0100 | [diff] [blame] | 2754 | if (ret) |
| 2755 | goto err; |
John Harrison | 6689cb2 | 2015-03-19 12:30:08 +0000 | [diff] [blame] | 2756 | |
John Harrison | 40e895c | 2015-05-29 17:43:26 +0100 | [diff] [blame] | 2757 | kref_init(&req->ref); |
| 2758 | req->i915 = dev_priv; |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 2759 | req->engine = engine; |
Chris Wilson | 299259a | 2016-04-13 17:35:06 +0100 | [diff] [blame] | 2760 | req->reset_counter = reset_counter; |
John Harrison | 40e895c | 2015-05-29 17:43:26 +0100 | [diff] [blame] | 2761 | req->ctx = ctx; |
| 2762 | i915_gem_context_reference(req->ctx); |
John Harrison | 6689cb2 | 2015-03-19 12:30:08 +0000 | [diff] [blame] | 2763 | |
| 2764 | if (i915.enable_execlists) |
John Harrison | 40e895c | 2015-05-29 17:43:26 +0100 | [diff] [blame] | 2765 | ret = intel_logical_ring_alloc_request_extras(req); |
John Harrison | 6689cb2 | 2015-03-19 12:30:08 +0000 | [diff] [blame] | 2766 | else |
Daniel Vetter | eed29a5 | 2015-05-21 14:21:25 +0200 | [diff] [blame] | 2767 | ret = intel_ring_alloc_request_extras(req); |
John Harrison | 40e895c | 2015-05-29 17:43:26 +0100 | [diff] [blame] | 2768 | if (ret) { |
| 2769 | i915_gem_context_unreference(req->ctx); |
Chris Wilson | 9a0c1e2 | 2015-05-21 21:01:45 +0100 | [diff] [blame] | 2770 | goto err; |
John Harrison | 40e895c | 2015-05-29 17:43:26 +0100 | [diff] [blame] | 2771 | } |
John Harrison | 6689cb2 | 2015-03-19 12:30:08 +0000 | [diff] [blame] | 2772 | |
John Harrison | 29b1b41 | 2015-06-18 13:10:09 +0100 | [diff] [blame] | 2773 | /* |
| 2774 | * Reserve space in the ring buffer for all the commands required to |
| 2775 | * eventually emit this request. This is to guarantee that the |
| 2776 | * i915_add_request() call can't fail. Note that the reserve may need |
| 2777 | * to be redone if the request is not actually submitted straight |
| 2778 | * away, e.g. because a GPU scheduler has deferred it. |
John Harrison | 29b1b41 | 2015-06-18 13:10:09 +0100 | [diff] [blame] | 2779 | */ |
John Harrison | ccd98fe | 2015-05-29 17:44:09 +0100 | [diff] [blame] | 2780 | if (i915.enable_execlists) |
| 2781 | ret = intel_logical_ring_reserve_space(req); |
| 2782 | else |
| 2783 | ret = intel_ring_reserve_space(req); |
| 2784 | if (ret) { |
| 2785 | /* |
| 2786 | * At this point, the request is fully allocated even if not |
| 2787 | * fully prepared. Thus it can be cleaned up using the proper |
| 2788 | * free code. |
| 2789 | */ |
Chris Wilson | aa9b781 | 2016-04-13 17:35:15 +0100 | [diff] [blame] | 2790 | intel_ring_reserved_space_cancel(req->ringbuf); |
| 2791 | i915_gem_request_unreference(req); |
John Harrison | ccd98fe | 2015-05-29 17:44:09 +0100 | [diff] [blame] | 2792 | return ret; |
| 2793 | } |
John Harrison | 29b1b41 | 2015-06-18 13:10:09 +0100 | [diff] [blame] | 2794 | |
John Harrison | bccca49 | 2015-05-29 17:44:11 +0100 | [diff] [blame] | 2795 | *req_out = req; |
John Harrison | 6689cb2 | 2015-03-19 12:30:08 +0000 | [diff] [blame] | 2796 | return 0; |
Chris Wilson | 9a0c1e2 | 2015-05-21 21:01:45 +0100 | [diff] [blame] | 2797 | |
| 2798 | err: |
| 2799 | kmem_cache_free(dev_priv->requests, req); |
| 2800 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2801 | } |
| 2802 | |
Dave Gordon | 2682708 | 2016-01-19 19:02:53 +0000 | [diff] [blame] | 2803 | /** |
| 2804 | * i915_gem_request_alloc - allocate a request structure |
| 2805 | * |
| 2806 | * @engine: engine that we wish to issue the request on. |
| 2807 | * @ctx: context that the request will be associated with. |
| 2808 | * This can be NULL if the request is not directly related to |
| 2809 | * any specific user context, in which case this function will |
| 2810 | * choose an appropriate context to use. |
| 2811 | * |
| 2812 | * Returns a pointer to the allocated request if successful, |
| 2813 | * or an error code if not. |
| 2814 | */ |
| 2815 | struct drm_i915_gem_request * |
| 2816 | i915_gem_request_alloc(struct intel_engine_cs *engine, |
| 2817 | struct intel_context *ctx) |
| 2818 | { |
| 2819 | struct drm_i915_gem_request *req; |
| 2820 | int err; |
| 2821 | |
| 2822 | if (ctx == NULL) |
Dave Gordon | ed54c1a | 2016-01-19 19:02:54 +0000 | [diff] [blame] | 2823 | ctx = to_i915(engine->dev)->kernel_context; |
Dave Gordon | 2682708 | 2016-01-19 19:02:53 +0000 | [diff] [blame] | 2824 | err = __i915_gem_request_alloc(engine, ctx, &req); |
| 2825 | return err ? ERR_PTR(err) : req; |
| 2826 | } |
| 2827 | |
Chris Wilson | 8d9fc7f | 2014-02-25 17:11:23 +0200 | [diff] [blame] | 2828 | struct drm_i915_gem_request * |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2829 | i915_gem_find_active_request(struct intel_engine_cs *engine) |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 2830 | { |
Chris Wilson | 4db080f | 2013-12-04 11:37:09 +0000 | [diff] [blame] | 2831 | struct drm_i915_gem_request *request; |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2832 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2833 | list_for_each_entry(request, &engine->request_list, list) { |
John Harrison | 1b5a433 | 2014-11-24 18:49:42 +0000 | [diff] [blame] | 2834 | if (i915_gem_request_completed(request, false)) |
Chris Wilson | 4db080f | 2013-12-04 11:37:09 +0000 | [diff] [blame] | 2835 | continue; |
Mika Kuoppala | aa60c66 | 2013-06-12 15:13:20 +0300 | [diff] [blame] | 2836 | |
Mika Kuoppala | b6b0fac | 2014-01-30 19:04:43 +0200 | [diff] [blame] | 2837 | return request; |
Chris Wilson | 4db080f | 2013-12-04 11:37:09 +0000 | [diff] [blame] | 2838 | } |
Mika Kuoppala | b6b0fac | 2014-01-30 19:04:43 +0200 | [diff] [blame] | 2839 | |
| 2840 | return NULL; |
| 2841 | } |
| 2842 | |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 2843 | static void i915_gem_reset_engine_status(struct drm_i915_private *dev_priv, |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2844 | struct intel_engine_cs *engine) |
Mika Kuoppala | b6b0fac | 2014-01-30 19:04:43 +0200 | [diff] [blame] | 2845 | { |
| 2846 | struct drm_i915_gem_request *request; |
| 2847 | bool ring_hung; |
| 2848 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2849 | request = i915_gem_find_active_request(engine); |
Mika Kuoppala | b6b0fac | 2014-01-30 19:04:43 +0200 | [diff] [blame] | 2850 | |
| 2851 | if (request == NULL) |
| 2852 | return; |
| 2853 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2854 | ring_hung = engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG; |
Mika Kuoppala | b6b0fac | 2014-01-30 19:04:43 +0200 | [diff] [blame] | 2855 | |
Mika Kuoppala | 939fd76 | 2014-01-30 19:04:44 +0200 | [diff] [blame] | 2856 | i915_set_reset_status(dev_priv, request->ctx, ring_hung); |
Mika Kuoppala | b6b0fac | 2014-01-30 19:04:43 +0200 | [diff] [blame] | 2857 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2858 | list_for_each_entry_continue(request, &engine->request_list, list) |
Mika Kuoppala | 939fd76 | 2014-01-30 19:04:44 +0200 | [diff] [blame] | 2859 | i915_set_reset_status(dev_priv, request->ctx, false); |
Chris Wilson | 4db080f | 2013-12-04 11:37:09 +0000 | [diff] [blame] | 2860 | } |
| 2861 | |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 2862 | static void i915_gem_reset_engine_cleanup(struct drm_i915_private *dev_priv, |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2863 | struct intel_engine_cs *engine) |
Chris Wilson | 4db080f | 2013-12-04 11:37:09 +0000 | [diff] [blame] | 2864 | { |
Chris Wilson | 608c1a5 | 2015-09-03 13:01:40 +0100 | [diff] [blame] | 2865 | struct intel_ringbuffer *buffer; |
| 2866 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2867 | while (!list_empty(&engine->active_list)) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2868 | struct drm_i915_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2869 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2870 | obj = list_first_entry(&engine->active_list, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 2871 | struct drm_i915_gem_object, |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 2872 | engine_list[engine->id]); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2873 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2874 | i915_gem_object_retire__read(obj, engine->id); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2875 | } |
Ben Widawsky | 1d62bee | 2014-01-01 10:15:13 -0800 | [diff] [blame] | 2876 | |
| 2877 | /* |
Oscar Mateo | dcb4c12 | 2014-11-13 10:28:10 +0000 | [diff] [blame] | 2878 | * Clear the execlists queue up before freeing the requests, as those |
| 2879 | * are the ones that keep the context and ringbuffer backing objects |
| 2880 | * pinned in place. |
| 2881 | */ |
Oscar Mateo | dcb4c12 | 2014-11-13 10:28:10 +0000 | [diff] [blame] | 2882 | |
Tomas Elf | 7de1691 | 2015-10-19 16:32:32 +0100 | [diff] [blame] | 2883 | if (i915.enable_execlists) { |
Tvrtko Ursulin | 27af5ee | 2016-04-04 12:11:56 +0100 | [diff] [blame] | 2884 | /* Ensure irq handler finishes or is cancelled. */ |
| 2885 | tasklet_kill(&engine->irq_tasklet); |
Mika Kuoppala | 1197b4f | 2015-01-13 11:32:24 +0200 | [diff] [blame] | 2886 | |
Tvrtko Ursulin | 27af5ee | 2016-04-04 12:11:56 +0100 | [diff] [blame] | 2887 | spin_lock_bh(&engine->execlist_lock); |
Tomas Elf | c5baa56 | 2015-10-23 18:02:37 +0100 | [diff] [blame] | 2888 | /* list_splice_tail_init checks for empty lists */ |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2889 | list_splice_tail_init(&engine->execlist_queue, |
| 2890 | &engine->execlist_retired_req_list); |
Tvrtko Ursulin | 27af5ee | 2016-04-04 12:11:56 +0100 | [diff] [blame] | 2891 | spin_unlock_bh(&engine->execlist_lock); |
Mika Kuoppala | 1197b4f | 2015-01-13 11:32:24 +0200 | [diff] [blame] | 2892 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2893 | intel_execlists_retire_requests(engine); |
Oscar Mateo | dcb4c12 | 2014-11-13 10:28:10 +0000 | [diff] [blame] | 2894 | } |
| 2895 | |
| 2896 | /* |
Ben Widawsky | 1d62bee | 2014-01-01 10:15:13 -0800 | [diff] [blame] | 2897 | * We must free the requests after all the corresponding objects have |
| 2898 | * been moved off active lists. Which is the same order as the normal |
| 2899 | * retire_requests function does. This is important if object hold |
| 2900 | * implicit references on things like e.g. ppgtt address spaces through |
| 2901 | * the request. |
| 2902 | */ |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2903 | while (!list_empty(&engine->request_list)) { |
Ben Widawsky | 1d62bee | 2014-01-01 10:15:13 -0800 | [diff] [blame] | 2904 | struct drm_i915_gem_request *request; |
| 2905 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2906 | request = list_first_entry(&engine->request_list, |
Ben Widawsky | 1d62bee | 2014-01-01 10:15:13 -0800 | [diff] [blame] | 2907 | struct drm_i915_gem_request, |
| 2908 | list); |
| 2909 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2910 | i915_gem_request_retire(request); |
Ben Widawsky | 1d62bee | 2014-01-01 10:15:13 -0800 | [diff] [blame] | 2911 | } |
Chris Wilson | 608c1a5 | 2015-09-03 13:01:40 +0100 | [diff] [blame] | 2912 | |
| 2913 | /* Having flushed all requests from all queues, we know that all |
| 2914 | * ringbuffers must now be empty. However, since we do not reclaim |
| 2915 | * all space when retiring the request (to prevent HEADs colliding |
| 2916 | * with rapid ringbuffer wraparound) the amount of available space |
| 2917 | * upon reset is less than when we start. Do one more pass over |
| 2918 | * all the ringbuffers to reset last_retired_head. |
| 2919 | */ |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2920 | list_for_each_entry(buffer, &engine->buffers, link) { |
Chris Wilson | 608c1a5 | 2015-09-03 13:01:40 +0100 | [diff] [blame] | 2921 | buffer->last_retired_head = buffer->tail; |
| 2922 | intel_ring_update_space(buffer); |
| 2923 | } |
Chris Wilson | 2ed53a9 | 2016-04-07 07:29:11 +0100 | [diff] [blame] | 2924 | |
| 2925 | intel_ring_init_seqno(engine, engine->last_submitted_seqno); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2926 | } |
| 2927 | |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 2928 | void i915_gem_reset(struct drm_device *dev) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2929 | { |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2930 | struct drm_i915_private *dev_priv = dev->dev_private; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 2931 | struct intel_engine_cs *engine; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2932 | |
Chris Wilson | 4db080f | 2013-12-04 11:37:09 +0000 | [diff] [blame] | 2933 | /* |
| 2934 | * Before we free the objects from the requests, we need to inspect |
| 2935 | * them for finding the guilty party. As the requests only borrow |
| 2936 | * their reference to the objects, the inspection must be done first. |
| 2937 | */ |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 2938 | for_each_engine(engine, dev_priv) |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 2939 | i915_gem_reset_engine_status(dev_priv, engine); |
Chris Wilson | 4db080f | 2013-12-04 11:37:09 +0000 | [diff] [blame] | 2940 | |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 2941 | for_each_engine(engine, dev_priv) |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 2942 | i915_gem_reset_engine_cleanup(dev_priv, engine); |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 2943 | |
Ben Widawsky | acce9ff | 2013-12-06 14:11:03 -0800 | [diff] [blame] | 2944 | i915_gem_context_reset(dev); |
| 2945 | |
Chris Wilson | 19b2dbd | 2013-06-12 10:15:12 +0100 | [diff] [blame] | 2946 | i915_gem_restore_fences(dev); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2947 | |
| 2948 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2949 | } |
| 2950 | |
| 2951 | /** |
| 2952 | * This function clears the request list as sequence numbers are passed. |
| 2953 | */ |
Chris Wilson | 1cf0ba1 | 2014-05-05 09:07:33 +0100 | [diff] [blame] | 2954 | void |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2955 | i915_gem_retire_requests_ring(struct intel_engine_cs *engine) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2956 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2957 | WARN_ON(i915_verify_lists(engine->dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2958 | |
Chris Wilson | 832a3aa | 2015-03-18 18:19:22 +0000 | [diff] [blame] | 2959 | /* Retire requests first as we use it above for the early return. |
| 2960 | * If we retire requests last, we may use a later seqno and so clear |
| 2961 | * the requests lists without clearing the active list, leading to |
| 2962 | * confusion. |
Chris Wilson | e910303 | 2014-01-07 11:45:14 +0000 | [diff] [blame] | 2963 | */ |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2964 | while (!list_empty(&engine->request_list)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2965 | struct drm_i915_gem_request *request; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2966 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2967 | request = list_first_entry(&engine->request_list, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2968 | struct drm_i915_gem_request, |
| 2969 | list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2970 | |
John Harrison | 1b5a433 | 2014-11-24 18:49:42 +0000 | [diff] [blame] | 2971 | if (!i915_gem_request_completed(request, true)) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2972 | break; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 2973 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 2974 | i915_gem_request_retire(request); |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 2975 | } |
| 2976 | |
Chris Wilson | 832a3aa | 2015-03-18 18:19:22 +0000 | [diff] [blame] | 2977 | /* Move any buffers on the active list that are no longer referenced |
| 2978 | * by the ringbuffer to the flushing/inactive lists as appropriate, |
| 2979 | * before we free the context associated with the requests. |
| 2980 | */ |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2981 | while (!list_empty(&engine->active_list)) { |
Chris Wilson | 832a3aa | 2015-03-18 18:19:22 +0000 | [diff] [blame] | 2982 | struct drm_i915_gem_object *obj; |
| 2983 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2984 | obj = list_first_entry(&engine->active_list, |
| 2985 | struct drm_i915_gem_object, |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 2986 | engine_list[engine->id]); |
Chris Wilson | 832a3aa | 2015-03-18 18:19:22 +0000 | [diff] [blame] | 2987 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2988 | if (!list_empty(&obj->last_read_req[engine->id]->list)) |
Chris Wilson | 832a3aa | 2015-03-18 18:19:22 +0000 | [diff] [blame] | 2989 | break; |
| 2990 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2991 | i915_gem_object_retire__read(obj, engine->id); |
Chris Wilson | 832a3aa | 2015-03-18 18:19:22 +0000 | [diff] [blame] | 2992 | } |
| 2993 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 2994 | if (unlikely(engine->trace_irq_req && |
| 2995 | i915_gem_request_completed(engine->trace_irq_req, true))) { |
| 2996 | engine->irq_put(engine); |
| 2997 | i915_gem_request_assign(&engine->trace_irq_req, NULL); |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 2998 | } |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 2999 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 3000 | WARN_ON(i915_verify_lists(engine->dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3001 | } |
| 3002 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 3003 | bool |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 3004 | i915_gem_retire_requests(struct drm_device *dev) |
| 3005 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 3006 | struct drm_i915_private *dev_priv = dev->dev_private; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3007 | struct intel_engine_cs *engine; |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 3008 | bool idle = true; |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 3009 | |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 3010 | for_each_engine(engine, dev_priv) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3011 | i915_gem_retire_requests_ring(engine); |
| 3012 | idle &= list_empty(&engine->request_list); |
Thomas Daniel | c86ee3a9 | 2014-11-13 10:27:05 +0000 | [diff] [blame] | 3013 | if (i915.enable_execlists) { |
Tvrtko Ursulin | 27af5ee | 2016-04-04 12:11:56 +0100 | [diff] [blame] | 3014 | spin_lock_bh(&engine->execlist_lock); |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3015 | idle &= list_empty(&engine->execlist_queue); |
Tvrtko Ursulin | 27af5ee | 2016-04-04 12:11:56 +0100 | [diff] [blame] | 3016 | spin_unlock_bh(&engine->execlist_lock); |
Thomas Daniel | c86ee3a9 | 2014-11-13 10:27:05 +0000 | [diff] [blame] | 3017 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3018 | intel_execlists_retire_requests(engine); |
Thomas Daniel | c86ee3a9 | 2014-11-13 10:27:05 +0000 | [diff] [blame] | 3019 | } |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 3020 | } |
| 3021 | |
| 3022 | if (idle) |
| 3023 | mod_delayed_work(dev_priv->wq, |
| 3024 | &dev_priv->mm.idle_work, |
| 3025 | msecs_to_jiffies(100)); |
| 3026 | |
| 3027 | return idle; |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 3028 | } |
| 3029 | |
Daniel Vetter | 75ef9da | 2010-08-21 00:25:16 +0200 | [diff] [blame] | 3030 | static void |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3031 | i915_gem_retire_work_handler(struct work_struct *work) |
| 3032 | { |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 3033 | struct drm_i915_private *dev_priv = |
| 3034 | container_of(work, typeof(*dev_priv), mm.retire_work.work); |
| 3035 | struct drm_device *dev = dev_priv->dev; |
Chris Wilson | 0a58705 | 2011-01-09 21:05:44 +0000 | [diff] [blame] | 3036 | bool idle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3037 | |
Chris Wilson | 891b48c | 2010-09-29 12:26:37 +0100 | [diff] [blame] | 3038 | /* Come back later if the device is busy... */ |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 3039 | idle = false; |
| 3040 | if (mutex_trylock(&dev->struct_mutex)) { |
| 3041 | idle = i915_gem_retire_requests(dev); |
| 3042 | mutex_unlock(&dev->struct_mutex); |
| 3043 | } |
| 3044 | if (!idle) |
Chris Wilson | bcb4508 | 2012-10-05 17:02:57 +0100 | [diff] [blame] | 3045 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
| 3046 | round_jiffies_up_relative(HZ)); |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 3047 | } |
Chris Wilson | 891b48c | 2010-09-29 12:26:37 +0100 | [diff] [blame] | 3048 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 3049 | static void |
| 3050 | i915_gem_idle_work_handler(struct work_struct *work) |
| 3051 | { |
| 3052 | struct drm_i915_private *dev_priv = |
| 3053 | container_of(work, typeof(*dev_priv), mm.idle_work.work); |
Chris Wilson | 35c9418 | 2015-04-07 16:20:37 +0100 | [diff] [blame] | 3054 | struct drm_device *dev = dev_priv->dev; |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 3055 | struct intel_engine_cs *engine; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3056 | |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 3057 | for_each_engine(engine, dev_priv) |
| 3058 | if (!list_empty(&engine->request_list)) |
Chris Wilson | 423795c | 2015-04-07 16:21:08 +0100 | [diff] [blame] | 3059 | return; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 3060 | |
Daniel Vetter | 30ecad7 | 2015-12-09 09:29:36 +0100 | [diff] [blame] | 3061 | /* we probably should sync with hangcheck here, using cancel_work_sync. |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 3062 | * Also locking seems to be fubar here, engine->request_list is protected |
Daniel Vetter | 30ecad7 | 2015-12-09 09:29:36 +0100 | [diff] [blame] | 3063 | * by dev->struct_mutex. */ |
| 3064 | |
Chris Wilson | 35c9418 | 2015-04-07 16:20:37 +0100 | [diff] [blame] | 3065 | intel_mark_idle(dev); |
| 3066 | |
| 3067 | if (mutex_trylock(&dev->struct_mutex)) { |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 3068 | for_each_engine(engine, dev_priv) |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3069 | i915_gem_batch_pool_fini(&engine->batch_pool); |
Chris Wilson | 35c9418 | 2015-04-07 16:20:37 +0100 | [diff] [blame] | 3070 | |
| 3071 | mutex_unlock(&dev->struct_mutex); |
| 3072 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3073 | } |
| 3074 | |
Ben Widawsky | 5816d64 | 2012-04-11 11:18:19 -0700 | [diff] [blame] | 3075 | /** |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 3076 | * Ensures that an object will eventually get non-busy by flushing any required |
| 3077 | * write domains, emitting any outstanding lazy request and retiring and |
| 3078 | * completed requests. |
| 3079 | */ |
| 3080 | static int |
| 3081 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) |
| 3082 | { |
John Harrison | a5ac0f9 | 2015-05-29 17:44:15 +0100 | [diff] [blame] | 3083 | int i; |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 3084 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3085 | if (!obj->active) |
| 3086 | return 0; |
John Harrison | 41c5241 | 2014-11-24 18:49:43 +0000 | [diff] [blame] | 3087 | |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 3088 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3089 | struct drm_i915_gem_request *req; |
| 3090 | |
| 3091 | req = obj->last_read_req[i]; |
| 3092 | if (req == NULL) |
| 3093 | continue; |
| 3094 | |
| 3095 | if (list_empty(&req->list)) |
| 3096 | goto retire; |
| 3097 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3098 | if (i915_gem_request_completed(req, true)) { |
| 3099 | __i915_gem_request_retire__upto(req); |
| 3100 | retire: |
| 3101 | i915_gem_object_retire__read(obj, i); |
| 3102 | } |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 3103 | } |
| 3104 | |
| 3105 | return 0; |
| 3106 | } |
| 3107 | |
| 3108 | /** |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 3109 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT |
| 3110 | * @DRM_IOCTL_ARGS: standard ioctl arguments |
| 3111 | * |
| 3112 | * Returns 0 if successful, else an error is returned with the remaining time in |
| 3113 | * the timeout parameter. |
| 3114 | * -ETIME: object is still busy after timeout |
| 3115 | * -ERESTARTSYS: signal interrupted the wait |
| 3116 | * -ENONENT: object doesn't exist |
| 3117 | * Also possible, but rare: |
| 3118 | * -EAGAIN: GPU wedged |
| 3119 | * -ENOMEM: damn |
| 3120 | * -ENODEV: Internal IRQ fail |
| 3121 | * -E?: The add request failed |
| 3122 | * |
| 3123 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any |
| 3124 | * non-zero timeout parameter the wait ioctl will wait for the given number of |
| 3125 | * nanoseconds on an object becoming unbusy. Since the wait itself does so |
| 3126 | * without holding struct_mutex the object may become re-busied before this |
| 3127 | * function completes. A similar but shorter * race condition exists in the busy |
| 3128 | * ioctl |
| 3129 | */ |
| 3130 | int |
| 3131 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) |
| 3132 | { |
| 3133 | struct drm_i915_gem_wait *args = data; |
| 3134 | struct drm_i915_gem_object *obj; |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 3135 | struct drm_i915_gem_request *req[I915_NUM_ENGINES]; |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3136 | int i, n = 0; |
| 3137 | int ret; |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 3138 | |
Daniel Vetter | 11b5d51 | 2014-09-29 15:31:26 +0200 | [diff] [blame] | 3139 | if (args->flags != 0) |
| 3140 | return -EINVAL; |
| 3141 | |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 3142 | ret = i915_mutex_lock_interruptible(dev); |
| 3143 | if (ret) |
| 3144 | return ret; |
| 3145 | |
| 3146 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); |
| 3147 | if (&obj->base == NULL) { |
| 3148 | mutex_unlock(&dev->struct_mutex); |
| 3149 | return -ENOENT; |
| 3150 | } |
| 3151 | |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 3152 | /* Need to make sure the object gets inactive eventually. */ |
| 3153 | ret = i915_gem_object_flush_active(obj); |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 3154 | if (ret) |
| 3155 | goto out; |
| 3156 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3157 | if (!obj->active) |
John Harrison | 97b2a6a | 2014-11-24 18:49:26 +0000 | [diff] [blame] | 3158 | goto out; |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 3159 | |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 3160 | /* Do this after OLR check to make sure we make forward progress polling |
Chris Wilson | 762e458 | 2015-03-04 18:09:26 +0000 | [diff] [blame] | 3161 | * on this IOCTL with a timeout == 0 (like busy ioctl) |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 3162 | */ |
Chris Wilson | 762e458 | 2015-03-04 18:09:26 +0000 | [diff] [blame] | 3163 | if (args->timeout_ns == 0) { |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 3164 | ret = -ETIME; |
| 3165 | goto out; |
| 3166 | } |
| 3167 | |
| 3168 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3169 | |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 3170 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3171 | if (obj->last_read_req[i] == NULL) |
| 3172 | continue; |
| 3173 | |
| 3174 | req[n++] = i915_gem_request_reference(obj->last_read_req[i]); |
| 3175 | } |
| 3176 | |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 3177 | mutex_unlock(&dev->struct_mutex); |
| 3178 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3179 | for (i = 0; i < n; i++) { |
| 3180 | if (ret == 0) |
Chris Wilson | 299259a | 2016-04-13 17:35:06 +0100 | [diff] [blame] | 3181 | ret = __i915_wait_request(req[i], true, |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3182 | args->timeout_ns > 0 ? &args->timeout_ns : NULL, |
Chris Wilson | b6aa087 | 2015-12-02 09:13:46 +0000 | [diff] [blame] | 3183 | to_rps_client(file)); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3184 | i915_gem_request_unreference__unlocked(req[i]); |
| 3185 | } |
John Harrison | ff86588 | 2014-11-24 18:49:28 +0000 | [diff] [blame] | 3186 | return ret; |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 3187 | |
| 3188 | out: |
| 3189 | drm_gem_object_unreference(&obj->base); |
| 3190 | mutex_unlock(&dev->struct_mutex); |
| 3191 | return ret; |
| 3192 | } |
| 3193 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3194 | static int |
| 3195 | __i915_gem_object_sync(struct drm_i915_gem_object *obj, |
| 3196 | struct intel_engine_cs *to, |
John Harrison | 91af127 | 2015-06-18 13:14:56 +0100 | [diff] [blame] | 3197 | struct drm_i915_gem_request *from_req, |
| 3198 | struct drm_i915_gem_request **to_req) |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3199 | { |
| 3200 | struct intel_engine_cs *from; |
| 3201 | int ret; |
| 3202 | |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 3203 | from = i915_gem_request_get_engine(from_req); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3204 | if (to == from) |
| 3205 | return 0; |
| 3206 | |
John Harrison | 91af127 | 2015-06-18 13:14:56 +0100 | [diff] [blame] | 3207 | if (i915_gem_request_completed(from_req, true)) |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3208 | return 0; |
| 3209 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3210 | if (!i915_semaphore_is_enabled(obj->base.dev)) { |
Chris Wilson | a6f766f | 2015-04-27 13:41:20 +0100 | [diff] [blame] | 3211 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
John Harrison | 91af127 | 2015-06-18 13:14:56 +0100 | [diff] [blame] | 3212 | ret = __i915_wait_request(from_req, |
Chris Wilson | a6f766f | 2015-04-27 13:41:20 +0100 | [diff] [blame] | 3213 | i915->mm.interruptible, |
| 3214 | NULL, |
| 3215 | &i915->rps.semaphores); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3216 | if (ret) |
| 3217 | return ret; |
| 3218 | |
John Harrison | 91af127 | 2015-06-18 13:14:56 +0100 | [diff] [blame] | 3219 | i915_gem_object_retire_request(obj, from_req); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3220 | } else { |
| 3221 | int idx = intel_ring_sync_index(from, to); |
John Harrison | 91af127 | 2015-06-18 13:14:56 +0100 | [diff] [blame] | 3222 | u32 seqno = i915_gem_request_get_seqno(from_req); |
| 3223 | |
| 3224 | WARN_ON(!to_req); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3225 | |
| 3226 | if (seqno <= from->semaphore.sync_seqno[idx]) |
| 3227 | return 0; |
| 3228 | |
John Harrison | 91af127 | 2015-06-18 13:14:56 +0100 | [diff] [blame] | 3229 | if (*to_req == NULL) { |
Dave Gordon | 2682708 | 2016-01-19 19:02:53 +0000 | [diff] [blame] | 3230 | struct drm_i915_gem_request *req; |
| 3231 | |
| 3232 | req = i915_gem_request_alloc(to, NULL); |
| 3233 | if (IS_ERR(req)) |
| 3234 | return PTR_ERR(req); |
| 3235 | |
| 3236 | *to_req = req; |
John Harrison | 91af127 | 2015-06-18 13:14:56 +0100 | [diff] [blame] | 3237 | } |
| 3238 | |
John Harrison | 599d924 | 2015-05-29 17:44:04 +0100 | [diff] [blame] | 3239 | trace_i915_gem_ring_sync_to(*to_req, from, from_req); |
| 3240 | ret = to->semaphore.sync_to(*to_req, from, seqno); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3241 | if (ret) |
| 3242 | return ret; |
| 3243 | |
| 3244 | /* We use last_read_req because sync_to() |
| 3245 | * might have just caused seqno wrap under |
| 3246 | * the radar. |
| 3247 | */ |
| 3248 | from->semaphore.sync_seqno[idx] = |
| 3249 | i915_gem_request_get_seqno(obj->last_read_req[from->id]); |
| 3250 | } |
| 3251 | |
| 3252 | return 0; |
| 3253 | } |
| 3254 | |
Ben Widawsky | 23ba4fd | 2012-05-24 15:03:10 -0700 | [diff] [blame] | 3255 | /** |
Ben Widawsky | 5816d64 | 2012-04-11 11:18:19 -0700 | [diff] [blame] | 3256 | * i915_gem_object_sync - sync an object to a ring. |
| 3257 | * |
| 3258 | * @obj: object which may be in use on another ring. |
| 3259 | * @to: ring we wish to use the object on. May be NULL. |
John Harrison | 91af127 | 2015-06-18 13:14:56 +0100 | [diff] [blame] | 3260 | * @to_req: request we wish to use the object for. See below. |
| 3261 | * This will be allocated and returned if a request is |
| 3262 | * required but not passed in. |
Ben Widawsky | 5816d64 | 2012-04-11 11:18:19 -0700 | [diff] [blame] | 3263 | * |
| 3264 | * This code is meant to abstract object synchronization with the GPU. |
| 3265 | * Calling with NULL implies synchronizing the object with the CPU |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3266 | * rather than a particular GPU ring. Conceptually we serialise writes |
John Harrison | 91af127 | 2015-06-18 13:14:56 +0100 | [diff] [blame] | 3267 | * between engines inside the GPU. We only allow one engine to write |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3268 | * into a buffer at any time, but multiple readers. To ensure each has |
| 3269 | * a coherent view of memory, we must: |
| 3270 | * |
| 3271 | * - If there is an outstanding write request to the object, the new |
| 3272 | * request must wait for it to complete (either CPU or in hw, requests |
| 3273 | * on the same ring will be naturally ordered). |
| 3274 | * |
| 3275 | * - If we are a write request (pending_write_domain is set), the new |
| 3276 | * request must wait for outstanding read requests to complete. |
Ben Widawsky | 5816d64 | 2012-04-11 11:18:19 -0700 | [diff] [blame] | 3277 | * |
John Harrison | 91af127 | 2015-06-18 13:14:56 +0100 | [diff] [blame] | 3278 | * For CPU synchronisation (NULL to) no request is required. For syncing with |
| 3279 | * rings to_req must be non-NULL. However, a request does not have to be |
| 3280 | * pre-allocated. If *to_req is NULL and sync commands will be emitted then a |
| 3281 | * request will be allocated automatically and returned through *to_req. Note |
| 3282 | * that it is not guaranteed that commands will be emitted (because the system |
| 3283 | * might already be idle). Hence there is no need to create a request that |
| 3284 | * might never have any work submitted. Note further that if a request is |
| 3285 | * returned in *to_req, it is the responsibility of the caller to submit |
| 3286 | * that request (after potentially adding more work to it). |
| 3287 | * |
Ben Widawsky | 5816d64 | 2012-04-11 11:18:19 -0700 | [diff] [blame] | 3288 | * Returns 0 if successful, else propagates up the lower layer error. |
| 3289 | */ |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 3290 | int |
| 3291 | i915_gem_object_sync(struct drm_i915_gem_object *obj, |
John Harrison | 91af127 | 2015-06-18 13:14:56 +0100 | [diff] [blame] | 3292 | struct intel_engine_cs *to, |
| 3293 | struct drm_i915_gem_request **to_req) |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 3294 | { |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3295 | const bool readonly = obj->base.pending_write_domain == 0; |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 3296 | struct drm_i915_gem_request *req[I915_NUM_ENGINES]; |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3297 | int ret, i, n; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 3298 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3299 | if (!obj->active) |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 3300 | return 0; |
| 3301 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3302 | if (to == NULL) |
| 3303 | return i915_gem_object_wait_rendering(obj, readonly); |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 3304 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3305 | n = 0; |
| 3306 | if (readonly) { |
| 3307 | if (obj->last_write_req) |
| 3308 | req[n++] = obj->last_write_req; |
| 3309 | } else { |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 3310 | for (i = 0; i < I915_NUM_ENGINES; i++) |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3311 | if (obj->last_read_req[i]) |
| 3312 | req[n++] = obj->last_read_req[i]; |
| 3313 | } |
| 3314 | for (i = 0; i < n; i++) { |
John Harrison | 91af127 | 2015-06-18 13:14:56 +0100 | [diff] [blame] | 3315 | ret = __i915_gem_object_sync(obj, to, req[i], to_req); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3316 | if (ret) |
| 3317 | return ret; |
| 3318 | } |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 3319 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3320 | return 0; |
Ben Widawsky | 2911a35 | 2012-04-05 14:47:36 -0700 | [diff] [blame] | 3321 | } |
| 3322 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 3323 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
| 3324 | { |
| 3325 | u32 old_write_domain, old_read_domains; |
| 3326 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 3327 | /* Force a pagefault for domain tracking on next user access */ |
| 3328 | i915_gem_release_mmap(obj); |
| 3329 | |
Keith Packard | b97c3d9 | 2011-06-24 21:02:59 -0700 | [diff] [blame] | 3330 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
| 3331 | return; |
| 3332 | |
Chris Wilson | b5ffc9b | 2011-04-13 22:06:03 +0100 | [diff] [blame] | 3333 | old_read_domains = obj->base.read_domains; |
| 3334 | old_write_domain = obj->base.write_domain; |
| 3335 | |
| 3336 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; |
| 3337 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; |
| 3338 | |
| 3339 | trace_i915_gem_object_change_domain(obj, |
| 3340 | old_read_domains, |
| 3341 | old_write_domain); |
| 3342 | } |
| 3343 | |
Tvrtko Ursulin | e9f24d5 | 2015-10-05 13:26:36 +0100 | [diff] [blame] | 3344 | static int __i915_vma_unbind(struct i915_vma *vma, bool wait) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3345 | { |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3346 | struct drm_i915_gem_object *obj = vma->obj; |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 3347 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Chris Wilson | 43e28f0 | 2013-01-08 10:53:09 +0000 | [diff] [blame] | 3348 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3349 | |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 3350 | if (list_empty(&vma->obj_link)) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3351 | return 0; |
| 3352 | |
Daniel Vetter | 0ff501c | 2013-08-29 19:50:31 +0200 | [diff] [blame] | 3353 | if (!drm_mm_node_allocated(&vma->node)) { |
| 3354 | i915_gem_vma_destroy(vma); |
Daniel Vetter | 0ff501c | 2013-08-29 19:50:31 +0200 | [diff] [blame] | 3355 | return 0; |
| 3356 | } |
Ben Widawsky | 433544b | 2013-08-13 18:09:06 -0700 | [diff] [blame] | 3357 | |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 3358 | if (vma->pin_count) |
Chris Wilson | 31d8d65 | 2012-05-24 19:11:20 +0100 | [diff] [blame] | 3359 | return -EBUSY; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3360 | |
Chris Wilson | c4670ad | 2012-08-20 10:23:27 +0100 | [diff] [blame] | 3361 | BUG_ON(obj->pages == NULL); |
| 3362 | |
Tvrtko Ursulin | e9f24d5 | 2015-10-05 13:26:36 +0100 | [diff] [blame] | 3363 | if (wait) { |
| 3364 | ret = i915_gem_object_wait_rendering(obj, false); |
| 3365 | if (ret) |
| 3366 | return ret; |
| 3367 | } |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 3368 | |
Chris Wilson | 596c592 | 2016-02-26 11:03:20 +0000 | [diff] [blame] | 3369 | if (vma->is_ggtt && vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) { |
Daniel Vetter | 8b1bc9b | 2014-02-14 14:06:07 +0100 | [diff] [blame] | 3370 | i915_gem_object_finish_gtt(obj); |
Chris Wilson | a8198ee | 2011-04-13 22:04:09 +0100 | [diff] [blame] | 3371 | |
Daniel Vetter | 8b1bc9b | 2014-02-14 14:06:07 +0100 | [diff] [blame] | 3372 | /* release the fence reg _after_ flushing */ |
| 3373 | ret = i915_gem_object_put_fence(obj); |
| 3374 | if (ret) |
| 3375 | return ret; |
| 3376 | } |
Daniel Vetter | 96b47b6 | 2009-12-15 17:50:00 +0100 | [diff] [blame] | 3377 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3378 | trace_i915_vma_unbind(vma); |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 3379 | |
Daniel Vetter | 777dc5b | 2015-04-14 17:35:12 +0200 | [diff] [blame] | 3380 | vma->vm->unbind_vma(vma); |
Mika Kuoppala | 5e562f1 | 2015-04-30 11:02:31 +0300 | [diff] [blame] | 3381 | vma->bound = 0; |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 3382 | |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 3383 | list_del_init(&vma->vm_link); |
Chris Wilson | 596c592 | 2016-02-26 11:03:20 +0000 | [diff] [blame] | 3384 | if (vma->is_ggtt) { |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 3385 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) { |
| 3386 | obj->map_and_fenceable = false; |
| 3387 | } else if (vma->ggtt_view.pages) { |
| 3388 | sg_free_table(vma->ggtt_view.pages); |
| 3389 | kfree(vma->ggtt_view.pages); |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 3390 | } |
Chris Wilson | 016a65a | 2015-06-11 08:06:08 +0100 | [diff] [blame] | 3391 | vma->ggtt_view.pages = NULL; |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 3392 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3393 | |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3394 | drm_mm_remove_node(&vma->node); |
| 3395 | i915_gem_vma_destroy(vma); |
| 3396 | |
| 3397 | /* Since the unbound list is global, only move to that list if |
Daniel Vetter | b93dab6 | 2013-08-26 11:23:47 +0200 | [diff] [blame] | 3398 | * no more VMAs exist. */ |
Imre Deak | e227330 | 2015-07-09 12:59:05 +0300 | [diff] [blame] | 3399 | if (list_empty(&obj->vma_list)) |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3400 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3401 | |
Chris Wilson | 70903c3 | 2013-12-04 09:59:09 +0000 | [diff] [blame] | 3402 | /* And finally now the object is completely decoupled from this vma, |
| 3403 | * we can drop its hold on the backing storage and allow it to be |
| 3404 | * reaped by the shrinker. |
| 3405 | */ |
| 3406 | i915_gem_object_unpin_pages(obj); |
| 3407 | |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3408 | return 0; |
Chris Wilson | 54cf91d | 2010-11-25 18:00:26 +0000 | [diff] [blame] | 3409 | } |
| 3410 | |
Tvrtko Ursulin | e9f24d5 | 2015-10-05 13:26:36 +0100 | [diff] [blame] | 3411 | int i915_vma_unbind(struct i915_vma *vma) |
| 3412 | { |
| 3413 | return __i915_vma_unbind(vma, true); |
| 3414 | } |
| 3415 | |
| 3416 | int __i915_vma_unbind_no_wait(struct i915_vma *vma) |
| 3417 | { |
| 3418 | return __i915_vma_unbind(vma, false); |
| 3419 | } |
| 3420 | |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 3421 | int i915_gpu_idle(struct drm_device *dev) |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 3422 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 3423 | struct drm_i915_private *dev_priv = dev->dev_private; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3424 | struct intel_engine_cs *engine; |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 3425 | int ret; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 3426 | |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 3427 | /* Flush everything onto the inactive list. */ |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 3428 | for_each_engine(engine, dev_priv) { |
Thomas Daniel | ecdb5fd | 2014-08-20 16:29:24 +0100 | [diff] [blame] | 3429 | if (!i915.enable_execlists) { |
John Harrison | 73cfa86 | 2015-05-29 17:43:35 +0100 | [diff] [blame] | 3430 | struct drm_i915_gem_request *req; |
| 3431 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 3432 | req = i915_gem_request_alloc(engine, NULL); |
Dave Gordon | 2682708 | 2016-01-19 19:02:53 +0000 | [diff] [blame] | 3433 | if (IS_ERR(req)) |
| 3434 | return PTR_ERR(req); |
John Harrison | 73cfa86 | 2015-05-29 17:43:35 +0100 | [diff] [blame] | 3435 | |
John Harrison | ba01cc9 | 2015-05-29 17:43:41 +0100 | [diff] [blame] | 3436 | ret = i915_switch_context(req); |
John Harrison | 7528987 | 2015-05-29 17:43:49 +0100 | [diff] [blame] | 3437 | i915_add_request_no_flush(req); |
Chris Wilson | aa9b781 | 2016-04-13 17:35:15 +0100 | [diff] [blame] | 3438 | if (ret) |
| 3439 | return ret; |
Thomas Daniel | ecdb5fd | 2014-08-20 16:29:24 +0100 | [diff] [blame] | 3440 | } |
Ben Widawsky | b6c7488 | 2012-08-14 14:35:14 -0700 | [diff] [blame] | 3441 | |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 3442 | ret = intel_engine_idle(engine); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 3443 | if (ret) |
| 3444 | return ret; |
| 3445 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3446 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 3447 | WARN_ON(i915_verify_lists(dev)); |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 3448 | return 0; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 3449 | } |
| 3450 | |
Chris Wilson | 4144f9b | 2014-09-11 08:43:48 +0100 | [diff] [blame] | 3451 | static bool i915_gem_valid_gtt_space(struct i915_vma *vma, |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3452 | unsigned long cache_level) |
| 3453 | { |
Chris Wilson | 4144f9b | 2014-09-11 08:43:48 +0100 | [diff] [blame] | 3454 | struct drm_mm_node *gtt_space = &vma->node; |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3455 | struct drm_mm_node *other; |
| 3456 | |
Chris Wilson | 4144f9b | 2014-09-11 08:43:48 +0100 | [diff] [blame] | 3457 | /* |
| 3458 | * On some machines we have to be careful when putting differing types |
| 3459 | * of snoopable memory together to avoid the prefetcher crossing memory |
| 3460 | * domains and dying. During vm initialisation, we decide whether or not |
| 3461 | * these constraints apply and set the drm_mm.color_adjust |
| 3462 | * appropriately. |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3463 | */ |
Chris Wilson | 4144f9b | 2014-09-11 08:43:48 +0100 | [diff] [blame] | 3464 | if (vma->vm->mm.color_adjust == NULL) |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3465 | return true; |
| 3466 | |
Ben Widawsky | c6cfb32 | 2013-07-05 14:41:06 -0700 | [diff] [blame] | 3467 | if (!drm_mm_node_allocated(gtt_space)) |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3468 | return true; |
| 3469 | |
| 3470 | if (list_empty(>t_space->node_list)) |
| 3471 | return true; |
| 3472 | |
| 3473 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); |
| 3474 | if (other->allocated && !other->hole_follows && other->color != cache_level) |
| 3475 | return false; |
| 3476 | |
| 3477 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); |
| 3478 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) |
| 3479 | return false; |
| 3480 | |
| 3481 | return true; |
| 3482 | } |
| 3483 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 3484 | /** |
Joonas Lahtinen | 91e6711 | 2015-05-06 14:33:58 +0300 | [diff] [blame] | 3485 | * Finds free space in the GTT aperture and binds the object or a view of it |
| 3486 | * there. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3487 | */ |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 3488 | static struct i915_vma * |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3489 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
| 3490 | struct i915_address_space *vm, |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 3491 | const struct i915_ggtt_view *ggtt_view, |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3492 | unsigned alignment, |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 3493 | uint64_t flags) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3494 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3495 | struct drm_device *dev = obj->base.dev; |
Joonas Lahtinen | 72e96d6 | 2016-03-30 16:57:10 +0300 | [diff] [blame] | 3496 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 3497 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
Michel Thierry | 65bd342 | 2015-07-29 17:23:58 +0100 | [diff] [blame] | 3498 | u32 fence_alignment, unfenced_alignment; |
Michel Thierry | 101b506 | 2015-10-01 13:33:57 +0100 | [diff] [blame] | 3499 | u32 search_flag, alloc_flag; |
| 3500 | u64 start, end; |
Michel Thierry | 65bd342 | 2015-07-29 17:23:58 +0100 | [diff] [blame] | 3501 | u64 size, fence_size; |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3502 | struct i915_vma *vma; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 3503 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3504 | |
Joonas Lahtinen | 91e6711 | 2015-05-06 14:33:58 +0300 | [diff] [blame] | 3505 | if (i915_is_ggtt(vm)) { |
| 3506 | u32 view_size; |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 3507 | |
Joonas Lahtinen | 91e6711 | 2015-05-06 14:33:58 +0300 | [diff] [blame] | 3508 | if (WARN_ON(!ggtt_view)) |
| 3509 | return ERR_PTR(-EINVAL); |
| 3510 | |
| 3511 | view_size = i915_ggtt_view_size(obj, ggtt_view); |
| 3512 | |
| 3513 | fence_size = i915_gem_get_gtt_size(dev, |
| 3514 | view_size, |
| 3515 | obj->tiling_mode); |
| 3516 | fence_alignment = i915_gem_get_gtt_alignment(dev, |
| 3517 | view_size, |
| 3518 | obj->tiling_mode, |
| 3519 | true); |
| 3520 | unfenced_alignment = i915_gem_get_gtt_alignment(dev, |
| 3521 | view_size, |
| 3522 | obj->tiling_mode, |
| 3523 | false); |
| 3524 | size = flags & PIN_MAPPABLE ? fence_size : view_size; |
| 3525 | } else { |
| 3526 | fence_size = i915_gem_get_gtt_size(dev, |
| 3527 | obj->base.size, |
| 3528 | obj->tiling_mode); |
| 3529 | fence_alignment = i915_gem_get_gtt_alignment(dev, |
| 3530 | obj->base.size, |
| 3531 | obj->tiling_mode, |
| 3532 | true); |
| 3533 | unfenced_alignment = |
| 3534 | i915_gem_get_gtt_alignment(dev, |
| 3535 | obj->base.size, |
| 3536 | obj->tiling_mode, |
| 3537 | false); |
| 3538 | size = flags & PIN_MAPPABLE ? fence_size : obj->base.size; |
| 3539 | } |
Chris Wilson | a00b10c | 2010-09-24 21:15:47 +0100 | [diff] [blame] | 3540 | |
Michel Thierry | 101b506 | 2015-10-01 13:33:57 +0100 | [diff] [blame] | 3541 | start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0; |
| 3542 | end = vm->total; |
| 3543 | if (flags & PIN_MAPPABLE) |
Joonas Lahtinen | 72e96d6 | 2016-03-30 16:57:10 +0300 | [diff] [blame] | 3544 | end = min_t(u64, end, ggtt->mappable_end); |
Michel Thierry | 101b506 | 2015-10-01 13:33:57 +0100 | [diff] [blame] | 3545 | if (flags & PIN_ZONE_4G) |
Michel Thierry | 48ea1e3 | 2016-01-11 11:39:27 +0000 | [diff] [blame] | 3546 | end = min_t(u64, end, (1ULL << 32) - PAGE_SIZE); |
Michel Thierry | 101b506 | 2015-10-01 13:33:57 +0100 | [diff] [blame] | 3547 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3548 | if (alignment == 0) |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 3549 | alignment = flags & PIN_MAPPABLE ? fence_alignment : |
Daniel Vetter | 5e78330 | 2010-11-14 22:32:36 +0100 | [diff] [blame] | 3550 | unfenced_alignment; |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 3551 | if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) { |
Joonas Lahtinen | 91e6711 | 2015-05-06 14:33:58 +0300 | [diff] [blame] | 3552 | DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n", |
| 3553 | ggtt_view ? ggtt_view->type : 0, |
| 3554 | alignment); |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 3555 | return ERR_PTR(-EINVAL); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3556 | } |
| 3557 | |
Joonas Lahtinen | 91e6711 | 2015-05-06 14:33:58 +0300 | [diff] [blame] | 3558 | /* If binding the object/GGTT view requires more space than the entire |
| 3559 | * aperture has, reject it early before evicting everything in a vain |
| 3560 | * attempt to find space. |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 3561 | */ |
Joonas Lahtinen | 91e6711 | 2015-05-06 14:33:58 +0300 | [diff] [blame] | 3562 | if (size > end) { |
Michel Thierry | 65bd342 | 2015-07-29 17:23:58 +0100 | [diff] [blame] | 3563 | DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%llu > %s aperture=%llu\n", |
Joonas Lahtinen | 91e6711 | 2015-05-06 14:33:58 +0300 | [diff] [blame] | 3564 | ggtt_view ? ggtt_view->type : 0, |
| 3565 | size, |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 3566 | flags & PIN_MAPPABLE ? "mappable" : "total", |
Chris Wilson | d23db88 | 2014-05-23 08:48:08 +0200 | [diff] [blame] | 3567 | end); |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 3568 | return ERR_PTR(-E2BIG); |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 3569 | } |
| 3570 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 3571 | ret = i915_gem_object_get_pages(obj); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 3572 | if (ret) |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 3573 | return ERR_PTR(ret); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 3574 | |
Chris Wilson | fbdda6f | 2012-11-20 10:45:16 +0000 | [diff] [blame] | 3575 | i915_gem_object_pin_pages(obj); |
| 3576 | |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 3577 | vma = ggtt_view ? i915_gem_obj_lookup_or_create_ggtt_vma(obj, ggtt_view) : |
| 3578 | i915_gem_obj_lookup_or_create_vma(obj, vm); |
| 3579 | |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 3580 | if (IS_ERR(vma)) |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3581 | goto err_unpin; |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3582 | |
Chris Wilson | 506a8e8 | 2015-12-08 11:55:07 +0000 | [diff] [blame] | 3583 | if (flags & PIN_OFFSET_FIXED) { |
| 3584 | uint64_t offset = flags & PIN_OFFSET_MASK; |
| 3585 | |
| 3586 | if (offset & (alignment - 1) || offset + size > end) { |
| 3587 | ret = -EINVAL; |
| 3588 | goto err_free_vma; |
| 3589 | } |
| 3590 | vma->node.start = offset; |
| 3591 | vma->node.size = size; |
| 3592 | vma->node.color = obj->cache_level; |
| 3593 | ret = drm_mm_reserve_node(&vm->mm, &vma->node); |
| 3594 | if (ret) { |
| 3595 | ret = i915_gem_evict_for_vma(vma); |
| 3596 | if (ret == 0) |
| 3597 | ret = drm_mm_reserve_node(&vm->mm, &vma->node); |
| 3598 | } |
| 3599 | if (ret) |
| 3600 | goto err_free_vma; |
Michel Thierry | 101b506 | 2015-10-01 13:33:57 +0100 | [diff] [blame] | 3601 | } else { |
Chris Wilson | 506a8e8 | 2015-12-08 11:55:07 +0000 | [diff] [blame] | 3602 | if (flags & PIN_HIGH) { |
| 3603 | search_flag = DRM_MM_SEARCH_BELOW; |
| 3604 | alloc_flag = DRM_MM_CREATE_TOP; |
| 3605 | } else { |
| 3606 | search_flag = DRM_MM_SEARCH_DEFAULT; |
| 3607 | alloc_flag = DRM_MM_CREATE_DEFAULT; |
| 3608 | } |
Michel Thierry | 101b506 | 2015-10-01 13:33:57 +0100 | [diff] [blame] | 3609 | |
Ben Widawsky | 0a9ae0d | 2013-05-25 12:26:35 -0700 | [diff] [blame] | 3610 | search_free: |
Chris Wilson | 506a8e8 | 2015-12-08 11:55:07 +0000 | [diff] [blame] | 3611 | ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, |
| 3612 | size, alignment, |
| 3613 | obj->cache_level, |
| 3614 | start, end, |
| 3615 | search_flag, |
| 3616 | alloc_flag); |
| 3617 | if (ret) { |
| 3618 | ret = i915_gem_evict_something(dev, vm, size, alignment, |
| 3619 | obj->cache_level, |
| 3620 | start, end, |
| 3621 | flags); |
| 3622 | if (ret == 0) |
| 3623 | goto search_free; |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 3624 | |
Chris Wilson | 506a8e8 | 2015-12-08 11:55:07 +0000 | [diff] [blame] | 3625 | goto err_free_vma; |
| 3626 | } |
Chris Wilson | dc9dd7a | 2012-12-07 20:37:07 +0000 | [diff] [blame] | 3627 | } |
Chris Wilson | 4144f9b | 2014-09-11 08:43:48 +0100 | [diff] [blame] | 3628 | if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) { |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3629 | ret = -EINVAL; |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3630 | goto err_remove_node; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3631 | } |
| 3632 | |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 3633 | trace_i915_vma_bind(vma, flags); |
Daniel Vetter | 0875546 | 2015-04-20 09:04:05 -0700 | [diff] [blame] | 3634 | ret = i915_vma_bind(vma, obj->cache_level, flags); |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 3635 | if (ret) |
Imre Deak | e227330 | 2015-07-09 12:59:05 +0300 | [diff] [blame] | 3636 | goto err_remove_node; |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 3637 | |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 3638 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 3639 | list_add_tail(&vma->vm_link, &vm->inactive_list); |
Chris Wilson | bf1a109 | 2010-08-07 11:01:20 +0100 | [diff] [blame] | 3640 | |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 3641 | return vma; |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3642 | |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3643 | err_remove_node: |
Dan Carpenter | 6286ef9 | 2013-07-19 08:46:27 +0300 | [diff] [blame] | 3644 | drm_mm_remove_node(&vma->node); |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3645 | err_free_vma: |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3646 | i915_gem_vma_destroy(vma); |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 3647 | vma = ERR_PTR(ret); |
Daniel Vetter | bc6bc15 | 2013-07-22 12:12:38 +0200 | [diff] [blame] | 3648 | err_unpin: |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 3649 | i915_gem_object_unpin_pages(obj); |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 3650 | return vma; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3651 | } |
| 3652 | |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 3653 | bool |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 3654 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
| 3655 | bool force) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3656 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3657 | /* If we don't have a page list set up, then we're not pinned |
| 3658 | * to GPU, and we can ignore the cache flush because it'll happen |
| 3659 | * again at bind time. |
| 3660 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3661 | if (obj->pages == NULL) |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 3662 | return false; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3663 | |
Imre Deak | 769ce46 | 2013-02-13 21:56:05 +0200 | [diff] [blame] | 3664 | /* |
| 3665 | * Stolen memory is always coherent with the GPU as it is explicitly |
| 3666 | * marked as wc by the system, or the system is cache-coherent. |
| 3667 | */ |
Chris Wilson | 6a2c423 | 2014-11-04 04:51:40 -0800 | [diff] [blame] | 3668 | if (obj->stolen || obj->phys_handle) |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 3669 | return false; |
Imre Deak | 769ce46 | 2013-02-13 21:56:05 +0200 | [diff] [blame] | 3670 | |
Chris Wilson | 9c23f7f | 2011-03-29 16:59:52 -0700 | [diff] [blame] | 3671 | /* If the GPU is snooping the contents of the CPU cache, |
| 3672 | * we do not need to manually clear the CPU cache lines. However, |
| 3673 | * the caches are only snooped when the render cache is |
| 3674 | * flushed/invalidated. As we always have to emit invalidations |
| 3675 | * and flushes when moving into and out of the RENDER domain, correct |
| 3676 | * snooping behaviour occurs naturally as the result of our domain |
| 3677 | * tracking. |
| 3678 | */ |
Chris Wilson | 0f71979 | 2015-01-13 13:32:52 +0000 | [diff] [blame] | 3679 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) { |
| 3680 | obj->cache_dirty = true; |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 3681 | return false; |
Chris Wilson | 0f71979 | 2015-01-13 13:32:52 +0000 | [diff] [blame] | 3682 | } |
Chris Wilson | 9c23f7f | 2011-03-29 16:59:52 -0700 | [diff] [blame] | 3683 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3684 | trace_i915_gem_object_clflush(obj); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 3685 | drm_clflush_sg(obj->pages); |
Chris Wilson | 0f71979 | 2015-01-13 13:32:52 +0000 | [diff] [blame] | 3686 | obj->cache_dirty = false; |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 3687 | |
| 3688 | return true; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3689 | } |
| 3690 | |
| 3691 | /** Flushes the GTT write domain for the object if it's dirty. */ |
| 3692 | static void |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3693 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3694 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3695 | uint32_t old_write_domain; |
| 3696 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3697 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3698 | return; |
| 3699 | |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 3700 | /* No actual flushing is required for the GTT write domain. Writes |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3701 | * to it immediately go to main memory as far as we know, so there's |
| 3702 | * no chipset flush. It also doesn't land in render cache. |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 3703 | * |
| 3704 | * However, we do have to enforce the order so that all writes through |
| 3705 | * the GTT land before any writes to the device, such as updates to |
| 3706 | * the GATT itself. |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3707 | */ |
Chris Wilson | 63256ec | 2011-01-04 18:42:07 +0000 | [diff] [blame] | 3708 | wmb(); |
| 3709 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3710 | old_write_domain = obj->base.write_domain; |
| 3711 | obj->base.write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3712 | |
Rodrigo Vivi | de152b6 | 2015-07-07 16:28:51 -0700 | [diff] [blame] | 3713 | intel_fb_obj_flush(obj, false, ORIGIN_GTT); |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 3714 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3715 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3716 | obj->base.read_domains, |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3717 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3718 | } |
| 3719 | |
| 3720 | /** Flushes the CPU write domain for the object if it's dirty. */ |
| 3721 | static void |
Daniel Vetter | e62b59e | 2015-01-21 14:53:48 +0100 | [diff] [blame] | 3722 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3723 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3724 | uint32_t old_write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3725 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3726 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3727 | return; |
| 3728 | |
Daniel Vetter | e62b59e | 2015-01-21 14:53:48 +0100 | [diff] [blame] | 3729 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
Chris Wilson | 000433b | 2013-08-08 14:41:09 +0100 | [diff] [blame] | 3730 | i915_gem_chipset_flush(obj->base.dev); |
| 3731 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3732 | old_write_domain = obj->base.write_domain; |
| 3733 | obj->base.write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3734 | |
Rodrigo Vivi | de152b6 | 2015-07-07 16:28:51 -0700 | [diff] [blame] | 3735 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 3736 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3737 | trace_i915_gem_object_change_domain(obj, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3738 | obj->base.read_domains, |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3739 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3740 | } |
| 3741 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3742 | /** |
| 3743 | * Moves a single object to the GTT read, and possibly write domain. |
| 3744 | * |
| 3745 | * This function returns when the move is complete, including waiting on |
| 3746 | * flushes to occur. |
| 3747 | */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 3748 | int |
Chris Wilson | 2021746 | 2010-11-23 15:26:33 +0000 | [diff] [blame] | 3749 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3750 | { |
Joonas Lahtinen | 72e96d6 | 2016-03-30 16:57:10 +0300 | [diff] [blame] | 3751 | struct drm_device *dev = obj->base.dev; |
| 3752 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 3753 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3754 | uint32_t old_write_domain, old_read_domains; |
Chris Wilson | 43566de | 2015-01-02 16:29:29 +0530 | [diff] [blame] | 3755 | struct i915_vma *vma; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3756 | int ret; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3757 | |
Chris Wilson | 8d7e3de | 2011-02-07 15:23:02 +0000 | [diff] [blame] | 3758 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
| 3759 | return 0; |
| 3760 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 3761 | ret = i915_gem_object_wait_rendering(obj, !write); |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 3762 | if (ret) |
| 3763 | return ret; |
| 3764 | |
Chris Wilson | 43566de | 2015-01-02 16:29:29 +0530 | [diff] [blame] | 3765 | /* Flush and acquire obj->pages so that we are coherent through |
| 3766 | * direct access in memory with previous cached writes through |
| 3767 | * shmemfs and that our cache domain tracking remains valid. |
| 3768 | * For example, if the obj->filp was moved to swap without us |
| 3769 | * being notified and releasing the pages, we would mistakenly |
| 3770 | * continue to assume that the obj remained out of the CPU cached |
| 3771 | * domain. |
| 3772 | */ |
| 3773 | ret = i915_gem_object_get_pages(obj); |
| 3774 | if (ret) |
| 3775 | return ret; |
| 3776 | |
Daniel Vetter | e62b59e | 2015-01-21 14:53:48 +0100 | [diff] [blame] | 3777 | i915_gem_object_flush_cpu_write_domain(obj); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3778 | |
Chris Wilson | d0a5778 | 2012-10-09 19:24:37 +0100 | [diff] [blame] | 3779 | /* Serialise direct access to this object with the barriers for |
| 3780 | * coherent writes from the GPU, by effectively invalidating the |
| 3781 | * GTT domain upon first access. |
| 3782 | */ |
| 3783 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
| 3784 | mb(); |
| 3785 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3786 | old_write_domain = obj->base.write_domain; |
| 3787 | old_read_domains = obj->base.read_domains; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3788 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3789 | /* It should now be out of any other write domains, and we can update |
| 3790 | * the domain values for our changes. |
| 3791 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3792 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
| 3793 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3794 | if (write) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 3795 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
| 3796 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; |
| 3797 | obj->dirty = 1; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3798 | } |
| 3799 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3800 | trace_i915_gem_object_change_domain(obj, |
| 3801 | old_read_domains, |
| 3802 | old_write_domain); |
| 3803 | |
Chris Wilson | 8325a09 | 2012-04-24 15:52:35 +0100 | [diff] [blame] | 3804 | /* And bump the LRU for this access */ |
Chris Wilson | 43566de | 2015-01-02 16:29:29 +0530 | [diff] [blame] | 3805 | vma = i915_gem_obj_to_ggtt(obj); |
| 3806 | if (vma && drm_mm_node_allocated(&vma->node) && !obj->active) |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 3807 | list_move_tail(&vma->vm_link, |
Joonas Lahtinen | 72e96d6 | 2016-03-30 16:57:10 +0300 | [diff] [blame] | 3808 | &ggtt->base.inactive_list); |
Chris Wilson | 8325a09 | 2012-04-24 15:52:35 +0100 | [diff] [blame] | 3809 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3810 | return 0; |
| 3811 | } |
| 3812 | |
Chris Wilson | ef55f92 | 2015-10-09 14:11:27 +0100 | [diff] [blame] | 3813 | /** |
| 3814 | * Changes the cache-level of an object across all VMA. |
| 3815 | * |
| 3816 | * After this function returns, the object will be in the new cache-level |
| 3817 | * across all GTT and the contents of the backing storage will be coherent, |
| 3818 | * with respect to the new cache-level. In order to keep the backing storage |
| 3819 | * coherent for all users, we only allow a single cache level to be set |
| 3820 | * globally on the object and prevent it from being changed whilst the |
| 3821 | * hardware is reading from the object. That is if the object is currently |
| 3822 | * on the scanout it will be set to uncached (or equivalent display |
| 3823 | * cache coherency) and all non-MOCS GPU access will also be uncached so |
| 3824 | * that all direct access to the scanout remains coherent. |
| 3825 | */ |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3826 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
| 3827 | enum i915_cache_level cache_level) |
| 3828 | { |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 3829 | struct drm_device *dev = obj->base.dev; |
Chris Wilson | df6f783 | 2014-03-21 07:40:56 +0000 | [diff] [blame] | 3830 | struct i915_vma *vma, *next; |
Chris Wilson | ef55f92 | 2015-10-09 14:11:27 +0100 | [diff] [blame] | 3831 | bool bound = false; |
Ville Syrjälä | ed75a55 | 2015-08-11 19:47:10 +0300 | [diff] [blame] | 3832 | int ret = 0; |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3833 | |
| 3834 | if (obj->cache_level == cache_level) |
Ville Syrjälä | ed75a55 | 2015-08-11 19:47:10 +0300 | [diff] [blame] | 3835 | goto out; |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3836 | |
Chris Wilson | ef55f92 | 2015-10-09 14:11:27 +0100 | [diff] [blame] | 3837 | /* Inspect the list of currently bound VMA and unbind any that would |
| 3838 | * be invalid given the new cache-level. This is principally to |
| 3839 | * catch the issue of the CS prefetch crossing page boundaries and |
| 3840 | * reading an invalid PTE on older architectures. |
| 3841 | */ |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 3842 | list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) { |
Chris Wilson | ef55f92 | 2015-10-09 14:11:27 +0100 | [diff] [blame] | 3843 | if (!drm_mm_node_allocated(&vma->node)) |
| 3844 | continue; |
| 3845 | |
| 3846 | if (vma->pin_count) { |
| 3847 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
| 3848 | return -EBUSY; |
| 3849 | } |
| 3850 | |
Chris Wilson | 4144f9b | 2014-09-11 08:43:48 +0100 | [diff] [blame] | 3851 | if (!i915_gem_valid_gtt_space(vma, cache_level)) { |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 3852 | ret = i915_vma_unbind(vma); |
Ben Widawsky | 3089c6f | 2013-07-31 17:00:03 -0700 | [diff] [blame] | 3853 | if (ret) |
| 3854 | return ret; |
Chris Wilson | ef55f92 | 2015-10-09 14:11:27 +0100 | [diff] [blame] | 3855 | } else |
| 3856 | bound = true; |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 3857 | } |
| 3858 | |
Chris Wilson | ef55f92 | 2015-10-09 14:11:27 +0100 | [diff] [blame] | 3859 | /* We can reuse the existing drm_mm nodes but need to change the |
| 3860 | * cache-level on the PTE. We could simply unbind them all and |
| 3861 | * rebind with the correct cache-level on next use. However since |
| 3862 | * we already have a valid slot, dma mapping, pages etc, we may as |
| 3863 | * rewrite the PTE in the belief that doing so tramples upon less |
| 3864 | * state and so involves less work. |
| 3865 | */ |
| 3866 | if (bound) { |
| 3867 | /* Before we change the PTE, the GPU must not be accessing it. |
| 3868 | * If we wait upon the object, we know that all the bound |
| 3869 | * VMA are no longer active. |
| 3870 | */ |
Chris Wilson | 2e2f351 | 2015-04-27 13:41:14 +0100 | [diff] [blame] | 3871 | ret = i915_gem_object_wait_rendering(obj, false); |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3872 | if (ret) |
| 3873 | return ret; |
| 3874 | |
Chris Wilson | ef55f92 | 2015-10-09 14:11:27 +0100 | [diff] [blame] | 3875 | if (!HAS_LLC(dev) && cache_level != I915_CACHE_NONE) { |
| 3876 | /* Access to snoopable pages through the GTT is |
| 3877 | * incoherent and on some machines causes a hard |
| 3878 | * lockup. Relinquish the CPU mmaping to force |
| 3879 | * userspace to refault in the pages and we can |
| 3880 | * then double check if the GTT mapping is still |
| 3881 | * valid for that pointer access. |
| 3882 | */ |
| 3883 | i915_gem_release_mmap(obj); |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3884 | |
Chris Wilson | ef55f92 | 2015-10-09 14:11:27 +0100 | [diff] [blame] | 3885 | /* As we no longer need a fence for GTT access, |
| 3886 | * we can relinquish it now (and so prevent having |
| 3887 | * to steal a fence from someone else on the next |
| 3888 | * fence request). Note GPU activity would have |
| 3889 | * dropped the fence as all snoopable access is |
| 3890 | * supposed to be linear. |
| 3891 | */ |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3892 | ret = i915_gem_object_put_fence(obj); |
| 3893 | if (ret) |
| 3894 | return ret; |
Chris Wilson | ef55f92 | 2015-10-09 14:11:27 +0100 | [diff] [blame] | 3895 | } else { |
| 3896 | /* We either have incoherent backing store and |
| 3897 | * so no GTT access or the architecture is fully |
| 3898 | * coherent. In such cases, existing GTT mmaps |
| 3899 | * ignore the cache bit in the PTE and we can |
| 3900 | * rewrite it without confusing the GPU or having |
| 3901 | * to force userspace to fault back in its mmaps. |
| 3902 | */ |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3903 | } |
| 3904 | |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 3905 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
Chris Wilson | ef55f92 | 2015-10-09 14:11:27 +0100 | [diff] [blame] | 3906 | if (!drm_mm_node_allocated(&vma->node)) |
| 3907 | continue; |
| 3908 | |
| 3909 | ret = i915_vma_bind(vma, cache_level, PIN_UPDATE); |
| 3910 | if (ret) |
| 3911 | return ret; |
| 3912 | } |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3913 | } |
| 3914 | |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 3915 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 3916 | vma->node.color = cache_level; |
| 3917 | obj->cache_level = cache_level; |
| 3918 | |
Ville Syrjälä | ed75a55 | 2015-08-11 19:47:10 +0300 | [diff] [blame] | 3919 | out: |
Chris Wilson | ef55f92 | 2015-10-09 14:11:27 +0100 | [diff] [blame] | 3920 | /* Flush the dirty CPU caches to the backing storage so that the |
| 3921 | * object is now coherent at its new cache level (with respect |
| 3922 | * to the access domain). |
| 3923 | */ |
Chris Wilson | 0f71979 | 2015-01-13 13:32:52 +0000 | [diff] [blame] | 3924 | if (obj->cache_dirty && |
| 3925 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && |
| 3926 | cpu_write_needs_clflush(obj)) { |
| 3927 | if (i915_gem_clflush_object(obj, true)) |
| 3928 | i915_gem_chipset_flush(obj->base.dev); |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3929 | } |
| 3930 | |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 3931 | return 0; |
| 3932 | } |
| 3933 | |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3934 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
| 3935 | struct drm_file *file) |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3936 | { |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3937 | struct drm_i915_gem_caching *args = data; |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3938 | struct drm_i915_gem_object *obj; |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3939 | |
| 3940 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | 432be69 | 2015-05-07 12:14:55 +0100 | [diff] [blame] | 3941 | if (&obj->base == NULL) |
| 3942 | return -ENOENT; |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3943 | |
Chris Wilson | 651d794 | 2013-08-08 14:41:10 +0100 | [diff] [blame] | 3944 | switch (obj->cache_level) { |
| 3945 | case I915_CACHE_LLC: |
| 3946 | case I915_CACHE_L3_LLC: |
| 3947 | args->caching = I915_CACHING_CACHED; |
| 3948 | break; |
| 3949 | |
Chris Wilson | 4257d3b | 2013-08-08 14:41:11 +0100 | [diff] [blame] | 3950 | case I915_CACHE_WT: |
| 3951 | args->caching = I915_CACHING_DISPLAY; |
| 3952 | break; |
| 3953 | |
Chris Wilson | 651d794 | 2013-08-08 14:41:10 +0100 | [diff] [blame] | 3954 | default: |
| 3955 | args->caching = I915_CACHING_NONE; |
| 3956 | break; |
| 3957 | } |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3958 | |
Chris Wilson | 432be69 | 2015-05-07 12:14:55 +0100 | [diff] [blame] | 3959 | drm_gem_object_unreference_unlocked(&obj->base); |
| 3960 | return 0; |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3961 | } |
| 3962 | |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3963 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
| 3964 | struct drm_file *file) |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3965 | { |
Imre Deak | fd0fe6a | 2015-11-04 21:25:32 +0200 | [diff] [blame] | 3966 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3967 | struct drm_i915_gem_caching *args = data; |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3968 | struct drm_i915_gem_object *obj; |
| 3969 | enum i915_cache_level level; |
| 3970 | int ret; |
| 3971 | |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3972 | switch (args->caching) { |
| 3973 | case I915_CACHING_NONE: |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3974 | level = I915_CACHE_NONE; |
| 3975 | break; |
Ben Widawsky | 199adf4 | 2012-09-21 17:01:20 -0700 | [diff] [blame] | 3976 | case I915_CACHING_CACHED: |
Imre Deak | e5756c1 | 2015-08-14 18:43:30 +0300 | [diff] [blame] | 3977 | /* |
| 3978 | * Due to a HW issue on BXT A stepping, GPU stores via a |
| 3979 | * snooped mapping may leave stale data in a corresponding CPU |
| 3980 | * cacheline, whereas normally such cachelines would get |
| 3981 | * invalidated. |
| 3982 | */ |
Tvrtko Ursulin | ca37780 | 2016-03-02 12:10:31 +0000 | [diff] [blame] | 3983 | if (!HAS_LLC(dev) && !HAS_SNOOP(dev)) |
Imre Deak | e5756c1 | 2015-08-14 18:43:30 +0300 | [diff] [blame] | 3984 | return -ENODEV; |
| 3985 | |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3986 | level = I915_CACHE_LLC; |
| 3987 | break; |
Chris Wilson | 4257d3b | 2013-08-08 14:41:11 +0100 | [diff] [blame] | 3988 | case I915_CACHING_DISPLAY: |
| 3989 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; |
| 3990 | break; |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 3991 | default: |
| 3992 | return -EINVAL; |
| 3993 | } |
| 3994 | |
Imre Deak | fd0fe6a | 2015-11-04 21:25:32 +0200 | [diff] [blame] | 3995 | intel_runtime_pm_get(dev_priv); |
| 3996 | |
Ben Widawsky | 3bc2913 | 2012-09-26 16:15:20 -0700 | [diff] [blame] | 3997 | ret = i915_mutex_lock_interruptible(dev); |
| 3998 | if (ret) |
Imre Deak | fd0fe6a | 2015-11-04 21:25:32 +0200 | [diff] [blame] | 3999 | goto rpm_put; |
Ben Widawsky | 3bc2913 | 2012-09-26 16:15:20 -0700 | [diff] [blame] | 4000 | |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 4001 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
| 4002 | if (&obj->base == NULL) { |
| 4003 | ret = -ENOENT; |
| 4004 | goto unlock; |
| 4005 | } |
| 4006 | |
| 4007 | ret = i915_gem_object_set_cache_level(obj, level); |
| 4008 | |
| 4009 | drm_gem_object_unreference(&obj->base); |
| 4010 | unlock: |
| 4011 | mutex_unlock(&dev->struct_mutex); |
Imre Deak | fd0fe6a | 2015-11-04 21:25:32 +0200 | [diff] [blame] | 4012 | rpm_put: |
| 4013 | intel_runtime_pm_put(dev_priv); |
| 4014 | |
Chris Wilson | e6994ae | 2012-07-10 10:27:08 +0100 | [diff] [blame] | 4015 | return ret; |
| 4016 | } |
| 4017 | |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 4018 | /* |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 4019 | * Prepare buffer for display plane (scanout, cursors, etc). |
| 4020 | * Can be called from an uninterruptible phase (modesetting) and allows |
| 4021 | * any flushes to be pipelined (for pageflips). |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 4022 | */ |
| 4023 | int |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 4024 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
| 4025 | u32 alignment, |
Tvrtko Ursulin | e661733 | 2015-03-23 11:10:33 +0000 | [diff] [blame] | 4026 | const struct i915_ggtt_view *view) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 4027 | { |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 4028 | u32 old_read_domains, old_write_domain; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 4029 | int ret; |
| 4030 | |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 4031 | /* Mark the pin_display early so that we account for the |
| 4032 | * display coherency whilst setting up the cache domains. |
| 4033 | */ |
Tvrtko Ursulin | 8a0c39b | 2015-04-13 11:50:09 +0100 | [diff] [blame] | 4034 | obj->pin_display++; |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 4035 | |
Eric Anholt | a7ef064 | 2011-03-29 16:59:54 -0700 | [diff] [blame] | 4036 | /* The display engine is not coherent with the LLC cache on gen6. As |
| 4037 | * a result, we make sure that the pinning that is about to occur is |
| 4038 | * done with uncached PTEs. This is lowest common denominator for all |
| 4039 | * chipsets. |
| 4040 | * |
| 4041 | * However for gen6+, we could do better by using the GFDT bit instead |
| 4042 | * of uncaching, which would allow us to flush all the LLC-cached data |
| 4043 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. |
| 4044 | */ |
Chris Wilson | 651d794 | 2013-08-08 14:41:10 +0100 | [diff] [blame] | 4045 | ret = i915_gem_object_set_cache_level(obj, |
| 4046 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); |
Eric Anholt | a7ef064 | 2011-03-29 16:59:54 -0700 | [diff] [blame] | 4047 | if (ret) |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 4048 | goto err_unpin_display; |
Eric Anholt | a7ef064 | 2011-03-29 16:59:54 -0700 | [diff] [blame] | 4049 | |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 4050 | /* As the user may map the buffer once pinned in the display plane |
| 4051 | * (e.g. libkms for the bootup splash), we have to ensure that we |
| 4052 | * always use map_and_fenceable for all scanout buffers. |
| 4053 | */ |
Tvrtko Ursulin | 50470bb | 2015-03-23 11:10:36 +0000 | [diff] [blame] | 4054 | ret = i915_gem_object_ggtt_pin(obj, view, alignment, |
| 4055 | view->type == I915_GGTT_VIEW_NORMAL ? |
| 4056 | PIN_MAPPABLE : 0); |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 4057 | if (ret) |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 4058 | goto err_unpin_display; |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 4059 | |
Daniel Vetter | e62b59e | 2015-01-21 14:53:48 +0100 | [diff] [blame] | 4060 | i915_gem_object_flush_cpu_write_domain(obj); |
Chris Wilson | b118c1e | 2010-05-27 13:18:14 +0100 | [diff] [blame] | 4061 | |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 4062 | old_write_domain = obj->base.write_domain; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4063 | old_read_domains = obj->base.read_domains; |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 4064 | |
| 4065 | /* It should now be out of any other write domains, and we can update |
| 4066 | * the domain values for our changes. |
| 4067 | */ |
Chris Wilson | e5f1d96 | 2012-07-20 12:41:00 +0100 | [diff] [blame] | 4068 | obj->base.write_domain = 0; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4069 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 4070 | |
| 4071 | trace_i915_gem_object_change_domain(obj, |
| 4072 | old_read_domains, |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 4073 | old_write_domain); |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 4074 | |
| 4075 | return 0; |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 4076 | |
| 4077 | err_unpin_display: |
Tvrtko Ursulin | 8a0c39b | 2015-04-13 11:50:09 +0100 | [diff] [blame] | 4078 | obj->pin_display--; |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 4079 | return ret; |
| 4080 | } |
| 4081 | |
| 4082 | void |
Tvrtko Ursulin | e661733 | 2015-03-23 11:10:33 +0000 | [diff] [blame] | 4083 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj, |
| 4084 | const struct i915_ggtt_view *view) |
Chris Wilson | cc98b41 | 2013-08-09 12:25:09 +0100 | [diff] [blame] | 4085 | { |
Tvrtko Ursulin | 8a0c39b | 2015-04-13 11:50:09 +0100 | [diff] [blame] | 4086 | if (WARN_ON(obj->pin_display == 0)) |
| 4087 | return; |
| 4088 | |
Tvrtko Ursulin | e661733 | 2015-03-23 11:10:33 +0000 | [diff] [blame] | 4089 | i915_gem_object_ggtt_unpin_view(obj, view); |
| 4090 | |
Tvrtko Ursulin | 8a0c39b | 2015-04-13 11:50:09 +0100 | [diff] [blame] | 4091 | obj->pin_display--; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 4092 | } |
| 4093 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4094 | /** |
| 4095 | * Moves a single object to the CPU read, and possibly write domain. |
| 4096 | * |
| 4097 | * This function returns when the move is complete, including waiting on |
| 4098 | * flushes to occur. |
| 4099 | */ |
Chris Wilson | dabdfe0 | 2012-03-26 10:10:27 +0200 | [diff] [blame] | 4100 | int |
Chris Wilson | 919926a | 2010-11-12 13:42:53 +0000 | [diff] [blame] | 4101 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4102 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 4103 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4104 | int ret; |
| 4105 | |
Chris Wilson | 8d7e3de | 2011-02-07 15:23:02 +0000 | [diff] [blame] | 4106 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
| 4107 | return 0; |
| 4108 | |
Chris Wilson | 0201f1e | 2012-07-20 12:41:01 +0100 | [diff] [blame] | 4109 | ret = i915_gem_object_wait_rendering(obj, !write); |
Chris Wilson | 8824178 | 2011-01-07 17:09:48 +0000 | [diff] [blame] | 4110 | if (ret) |
| 4111 | return ret; |
| 4112 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4113 | i915_gem_object_flush_gtt_write_domain(obj); |
| 4114 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4115 | old_write_domain = obj->base.write_domain; |
| 4116 | old_read_domains = obj->base.read_domains; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 4117 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4118 | /* Flush the CPU cache if it's still invalid. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4119 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
Chris Wilson | 2c22569 | 2013-08-09 12:26:45 +0100 | [diff] [blame] | 4120 | i915_gem_clflush_object(obj, false); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4121 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4122 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4123 | } |
| 4124 | |
| 4125 | /* It should now be out of any other write domains, and we can update |
| 4126 | * the domain values for our changes. |
| 4127 | */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4128 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4129 | |
| 4130 | /* If we're writing through the CPU, then the GPU read domains will |
| 4131 | * need to be invalidated at next use. |
| 4132 | */ |
| 4133 | if (write) { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4134 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 4135 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4136 | } |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 4137 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 4138 | trace_i915_gem_object_change_domain(obj, |
| 4139 | old_read_domains, |
| 4140 | old_write_domain); |
| 4141 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 4142 | return 0; |
| 4143 | } |
| 4144 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4145 | /* Throttle our rendering by waiting until the ring has completed our requests |
| 4146 | * emitted over 20 msec ago. |
| 4147 | * |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4148 | * Note that if we were to use the current jiffies each time around the loop, |
| 4149 | * we wouldn't escape the function with any frames outstanding if the time to |
| 4150 | * render a frame was over 20ms. |
| 4151 | * |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4152 | * This should get us reasonable parallelism between CPU and GPU but also |
| 4153 | * relatively low latency when blocking on a particular request to finish. |
| 4154 | */ |
| 4155 | static int |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4156 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4157 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4158 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4159 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Chris Wilson | d0bc54f | 2015-05-21 21:01:48 +0100 | [diff] [blame] | 4160 | unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES; |
John Harrison | 54fb241 | 2014-11-24 18:49:27 +0000 | [diff] [blame] | 4161 | struct drm_i915_gem_request *request, *target = NULL; |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4162 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4163 | |
Daniel Vetter | 308887a | 2012-11-14 17:14:06 +0100 | [diff] [blame] | 4164 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
| 4165 | if (ret) |
| 4166 | return ret; |
| 4167 | |
Chris Wilson | f4457ae | 2016-04-13 17:35:08 +0100 | [diff] [blame] | 4168 | /* ABI: return -EIO if already wedged */ |
| 4169 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
| 4170 | return -EIO; |
Chris Wilson | e110e8d | 2011-01-26 15:39:14 +0000 | [diff] [blame] | 4171 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 4172 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4173 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4174 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
| 4175 | break; |
| 4176 | |
John Harrison | fcfa423c | 2015-05-29 17:44:12 +0100 | [diff] [blame] | 4177 | /* |
| 4178 | * Note that the request might not have been submitted yet. |
| 4179 | * In which case emitted_jiffies will be zero. |
| 4180 | */ |
| 4181 | if (!request->emitted_jiffies) |
| 4182 | continue; |
| 4183 | |
John Harrison | 54fb241 | 2014-11-24 18:49:27 +0000 | [diff] [blame] | 4184 | target = request; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4185 | } |
John Harrison | ff86588 | 2014-11-24 18:49:28 +0000 | [diff] [blame] | 4186 | if (target) |
| 4187 | i915_gem_request_reference(target); |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 4188 | spin_unlock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4189 | |
John Harrison | 54fb241 | 2014-11-24 18:49:27 +0000 | [diff] [blame] | 4190 | if (target == NULL) |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4191 | return 0; |
| 4192 | |
Chris Wilson | 299259a | 2016-04-13 17:35:06 +0100 | [diff] [blame] | 4193 | ret = __i915_wait_request(target, true, NULL, NULL); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4194 | if (ret == 0) |
| 4195 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4196 | |
Chris Wilson | 41037f9 | 2015-03-27 11:01:36 +0000 | [diff] [blame] | 4197 | i915_gem_request_unreference__unlocked(target); |
John Harrison | ff86588 | 2014-11-24 18:49:28 +0000 | [diff] [blame] | 4198 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4199 | return ret; |
| 4200 | } |
| 4201 | |
Chris Wilson | d23db88 | 2014-05-23 08:48:08 +0200 | [diff] [blame] | 4202 | static bool |
| 4203 | i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags) |
| 4204 | { |
| 4205 | struct drm_i915_gem_object *obj = vma->obj; |
| 4206 | |
| 4207 | if (alignment && |
| 4208 | vma->node.start & (alignment - 1)) |
| 4209 | return true; |
| 4210 | |
| 4211 | if (flags & PIN_MAPPABLE && !obj->map_and_fenceable) |
| 4212 | return true; |
| 4213 | |
| 4214 | if (flags & PIN_OFFSET_BIAS && |
| 4215 | vma->node.start < (flags & PIN_OFFSET_MASK)) |
| 4216 | return true; |
| 4217 | |
Chris Wilson | 506a8e8 | 2015-12-08 11:55:07 +0000 | [diff] [blame] | 4218 | if (flags & PIN_OFFSET_FIXED && |
| 4219 | vma->node.start != (flags & PIN_OFFSET_MASK)) |
| 4220 | return true; |
| 4221 | |
Chris Wilson | d23db88 | 2014-05-23 08:48:08 +0200 | [diff] [blame] | 4222 | return false; |
| 4223 | } |
| 4224 | |
Chris Wilson | d0710ab | 2015-11-20 14:16:39 +0000 | [diff] [blame] | 4225 | void __i915_vma_set_map_and_fenceable(struct i915_vma *vma) |
| 4226 | { |
| 4227 | struct drm_i915_gem_object *obj = vma->obj; |
| 4228 | bool mappable, fenceable; |
| 4229 | u32 fence_size, fence_alignment; |
| 4230 | |
| 4231 | fence_size = i915_gem_get_gtt_size(obj->base.dev, |
| 4232 | obj->base.size, |
| 4233 | obj->tiling_mode); |
| 4234 | fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev, |
| 4235 | obj->base.size, |
| 4236 | obj->tiling_mode, |
| 4237 | true); |
| 4238 | |
| 4239 | fenceable = (vma->node.size == fence_size && |
| 4240 | (vma->node.start & (fence_alignment - 1)) == 0); |
| 4241 | |
| 4242 | mappable = (vma->node.start + fence_size <= |
Joonas Lahtinen | 62106b4 | 2016-03-18 10:42:57 +0200 | [diff] [blame] | 4243 | to_i915(obj->base.dev)->ggtt.mappable_end); |
Chris Wilson | d0710ab | 2015-11-20 14:16:39 +0000 | [diff] [blame] | 4244 | |
| 4245 | obj->map_and_fenceable = mappable && fenceable; |
| 4246 | } |
| 4247 | |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 4248 | static int |
| 4249 | i915_gem_object_do_pin(struct drm_i915_gem_object *obj, |
| 4250 | struct i915_address_space *vm, |
| 4251 | const struct i915_ggtt_view *ggtt_view, |
| 4252 | uint32_t alignment, |
| 4253 | uint64_t flags) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4254 | { |
Ben Widawsky | 6e7186a | 2014-05-06 22:21:36 -0700 | [diff] [blame] | 4255 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4256 | struct i915_vma *vma; |
Chris Wilson | ef79e17 | 2014-10-31 13:53:52 +0000 | [diff] [blame] | 4257 | unsigned bound; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4258 | int ret; |
| 4259 | |
Ben Widawsky | 6e7186a | 2014-05-06 22:21:36 -0700 | [diff] [blame] | 4260 | if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base)) |
| 4261 | return -ENODEV; |
| 4262 | |
Daniel Vetter | bf3d149 | 2014-02-14 14:01:12 +0100 | [diff] [blame] | 4263 | if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm))) |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 4264 | return -EINVAL; |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4265 | |
Chris Wilson | c826c44 | 2014-10-31 13:53:53 +0000 | [diff] [blame] | 4266 | if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE)) |
| 4267 | return -EINVAL; |
| 4268 | |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 4269 | if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view)) |
| 4270 | return -EINVAL; |
| 4271 | |
| 4272 | vma = ggtt_view ? i915_gem_obj_to_ggtt_view(obj, ggtt_view) : |
| 4273 | i915_gem_obj_to_vma(obj, vm); |
| 4274 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4275 | if (vma) { |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 4276 | if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
| 4277 | return -EBUSY; |
| 4278 | |
Chris Wilson | d23db88 | 2014-05-23 08:48:08 +0200 | [diff] [blame] | 4279 | if (i915_vma_misplaced(vma, alignment, flags)) { |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 4280 | WARN(vma->pin_count, |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 4281 | "bo is already pinned in %s with incorrect alignment:" |
Michel Thierry | 088e0df | 2015-08-07 17:40:17 +0100 | [diff] [blame] | 4282 | " offset=%08x %08x, req.alignment=%x, req.map_and_fenceable=%d," |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 4283 | " obj->map_and_fenceable=%d\n", |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 4284 | ggtt_view ? "ggtt" : "ppgtt", |
Michel Thierry | 088e0df | 2015-08-07 17:40:17 +0100 | [diff] [blame] | 4285 | upper_32_bits(vma->node.start), |
| 4286 | lower_32_bits(vma->node.start), |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 4287 | alignment, |
Chris Wilson | d23db88 | 2014-05-23 08:48:08 +0200 | [diff] [blame] | 4288 | !!(flags & PIN_MAPPABLE), |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4289 | obj->map_and_fenceable); |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4290 | ret = i915_vma_unbind(vma); |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 4291 | if (ret) |
| 4292 | return ret; |
Daniel Vetter | 8ea99c9 | 2014-02-14 14:01:21 +0100 | [diff] [blame] | 4293 | |
| 4294 | vma = NULL; |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 4295 | } |
| 4296 | } |
| 4297 | |
Chris Wilson | ef79e17 | 2014-10-31 13:53:52 +0000 | [diff] [blame] | 4298 | bound = vma ? vma->bound : 0; |
Daniel Vetter | 8ea99c9 | 2014-02-14 14:01:21 +0100 | [diff] [blame] | 4299 | if (vma == NULL || !drm_mm_node_allocated(&vma->node)) { |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 4300 | vma = i915_gem_object_bind_to_vm(obj, vm, ggtt_view, alignment, |
| 4301 | flags); |
Daniel Vetter | 262de14 | 2014-02-14 14:01:20 +0100 | [diff] [blame] | 4302 | if (IS_ERR(vma)) |
| 4303 | return PTR_ERR(vma); |
Daniel Vetter | 0875546 | 2015-04-20 09:04:05 -0700 | [diff] [blame] | 4304 | } else { |
| 4305 | ret = i915_vma_bind(vma, obj->cache_level, flags); |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 4306 | if (ret) |
| 4307 | return ret; |
| 4308 | } |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 4309 | |
Joonas Lahtinen | 91e6711 | 2015-05-06 14:33:58 +0300 | [diff] [blame] | 4310 | if (ggtt_view && ggtt_view->type == I915_GGTT_VIEW_NORMAL && |
| 4311 | (bound ^ vma->bound) & GLOBAL_BIND) { |
Chris Wilson | d0710ab | 2015-11-20 14:16:39 +0000 | [diff] [blame] | 4312 | __i915_vma_set_map_and_fenceable(vma); |
Joonas Lahtinen | 91e6711 | 2015-05-06 14:33:58 +0300 | [diff] [blame] | 4313 | WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable); |
| 4314 | } |
Chris Wilson | ef79e17 | 2014-10-31 13:53:52 +0000 | [diff] [blame] | 4315 | |
Daniel Vetter | 8ea99c9 | 2014-02-14 14:01:21 +0100 | [diff] [blame] | 4316 | vma->pin_count++; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4317 | return 0; |
| 4318 | } |
| 4319 | |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 4320 | int |
| 4321 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
| 4322 | struct i915_address_space *vm, |
| 4323 | uint32_t alignment, |
| 4324 | uint64_t flags) |
| 4325 | { |
| 4326 | return i915_gem_object_do_pin(obj, vm, |
| 4327 | i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL, |
| 4328 | alignment, flags); |
| 4329 | } |
| 4330 | |
| 4331 | int |
| 4332 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, |
| 4333 | const struct i915_ggtt_view *view, |
| 4334 | uint32_t alignment, |
| 4335 | uint64_t flags) |
| 4336 | { |
Joonas Lahtinen | 72e96d6 | 2016-03-30 16:57:10 +0300 | [diff] [blame] | 4337 | struct drm_device *dev = obj->base.dev; |
| 4338 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 4339 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
| 4340 | |
Matthew Auld | ade7daa | 2016-03-24 15:54:20 +0000 | [diff] [blame] | 4341 | BUG_ON(!view); |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 4342 | |
Joonas Lahtinen | 72e96d6 | 2016-03-30 16:57:10 +0300 | [diff] [blame] | 4343 | return i915_gem_object_do_pin(obj, &ggtt->base, view, |
Tvrtko Ursulin | 6fafab7 | 2015-03-17 15:36:51 +0000 | [diff] [blame] | 4344 | alignment, flags | PIN_GLOBAL); |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 4345 | } |
| 4346 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4347 | void |
Tvrtko Ursulin | e661733 | 2015-03-23 11:10:33 +0000 | [diff] [blame] | 4348 | i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj, |
| 4349 | const struct i915_ggtt_view *view) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4350 | { |
Tvrtko Ursulin | e661733 | 2015-03-23 11:10:33 +0000 | [diff] [blame] | 4351 | struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4352 | |
Tvrtko Ursulin | e661733 | 2015-03-23 11:10:33 +0000 | [diff] [blame] | 4353 | WARN_ON(vma->pin_count == 0); |
Joonas Lahtinen | 9abc464 | 2015-03-27 13:09:22 +0200 | [diff] [blame] | 4354 | WARN_ON(!i915_gem_obj_ggtt_bound_view(obj, view)); |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 4355 | |
Chris Wilson | 3015465 | 2015-04-07 17:28:24 +0100 | [diff] [blame] | 4356 | --vma->pin_count; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4357 | } |
| 4358 | |
| 4359 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4360 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4361 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4362 | { |
| 4363 | struct drm_i915_gem_busy *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4364 | struct drm_i915_gem_object *obj; |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 4365 | int ret; |
| 4366 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4367 | ret = i915_mutex_lock_interruptible(dev); |
| 4368 | if (ret) |
| 4369 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4370 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4371 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 4372 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4373 | ret = -ENOENT; |
| 4374 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4375 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4376 | |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 4377 | /* Count all active objects as busy, even if they are currently not used |
| 4378 | * by the gpu. Users of this interface expect objects to eventually |
| 4379 | * become non-busy without any further actions, therefore emit any |
| 4380 | * necessary flushes here. |
Eric Anholt | c4de0a5 | 2008-12-14 19:05:04 -0800 | [diff] [blame] | 4381 | */ |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 4382 | ret = i915_gem_object_flush_active(obj); |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 4383 | if (ret) |
| 4384 | goto unref; |
Daniel Vetter | 30dfebf | 2012-06-01 15:21:23 +0200 | [diff] [blame] | 4385 | |
Chris Wilson | 426960b | 2016-01-15 16:51:46 +0000 | [diff] [blame] | 4386 | args->busy = 0; |
| 4387 | if (obj->active) { |
| 4388 | int i; |
| 4389 | |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 4390 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
Chris Wilson | 426960b | 2016-01-15 16:51:46 +0000 | [diff] [blame] | 4391 | struct drm_i915_gem_request *req; |
| 4392 | |
| 4393 | req = obj->last_read_req[i]; |
| 4394 | if (req) |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 4395 | args->busy |= 1 << (16 + req->engine->exec_id); |
Chris Wilson | 426960b | 2016-01-15 16:51:46 +0000 | [diff] [blame] | 4396 | } |
| 4397 | if (obj->last_write_req) |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 4398 | args->busy |= obj->last_write_req->engine->exec_id; |
Chris Wilson | 426960b | 2016-01-15 16:51:46 +0000 | [diff] [blame] | 4399 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4400 | |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 4401 | unref: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4402 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4403 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4404 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4405 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4406 | } |
| 4407 | |
| 4408 | int |
| 4409 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
| 4410 | struct drm_file *file_priv) |
| 4411 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 4412 | return i915_gem_ring_throttle(dev, file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4413 | } |
| 4414 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4415 | int |
| 4416 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
| 4417 | struct drm_file *file_priv) |
| 4418 | { |
Daniel Vetter | 656bfa3 | 2014-11-20 09:26:30 +0100 | [diff] [blame] | 4419 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4420 | struct drm_i915_gem_madvise *args = data; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4421 | struct drm_i915_gem_object *obj; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 4422 | int ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4423 | |
| 4424 | switch (args->madv) { |
| 4425 | case I915_MADV_DONTNEED: |
| 4426 | case I915_MADV_WILLNEED: |
| 4427 | break; |
| 4428 | default: |
| 4429 | return -EINVAL; |
| 4430 | } |
| 4431 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4432 | ret = i915_mutex_lock_interruptible(dev); |
| 4433 | if (ret) |
| 4434 | return ret; |
| 4435 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4436 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 4437 | if (&obj->base == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4438 | ret = -ENOENT; |
| 4439 | goto unlock; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4440 | } |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4441 | |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 4442 | if (i915_gem_obj_is_pinned(obj)) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4443 | ret = -EINVAL; |
| 4444 | goto out; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4445 | } |
| 4446 | |
Daniel Vetter | 656bfa3 | 2014-11-20 09:26:30 +0100 | [diff] [blame] | 4447 | if (obj->pages && |
| 4448 | obj->tiling_mode != I915_TILING_NONE && |
| 4449 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) { |
| 4450 | if (obj->madv == I915_MADV_WILLNEED) |
| 4451 | i915_gem_object_unpin_pages(obj); |
| 4452 | if (args->madv == I915_MADV_WILLNEED) |
| 4453 | i915_gem_object_pin_pages(obj); |
| 4454 | } |
| 4455 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4456 | if (obj->madv != __I915_MADV_PURGED) |
| 4457 | obj->madv = args->madv; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4458 | |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 4459 | /* if the object is no longer attached, discard its backing storage */ |
Daniel Vetter | be6a037 | 2015-03-18 10:46:04 +0100 | [diff] [blame] | 4460 | if (obj->madv == I915_MADV_DONTNEED && obj->pages == NULL) |
Chris Wilson | 2d7ef39 | 2009-09-20 23:13:10 +0100 | [diff] [blame] | 4461 | i915_gem_object_truncate(obj); |
| 4462 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4463 | args->retained = obj->madv != __I915_MADV_PURGED; |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 4464 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4465 | out: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4466 | drm_gem_object_unreference(&obj->base); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4467 | unlock: |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4468 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4469 | return ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4470 | } |
| 4471 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 4472 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
| 4473 | const struct drm_i915_gem_object_ops *ops) |
Chris Wilson | 0327d6b | 2012-08-11 15:41:06 +0100 | [diff] [blame] | 4474 | { |
Chris Wilson | b471618 | 2015-04-27 13:41:17 +0100 | [diff] [blame] | 4475 | int i; |
| 4476 | |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 4477 | INIT_LIST_HEAD(&obj->global_list); |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 4478 | for (i = 0; i < I915_NUM_ENGINES; i++) |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 4479 | INIT_LIST_HEAD(&obj->engine_list[i]); |
Ben Widawsky | b25cb2f | 2013-08-14 11:38:33 +0200 | [diff] [blame] | 4480 | INIT_LIST_HEAD(&obj->obj_exec_link); |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 4481 | INIT_LIST_HEAD(&obj->vma_list); |
Chris Wilson | 8d9d574 | 2015-04-07 16:20:38 +0100 | [diff] [blame] | 4482 | INIT_LIST_HEAD(&obj->batch_pool_link); |
Chris Wilson | 0327d6b | 2012-08-11 15:41:06 +0100 | [diff] [blame] | 4483 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 4484 | obj->ops = ops; |
| 4485 | |
Chris Wilson | 0327d6b | 2012-08-11 15:41:06 +0100 | [diff] [blame] | 4486 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 4487 | obj->madv = I915_MADV_WILLNEED; |
Chris Wilson | 0327d6b | 2012-08-11 15:41:06 +0100 | [diff] [blame] | 4488 | |
| 4489 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); |
| 4490 | } |
| 4491 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 4492 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
Chris Wilson | de47266 | 2016-01-22 18:32:31 +0000 | [diff] [blame] | 4493 | .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE, |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 4494 | .get_pages = i915_gem_object_get_pages_gtt, |
| 4495 | .put_pages = i915_gem_object_put_pages_gtt, |
| 4496 | }; |
| 4497 | |
Dave Gordon | d37cd8a | 2016-04-22 19:14:32 +0100 | [diff] [blame] | 4498 | struct drm_i915_gem_object *i915_gem_object_create(struct drm_device *dev, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4499 | size_t size) |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 4500 | { |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4501 | struct drm_i915_gem_object *obj; |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 4502 | struct address_space *mapping; |
Daniel Vetter | 1a240d4 | 2012-11-29 22:18:51 +0100 | [diff] [blame] | 4503 | gfp_t mask; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4504 | |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 4505 | obj = i915_gem_object_alloc(dev); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4506 | if (obj == NULL) |
| 4507 | return NULL; |
| 4508 | |
| 4509 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 4510 | i915_gem_object_free(obj); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4511 | return NULL; |
| 4512 | } |
| 4513 | |
Chris Wilson | bed1ea9 | 2012-05-24 20:48:12 +0100 | [diff] [blame] | 4514 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
| 4515 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { |
| 4516 | /* 965gm cannot relocate objects above 4GiB. */ |
| 4517 | mask &= ~__GFP_HIGHMEM; |
| 4518 | mask |= __GFP_DMA32; |
| 4519 | } |
| 4520 | |
Al Viro | 496ad9a | 2013-01-23 17:07:38 -0500 | [diff] [blame] | 4521 | mapping = file_inode(obj->base.filp)->i_mapping; |
Chris Wilson | bed1ea9 | 2012-05-24 20:48:12 +0100 | [diff] [blame] | 4522 | mapping_set_gfp_mask(mapping, mask); |
Hugh Dickins | 5949eac | 2011-06-27 16:18:18 -0700 | [diff] [blame] | 4523 | |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 4524 | i915_gem_object_init(obj, &i915_gem_object_ops); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 4525 | |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4526 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 4527 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 4528 | |
Eugeni Dodonov | 3d29b84 | 2012-01-17 14:43:53 -0200 | [diff] [blame] | 4529 | if (HAS_LLC(dev)) { |
| 4530 | /* On some devices, we can have the GPU use the LLC (the CPU |
Eric Anholt | a187111 | 2011-03-29 16:59:55 -0700 | [diff] [blame] | 4531 | * cache) for about a 10% performance improvement |
| 4532 | * compared to uncached. Graphics requests other than |
| 4533 | * display scanout are coherent with the CPU in |
| 4534 | * accessing this cache. This means in this mode we |
| 4535 | * don't need to clflush on the CPU side, and on the |
| 4536 | * GPU side we only need to flush internal caches to |
| 4537 | * get data visible to the CPU. |
| 4538 | * |
| 4539 | * However, we maintain the display planes as UC, and so |
| 4540 | * need to rebind when first used as such. |
| 4541 | */ |
| 4542 | obj->cache_level = I915_CACHE_LLC; |
| 4543 | } else |
| 4544 | obj->cache_level = I915_CACHE_NONE; |
| 4545 | |
Daniel Vetter | d861e33 | 2013-07-24 23:25:03 +0200 | [diff] [blame] | 4546 | trace_i915_gem_object_create(obj); |
| 4547 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4548 | return obj; |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 4549 | } |
| 4550 | |
Chris Wilson | 340fbd8 | 2014-05-22 09:16:52 +0100 | [diff] [blame] | 4551 | static bool discard_backing_storage(struct drm_i915_gem_object *obj) |
| 4552 | { |
| 4553 | /* If we are the last user of the backing storage (be it shmemfs |
| 4554 | * pages or stolen etc), we know that the pages are going to be |
| 4555 | * immediately released. In this case, we can then skip copying |
| 4556 | * back the contents from the GPU. |
| 4557 | */ |
| 4558 | |
| 4559 | if (obj->madv != I915_MADV_WILLNEED) |
| 4560 | return false; |
| 4561 | |
| 4562 | if (obj->base.filp == NULL) |
| 4563 | return true; |
| 4564 | |
| 4565 | /* At first glance, this looks racy, but then again so would be |
| 4566 | * userspace racing mmap against close. However, the first external |
| 4567 | * reference to the filp can only be obtained through the |
| 4568 | * i915_gem_mmap_ioctl() which safeguards us against the user |
| 4569 | * acquiring such a reference whilst we are in the middle of |
| 4570 | * freeing the object. |
| 4571 | */ |
| 4572 | return atomic_long_read(&obj->base.filp->f_count) == 1; |
| 4573 | } |
| 4574 | |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 4575 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4576 | { |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 4577 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4578 | struct drm_device *dev = obj->base.dev; |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 4579 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4580 | struct i915_vma *vma, *next; |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4581 | |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 4582 | intel_runtime_pm_get(dev_priv); |
| 4583 | |
Chris Wilson | 26e12f89 | 2011-03-20 11:20:19 +0000 | [diff] [blame] | 4584 | trace_i915_gem_object_destroy(obj); |
| 4585 | |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 4586 | list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) { |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 4587 | int ret; |
| 4588 | |
| 4589 | vma->pin_count = 0; |
| 4590 | ret = i915_vma_unbind(vma); |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4591 | if (WARN_ON(ret == -ERESTARTSYS)) { |
| 4592 | bool was_interruptible; |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 4593 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4594 | was_interruptible = dev_priv->mm.interruptible; |
| 4595 | dev_priv->mm.interruptible = false; |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 4596 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4597 | WARN_ON(i915_vma_unbind(vma)); |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 4598 | |
Ben Widawsky | 07fe0b1 | 2013-07-31 17:00:10 -0700 | [diff] [blame] | 4599 | dev_priv->mm.interruptible = was_interruptible; |
| 4600 | } |
Chris Wilson | 1488fc0 | 2012-04-24 15:47:31 +0100 | [diff] [blame] | 4601 | } |
| 4602 | |
Ben Widawsky | 1d64ae7 | 2013-05-31 14:46:20 -0700 | [diff] [blame] | 4603 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
| 4604 | * before progressing. */ |
| 4605 | if (obj->stolen) |
| 4606 | i915_gem_object_unpin_pages(obj); |
| 4607 | |
Daniel Vetter | a071fa0 | 2014-06-18 23:28:09 +0200 | [diff] [blame] | 4608 | WARN_ON(obj->frontbuffer_bits); |
| 4609 | |
Daniel Vetter | 656bfa3 | 2014-11-20 09:26:30 +0100 | [diff] [blame] | 4610 | if (obj->pages && obj->madv == I915_MADV_WILLNEED && |
| 4611 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES && |
| 4612 | obj->tiling_mode != I915_TILING_NONE) |
| 4613 | i915_gem_object_unpin_pages(obj); |
| 4614 | |
Ben Widawsky | 401c29f | 2013-05-31 11:28:47 -0700 | [diff] [blame] | 4615 | if (WARN_ON(obj->pages_pin_count)) |
| 4616 | obj->pages_pin_count = 0; |
Chris Wilson | 340fbd8 | 2014-05-22 09:16:52 +0100 | [diff] [blame] | 4617 | if (discard_backing_storage(obj)) |
Chris Wilson | 5537252 | 2014-03-25 13:23:06 +0000 | [diff] [blame] | 4618 | obj->madv = I915_MADV_DONTNEED; |
Chris Wilson | 37e680a | 2012-06-07 15:38:42 +0100 | [diff] [blame] | 4619 | i915_gem_object_put_pages(obj); |
Chris Wilson | d8cb508 | 2012-08-11 15:41:03 +0100 | [diff] [blame] | 4620 | i915_gem_object_free_mmap_offset(obj); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4621 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 4622 | BUG_ON(obj->pages); |
| 4623 | |
Chris Wilson | 2f745ad | 2012-09-04 21:02:58 +0100 | [diff] [blame] | 4624 | if (obj->base.import_attach) |
| 4625 | drm_prime_gem_destroy(&obj->base, NULL); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4626 | |
Chris Wilson | 5cc9ed4 | 2014-05-16 14:22:37 +0100 | [diff] [blame] | 4627 | if (obj->ops->release) |
| 4628 | obj->ops->release(obj); |
| 4629 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4630 | drm_gem_object_release(&obj->base); |
| 4631 | i915_gem_info_remove_obj(dev_priv, obj->base.size); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4632 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 4633 | kfree(obj->bit_17); |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 4634 | i915_gem_object_free(obj); |
Paulo Zanoni | f65c916 | 2013-11-27 18:20:34 -0200 | [diff] [blame] | 4635 | |
| 4636 | intel_runtime_pm_put(dev_priv); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4637 | } |
| 4638 | |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 4639 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
| 4640 | struct i915_address_space *vm) |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 4641 | { |
Daniel Vetter | e656a6c | 2013-08-14 14:14:04 +0200 | [diff] [blame] | 4642 | struct i915_vma *vma; |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 4643 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
Tvrtko Ursulin | 1b68372 | 2015-11-12 11:59:55 +0000 | [diff] [blame] | 4644 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL && |
| 4645 | vma->vm == vm) |
Daniel Vetter | e656a6c | 2013-08-14 14:14:04 +0200 | [diff] [blame] | 4646 | return vma; |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 4647 | } |
| 4648 | return NULL; |
| 4649 | } |
Daniel Vetter | e656a6c | 2013-08-14 14:14:04 +0200 | [diff] [blame] | 4650 | |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 4651 | struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj, |
| 4652 | const struct i915_ggtt_view *view) |
| 4653 | { |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 4654 | struct i915_vma *vma; |
| 4655 | |
Tvrtko Ursulin | 598b9ec | 2016-04-21 13:04:44 +0100 | [diff] [blame] | 4656 | GEM_BUG_ON(!view); |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 4657 | |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 4658 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
Tvrtko Ursulin | 598b9ec | 2016-04-21 13:04:44 +0100 | [diff] [blame] | 4659 | if (vma->is_ggtt && i915_ggtt_view_equal(&vma->ggtt_view, view)) |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 4660 | return vma; |
Daniel Vetter | e656a6c | 2013-08-14 14:14:04 +0200 | [diff] [blame] | 4661 | return NULL; |
| 4662 | } |
| 4663 | |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 4664 | void i915_gem_vma_destroy(struct i915_vma *vma) |
| 4665 | { |
| 4666 | WARN_ON(vma->node.allocated); |
Chris Wilson | aaa0566 | 2013-08-20 12:56:40 +0100 | [diff] [blame] | 4667 | |
| 4668 | /* Keep the vma as a placeholder in the execbuffer reservation lists */ |
| 4669 | if (!list_empty(&vma->exec_list)) |
| 4670 | return; |
| 4671 | |
Chris Wilson | 596c592 | 2016-02-26 11:03:20 +0000 | [diff] [blame] | 4672 | if (!vma->is_ggtt) |
| 4673 | i915_ppgtt_put(i915_vm_to_ppgtt(vma->vm)); |
Michel Thierry | b9d06dd | 2014-08-06 15:04:44 +0200 | [diff] [blame] | 4674 | |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 4675 | list_del(&vma->obj_link); |
Daniel Vetter | b93dab6 | 2013-08-26 11:23:47 +0200 | [diff] [blame] | 4676 | |
Chris Wilson | e20d2ab | 2015-04-07 16:20:58 +0100 | [diff] [blame] | 4677 | kmem_cache_free(to_i915(vma->obj->base.dev)->vmas, vma); |
Ben Widawsky | 2f63315 | 2013-07-17 12:19:03 -0700 | [diff] [blame] | 4678 | } |
| 4679 | |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 4680 | static void |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 4681 | i915_gem_stop_engines(struct drm_device *dev) |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 4682 | { |
| 4683 | struct drm_i915_private *dev_priv = dev->dev_private; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 4684 | struct intel_engine_cs *engine; |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 4685 | |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 4686 | for_each_engine(engine, dev_priv) |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 4687 | dev_priv->gt.stop_engine(engine); |
Chris Wilson | e3efda4 | 2014-04-09 09:19:41 +0100 | [diff] [blame] | 4688 | } |
| 4689 | |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 4690 | int |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 4691 | i915_gem_suspend(struct drm_device *dev) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4692 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 4693 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 4694 | int ret = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4695 | |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 4696 | mutex_lock(&dev->struct_mutex); |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 4697 | ret = i915_gpu_idle(dev); |
Chris Wilson | f740334 | 2013-09-13 23:57:04 +0100 | [diff] [blame] | 4698 | if (ret) |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 4699 | goto err; |
Chris Wilson | f740334 | 2013-09-13 23:57:04 +0100 | [diff] [blame] | 4700 | |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 4701 | i915_gem_retire_requests(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4702 | |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 4703 | i915_gem_stop_engines(dev); |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 4704 | mutex_unlock(&dev->struct_mutex); |
| 4705 | |
Chris Wilson | 737b150 | 2015-01-26 18:03:03 +0200 | [diff] [blame] | 4706 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4707 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
Deepak S | 274fa1c | 2014-08-05 07:51:20 -0700 | [diff] [blame] | 4708 | flush_delayed_work(&dev_priv->mm.idle_work); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4709 | |
Chris Wilson | bdcf120 | 2014-11-25 11:56:33 +0000 | [diff] [blame] | 4710 | /* Assert that we sucessfully flushed all the work and |
| 4711 | * reset the GPU back to its idle, low power state. |
| 4712 | */ |
| 4713 | WARN_ON(dev_priv->mm.busy); |
| 4714 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4715 | return 0; |
Chris Wilson | 45c5f20 | 2013-10-16 11:50:01 +0100 | [diff] [blame] | 4716 | |
| 4717 | err: |
| 4718 | mutex_unlock(&dev->struct_mutex); |
| 4719 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4720 | } |
| 4721 | |
John Harrison | 6909a66 | 2015-05-29 17:43:51 +0100 | [diff] [blame] | 4722 | int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice) |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4723 | { |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 4724 | struct intel_engine_cs *engine = req->engine; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 4725 | struct drm_device *dev = engine->dev; |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 4726 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 35a85ac | 2013-09-19 11:13:41 -0700 | [diff] [blame] | 4727 | u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 4728 | int i, ret; |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4729 | |
Ben Widawsky | 040d2ba | 2013-09-19 11:01:40 -0700 | [diff] [blame] | 4730 | if (!HAS_L3_DPF(dev) || !remap_info) |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 4731 | return 0; |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4732 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 4733 | ret = intel_ring_begin(req, GEN7_L3LOG_SIZE / 4 * 3); |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 4734 | if (ret) |
| 4735 | return ret; |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4736 | |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 4737 | /* |
| 4738 | * Note: We do not worry about the concurrent register cacheline hang |
| 4739 | * here because no other code should access these registers other than |
| 4740 | * at initialization time. |
| 4741 | */ |
Ville Syrjälä | 6fa1c5f | 2015-11-04 23:20:02 +0200 | [diff] [blame] | 4742 | for (i = 0; i < GEN7_L3LOG_SIZE / 4; i++) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 4743 | intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1)); |
| 4744 | intel_ring_emit_reg(engine, GEN7_L3LOG(slice, i)); |
| 4745 | intel_ring_emit(engine, remap_info[i]); |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4746 | } |
| 4747 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 4748 | intel_ring_advance(engine); |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4749 | |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 4750 | return ret; |
Ben Widawsky | b9524a1 | 2012-05-25 16:56:24 -0700 | [diff] [blame] | 4751 | } |
| 4752 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 4753 | void i915_gem_init_swizzling(struct drm_device *dev) |
| 4754 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 4755 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 4756 | |
Daniel Vetter | 11782b0 | 2012-01-31 16:47:55 +0100 | [diff] [blame] | 4757 | if (INTEL_INFO(dev)->gen < 5 || |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 4758 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
| 4759 | return; |
| 4760 | |
| 4761 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | |
| 4762 | DISP_TILE_SURFACE_SWIZZLING); |
| 4763 | |
Daniel Vetter | 11782b0 | 2012-01-31 16:47:55 +0100 | [diff] [blame] | 4764 | if (IS_GEN5(dev)) |
| 4765 | return; |
| 4766 | |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 4767 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
| 4768 | if (IS_GEN6(dev)) |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 4769 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
Ben Widawsky | 8782e26 | 2012-12-18 10:31:23 -0800 | [diff] [blame] | 4770 | else if (IS_GEN7(dev)) |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 4771 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
Ben Widawsky | 31a5336 | 2013-11-02 21:07:04 -0700 | [diff] [blame] | 4772 | else if (IS_GEN8(dev)) |
| 4773 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); |
Ben Widawsky | 8782e26 | 2012-12-18 10:31:23 -0800 | [diff] [blame] | 4774 | else |
| 4775 | BUG(); |
Daniel Vetter | f691e2f | 2012-02-02 09:58:12 +0100 | [diff] [blame] | 4776 | } |
Daniel Vetter | e21af88 | 2012-02-09 20:53:27 +0100 | [diff] [blame] | 4777 | |
Ville Syrjälä | 81e7f20 | 2014-08-15 01:21:55 +0300 | [diff] [blame] | 4778 | static void init_unused_ring(struct drm_device *dev, u32 base) |
| 4779 | { |
| 4780 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4781 | |
| 4782 | I915_WRITE(RING_CTL(base), 0); |
| 4783 | I915_WRITE(RING_HEAD(base), 0); |
| 4784 | I915_WRITE(RING_TAIL(base), 0); |
| 4785 | I915_WRITE(RING_START(base), 0); |
| 4786 | } |
| 4787 | |
| 4788 | static void init_unused_rings(struct drm_device *dev) |
| 4789 | { |
| 4790 | if (IS_I830(dev)) { |
| 4791 | init_unused_ring(dev, PRB1_BASE); |
| 4792 | init_unused_ring(dev, SRB0_BASE); |
| 4793 | init_unused_ring(dev, SRB1_BASE); |
| 4794 | init_unused_ring(dev, SRB2_BASE); |
| 4795 | init_unused_ring(dev, SRB3_BASE); |
| 4796 | } else if (IS_GEN2(dev)) { |
| 4797 | init_unused_ring(dev, SRB0_BASE); |
| 4798 | init_unused_ring(dev, SRB1_BASE); |
| 4799 | } else if (IS_GEN3(dev)) { |
| 4800 | init_unused_ring(dev, PRB1_BASE); |
| 4801 | init_unused_ring(dev, PRB2_BASE); |
| 4802 | } |
| 4803 | } |
| 4804 | |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 4805 | int i915_gem_init_engines(struct drm_device *dev) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4806 | { |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4807 | struct drm_i915_private *dev_priv = dev->dev_private; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4808 | int ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4809 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 4810 | ret = intel_init_render_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4811 | if (ret) |
Chris Wilson | b6913e4 | 2010-11-12 10:46:37 +0000 | [diff] [blame] | 4812 | return ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4813 | |
| 4814 | if (HAS_BSD(dev)) { |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 4815 | ret = intel_init_bsd_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4816 | if (ret) |
| 4817 | goto cleanup_render_ring; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4818 | } |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4819 | |
Jani Nikula | d39398f | 2015-10-07 11:17:44 +0300 | [diff] [blame] | 4820 | if (HAS_BLT(dev)) { |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 4821 | ret = intel_init_blt_ring_buffer(dev); |
| 4822 | if (ret) |
| 4823 | goto cleanup_bsd_ring; |
| 4824 | } |
| 4825 | |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 4826 | if (HAS_VEBOX(dev)) { |
| 4827 | ret = intel_init_vebox_ring_buffer(dev); |
| 4828 | if (ret) |
| 4829 | goto cleanup_blt_ring; |
| 4830 | } |
| 4831 | |
Zhao Yakui | 845f74a | 2014-04-17 10:37:37 +0800 | [diff] [blame] | 4832 | if (HAS_BSD2(dev)) { |
| 4833 | ret = intel_init_bsd2_ring_buffer(dev); |
| 4834 | if (ret) |
| 4835 | goto cleanup_vebox_ring; |
| 4836 | } |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 4837 | |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4838 | return 0; |
| 4839 | |
Ben Widawsky | 9a8a221 | 2013-05-28 19:22:23 -0700 | [diff] [blame] | 4840 | cleanup_vebox_ring: |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 4841 | intel_cleanup_engine(&dev_priv->engine[VECS]); |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4842 | cleanup_blt_ring: |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 4843 | intel_cleanup_engine(&dev_priv->engine[BCS]); |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4844 | cleanup_bsd_ring: |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 4845 | intel_cleanup_engine(&dev_priv->engine[VCS]); |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4846 | cleanup_render_ring: |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 4847 | intel_cleanup_engine(&dev_priv->engine[RCS]); |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4848 | |
| 4849 | return ret; |
| 4850 | } |
| 4851 | |
| 4852 | int |
| 4853 | i915_gem_init_hw(struct drm_device *dev) |
| 4854 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 4855 | struct drm_i915_private *dev_priv = dev->dev_private; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 4856 | struct intel_engine_cs *engine; |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 4857 | int ret, j; |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4858 | |
| 4859 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) |
| 4860 | return -EIO; |
| 4861 | |
Chris Wilson | 5e4f518 | 2015-02-13 14:35:59 +0000 | [diff] [blame] | 4862 | /* Double layer security blanket, see i915_gem_init() */ |
| 4863 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
| 4864 | |
Mika Kuoppala | 3accaf7 | 2016-04-13 17:26:43 +0300 | [diff] [blame] | 4865 | if (HAS_EDRAM(dev) && INTEL_GEN(dev_priv) < 9) |
Ben Widawsky | 05e21cc | 2013-07-04 11:02:04 -0700 | [diff] [blame] | 4866 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4867 | |
Ville Syrjälä | 0bf2134 | 2013-11-29 14:56:12 +0200 | [diff] [blame] | 4868 | if (IS_HASWELL(dev)) |
| 4869 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? |
| 4870 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); |
Rodrigo Vivi | 9435373 | 2013-08-28 16:45:46 -0300 | [diff] [blame] | 4871 | |
Ben Widawsky | 88a2b2a | 2013-04-05 13:12:43 -0700 | [diff] [blame] | 4872 | if (HAS_PCH_NOP(dev)) { |
Daniel Vetter | 6ba844b | 2014-01-22 23:39:30 +0100 | [diff] [blame] | 4873 | if (IS_IVYBRIDGE(dev)) { |
| 4874 | u32 temp = I915_READ(GEN7_MSG_CTL); |
| 4875 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); |
| 4876 | I915_WRITE(GEN7_MSG_CTL, temp); |
| 4877 | } else if (INTEL_INFO(dev)->gen >= 7) { |
| 4878 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); |
| 4879 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; |
| 4880 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); |
| 4881 | } |
Ben Widawsky | 88a2b2a | 2013-04-05 13:12:43 -0700 | [diff] [blame] | 4882 | } |
| 4883 | |
Ben Widawsky | 4fc7c97 | 2013-02-08 11:49:24 -0800 | [diff] [blame] | 4884 | i915_gem_init_swizzling(dev); |
| 4885 | |
Daniel Vetter | d5abdfd | 2014-11-20 09:45:19 +0100 | [diff] [blame] | 4886 | /* |
| 4887 | * At least 830 can leave some of the unused rings |
| 4888 | * "active" (ie. head != tail) after resume which |
| 4889 | * will prevent c3 entry. Makes sure all unused rings |
| 4890 | * are totally idle. |
| 4891 | */ |
| 4892 | init_unused_rings(dev); |
| 4893 | |
Dave Gordon | ed54c1a | 2016-01-19 19:02:54 +0000 | [diff] [blame] | 4894 | BUG_ON(!dev_priv->kernel_context); |
John Harrison | 90638cc | 2015-05-29 17:43:37 +0100 | [diff] [blame] | 4895 | |
John Harrison | 4ad2fd8 | 2015-06-18 13:11:20 +0100 | [diff] [blame] | 4896 | ret = i915_ppgtt_init_hw(dev); |
| 4897 | if (ret) { |
| 4898 | DRM_ERROR("PPGTT enable HW failed %d\n", ret); |
| 4899 | goto out; |
| 4900 | } |
| 4901 | |
| 4902 | /* Need to do basic initialisation of all rings first: */ |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 4903 | for_each_engine(engine, dev_priv) { |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 4904 | ret = engine->init_hw(engine); |
Daniel Vetter | 35a57ff | 2014-11-20 00:33:07 +0100 | [diff] [blame] | 4905 | if (ret) |
Chris Wilson | 5e4f518 | 2015-02-13 14:35:59 +0000 | [diff] [blame] | 4906 | goto out; |
Daniel Vetter | 35a57ff | 2014-11-20 00:33:07 +0100 | [diff] [blame] | 4907 | } |
Mika Kuoppala | 9943393 | 2013-01-22 14:12:17 +0200 | [diff] [blame] | 4908 | |
Peter Antoine | 0ccdacf | 2016-04-13 15:03:25 +0100 | [diff] [blame] | 4909 | intel_mocs_init_l3cc_table(dev); |
| 4910 | |
Alex Dai | 33a732f | 2015-08-12 15:43:36 +0100 | [diff] [blame] | 4911 | /* We can't enable contexts until all firmware is loaded */ |
Jesse Barnes | 87bcdd2 | 2015-09-10 14:55:00 -0700 | [diff] [blame] | 4912 | if (HAS_GUC_UCODE(dev)) { |
| 4913 | ret = intel_guc_ucode_load(dev); |
| 4914 | if (ret) { |
Daniel Vetter | 9f9e539 | 2015-10-23 11:10:59 +0200 | [diff] [blame] | 4915 | DRM_ERROR("Failed to initialize GuC, error %d\n", ret); |
| 4916 | ret = -EIO; |
| 4917 | goto out; |
Jesse Barnes | 87bcdd2 | 2015-09-10 14:55:00 -0700 | [diff] [blame] | 4918 | } |
Alex Dai | 33a732f | 2015-08-12 15:43:36 +0100 | [diff] [blame] | 4919 | } |
| 4920 | |
Nick Hoath | e84fe80 | 2015-09-11 12:53:46 +0100 | [diff] [blame] | 4921 | /* |
| 4922 | * Increment the next seqno by 0x100 so we have a visible break |
| 4923 | * on re-initialisation |
| 4924 | */ |
| 4925 | ret = i915_gem_set_seqno(dev, dev_priv->next_seqno+0x100); |
| 4926 | if (ret) |
| 4927 | goto out; |
| 4928 | |
John Harrison | 4ad2fd8 | 2015-06-18 13:11:20 +0100 | [diff] [blame] | 4929 | /* Now it is safe to go back round and do everything else: */ |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 4930 | for_each_engine(engine, dev_priv) { |
John Harrison | dc4be6071 | 2015-05-29 17:43:39 +0100 | [diff] [blame] | 4931 | struct drm_i915_gem_request *req; |
| 4932 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 4933 | req = i915_gem_request_alloc(engine, NULL); |
Dave Gordon | 2682708 | 2016-01-19 19:02:53 +0000 | [diff] [blame] | 4934 | if (IS_ERR(req)) { |
| 4935 | ret = PTR_ERR(req); |
Chris Wilson | aa9b781 | 2016-04-13 17:35:15 +0100 | [diff] [blame] | 4936 | break; |
John Harrison | dc4be6071 | 2015-05-29 17:43:39 +0100 | [diff] [blame] | 4937 | } |
| 4938 | |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 4939 | if (engine->id == RCS) { |
Chris Wilson | aa9b781 | 2016-04-13 17:35:15 +0100 | [diff] [blame] | 4940 | for (j = 0; j < NUM_L3_SLICES(dev); j++) { |
| 4941 | ret = i915_gem_l3_remap(req, j); |
| 4942 | if (ret) |
| 4943 | goto err_request; |
| 4944 | } |
John Harrison | 4ad2fd8 | 2015-06-18 13:11:20 +0100 | [diff] [blame] | 4945 | } |
Ben Widawsky | c3787e2 | 2013-09-17 21:12:44 -0700 | [diff] [blame] | 4946 | |
John Harrison | b3dd6b9 | 2015-05-29 17:43:40 +0100 | [diff] [blame] | 4947 | ret = i915_ppgtt_init_ring(req); |
Chris Wilson | aa9b781 | 2016-04-13 17:35:15 +0100 | [diff] [blame] | 4948 | if (ret) |
| 4949 | goto err_request; |
David Woodhouse | f48a016 | 2015-01-20 17:21:42 +0000 | [diff] [blame] | 4950 | |
John Harrison | b3dd6b9 | 2015-05-29 17:43:40 +0100 | [diff] [blame] | 4951 | ret = i915_gem_context_enable(req); |
Chris Wilson | aa9b781 | 2016-04-13 17:35:15 +0100 | [diff] [blame] | 4952 | if (ret) |
| 4953 | goto err_request; |
John Harrison | dc4be6071 | 2015-05-29 17:43:39 +0100 | [diff] [blame] | 4954 | |
Chris Wilson | aa9b781 | 2016-04-13 17:35:15 +0100 | [diff] [blame] | 4955 | err_request: |
John Harrison | 7528987 | 2015-05-29 17:43:49 +0100 | [diff] [blame] | 4956 | i915_add_request_no_flush(req); |
Chris Wilson | aa9b781 | 2016-04-13 17:35:15 +0100 | [diff] [blame] | 4957 | if (ret) { |
| 4958 | DRM_ERROR("Failed to enable %s, error=%d\n", |
| 4959 | engine->name, ret); |
| 4960 | i915_gem_cleanup_engines(dev); |
| 4961 | break; |
| 4962 | } |
Daniel Vetter | 82460d9 | 2014-08-06 20:19:53 +0200 | [diff] [blame] | 4963 | } |
| 4964 | |
Chris Wilson | 5e4f518 | 2015-02-13 14:35:59 +0000 | [diff] [blame] | 4965 | out: |
| 4966 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
Ben Widawsky | 2fa48d8 | 2013-12-06 14:11:04 -0800 | [diff] [blame] | 4967 | return ret; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4968 | } |
| 4969 | |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 4970 | int i915_gem_init(struct drm_device *dev) |
| 4971 | { |
| 4972 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 4973 | int ret; |
| 4974 | |
Oscar Mateo | 127f100 | 2014-07-24 17:04:11 +0100 | [diff] [blame] | 4975 | i915.enable_execlists = intel_sanitize_enable_execlists(dev, |
| 4976 | i915.enable_execlists); |
| 4977 | |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 4978 | mutex_lock(&dev->struct_mutex); |
Jesse Barnes | d62b489 | 2013-03-08 10:45:53 -0800 | [diff] [blame] | 4979 | |
Oscar Mateo | a83014d | 2014-07-24 17:04:21 +0100 | [diff] [blame] | 4980 | if (!i915.enable_execlists) { |
John Harrison | f3dc74c | 2015-03-19 12:30:06 +0000 | [diff] [blame] | 4981 | dev_priv->gt.execbuf_submit = i915_gem_ringbuffer_submission; |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 4982 | dev_priv->gt.init_engines = i915_gem_init_engines; |
| 4983 | dev_priv->gt.cleanup_engine = intel_cleanup_engine; |
| 4984 | dev_priv->gt.stop_engine = intel_stop_engine; |
Oscar Mateo | 454afeb | 2014-07-24 17:04:22 +0100 | [diff] [blame] | 4985 | } else { |
John Harrison | f3dc74c | 2015-03-19 12:30:06 +0000 | [diff] [blame] | 4986 | dev_priv->gt.execbuf_submit = intel_execlists_submission; |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 4987 | dev_priv->gt.init_engines = intel_logical_rings_init; |
| 4988 | dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup; |
| 4989 | dev_priv->gt.stop_engine = intel_logical_ring_stop; |
Oscar Mateo | a83014d | 2014-07-24 17:04:21 +0100 | [diff] [blame] | 4990 | } |
| 4991 | |
Chris Wilson | 5e4f518 | 2015-02-13 14:35:59 +0000 | [diff] [blame] | 4992 | /* This is just a security blanket to placate dragons. |
| 4993 | * On some systems, we very sporadically observe that the first TLBs |
| 4994 | * used by the CS may be stale, despite us poking the TLB reset. If |
| 4995 | * we hold the forcewake during initialisation these problems |
| 4996 | * just magically go away. |
| 4997 | */ |
| 4998 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
| 4999 | |
Daniel Vetter | 6c5566a | 2014-08-06 15:04:50 +0200 | [diff] [blame] | 5000 | ret = i915_gem_init_userptr(dev); |
Jani Nikula | 7bcc377 | 2014-12-05 14:17:42 +0200 | [diff] [blame] | 5001 | if (ret) |
| 5002 | goto out_unlock; |
Daniel Vetter | 6c5566a | 2014-08-06 15:04:50 +0200 | [diff] [blame] | 5003 | |
Joonas Lahtinen | d85489d | 2016-03-24 16:47:46 +0200 | [diff] [blame] | 5004 | i915_gem_init_ggtt(dev); |
Jesse Barnes | d62b489 | 2013-03-08 10:45:53 -0800 | [diff] [blame] | 5005 | |
Ben Widawsky | 2fa48d8 | 2013-12-06 14:11:04 -0800 | [diff] [blame] | 5006 | ret = i915_gem_context_init(dev); |
Jani Nikula | 7bcc377 | 2014-12-05 14:17:42 +0200 | [diff] [blame] | 5007 | if (ret) |
| 5008 | goto out_unlock; |
Ben Widawsky | 2fa48d8 | 2013-12-06 14:11:04 -0800 | [diff] [blame] | 5009 | |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 5010 | ret = dev_priv->gt.init_engines(dev); |
Daniel Vetter | 35a57ff | 2014-11-20 00:33:07 +0100 | [diff] [blame] | 5011 | if (ret) |
Jani Nikula | 7bcc377 | 2014-12-05 14:17:42 +0200 | [diff] [blame] | 5012 | goto out_unlock; |
Daniel Vetter | 53ca26c | 2012-04-26 23:28:03 +0200 | [diff] [blame] | 5013 | |
| 5014 | ret = i915_gem_init_hw(dev); |
Chris Wilson | 6099032 | 2014-04-09 09:19:42 +0100 | [diff] [blame] | 5015 | if (ret == -EIO) { |
| 5016 | /* Allow ring initialisation to fail by marking the GPU as |
| 5017 | * wedged. But we only want to do this where the GPU is angry, |
| 5018 | * for all other failure, such as an allocation failure, bail. |
| 5019 | */ |
| 5020 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); |
Peter Zijlstra | 805de8f4 | 2015-04-24 01:12:32 +0200 | [diff] [blame] | 5021 | atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter); |
Chris Wilson | 6099032 | 2014-04-09 09:19:42 +0100 | [diff] [blame] | 5022 | ret = 0; |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 5023 | } |
Jani Nikula | 7bcc377 | 2014-12-05 14:17:42 +0200 | [diff] [blame] | 5024 | |
| 5025 | out_unlock: |
Chris Wilson | 5e4f518 | 2015-02-13 14:35:59 +0000 | [diff] [blame] | 5026 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
Chris Wilson | 6099032 | 2014-04-09 09:19:42 +0100 | [diff] [blame] | 5027 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 5028 | |
Chris Wilson | 6099032 | 2014-04-09 09:19:42 +0100 | [diff] [blame] | 5029 | return ret; |
Chris Wilson | 1070a42 | 2012-04-24 15:47:41 +0100 | [diff] [blame] | 5030 | } |
| 5031 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 5032 | void |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 5033 | i915_gem_cleanup_engines(struct drm_device *dev) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 5034 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 5035 | struct drm_i915_private *dev_priv = dev->dev_private; |
Tvrtko Ursulin | e2f8039 | 2016-03-16 11:00:36 +0000 | [diff] [blame] | 5036 | struct intel_engine_cs *engine; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 5037 | |
Dave Gordon | b4ac5af | 2016-03-24 11:20:38 +0000 | [diff] [blame] | 5038 | for_each_engine(engine, dev_priv) |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 5039 | dev_priv->gt.cleanup_engine(engine); |
Niu,Bing | a647828 | 2015-07-04 00:27:34 +0800 | [diff] [blame] | 5040 | |
Mika Kuoppala | ee4b6fa | 2016-03-16 17:54:00 +0200 | [diff] [blame] | 5041 | if (i915.enable_execlists) |
| 5042 | /* |
| 5043 | * Neither the BIOS, ourselves or any other kernel |
| 5044 | * expects the system to be in execlists mode on startup, |
| 5045 | * so we need to reset the GPU back to legacy mode. |
| 5046 | */ |
| 5047 | intel_gpu_reset(dev, ALL_ENGINES); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 5048 | } |
| 5049 | |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 5050 | static void |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 5051 | init_engine_lists(struct intel_engine_cs *engine) |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 5052 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 5053 | INIT_LIST_HEAD(&engine->active_list); |
| 5054 | INIT_LIST_HEAD(&engine->request_list); |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 5055 | } |
| 5056 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 5057 | void |
Imre Deak | 40ae4e1 | 2016-03-16 14:54:03 +0200 | [diff] [blame] | 5058 | i915_gem_load_init_fences(struct drm_i915_private *dev_priv) |
| 5059 | { |
| 5060 | struct drm_device *dev = dev_priv->dev; |
| 5061 | |
| 5062 | if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) && |
| 5063 | !IS_CHERRYVIEW(dev_priv)) |
| 5064 | dev_priv->num_fence_regs = 32; |
| 5065 | else if (INTEL_INFO(dev_priv)->gen >= 4 || IS_I945G(dev_priv) || |
| 5066 | IS_I945GM(dev_priv) || IS_G33(dev_priv)) |
| 5067 | dev_priv->num_fence_regs = 16; |
| 5068 | else |
| 5069 | dev_priv->num_fence_regs = 8; |
| 5070 | |
| 5071 | if (intel_vgpu_active(dev)) |
| 5072 | dev_priv->num_fence_regs = |
| 5073 | I915_READ(vgtif_reg(avail_rs.fence_num)); |
| 5074 | |
| 5075 | /* Initialize fence registers to zero */ |
| 5076 | i915_gem_restore_fences(dev); |
| 5077 | |
| 5078 | i915_gem_detect_bit_6_swizzle(dev); |
| 5079 | } |
| 5080 | |
| 5081 | void |
Imre Deak | d64aa09 | 2016-01-19 15:26:29 +0200 | [diff] [blame] | 5082 | i915_gem_load_init(struct drm_device *dev) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 5083 | { |
Jani Nikula | 3e31c6c | 2014-03-31 14:27:16 +0300 | [diff] [blame] | 5084 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 5085 | int i; |
| 5086 | |
Chris Wilson | efab6d8 | 2015-04-07 16:20:57 +0100 | [diff] [blame] | 5087 | dev_priv->objects = |
Chris Wilson | 42dcedd | 2012-11-15 11:32:30 +0000 | [diff] [blame] | 5088 | kmem_cache_create("i915_gem_object", |
| 5089 | sizeof(struct drm_i915_gem_object), 0, |
| 5090 | SLAB_HWCACHE_ALIGN, |
| 5091 | NULL); |
Chris Wilson | e20d2ab | 2015-04-07 16:20:58 +0100 | [diff] [blame] | 5092 | dev_priv->vmas = |
| 5093 | kmem_cache_create("i915_gem_vma", |
| 5094 | sizeof(struct i915_vma), 0, |
| 5095 | SLAB_HWCACHE_ALIGN, |
| 5096 | NULL); |
Chris Wilson | efab6d8 | 2015-04-07 16:20:57 +0100 | [diff] [blame] | 5097 | dev_priv->requests = |
| 5098 | kmem_cache_create("i915_gem_request", |
| 5099 | sizeof(struct drm_i915_gem_request), 0, |
| 5100 | SLAB_HWCACHE_ALIGN, |
| 5101 | NULL); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 5102 | |
Ben Widawsky | fc8c067 | 2013-07-31 16:59:54 -0700 | [diff] [blame] | 5103 | INIT_LIST_HEAD(&dev_priv->vm_list); |
Ben Widawsky | a33afea | 2013-09-17 21:12:45 -0700 | [diff] [blame] | 5104 | INIT_LIST_HEAD(&dev_priv->context_list); |
Chris Wilson | 6c085a7 | 2012-08-20 11:40:46 +0200 | [diff] [blame] | 5105 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
| 5106 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 5107 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 5108 | for (i = 0; i < I915_NUM_ENGINES; i++) |
| 5109 | init_engine_lists(&dev_priv->engine[i]); |
Daniel Vetter | 4b9de73 | 2011-10-09 21:52:02 +0200 | [diff] [blame] | 5110 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 5111 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 5112 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
| 5113 | i915_gem_retire_work_handler); |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 5114 | INIT_DELAYED_WORK(&dev_priv->mm.idle_work, |
| 5115 | i915_gem_idle_work_handler); |
Daniel Vetter | 1f83fee | 2012-11-15 17:17:22 +0100 | [diff] [blame] | 5116 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5117 | |
Chris Wilson | 72bfa19 | 2010-12-19 11:42:05 +0000 | [diff] [blame] | 5118 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
| 5119 | |
Nick Hoath | e84fe80 | 2015-09-11 12:53:46 +0100 | [diff] [blame] | 5120 | /* |
| 5121 | * Set initial sequence number for requests. |
| 5122 | * Using this number allows the wraparound to happen early, |
| 5123 | * catching any obvious problems. |
| 5124 | */ |
| 5125 | dev_priv->next_seqno = ((u32)~0 - 0x1100); |
| 5126 | dev_priv->last_seqno = ((u32)~0 - 0x1101); |
| 5127 | |
Chris Wilson | 19b2dbd | 2013-06-12 10:15:12 +0100 | [diff] [blame] | 5128 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
Eric Anholt | 10ed13e | 2011-05-06 13:53:49 -0700 | [diff] [blame] | 5129 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 5130 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 5131 | |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 5132 | dev_priv->mm.interruptible = true; |
| 5133 | |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 5134 | mutex_init(&dev_priv->fb_tracking.lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 5135 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5136 | |
Imre Deak | d64aa09 | 2016-01-19 15:26:29 +0200 | [diff] [blame] | 5137 | void i915_gem_load_cleanup(struct drm_device *dev) |
| 5138 | { |
| 5139 | struct drm_i915_private *dev_priv = to_i915(dev); |
| 5140 | |
| 5141 | kmem_cache_destroy(dev_priv->requests); |
| 5142 | kmem_cache_destroy(dev_priv->vmas); |
| 5143 | kmem_cache_destroy(dev_priv->objects); |
| 5144 | } |
| 5145 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 5146 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 5147 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 5148 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 5149 | |
| 5150 | /* Clean up our request list when the client is going away, so that |
| 5151 | * later retire_requests won't dereference our soon-to-be-gone |
| 5152 | * file_priv. |
| 5153 | */ |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 5154 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 5155 | while (!list_empty(&file_priv->mm.request_list)) { |
| 5156 | struct drm_i915_gem_request *request; |
| 5157 | |
| 5158 | request = list_first_entry(&file_priv->mm.request_list, |
| 5159 | struct drm_i915_gem_request, |
| 5160 | client_list); |
| 5161 | list_del(&request->client_list); |
| 5162 | request->file_priv = NULL; |
| 5163 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 5164 | spin_unlock(&file_priv->mm.lock); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5165 | |
Chris Wilson | 2e1b873 | 2015-04-27 13:41:22 +0100 | [diff] [blame] | 5166 | if (!list_empty(&file_priv->rps.link)) { |
Chris Wilson | 8d3afd7 | 2015-05-21 21:01:47 +0100 | [diff] [blame] | 5167 | spin_lock(&to_i915(dev)->rps.client_lock); |
Chris Wilson | 2e1b873 | 2015-04-27 13:41:22 +0100 | [diff] [blame] | 5168 | list_del(&file_priv->rps.link); |
Chris Wilson | 8d3afd7 | 2015-05-21 21:01:47 +0100 | [diff] [blame] | 5169 | spin_unlock(&to_i915(dev)->rps.client_lock); |
Chris Wilson | 1854d5c | 2015-04-07 16:20:32 +0100 | [diff] [blame] | 5170 | } |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 5171 | } |
| 5172 | |
| 5173 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) |
| 5174 | { |
| 5175 | struct drm_i915_file_private *file_priv; |
Ben Widawsky | e422b88 | 2013-12-06 14:10:58 -0800 | [diff] [blame] | 5176 | int ret; |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 5177 | |
| 5178 | DRM_DEBUG_DRIVER("\n"); |
| 5179 | |
| 5180 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); |
| 5181 | if (!file_priv) |
| 5182 | return -ENOMEM; |
| 5183 | |
| 5184 | file->driver_priv = file_priv; |
| 5185 | file_priv->dev_priv = dev->dev_private; |
Chris Wilson | ab0e7ff | 2014-02-25 17:11:24 +0200 | [diff] [blame] | 5186 | file_priv->file = file; |
Chris Wilson | 2e1b873 | 2015-04-27 13:41:22 +0100 | [diff] [blame] | 5187 | INIT_LIST_HEAD(&file_priv->rps.link); |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 5188 | |
| 5189 | spin_lock_init(&file_priv->mm.lock); |
| 5190 | INIT_LIST_HEAD(&file_priv->mm.request_list); |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 5191 | |
Tvrtko Ursulin | de1add3 | 2016-01-15 15:12:50 +0000 | [diff] [blame] | 5192 | file_priv->bsd_ring = -1; |
| 5193 | |
Ben Widawsky | e422b88 | 2013-12-06 14:10:58 -0800 | [diff] [blame] | 5194 | ret = i915_gem_context_open(dev, file); |
| 5195 | if (ret) |
| 5196 | kfree(file_priv); |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 5197 | |
Ben Widawsky | e422b88 | 2013-12-06 14:10:58 -0800 | [diff] [blame] | 5198 | return ret; |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 5199 | } |
| 5200 | |
Daniel Vetter | b680c37 | 2014-09-19 18:27:27 +0200 | [diff] [blame] | 5201 | /** |
| 5202 | * i915_gem_track_fb - update frontbuffer tracking |
Geliang Tang | d9072a3 | 2015-09-15 05:58:44 -0700 | [diff] [blame] | 5203 | * @old: current GEM buffer for the frontbuffer slots |
| 5204 | * @new: new GEM buffer for the frontbuffer slots |
| 5205 | * @frontbuffer_bits: bitmask of frontbuffer slots |
Daniel Vetter | b680c37 | 2014-09-19 18:27:27 +0200 | [diff] [blame] | 5206 | * |
| 5207 | * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them |
| 5208 | * from @old and setting them in @new. Both @old and @new can be NULL. |
| 5209 | */ |
Daniel Vetter | a071fa0 | 2014-06-18 23:28:09 +0200 | [diff] [blame] | 5210 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
| 5211 | struct drm_i915_gem_object *new, |
| 5212 | unsigned frontbuffer_bits) |
| 5213 | { |
| 5214 | if (old) { |
| 5215 | WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex)); |
| 5216 | WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits)); |
| 5217 | old->frontbuffer_bits &= ~frontbuffer_bits; |
| 5218 | } |
| 5219 | |
| 5220 | if (new) { |
| 5221 | WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex)); |
| 5222 | WARN_ON(new->frontbuffer_bits & frontbuffer_bits); |
| 5223 | new->frontbuffer_bits |= frontbuffer_bits; |
| 5224 | } |
| 5225 | } |
| 5226 | |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5227 | /* All the new VM stuff */ |
Michel Thierry | 088e0df | 2015-08-07 17:40:17 +0100 | [diff] [blame] | 5228 | u64 i915_gem_obj_offset(struct drm_i915_gem_object *o, |
| 5229 | struct i915_address_space *vm) |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5230 | { |
| 5231 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; |
| 5232 | struct i915_vma *vma; |
| 5233 | |
Daniel Vetter | 896ab1a | 2014-08-06 15:04:51 +0200 | [diff] [blame] | 5234 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5235 | |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 5236 | list_for_each_entry(vma, &o->vma_list, obj_link) { |
Chris Wilson | 596c592 | 2016-02-26 11:03:20 +0000 | [diff] [blame] | 5237 | if (vma->is_ggtt && |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 5238 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) |
| 5239 | continue; |
| 5240 | if (vma->vm == vm) |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5241 | return vma->node.start; |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5242 | } |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 5243 | |
Daniel Vetter | f25748ea | 2014-06-17 22:34:38 +0200 | [diff] [blame] | 5244 | WARN(1, "%s vma for this object not found.\n", |
| 5245 | i915_is_ggtt(vm) ? "global" : "ppgtt"); |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5246 | return -1; |
| 5247 | } |
| 5248 | |
Michel Thierry | 088e0df | 2015-08-07 17:40:17 +0100 | [diff] [blame] | 5249 | u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o, |
| 5250 | const struct i915_ggtt_view *view) |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5251 | { |
| 5252 | struct i915_vma *vma; |
| 5253 | |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 5254 | list_for_each_entry(vma, &o->vma_list, obj_link) |
Tvrtko Ursulin | 8aac222 | 2016-04-21 13:04:45 +0100 | [diff] [blame] | 5255 | if (vma->is_ggtt && i915_ggtt_view_equal(&vma->ggtt_view, view)) |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 5256 | return vma->node.start; |
| 5257 | |
Tvrtko Ursulin | 5678ad7 | 2015-03-17 14:45:29 +0000 | [diff] [blame] | 5258 | WARN(1, "global vma for this object not found. (view=%u)\n", view->type); |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 5259 | return -1; |
| 5260 | } |
| 5261 | |
| 5262 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, |
| 5263 | struct i915_address_space *vm) |
| 5264 | { |
| 5265 | struct i915_vma *vma; |
| 5266 | |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 5267 | list_for_each_entry(vma, &o->vma_list, obj_link) { |
Chris Wilson | 596c592 | 2016-02-26 11:03:20 +0000 | [diff] [blame] | 5268 | if (vma->is_ggtt && |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 5269 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) |
| 5270 | continue; |
| 5271 | if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) |
| 5272 | return true; |
| 5273 | } |
| 5274 | |
| 5275 | return false; |
| 5276 | } |
| 5277 | |
| 5278 | bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o, |
Joonas Lahtinen | 9abc464 | 2015-03-27 13:09:22 +0200 | [diff] [blame] | 5279 | const struct i915_ggtt_view *view) |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 5280 | { |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 5281 | struct i915_vma *vma; |
| 5282 | |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 5283 | list_for_each_entry(vma, &o->vma_list, obj_link) |
Tvrtko Ursulin | ff5ec22 | 2016-04-21 13:04:46 +0100 | [diff] [blame] | 5284 | if (vma->is_ggtt && |
Joonas Lahtinen | 9abc464 | 2015-03-27 13:09:22 +0200 | [diff] [blame] | 5285 | i915_ggtt_view_equal(&vma->ggtt_view, view) && |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 5286 | drm_mm_node_allocated(&vma->node)) |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5287 | return true; |
| 5288 | |
| 5289 | return false; |
| 5290 | } |
| 5291 | |
| 5292 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) |
| 5293 | { |
Chris Wilson | 5a1d5eb | 2013-09-10 11:27:37 +0100 | [diff] [blame] | 5294 | struct i915_vma *vma; |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5295 | |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 5296 | list_for_each_entry(vma, &o->vma_list, obj_link) |
Chris Wilson | 5a1d5eb | 2013-09-10 11:27:37 +0100 | [diff] [blame] | 5297 | if (drm_mm_node_allocated(&vma->node)) |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5298 | return true; |
| 5299 | |
| 5300 | return false; |
| 5301 | } |
| 5302 | |
Tvrtko Ursulin | 8da3272 | 2016-04-21 13:04:43 +0100 | [diff] [blame] | 5303 | unsigned long i915_gem_obj_ggtt_size(struct drm_i915_gem_object *o) |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5304 | { |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5305 | struct i915_vma *vma; |
| 5306 | |
Tvrtko Ursulin | 8da3272 | 2016-04-21 13:04:43 +0100 | [diff] [blame] | 5307 | GEM_BUG_ON(list_empty(&o->vma_list)); |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5308 | |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 5309 | list_for_each_entry(vma, &o->vma_list, obj_link) { |
Chris Wilson | 596c592 | 2016-02-26 11:03:20 +0000 | [diff] [blame] | 5310 | if (vma->is_ggtt && |
Tvrtko Ursulin | 8da3272 | 2016-04-21 13:04:43 +0100 | [diff] [blame] | 5311 | vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5312 | return vma->node.size; |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 5313 | } |
Tvrtko Ursulin | 8da3272 | 2016-04-21 13:04:43 +0100 | [diff] [blame] | 5314 | |
Ben Widawsky | a70a314 | 2013-07-31 16:59:56 -0700 | [diff] [blame] | 5315 | return 0; |
| 5316 | } |
| 5317 | |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 5318 | bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) |
Ben Widawsky | 5c2abbe | 2013-09-24 09:57:57 -0700 | [diff] [blame] | 5319 | { |
| 5320 | struct i915_vma *vma; |
Chris Wilson | 1c7f4bc | 2016-02-26 11:03:19 +0000 | [diff] [blame] | 5321 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 5322 | if (vma->pin_count > 0) |
| 5323 | return true; |
Joonas Lahtinen | a6631ae | 2015-05-06 14:34:58 +0300 | [diff] [blame] | 5324 | |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 5325 | return false; |
Ben Widawsky | 5c2abbe | 2013-09-24 09:57:57 -0700 | [diff] [blame] | 5326 | } |
Dave Gordon | ea70299 | 2015-07-09 19:29:02 +0100 | [diff] [blame] | 5327 | |
Dave Gordon | 033908a | 2015-12-10 18:51:23 +0000 | [diff] [blame] | 5328 | /* Like i915_gem_object_get_page(), but mark the returned page dirty */ |
| 5329 | struct page * |
| 5330 | i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n) |
| 5331 | { |
| 5332 | struct page *page; |
| 5333 | |
| 5334 | /* Only default objects have per-page dirty tracking */ |
Chris Wilson | de47266 | 2016-01-22 18:32:31 +0000 | [diff] [blame] | 5335 | if (WARN_ON((obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE) == 0)) |
Dave Gordon | 033908a | 2015-12-10 18:51:23 +0000 | [diff] [blame] | 5336 | return NULL; |
| 5337 | |
| 5338 | page = i915_gem_object_get_page(obj, n); |
| 5339 | set_page_dirty(page); |
| 5340 | return page; |
| 5341 | } |
| 5342 | |
Dave Gordon | ea70299 | 2015-07-09 19:29:02 +0100 | [diff] [blame] | 5343 | /* Allocate a new GEM object and fill it with the supplied data */ |
| 5344 | struct drm_i915_gem_object * |
| 5345 | i915_gem_object_create_from_data(struct drm_device *dev, |
| 5346 | const void *data, size_t size) |
| 5347 | { |
| 5348 | struct drm_i915_gem_object *obj; |
| 5349 | struct sg_table *sg; |
| 5350 | size_t bytes; |
| 5351 | int ret; |
| 5352 | |
Dave Gordon | d37cd8a | 2016-04-22 19:14:32 +0100 | [diff] [blame] | 5353 | obj = i915_gem_object_create(dev, round_up(size, PAGE_SIZE)); |
Dave Gordon | ea70299 | 2015-07-09 19:29:02 +0100 | [diff] [blame] | 5354 | if (IS_ERR_OR_NULL(obj)) |
| 5355 | return obj; |
| 5356 | |
| 5357 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
| 5358 | if (ret) |
| 5359 | goto fail; |
| 5360 | |
| 5361 | ret = i915_gem_object_get_pages(obj); |
| 5362 | if (ret) |
| 5363 | goto fail; |
| 5364 | |
| 5365 | i915_gem_object_pin_pages(obj); |
| 5366 | sg = obj->pages; |
| 5367 | bytes = sg_copy_from_buffer(sg->sgl, sg->nents, (void *)data, size); |
Dave Gordon | 9e7d18c | 2015-12-10 18:51:24 +0000 | [diff] [blame] | 5368 | obj->dirty = 1; /* Backing store is now out of date */ |
Dave Gordon | ea70299 | 2015-07-09 19:29:02 +0100 | [diff] [blame] | 5369 | i915_gem_object_unpin_pages(obj); |
| 5370 | |
| 5371 | if (WARN_ON(bytes != size)) { |
| 5372 | DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes, size); |
| 5373 | ret = -EFAULT; |
| 5374 | goto fail; |
| 5375 | } |
| 5376 | |
| 5377 | return obj; |
| 5378 | |
| 5379 | fail: |
| 5380 | drm_gem_object_unreference(&obj->base); |
| 5381 | return ERR_PTR(ret); |
| 5382 | } |