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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Francois Romieu07d3f512007-02-21 22:40:46 +01002 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
Rafael J. Wysockie1759442010-03-14 14:33:51 +000026#include <linux/pm_runtime.h>
françois romieubca03d52011-01-03 15:07:31 +000027#include <linux/firmware.h>
Stanislaw Gruszkaba04c7c2011-02-22 02:00:11 +000028#include <linux/pci-aspm.h>
Paul Gortmaker70c71602011-05-22 16:47:17 -040029#include <linux/prefetch.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070030
Francois Romieu99f252b2007-04-02 22:59:59 +020031#include <asm/system.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070032#include <asm/io.h>
33#include <asm/irq.h>
34
Francois Romieu865c6522008-05-11 14:51:00 +020035#define RTL8169_VERSION "2.3LK-NAPI"
Linus Torvalds1da177e2005-04-16 15:20:36 -070036#define MODULENAME "r8169"
37#define PFX MODULENAME ": "
38
françois romieubca03d52011-01-03 15:07:31 +000039#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
40#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
hayeswang01dc7fe2011-03-21 01:50:28 +000041#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
42#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
Hayes Wang5a5e4442011-02-22 17:26:21 +080043#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
françois romieubca03d52011-01-03 15:07:31 +000044
Linus Torvalds1da177e2005-04-16 15:20:36 -070045#ifdef RTL8169_DEBUG
46#define assert(expr) \
Francois Romieu5b0384f2006-08-16 16:00:01 +020047 if (!(expr)) { \
48 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
Harvey Harrisonb39d66a2008-08-20 16:52:04 -070049 #expr,__FILE__,__func__,__LINE__); \
Francois Romieu5b0384f2006-08-16 16:00:01 +020050 }
Joe Perches06fa7352007-10-18 21:15:00 +020051#define dprintk(fmt, args...) \
52 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
Linus Torvalds1da177e2005-04-16 15:20:36 -070053#else
54#define assert(expr) do {} while (0)
55#define dprintk(fmt, args...) do {} while (0)
56#endif /* RTL8169_DEBUG */
57
Stephen Hemmingerb57b7e52005-05-27 21:11:52 +020058#define R8169_MSG_DEFAULT \
Francois Romieuf0e837d2005-09-30 16:54:02 -070059 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
Stephen Hemmingerb57b7e52005-05-27 21:11:52 +020060
Linus Torvalds1da177e2005-04-16 15:20:36 -070061#define TX_BUFFS_AVAIL(tp) \
62 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
63
Linus Torvalds1da177e2005-04-16 15:20:36 -070064/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
65 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
Arjan van de Venf71e1302006-03-03 21:33:57 -050066static const int multicast_filter_limit = 32;
Linus Torvalds1da177e2005-04-16 15:20:36 -070067
68/* MAC address length */
69#define MAC_ADDR_LEN 6
70
Francois Romieu9c14cea2008-07-05 00:21:15 +020071#define MAX_READ_REQUEST_SHIFT 12
Linus Torvalds1da177e2005-04-16 15:20:36 -070072#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
73#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
74#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070075#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
76#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
77
78#define R8169_REGS_SIZE 256
79#define R8169_NAPI_WEIGHT 64
80#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
81#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
82#define RX_BUF_SIZE 1536 /* Rx Buffer size */
83#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
84#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
85
86#define RTL8169_TX_TIMEOUT (6*HZ)
87#define RTL8169_PHY_TIMEOUT (10*HZ)
88
françois romieuea8dbdd2009-03-15 01:10:50 +000089#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
90#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
Francois Romieue1564ec2008-10-16 22:46:13 +020091#define RTL_EEPROM_SIG_ADDR 0x0000
92
Linus Torvalds1da177e2005-04-16 15:20:36 -070093/* write/read MMIO register */
94#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
95#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
96#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
97#define RTL_R8(reg) readb (ioaddr + (reg))
98#define RTL_R16(reg) readw (ioaddr + (reg))
Junchang Wang06f555f2010-05-30 02:26:07 +000099#define RTL_R32(reg) readl (ioaddr + (reg))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700100
101enum mac_version {
Francois Romieu85bffe62011-04-27 08:22:39 +0200102 RTL_GIGA_MAC_VER_01 = 0,
103 RTL_GIGA_MAC_VER_02,
104 RTL_GIGA_MAC_VER_03,
105 RTL_GIGA_MAC_VER_04,
106 RTL_GIGA_MAC_VER_05,
107 RTL_GIGA_MAC_VER_06,
108 RTL_GIGA_MAC_VER_07,
109 RTL_GIGA_MAC_VER_08,
110 RTL_GIGA_MAC_VER_09,
111 RTL_GIGA_MAC_VER_10,
112 RTL_GIGA_MAC_VER_11,
113 RTL_GIGA_MAC_VER_12,
114 RTL_GIGA_MAC_VER_13,
115 RTL_GIGA_MAC_VER_14,
116 RTL_GIGA_MAC_VER_15,
117 RTL_GIGA_MAC_VER_16,
118 RTL_GIGA_MAC_VER_17,
119 RTL_GIGA_MAC_VER_18,
120 RTL_GIGA_MAC_VER_19,
121 RTL_GIGA_MAC_VER_20,
122 RTL_GIGA_MAC_VER_21,
123 RTL_GIGA_MAC_VER_22,
124 RTL_GIGA_MAC_VER_23,
125 RTL_GIGA_MAC_VER_24,
126 RTL_GIGA_MAC_VER_25,
127 RTL_GIGA_MAC_VER_26,
128 RTL_GIGA_MAC_VER_27,
129 RTL_GIGA_MAC_VER_28,
130 RTL_GIGA_MAC_VER_29,
131 RTL_GIGA_MAC_VER_30,
132 RTL_GIGA_MAC_VER_31,
133 RTL_GIGA_MAC_VER_32,
134 RTL_GIGA_MAC_VER_33,
135 RTL_GIGA_MAC_NONE = 0xff,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700136};
137
Francois Romieu2b7b4312011-04-18 22:53:24 -0700138enum rtl_tx_desc_version {
139 RTL_TD_0 = 0,
140 RTL_TD_1 = 1,
141};
142
Francois Romieu85bffe62011-04-27 08:22:39 +0200143#define _R(NAME,TD,FW) \
144 { .name = NAME, .txd_version = TD, .fw_name = FW }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700145
Jesper Juhl3c6bee12006-01-09 20:54:01 -0800146static const struct {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700147 const char *name;
Francois Romieu2b7b4312011-04-18 22:53:24 -0700148 enum rtl_tx_desc_version txd_version;
Francois Romieu85bffe62011-04-27 08:22:39 +0200149 const char *fw_name;
150} rtl_chip_infos[] = {
151 /* PCI devices. */
152 [RTL_GIGA_MAC_VER_01] =
153 _R("RTL8169", RTL_TD_0, NULL),
154 [RTL_GIGA_MAC_VER_02] =
155 _R("RTL8169s", RTL_TD_0, NULL),
156 [RTL_GIGA_MAC_VER_03] =
157 _R("RTL8110s", RTL_TD_0, NULL),
158 [RTL_GIGA_MAC_VER_04] =
159 _R("RTL8169sb/8110sb", RTL_TD_0, NULL),
160 [RTL_GIGA_MAC_VER_05] =
161 _R("RTL8169sc/8110sc", RTL_TD_0, NULL),
162 [RTL_GIGA_MAC_VER_06] =
163 _R("RTL8169sc/8110sc", RTL_TD_0, NULL),
164 /* PCI-E devices. */
165 [RTL_GIGA_MAC_VER_07] =
166 _R("RTL8102e", RTL_TD_1, NULL),
167 [RTL_GIGA_MAC_VER_08] =
168 _R("RTL8102e", RTL_TD_1, NULL),
169 [RTL_GIGA_MAC_VER_09] =
170 _R("RTL8102e", RTL_TD_1, NULL),
171 [RTL_GIGA_MAC_VER_10] =
172 _R("RTL8101e", RTL_TD_0, NULL),
173 [RTL_GIGA_MAC_VER_11] =
174 _R("RTL8168b/8111b", RTL_TD_0, NULL),
175 [RTL_GIGA_MAC_VER_12] =
176 _R("RTL8168b/8111b", RTL_TD_0, NULL),
177 [RTL_GIGA_MAC_VER_13] =
178 _R("RTL8101e", RTL_TD_0, NULL),
179 [RTL_GIGA_MAC_VER_14] =
180 _R("RTL8100e", RTL_TD_0, NULL),
181 [RTL_GIGA_MAC_VER_15] =
182 _R("RTL8100e", RTL_TD_0, NULL),
183 [RTL_GIGA_MAC_VER_16] =
184 _R("RTL8101e", RTL_TD_0, NULL),
185 [RTL_GIGA_MAC_VER_17] =
186 _R("RTL8168b/8111b", RTL_TD_0, NULL),
187 [RTL_GIGA_MAC_VER_18] =
188 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
189 [RTL_GIGA_MAC_VER_19] =
190 _R("RTL8168c/8111c", RTL_TD_1, NULL),
191 [RTL_GIGA_MAC_VER_20] =
192 _R("RTL8168c/8111c", RTL_TD_1, NULL),
193 [RTL_GIGA_MAC_VER_21] =
194 _R("RTL8168c/8111c", RTL_TD_1, NULL),
195 [RTL_GIGA_MAC_VER_22] =
196 _R("RTL8168c/8111c", RTL_TD_1, NULL),
197 [RTL_GIGA_MAC_VER_23] =
198 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
199 [RTL_GIGA_MAC_VER_24] =
200 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
201 [RTL_GIGA_MAC_VER_25] =
202 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1),
203 [RTL_GIGA_MAC_VER_26] =
204 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2),
205 [RTL_GIGA_MAC_VER_27] =
206 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
207 [RTL_GIGA_MAC_VER_28] =
208 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
209 [RTL_GIGA_MAC_VER_29] =
210 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1),
211 [RTL_GIGA_MAC_VER_30] =
212 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1),
213 [RTL_GIGA_MAC_VER_31] =
214 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
215 [RTL_GIGA_MAC_VER_32] =
216 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1),
217 [RTL_GIGA_MAC_VER_33] =
218 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700219};
220#undef _R
221
Francois Romieubcf0bf92006-07-26 23:14:13 +0200222enum cfg_version {
223 RTL_CFG_0 = 0x00,
224 RTL_CFG_1,
225 RTL_CFG_2
226};
227
Francois Romieu07ce4062007-02-23 23:36:39 +0100228static void rtl_hw_start_8169(struct net_device *);
229static void rtl_hw_start_8168(struct net_device *);
230static void rtl_hw_start_8101(struct net_device *);
231
Alexey Dobriyana3aa1882010-01-07 11:58:11 +0000232static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
Francois Romieubcf0bf92006-07-26 23:14:13 +0200233 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
Francois Romieud2eed8c2006-08-31 22:01:07 +0200234 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
Francois Romieud81bf552006-09-20 21:31:20 +0200235 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
Francois Romieu07ce4062007-02-23 23:36:39 +0100236 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
Francois Romieubcf0bf92006-07-26 23:14:13 +0200237 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
238 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
Francois Romieubc1660b2007-10-12 23:58:09 +0200239 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
Francois Romieubcf0bf92006-07-26 23:14:13 +0200240 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
241 { PCI_VENDOR_ID_LINKSYS, 0x1032,
242 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
Ciaran McCreesh11d2e282007-11-01 22:48:15 +0100243 { 0x0001, 0x8168,
244 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700245 {0,},
246};
247
248MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
249
Eric Dumazet6f0333b2010-10-11 11:17:47 +0000250static int rx_buf_sz = 16383;
David S. Miller4300e8c2010-03-26 10:23:30 -0700251static int use_dac;
Stephen Hemmingerb57b7e52005-05-27 21:11:52 +0200252static struct {
253 u32 msg_enable;
254} debug = { -1 };
Linus Torvalds1da177e2005-04-16 15:20:36 -0700255
Francois Romieu07d3f512007-02-21 22:40:46 +0100256enum rtl_registers {
257 MAC0 = 0, /* Ethernet hardware address. */
Francois Romieu773d2022007-01-31 23:47:43 +0100258 MAC4 = 4,
Francois Romieu07d3f512007-02-21 22:40:46 +0100259 MAR0 = 8, /* Multicast filter. */
260 CounterAddrLow = 0x10,
261 CounterAddrHigh = 0x14,
262 TxDescStartAddrLow = 0x20,
263 TxDescStartAddrHigh = 0x24,
264 TxHDescStartAddrLow = 0x28,
265 TxHDescStartAddrHigh = 0x2c,
266 FLASH = 0x30,
267 ERSR = 0x36,
268 ChipCmd = 0x37,
269 TxPoll = 0x38,
270 IntrMask = 0x3c,
271 IntrStatus = 0x3e,
272 TxConfig = 0x40,
273 RxConfig = 0x44,
Francois Romieu2b7b4312011-04-18 22:53:24 -0700274
275#define RTL_RX_CONFIG_MASK 0xff7e1880u
276
Francois Romieu07d3f512007-02-21 22:40:46 +0100277 RxMissed = 0x4c,
278 Cfg9346 = 0x50,
279 Config0 = 0x51,
280 Config1 = 0x52,
281 Config2 = 0x53,
282 Config3 = 0x54,
283 Config4 = 0x55,
284 Config5 = 0x56,
285 MultiIntr = 0x5c,
286 PHYAR = 0x60,
Francois Romieu07d3f512007-02-21 22:40:46 +0100287 PHYstatus = 0x6c,
288 RxMaxSize = 0xda,
289 CPlusCmd = 0xe0,
290 IntrMitigate = 0xe2,
291 RxDescAddrLow = 0xe4,
292 RxDescAddrHigh = 0xe8,
françois romieuf0298f82011-01-03 15:07:42 +0000293 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
294
295#define NoEarlyTx 0x3f /* Max value : no early transmit. */
296
297 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
298
299#define TxPacketMax (8064 >> 7)
300
Francois Romieu07d3f512007-02-21 22:40:46 +0100301 FuncEvent = 0xf0,
302 FuncEventMask = 0xf4,
303 FuncPresetState = 0xf8,
304 FuncForceEvent = 0xfc,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700305};
306
Francois Romieuf162a5d2008-06-01 22:37:49 +0200307enum rtl8110_registers {
308 TBICSR = 0x64,
309 TBI_ANAR = 0x68,
310 TBI_LPAR = 0x6a,
311};
312
313enum rtl8168_8101_registers {
314 CSIDR = 0x64,
315 CSIAR = 0x68,
316#define CSIAR_FLAG 0x80000000
317#define CSIAR_WRITE_CMD 0x80000000
318#define CSIAR_BYTE_ENABLE 0x0f
319#define CSIAR_BYTE_ENABLE_SHIFT 12
320#define CSIAR_ADDR_MASK 0x0fff
françois romieu065c27c2011-01-03 15:08:12 +0000321 PMCH = 0x6f,
Francois Romieuf162a5d2008-06-01 22:37:49 +0200322 EPHYAR = 0x80,
323#define EPHYAR_FLAG 0x80000000
324#define EPHYAR_WRITE_CMD 0x80000000
325#define EPHYAR_REG_MASK 0x1f
326#define EPHYAR_REG_SHIFT 16
327#define EPHYAR_DATA_MASK 0xffff
Hayes Wang5a5e4442011-02-22 17:26:21 +0800328 DLLPR = 0xd0,
329#define PM_SWITCH (1 << 6)
Francois Romieuf162a5d2008-06-01 22:37:49 +0200330 DBG_REG = 0xd1,
331#define FIX_NAK_1 (1 << 4)
332#define FIX_NAK_2 (1 << 3)
Hayes Wang5a5e4442011-02-22 17:26:21 +0800333 TWSI = 0xd2,
334 MCU = 0xd3,
335#define EN_NDP (1 << 3)
336#define EN_OOB_RESET (1 << 2)
françois romieudaf9df62009-10-07 12:44:20 +0000337 EFUSEAR = 0xdc,
338#define EFUSEAR_FLAG 0x80000000
339#define EFUSEAR_WRITE_CMD 0x80000000
340#define EFUSEAR_READ_CMD 0x00000000
341#define EFUSEAR_REG_MASK 0x03ff
342#define EFUSEAR_REG_SHIFT 8
343#define EFUSEAR_DATA_MASK 0xff
Francois Romieuf162a5d2008-06-01 22:37:49 +0200344};
345
françois romieuc0e45c12011-01-03 15:08:04 +0000346enum rtl8168_registers {
françois romieub646d902011-01-03 15:08:21 +0000347 ERIDR = 0x70,
348 ERIAR = 0x74,
349#define ERIAR_FLAG 0x80000000
350#define ERIAR_WRITE_CMD 0x80000000
351#define ERIAR_READ_CMD 0x00000000
352#define ERIAR_ADDR_BYTE_ALIGN 4
353#define ERIAR_EXGMAC 0
354#define ERIAR_MSIX 1
355#define ERIAR_ASF 2
356#define ERIAR_TYPE_SHIFT 16
357#define ERIAR_BYTEEN 0x0f
358#define ERIAR_BYTEEN_SHIFT 12
françois romieuc0e45c12011-01-03 15:08:04 +0000359 EPHY_RXER_NUM = 0x7c,
360 OCPDR = 0xb0, /* OCP GPHY access */
361#define OCPDR_WRITE_CMD 0x80000000
362#define OCPDR_READ_CMD 0x00000000
363#define OCPDR_REG_MASK 0x7f
364#define OCPDR_GPHY_REG_SHIFT 16
365#define OCPDR_DATA_MASK 0xffff
366 OCPAR = 0xb4,
367#define OCPAR_FLAG 0x80000000
368#define OCPAR_GPHY_WRITE_CMD 0x8000f060
369#define OCPAR_GPHY_READ_CMD 0x0000f060
hayeswang01dc7fe2011-03-21 01:50:28 +0000370 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
371 MISC = 0xf0, /* 8168e only. */
Francois Romieucecb5fd2011-04-01 10:21:07 +0200372#define TXPLA_RST (1 << 29)
françois romieuc0e45c12011-01-03 15:08:04 +0000373};
374
Francois Romieu07d3f512007-02-21 22:40:46 +0100375enum rtl_register_content {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700376 /* InterruptStatusBits */
Francois Romieu07d3f512007-02-21 22:40:46 +0100377 SYSErr = 0x8000,
378 PCSTimeout = 0x4000,
379 SWInt = 0x0100,
380 TxDescUnavail = 0x0080,
381 RxFIFOOver = 0x0040,
382 LinkChg = 0x0020,
383 RxOverflow = 0x0010,
384 TxErr = 0x0008,
385 TxOK = 0x0004,
386 RxErr = 0x0002,
387 RxOK = 0x0001,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700388
389 /* RxStatusDesc */
Francois Romieu9dccf612006-05-14 12:31:17 +0200390 RxFOVF = (1 << 23),
391 RxRWT = (1 << 22),
392 RxRES = (1 << 21),
393 RxRUNT = (1 << 20),
394 RxCRC = (1 << 19),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700395
396 /* ChipCmdBits */
Francois Romieu07d3f512007-02-21 22:40:46 +0100397 CmdReset = 0x10,
398 CmdRxEnb = 0x08,
399 CmdTxEnb = 0x04,
400 RxBufEmpty = 0x01,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700401
Francois Romieu275391a2007-02-23 23:50:28 +0100402 /* TXPoll register p.5 */
403 HPQ = 0x80, /* Poll cmd on the high prio queue */
404 NPQ = 0x40, /* Poll cmd on the low prio queue */
405 FSWInt = 0x01, /* Forced software interrupt */
406
Linus Torvalds1da177e2005-04-16 15:20:36 -0700407 /* Cfg9346Bits */
Francois Romieu07d3f512007-02-21 22:40:46 +0100408 Cfg9346_Lock = 0x00,
409 Cfg9346_Unlock = 0xc0,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700410
411 /* rx_mode_bits */
Francois Romieu07d3f512007-02-21 22:40:46 +0100412 AcceptErr = 0x20,
413 AcceptRunt = 0x10,
414 AcceptBroadcast = 0x08,
415 AcceptMulticast = 0x04,
416 AcceptMyPhys = 0x02,
417 AcceptAllPhys = 0x01,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700418
419 /* RxConfigBits */
Francois Romieu07d3f512007-02-21 22:40:46 +0100420 RxCfgFIFOShift = 13,
421 RxCfgDMAShift = 8,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700422
423 /* TxConfigBits */
424 TxInterFrameGapShift = 24,
425 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
426
Francois Romieu5d06a992006-02-23 00:47:58 +0100427 /* Config1 register p.24 */
Francois Romieuf162a5d2008-06-01 22:37:49 +0200428 LEDS1 = (1 << 7),
429 LEDS0 = (1 << 6),
Francois Romieufbac58f2007-10-04 22:51:38 +0200430 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
Francois Romieuf162a5d2008-06-01 22:37:49 +0200431 Speed_down = (1 << 4),
432 MEMMAP = (1 << 3),
433 IOMAP = (1 << 2),
434 VPD = (1 << 1),
Francois Romieu5d06a992006-02-23 00:47:58 +0100435 PMEnable = (1 << 0), /* Power Management Enable */
436
Francois Romieu6dccd162007-02-13 23:38:05 +0100437 /* Config2 register p. 25 */
438 PCI_Clock_66MHz = 0x01,
439 PCI_Clock_33MHz = 0x00,
440
Francois Romieu61a4dcc2006-02-23 00:55:25 +0100441 /* Config3 register p.25 */
442 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
443 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
Francois Romieuf162a5d2008-06-01 22:37:49 +0200444 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
Francois Romieu61a4dcc2006-02-23 00:55:25 +0100445
Francois Romieu5d06a992006-02-23 00:47:58 +0100446 /* Config5 register p.27 */
Francois Romieu61a4dcc2006-02-23 00:55:25 +0100447 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
448 MWF = (1 << 5), /* Accept Multicast wakeup frame */
449 UWF = (1 << 4), /* Accept Unicast wakeup frame */
Francois Romieucecb5fd2011-04-01 10:21:07 +0200450 Spi_en = (1 << 3),
Francois Romieu61a4dcc2006-02-23 00:55:25 +0100451 LanWake = (1 << 1), /* LanWake enable/disable */
Francois Romieu5d06a992006-02-23 00:47:58 +0100452 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
453
Linus Torvalds1da177e2005-04-16 15:20:36 -0700454 /* TBICSR p.28 */
455 TBIReset = 0x80000000,
456 TBILoopback = 0x40000000,
457 TBINwEnable = 0x20000000,
458 TBINwRestart = 0x10000000,
459 TBILinkOk = 0x02000000,
460 TBINwComplete = 0x01000000,
461
462 /* CPlusCmd p.31 */
Francois Romieuf162a5d2008-06-01 22:37:49 +0200463 EnableBist = (1 << 15), // 8168 8101
464 Mac_dbgo_oe = (1 << 14), // 8168 8101
465 Normal_mode = (1 << 13), // unused
466 Force_half_dup = (1 << 12), // 8168 8101
467 Force_rxflow_en = (1 << 11), // 8168 8101
468 Force_txflow_en = (1 << 10), // 8168 8101
469 Cxpl_dbg_sel = (1 << 9), // 8168 8101
470 ASF = (1 << 8), // 8168 8101
471 PktCntrDisable = (1 << 7), // 8168 8101
472 Mac_dbgo_sel = 0x001c, // 8168
Linus Torvalds1da177e2005-04-16 15:20:36 -0700473 RxVlan = (1 << 6),
474 RxChkSum = (1 << 5),
475 PCIDAC = (1 << 4),
476 PCIMulRW = (1 << 3),
Francois Romieu0e485152007-02-20 00:00:26 +0100477 INTT_0 = 0x0000, // 8168
478 INTT_1 = 0x0001, // 8168
479 INTT_2 = 0x0002, // 8168
480 INTT_3 = 0x0003, // 8168
Linus Torvalds1da177e2005-04-16 15:20:36 -0700481
482 /* rtl8169_PHYstatus */
Francois Romieu07d3f512007-02-21 22:40:46 +0100483 TBI_Enable = 0x80,
484 TxFlowCtrl = 0x40,
485 RxFlowCtrl = 0x20,
486 _1000bpsF = 0x10,
487 _100bps = 0x08,
488 _10bps = 0x04,
489 LinkStatus = 0x02,
490 FullDup = 0x01,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700491
Linus Torvalds1da177e2005-04-16 15:20:36 -0700492 /* _TBICSRBit */
Francois Romieu07d3f512007-02-21 22:40:46 +0100493 TBILinkOK = 0x02000000,
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +0200494
495 /* DumpCounterCommand */
Francois Romieu07d3f512007-02-21 22:40:46 +0100496 CounterDump = 0x8,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700497};
498
Francois Romieu2b7b4312011-04-18 22:53:24 -0700499enum rtl_desc_bit {
500 /* First doubleword. */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700501 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
502 RingEnd = (1 << 30), /* End of descriptor ring */
503 FirstFrag = (1 << 29), /* First segment of a packet */
504 LastFrag = (1 << 28), /* Final segment of a packet */
Francois Romieu2b7b4312011-04-18 22:53:24 -0700505};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700506
Francois Romieu2b7b4312011-04-18 22:53:24 -0700507/* Generic case. */
508enum rtl_tx_desc_bit {
509 /* First doubleword. */
510 TD_LSO = (1 << 27), /* Large Send Offload */
511#define TD_MSS_MAX 0x07ffu /* MSS value */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700512
Francois Romieu2b7b4312011-04-18 22:53:24 -0700513 /* Second doubleword. */
514 TxVlanTag = (1 << 17), /* Add VLAN tag */
515};
516
517/* 8169, 8168b and 810x except 8102e. */
518enum rtl_tx_desc_bit_0 {
519 /* First doubleword. */
520#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
521 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
522 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
523 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
524};
525
526/* 8102e, 8168c and beyond. */
527enum rtl_tx_desc_bit_1 {
528 /* Second doubleword. */
529#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
530 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
531 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
532 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
533};
534
535static const struct rtl_tx_desc_info {
536 struct {
537 u32 udp;
538 u32 tcp;
539 } checksum;
540 u16 mss_shift;
541 u16 opts_offset;
542} tx_desc_info [] = {
543 [RTL_TD_0] = {
544 .checksum = {
545 .udp = TD0_IP_CS | TD0_UDP_CS,
546 .tcp = TD0_IP_CS | TD0_TCP_CS
547 },
548 .mss_shift = TD0_MSS_SHIFT,
549 .opts_offset = 0
550 },
551 [RTL_TD_1] = {
552 .checksum = {
553 .udp = TD1_IP_CS | TD1_UDP_CS,
554 .tcp = TD1_IP_CS | TD1_TCP_CS
555 },
556 .mss_shift = TD1_MSS_SHIFT,
557 .opts_offset = 1
558 }
559};
560
561enum rtl_rx_desc_bit {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700562 /* Rx private */
563 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
564 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
565
566#define RxProtoUDP (PID1)
567#define RxProtoTCP (PID0)
568#define RxProtoIP (PID1 | PID0)
569#define RxProtoMask RxProtoIP
570
571 IPFail = (1 << 16), /* IP checksum failed */
572 UDPFail = (1 << 15), /* UDP/IP checksum failed */
573 TCPFail = (1 << 14), /* TCP/IP checksum failed */
574 RxVlanTag = (1 << 16), /* VLAN tag available */
575};
576
577#define RsvdMask 0x3fffc000
578
579struct TxDesc {
Rolf Eike Beer6cccd6e2007-05-21 22:11:04 +0200580 __le32 opts1;
581 __le32 opts2;
582 __le64 addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700583};
584
585struct RxDesc {
Rolf Eike Beer6cccd6e2007-05-21 22:11:04 +0200586 __le32 opts1;
587 __le32 opts2;
588 __le64 addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700589};
590
591struct ring_info {
592 struct sk_buff *skb;
593 u32 len;
594 u8 __pad[sizeof(void *) - sizeof(u32)];
595};
596
Francois Romieuf23e7fd2007-10-04 22:36:14 +0200597enum features {
Francois Romieuccdffb92008-07-26 14:26:06 +0200598 RTL_FEATURE_WOL = (1 << 0),
599 RTL_FEATURE_MSI = (1 << 1),
600 RTL_FEATURE_GMII = (1 << 2),
Francois Romieuf23e7fd2007-10-04 22:36:14 +0200601};
602
Ivan Vecera355423d2009-02-06 21:49:57 -0800603struct rtl8169_counters {
604 __le64 tx_packets;
605 __le64 rx_packets;
606 __le64 tx_errors;
607 __le32 rx_errors;
608 __le16 rx_missed;
609 __le16 align_errors;
610 __le32 tx_one_collision;
611 __le32 tx_multi_collision;
612 __le64 rx_unicast;
613 __le64 rx_broadcast;
614 __le32 rx_multicast;
615 __le16 tx_aborted;
616 __le16 tx_underun;
617};
618
Linus Torvalds1da177e2005-04-16 15:20:36 -0700619struct rtl8169_private {
620 void __iomem *mmio_addr; /* memory map physical address */
Francois Romieucecb5fd2011-04-01 10:21:07 +0200621 struct pci_dev *pci_dev;
David Howellsc4028952006-11-22 14:57:56 +0000622 struct net_device *dev;
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700623 struct napi_struct napi;
Francois Romieucecb5fd2011-04-01 10:21:07 +0200624 spinlock_t lock;
Stephen Hemmingerb57b7e52005-05-27 21:11:52 +0200625 u32 msg_enable;
Francois Romieu2b7b4312011-04-18 22:53:24 -0700626 u16 txd_version;
627 u16 mac_version;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700628 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
629 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
630 u32 dirty_rx;
631 u32 dirty_tx;
632 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
633 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
634 dma_addr_t TxPhyAddr;
635 dma_addr_t RxPhyAddr;
Eric Dumazet6f0333b2010-10-11 11:17:47 +0000636 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700637 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700638 struct timer_list timer;
639 u16 cp_cmd;
Francois Romieu0e485152007-02-20 00:00:26 +0100640 u16 intr_event;
641 u16 napi_event;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700642 u16 intr_mask;
françois romieuc0e45c12011-01-03 15:08:04 +0000643
644 struct mdio_ops {
645 void (*write)(void __iomem *, int, int);
646 int (*read)(void __iomem *, int);
647 } mdio_ops;
648
françois romieu065c27c2011-01-03 15:08:12 +0000649 struct pll_power_ops {
650 void (*down)(struct rtl8169_private *);
651 void (*up)(struct rtl8169_private *);
652 } pll_power_ops;
653
Oliver Neukum54405cd2011-01-06 21:55:13 +0100654 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
Francois Romieuccdffb92008-07-26 14:26:06 +0200655 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
françois romieu4da19632011-01-03 15:07:55 +0000656 void (*phy_reset_enable)(struct rtl8169_private *tp);
Francois Romieu07ce4062007-02-23 23:36:39 +0100657 void (*hw_start)(struct net_device *);
françois romieu4da19632011-01-03 15:07:55 +0000658 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700659 unsigned int (*link_ok)(void __iomem *);
Francois Romieu8b4ab282008-11-19 22:05:25 -0800660 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
Francois Romieu9c14cea2008-07-05 00:21:15 +0200661 int pcie_cap;
David Howellsc4028952006-11-22 14:57:56 +0000662 struct delayed_work task;
Francois Romieuf23e7fd2007-10-04 22:36:14 +0200663 unsigned features;
Francois Romieuccdffb92008-07-26 14:26:06 +0200664
665 struct mii_if_info mii;
Ivan Vecera355423d2009-02-06 21:49:57 -0800666 struct rtl8169_counters counters;
Rafael J. Wysockie1759442010-03-14 14:33:51 +0000667 u32 saved_wolopts;
françois romieuf1e02ed2011-01-13 13:07:53 +0000668
669 const struct firmware *fw;
François Romieu953a12c2011-04-24 17:38:48 +0200670#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700671};
672
Ralf Baechle979b6c12005-06-13 14:30:40 -0700673MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700674MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700675module_param(use_dac, int, 0);
David S. Miller4300e8c2010-03-26 10:23:30 -0700676MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
Stephen Hemmingerb57b7e52005-05-27 21:11:52 +0200677module_param_named(debug, debug.msg_enable, int, 0);
678MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700679MODULE_LICENSE("GPL");
680MODULE_VERSION(RTL8169_VERSION);
françois romieubca03d52011-01-03 15:07:31 +0000681MODULE_FIRMWARE(FIRMWARE_8168D_1);
682MODULE_FIRMWARE(FIRMWARE_8168D_2);
hayeswang01dc7fe2011-03-21 01:50:28 +0000683MODULE_FIRMWARE(FIRMWARE_8168E_1);
684MODULE_FIRMWARE(FIRMWARE_8168E_2);
Hayes Wang5a5e4442011-02-22 17:26:21 +0800685MODULE_FIRMWARE(FIRMWARE_8105E_1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700686
687static int rtl8169_open(struct net_device *dev);
Stephen Hemminger613573252009-08-31 19:50:58 +0000688static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
689 struct net_device *dev);
David Howells7d12e782006-10-05 14:55:46 +0100690static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700691static int rtl8169_init_ring(struct net_device *dev);
Francois Romieu07ce4062007-02-23 23:36:39 +0100692static void rtl_hw_start(struct net_device *dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700693static int rtl8169_close(struct net_device *dev);
Francois Romieu07ce4062007-02-23 23:36:39 +0100694static void rtl_set_rx_mode(struct net_device *dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700695static void rtl8169_tx_timeout(struct net_device *dev);
Richard Dawe4dcb7d32005-05-27 21:12:00 +0200696static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700697static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700698 void __iomem *, u32 budget);
Richard Dawe4dcb7d32005-05-27 21:12:00 +0200699static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700700static void rtl8169_down(struct net_device *dev);
Francois Romieu99f252b2007-04-02 22:59:59 +0200701static void rtl8169_rx_clear(struct rtl8169_private *tp);
Stephen Hemmingerbea33482007-10-03 16:41:36 -0700702static int rtl8169_poll(struct napi_struct *napi, int budget);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700703
Linus Torvalds1da177e2005-04-16 15:20:36 -0700704static const unsigned int rtl8169_rx_config =
Francois Romieu5b0384f2006-08-16 16:00:01 +0200705 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700706
françois romieub646d902011-01-03 15:08:21 +0000707static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
708{
709 void __iomem *ioaddr = tp->mmio_addr;
710 int i;
711
712 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
713 for (i = 0; i < 20; i++) {
714 udelay(100);
715 if (RTL_R32(OCPAR) & OCPAR_FLAG)
716 break;
717 }
718 return RTL_R32(OCPDR);
719}
720
721static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
722{
723 void __iomem *ioaddr = tp->mmio_addr;
724 int i;
725
726 RTL_W32(OCPDR, data);
727 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
728 for (i = 0; i < 20; i++) {
729 udelay(100);
730 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
731 break;
732 }
733}
734
Hayes Wangfac5b3c2011-02-22 17:26:20 +0800735static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
françois romieub646d902011-01-03 15:08:21 +0000736{
Hayes Wangfac5b3c2011-02-22 17:26:20 +0800737 void __iomem *ioaddr = tp->mmio_addr;
françois romieub646d902011-01-03 15:08:21 +0000738 int i;
739
740 RTL_W8(ERIDR, cmd);
741 RTL_W32(ERIAR, 0x800010e8);
742 msleep(2);
743 for (i = 0; i < 5; i++) {
744 udelay(100);
745 if (!(RTL_R32(ERIDR) & ERIAR_FLAG))
746 break;
747 }
748
Hayes Wangfac5b3c2011-02-22 17:26:20 +0800749 ocp_write(tp, 0x1, 0x30, 0x00000001);
françois romieub646d902011-01-03 15:08:21 +0000750}
751
752#define OOB_CMD_RESET 0x00
753#define OOB_CMD_DRIVER_START 0x05
754#define OOB_CMD_DRIVER_STOP 0x06
755
Francois Romieucecb5fd2011-04-01 10:21:07 +0200756static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
757{
758 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
759}
760
françois romieub646d902011-01-03 15:08:21 +0000761static void rtl8168_driver_start(struct rtl8169_private *tp)
762{
Francois Romieucecb5fd2011-04-01 10:21:07 +0200763 u16 reg;
françois romieub646d902011-01-03 15:08:21 +0000764 int i;
765
766 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
767
Francois Romieucecb5fd2011-04-01 10:21:07 +0200768 reg = rtl8168_get_ocp_reg(tp);
hayeswang4804b3b2011-03-21 01:50:29 +0000769
françois romieub646d902011-01-03 15:08:21 +0000770 for (i = 0; i < 10; i++) {
771 msleep(10);
hayeswang4804b3b2011-03-21 01:50:29 +0000772 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
françois romieub646d902011-01-03 15:08:21 +0000773 break;
774 }
775}
776
777static void rtl8168_driver_stop(struct rtl8169_private *tp)
778{
Francois Romieucecb5fd2011-04-01 10:21:07 +0200779 u16 reg;
françois romieub646d902011-01-03 15:08:21 +0000780 int i;
781
782 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
783
Francois Romieucecb5fd2011-04-01 10:21:07 +0200784 reg = rtl8168_get_ocp_reg(tp);
hayeswang4804b3b2011-03-21 01:50:29 +0000785
françois romieub646d902011-01-03 15:08:21 +0000786 for (i = 0; i < 10; i++) {
787 msleep(10);
hayeswang4804b3b2011-03-21 01:50:29 +0000788 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
françois romieub646d902011-01-03 15:08:21 +0000789 break;
790 }
791}
792
hayeswang4804b3b2011-03-21 01:50:29 +0000793static int r8168dp_check_dash(struct rtl8169_private *tp)
794{
Francois Romieucecb5fd2011-04-01 10:21:07 +0200795 u16 reg = rtl8168_get_ocp_reg(tp);
hayeswang4804b3b2011-03-21 01:50:29 +0000796
Francois Romieucecb5fd2011-04-01 10:21:07 +0200797 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
hayeswang4804b3b2011-03-21 01:50:29 +0000798}
françois romieub646d902011-01-03 15:08:21 +0000799
françois romieu4da19632011-01-03 15:07:55 +0000800static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700801{
802 int i;
803
Francois Romieua6baf3a2007-11-08 23:23:21 +0100804 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700805
Francois Romieu23714082006-01-29 00:49:09 +0100806 for (i = 20; i > 0; i--) {
Francois Romieu07d3f512007-02-21 22:40:46 +0100807 /*
808 * Check if the RTL8169 has completed writing to the specified
809 * MII register.
810 */
Francois Romieu5b0384f2006-08-16 16:00:01 +0200811 if (!(RTL_R32(PHYAR) & 0x80000000))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700812 break;
Francois Romieu23714082006-01-29 00:49:09 +0100813 udelay(25);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700814 }
Timo Teräs024a07b2010-06-06 15:38:47 -0700815 /*
Timo Teräs81a95f02010-06-09 17:31:48 -0700816 * According to hardware specs a 20us delay is required after write
817 * complete indication, but before sending next command.
Timo Teräs024a07b2010-06-06 15:38:47 -0700818 */
Timo Teräs81a95f02010-06-09 17:31:48 -0700819 udelay(20);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700820}
821
françois romieu4da19632011-01-03 15:07:55 +0000822static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700823{
824 int i, value = -1;
825
Francois Romieua6baf3a2007-11-08 23:23:21 +0100826 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700827
Francois Romieu23714082006-01-29 00:49:09 +0100828 for (i = 20; i > 0; i--) {
Francois Romieu07d3f512007-02-21 22:40:46 +0100829 /*
830 * Check if the RTL8169 has completed retrieving data from
831 * the specified MII register.
832 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700833 if (RTL_R32(PHYAR) & 0x80000000) {
Francois Romieua6baf3a2007-11-08 23:23:21 +0100834 value = RTL_R32(PHYAR) & 0xffff;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700835 break;
836 }
Francois Romieu23714082006-01-29 00:49:09 +0100837 udelay(25);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700838 }
Timo Teräs81a95f02010-06-09 17:31:48 -0700839 /*
840 * According to hardware specs a 20us delay is required after read
841 * complete indication, but before sending next command.
842 */
843 udelay(20);
844
Linus Torvalds1da177e2005-04-16 15:20:36 -0700845 return value;
846}
847
françois romieuc0e45c12011-01-03 15:08:04 +0000848static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
849{
850 int i;
851
852 RTL_W32(OCPDR, data |
853 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
854 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
855 RTL_W32(EPHY_RXER_NUM, 0);
856
857 for (i = 0; i < 100; i++) {
858 mdelay(1);
859 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
860 break;
861 }
862}
863
864static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
865{
866 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
867 (value & OCPDR_DATA_MASK));
868}
869
870static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
871{
872 int i;
873
874 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
875
876 mdelay(1);
877 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
878 RTL_W32(EPHY_RXER_NUM, 0);
879
880 for (i = 0; i < 100; i++) {
881 mdelay(1);
882 if (RTL_R32(OCPAR) & OCPAR_FLAG)
883 break;
884 }
885
886 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
887}
888
françois romieue6de30d2011-01-03 15:08:37 +0000889#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
890
891static void r8168dp_2_mdio_start(void __iomem *ioaddr)
892{
893 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
894}
895
896static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
897{
898 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
899}
900
901static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
902{
903 r8168dp_2_mdio_start(ioaddr);
904
905 r8169_mdio_write(ioaddr, reg_addr, value);
906
907 r8168dp_2_mdio_stop(ioaddr);
908}
909
910static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
911{
912 int value;
913
914 r8168dp_2_mdio_start(ioaddr);
915
916 value = r8169_mdio_read(ioaddr, reg_addr);
917
918 r8168dp_2_mdio_stop(ioaddr);
919
920 return value;
921}
922
françois romieu4da19632011-01-03 15:07:55 +0000923static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
Francois Romieudacf8152008-08-02 20:44:13 +0200924{
françois romieuc0e45c12011-01-03 15:08:04 +0000925 tp->mdio_ops.write(tp->mmio_addr, location, val);
Francois Romieudacf8152008-08-02 20:44:13 +0200926}
927
françois romieu4da19632011-01-03 15:07:55 +0000928static int rtl_readphy(struct rtl8169_private *tp, int location)
929{
françois romieuc0e45c12011-01-03 15:08:04 +0000930 return tp->mdio_ops.read(tp->mmio_addr, location);
françois romieu4da19632011-01-03 15:07:55 +0000931}
932
933static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
934{
935 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
936}
937
938static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
françois romieudaf9df62009-10-07 12:44:20 +0000939{
940 int val;
941
françois romieu4da19632011-01-03 15:07:55 +0000942 val = rtl_readphy(tp, reg_addr);
943 rtl_writephy(tp, reg_addr, (val | p) & ~m);
françois romieudaf9df62009-10-07 12:44:20 +0000944}
945
Francois Romieuccdffb92008-07-26 14:26:06 +0200946static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
947 int val)
948{
949 struct rtl8169_private *tp = netdev_priv(dev);
Francois Romieuccdffb92008-07-26 14:26:06 +0200950
françois romieu4da19632011-01-03 15:07:55 +0000951 rtl_writephy(tp, location, val);
Francois Romieuccdffb92008-07-26 14:26:06 +0200952}
953
954static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
955{
956 struct rtl8169_private *tp = netdev_priv(dev);
Francois Romieuccdffb92008-07-26 14:26:06 +0200957
françois romieu4da19632011-01-03 15:07:55 +0000958 return rtl_readphy(tp, location);
Francois Romieuccdffb92008-07-26 14:26:06 +0200959}
960
Francois Romieudacf8152008-08-02 20:44:13 +0200961static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
962{
963 unsigned int i;
964
965 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
966 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
967
968 for (i = 0; i < 100; i++) {
969 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
970 break;
971 udelay(10);
972 }
973}
974
975static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
976{
977 u16 value = 0xffff;
978 unsigned int i;
979
980 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
981
982 for (i = 0; i < 100; i++) {
983 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
984 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
985 break;
986 }
987 udelay(10);
988 }
989
990 return value;
991}
992
993static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
994{
995 unsigned int i;
996
997 RTL_W32(CSIDR, value);
998 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
999 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1000
1001 for (i = 0; i < 100; i++) {
1002 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1003 break;
1004 udelay(10);
1005 }
1006}
1007
1008static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1009{
1010 u32 value = ~0x00;
1011 unsigned int i;
1012
1013 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1014 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1015
1016 for (i = 0; i < 100; i++) {
1017 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1018 value = RTL_R32(CSIDR);
1019 break;
1020 }
1021 udelay(10);
1022 }
1023
1024 return value;
1025}
1026
françois romieudaf9df62009-10-07 12:44:20 +00001027static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1028{
1029 u8 value = 0xff;
1030 unsigned int i;
1031
1032 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1033
1034 for (i = 0; i < 300; i++) {
1035 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1036 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1037 break;
1038 }
1039 udelay(100);
1040 }
1041
1042 return value;
1043}
1044
Linus Torvalds1da177e2005-04-16 15:20:36 -07001045static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
1046{
1047 RTL_W16(IntrMask, 0x0000);
1048
1049 RTL_W16(IntrStatus, 0xffff);
1050}
1051
1052static void rtl8169_asic_down(void __iomem *ioaddr)
1053{
1054 RTL_W8(ChipCmd, 0x00);
1055 rtl8169_irq_mask_and_ack(ioaddr);
1056 RTL_R16(CPlusCmd);
1057}
1058
françois romieu4da19632011-01-03 15:07:55 +00001059static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001060{
françois romieu4da19632011-01-03 15:07:55 +00001061 void __iomem *ioaddr = tp->mmio_addr;
1062
Linus Torvalds1da177e2005-04-16 15:20:36 -07001063 return RTL_R32(TBICSR) & TBIReset;
1064}
1065
françois romieu4da19632011-01-03 15:07:55 +00001066static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001067{
françois romieu4da19632011-01-03 15:07:55 +00001068 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001069}
1070
1071static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1072{
1073 return RTL_R32(TBICSR) & TBILinkOk;
1074}
1075
1076static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1077{
1078 return RTL_R8(PHYstatus) & LinkStatus;
1079}
1080
françois romieu4da19632011-01-03 15:07:55 +00001081static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001082{
françois romieu4da19632011-01-03 15:07:55 +00001083 void __iomem *ioaddr = tp->mmio_addr;
1084
Linus Torvalds1da177e2005-04-16 15:20:36 -07001085 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1086}
1087
françois romieu4da19632011-01-03 15:07:55 +00001088static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001089{
1090 unsigned int val;
1091
françois romieu4da19632011-01-03 15:07:55 +00001092 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1093 rtl_writephy(tp, MII_BMCR, val & 0xffff);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001094}
1095
Rafael J. Wysockie4fbce72010-12-08 15:32:14 +00001096static void __rtl8169_check_link_status(struct net_device *dev,
Francois Romieucecb5fd2011-04-01 10:21:07 +02001097 struct rtl8169_private *tp,
1098 void __iomem *ioaddr, bool pm)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001099{
1100 unsigned long flags;
1101
1102 spin_lock_irqsave(&tp->lock, flags);
1103 if (tp->link_ok(ioaddr)) {
Rafael J. Wysockie1759442010-03-14 14:33:51 +00001104 /* This is to cancel a scheduled suspend if there's one. */
Rafael J. Wysockie4fbce72010-12-08 15:32:14 +00001105 if (pm)
1106 pm_request_resume(&tp->pci_dev->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001107 netif_carrier_on(dev);
Francois Romieu1519e572011-02-03 12:02:36 +01001108 if (net_ratelimit())
1109 netif_info(tp, ifup, dev, "link up\n");
Stephen Hemmingerb57b7e52005-05-27 21:11:52 +02001110 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001111 netif_carrier_off(dev);
Joe Perchesbf82c182010-02-09 11:49:50 +00001112 netif_info(tp, ifdown, dev, "link down\n");
Rafael J. Wysockie4fbce72010-12-08 15:32:14 +00001113 if (pm)
1114 pm_schedule_suspend(&tp->pci_dev->dev, 100);
Stephen Hemmingerb57b7e52005-05-27 21:11:52 +02001115 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001116 spin_unlock_irqrestore(&tp->lock, flags);
1117}
1118
Rafael J. Wysockie4fbce72010-12-08 15:32:14 +00001119static void rtl8169_check_link_status(struct net_device *dev,
1120 struct rtl8169_private *tp,
1121 void __iomem *ioaddr)
1122{
1123 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1124}
1125
Rafael J. Wysockie1759442010-03-14 14:33:51 +00001126#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1127
1128static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1129{
1130 void __iomem *ioaddr = tp->mmio_addr;
1131 u8 options;
1132 u32 wolopts = 0;
1133
1134 options = RTL_R8(Config1);
1135 if (!(options & PMEnable))
1136 return 0;
1137
1138 options = RTL_R8(Config3);
1139 if (options & LinkUp)
1140 wolopts |= WAKE_PHY;
1141 if (options & MagicPacket)
1142 wolopts |= WAKE_MAGIC;
1143
1144 options = RTL_R8(Config5);
1145 if (options & UWF)
1146 wolopts |= WAKE_UCAST;
1147 if (options & BWF)
1148 wolopts |= WAKE_BCAST;
1149 if (options & MWF)
1150 wolopts |= WAKE_MCAST;
1151
1152 return wolopts;
1153}
1154
Francois Romieu61a4dcc2006-02-23 00:55:25 +01001155static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1156{
1157 struct rtl8169_private *tp = netdev_priv(dev);
Francois Romieu61a4dcc2006-02-23 00:55:25 +01001158
1159 spin_lock_irq(&tp->lock);
1160
Rafael J. Wysockie1759442010-03-14 14:33:51 +00001161 wol->supported = WAKE_ANY;
1162 wol->wolopts = __rtl8169_get_wol(tp);
Francois Romieu61a4dcc2006-02-23 00:55:25 +01001163
Francois Romieu61a4dcc2006-02-23 00:55:25 +01001164 spin_unlock_irq(&tp->lock);
1165}
1166
Rafael J. Wysockie1759442010-03-14 14:33:51 +00001167static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
Francois Romieu61a4dcc2006-02-23 00:55:25 +01001168{
Francois Romieu61a4dcc2006-02-23 00:55:25 +01001169 void __iomem *ioaddr = tp->mmio_addr;
Francois Romieu07d3f512007-02-21 22:40:46 +01001170 unsigned int i;
Alexey Dobriyan350f7592009-11-25 15:54:21 -08001171 static const struct {
Francois Romieu61a4dcc2006-02-23 00:55:25 +01001172 u32 opt;
1173 u16 reg;
1174 u8 mask;
1175 } cfg[] = {
1176 { WAKE_ANY, Config1, PMEnable },
1177 { WAKE_PHY, Config3, LinkUp },
1178 { WAKE_MAGIC, Config3, MagicPacket },
1179 { WAKE_UCAST, Config5, UWF },
1180 { WAKE_BCAST, Config5, BWF },
1181 { WAKE_MCAST, Config5, MWF },
1182 { WAKE_ANY, Config5, LanWake }
1183 };
1184
Francois Romieu61a4dcc2006-02-23 00:55:25 +01001185 RTL_W8(Cfg9346, Cfg9346_Unlock);
1186
1187 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1188 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
Rafael J. Wysockie1759442010-03-14 14:33:51 +00001189 if (wolopts & cfg[i].opt)
Francois Romieu61a4dcc2006-02-23 00:55:25 +01001190 options |= cfg[i].mask;
1191 RTL_W8(cfg[i].reg, options);
1192 }
1193
1194 RTL_W8(Cfg9346, Cfg9346_Lock);
Rafael J. Wysockie1759442010-03-14 14:33:51 +00001195}
1196
1197static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1198{
1199 struct rtl8169_private *tp = netdev_priv(dev);
1200
1201 spin_lock_irq(&tp->lock);
Francois Romieu61a4dcc2006-02-23 00:55:25 +01001202
Francois Romieuf23e7fd2007-10-04 22:36:14 +02001203 if (wol->wolopts)
1204 tp->features |= RTL_FEATURE_WOL;
1205 else
1206 tp->features &= ~RTL_FEATURE_WOL;
Rafael J. Wysockie1759442010-03-14 14:33:51 +00001207 __rtl8169_set_wol(tp, wol->wolopts);
Francois Romieu61a4dcc2006-02-23 00:55:25 +01001208 spin_unlock_irq(&tp->lock);
1209
françois romieuea809072010-11-08 13:23:58 +00001210 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1211
Francois Romieu61a4dcc2006-02-23 00:55:25 +01001212 return 0;
1213}
1214
Francois Romieu31bd2042011-04-26 18:58:59 +02001215static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1216{
Francois Romieu85bffe62011-04-27 08:22:39 +02001217 return rtl_chip_infos[tp->mac_version].fw_name;
Francois Romieu31bd2042011-04-26 18:58:59 +02001218}
1219
Linus Torvalds1da177e2005-04-16 15:20:36 -07001220static void rtl8169_get_drvinfo(struct net_device *dev,
1221 struct ethtool_drvinfo *info)
1222{
1223 struct rtl8169_private *tp = netdev_priv(dev);
1224
1225 strcpy(info->driver, MODULENAME);
1226 strcpy(info->version, RTL8169_VERSION);
1227 strcpy(info->bus_info, pci_name(tp->pci_dev));
Francois Romieu31bd2042011-04-26 18:58:59 +02001228 strncpy(info->fw_version, IS_ERR_OR_NULL(tp->fw) ? "N/A" :
1229 rtl_lookup_firmware_name(tp), sizeof(info->fw_version) - 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001230}
1231
1232static int rtl8169_get_regs_len(struct net_device *dev)
1233{
1234 return R8169_REGS_SIZE;
1235}
1236
1237static int rtl8169_set_speed_tbi(struct net_device *dev,
Oliver Neukum54405cd2011-01-06 21:55:13 +01001238 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001239{
1240 struct rtl8169_private *tp = netdev_priv(dev);
1241 void __iomem *ioaddr = tp->mmio_addr;
1242 int ret = 0;
1243 u32 reg;
1244
1245 reg = RTL_R32(TBICSR);
1246 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1247 (duplex == DUPLEX_FULL)) {
1248 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1249 } else if (autoneg == AUTONEG_ENABLE)
1250 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1251 else {
Joe Perchesbf82c182010-02-09 11:49:50 +00001252 netif_warn(tp, link, dev,
1253 "incorrect speed setting refused in TBI mode\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001254 ret = -EOPNOTSUPP;
1255 }
1256
1257 return ret;
1258}
1259
1260static int rtl8169_set_speed_xmii(struct net_device *dev,
Oliver Neukum54405cd2011-01-06 21:55:13 +01001261 u8 autoneg, u16 speed, u8 duplex, u32 adv)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001262{
1263 struct rtl8169_private *tp = netdev_priv(dev);
françois romieu3577aa12009-05-19 10:46:48 +00001264 int giga_ctrl, bmcr;
Oliver Neukum54405cd2011-01-06 21:55:13 +01001265 int rc = -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001266
Hayes Wang716b50a2011-02-22 17:26:18 +08001267 rtl_writephy(tp, 0x1f, 0x0000);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001268
1269 if (autoneg == AUTONEG_ENABLE) {
françois romieu3577aa12009-05-19 10:46:48 +00001270 int auto_nego;
1271
françois romieu4da19632011-01-03 15:07:55 +00001272 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
Oliver Neukum54405cd2011-01-06 21:55:13 +01001273 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1274 ADVERTISE_100HALF | ADVERTISE_100FULL);
1275
1276 if (adv & ADVERTISED_10baseT_Half)
1277 auto_nego |= ADVERTISE_10HALF;
1278 if (adv & ADVERTISED_10baseT_Full)
1279 auto_nego |= ADVERTISE_10FULL;
1280 if (adv & ADVERTISED_100baseT_Half)
1281 auto_nego |= ADVERTISE_100HALF;
1282 if (adv & ADVERTISED_100baseT_Full)
1283 auto_nego |= ADVERTISE_100FULL;
1284
françois romieu3577aa12009-05-19 10:46:48 +00001285 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1286
françois romieu4da19632011-01-03 15:07:55 +00001287 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
françois romieu3577aa12009-05-19 10:46:48 +00001288 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1289
1290 /* The 8100e/8101e/8102e do Fast Ethernet only. */
Francois Romieu826e6cb2011-03-11 20:30:24 +01001291 if (tp->mii.supports_gmii) {
Oliver Neukum54405cd2011-01-06 21:55:13 +01001292 if (adv & ADVERTISED_1000baseT_Half)
1293 giga_ctrl |= ADVERTISE_1000HALF;
1294 if (adv & ADVERTISED_1000baseT_Full)
1295 giga_ctrl |= ADVERTISE_1000FULL;
1296 } else if (adv & (ADVERTISED_1000baseT_Half |
1297 ADVERTISED_1000baseT_Full)) {
Joe Perchesbf82c182010-02-09 11:49:50 +00001298 netif_info(tp, link, dev,
1299 "PHY does not support 1000Mbps\n");
Oliver Neukum54405cd2011-01-06 21:55:13 +01001300 goto out;
Francois Romieubcf0bf92006-07-26 23:14:13 +02001301 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001302
françois romieu3577aa12009-05-19 10:46:48 +00001303 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
Francois Romieu623a1592006-05-14 12:42:14 +02001304
françois romieu4da19632011-01-03 15:07:55 +00001305 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1306 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
françois romieu3577aa12009-05-19 10:46:48 +00001307 } else {
1308 giga_ctrl = 0;
1309
1310 if (speed == SPEED_10)
1311 bmcr = 0;
1312 else if (speed == SPEED_100)
1313 bmcr = BMCR_SPEED100;
1314 else
Oliver Neukum54405cd2011-01-06 21:55:13 +01001315 goto out;
françois romieu3577aa12009-05-19 10:46:48 +00001316
1317 if (duplex == DUPLEX_FULL)
1318 bmcr |= BMCR_FULLDPLX;
Roger So2584fbc2007-07-31 23:52:42 +02001319 }
1320
françois romieu4da19632011-01-03 15:07:55 +00001321 rtl_writephy(tp, MII_BMCR, bmcr);
françois romieu3577aa12009-05-19 10:46:48 +00001322
Francois Romieucecb5fd2011-04-01 10:21:07 +02001323 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1324 tp->mac_version == RTL_GIGA_MAC_VER_03) {
françois romieu3577aa12009-05-19 10:46:48 +00001325 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
françois romieu4da19632011-01-03 15:07:55 +00001326 rtl_writephy(tp, 0x17, 0x2138);
1327 rtl_writephy(tp, 0x0e, 0x0260);
françois romieu3577aa12009-05-19 10:46:48 +00001328 } else {
françois romieu4da19632011-01-03 15:07:55 +00001329 rtl_writephy(tp, 0x17, 0x2108);
1330 rtl_writephy(tp, 0x0e, 0x0000);
françois romieu3577aa12009-05-19 10:46:48 +00001331 }
1332 }
1333
Oliver Neukum54405cd2011-01-06 21:55:13 +01001334 rc = 0;
1335out:
1336 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001337}
1338
1339static int rtl8169_set_speed(struct net_device *dev,
Oliver Neukum54405cd2011-01-06 21:55:13 +01001340 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001341{
1342 struct rtl8169_private *tp = netdev_priv(dev);
1343 int ret;
1344
Oliver Neukum54405cd2011-01-06 21:55:13 +01001345 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
Francois Romieu4876cc12011-03-11 21:07:11 +01001346 if (ret < 0)
1347 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001348
Francois Romieu4876cc12011-03-11 21:07:11 +01001349 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1350 (advertising & ADVERTISED_1000baseT_Full)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001351 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
Francois Romieu4876cc12011-03-11 21:07:11 +01001352 }
1353out:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001354 return ret;
1355}
1356
1357static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1358{
1359 struct rtl8169_private *tp = netdev_priv(dev);
1360 unsigned long flags;
1361 int ret;
1362
Francois Romieu4876cc12011-03-11 21:07:11 +01001363 del_timer_sync(&tp->timer);
1364
Linus Torvalds1da177e2005-04-16 15:20:36 -07001365 spin_lock_irqsave(&tp->lock, flags);
Francois Romieucecb5fd2011-04-01 10:21:07 +02001366 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
David Decotigny25db0332011-04-27 18:32:39 +00001367 cmd->duplex, cmd->advertising);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001368 spin_unlock_irqrestore(&tp->lock, flags);
Francois Romieu5b0384f2006-08-16 16:00:01 +02001369
Linus Torvalds1da177e2005-04-16 15:20:36 -07001370 return ret;
1371}
1372
Michał Mirosław350fb322011-04-08 06:35:56 +00001373static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001374{
Francois Romieu2b7b4312011-04-18 22:53:24 -07001375 if (dev->mtu > TD_MSS_MAX)
Michał Mirosław350fb322011-04-08 06:35:56 +00001376 features &= ~NETIF_F_ALL_TSO;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001377
Michał Mirosław350fb322011-04-08 06:35:56 +00001378 return features;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001379}
1380
Michał Mirosław350fb322011-04-08 06:35:56 +00001381static int rtl8169_set_features(struct net_device *dev, u32 features)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001382{
1383 struct rtl8169_private *tp = netdev_priv(dev);
1384 void __iomem *ioaddr = tp->mmio_addr;
1385 unsigned long flags;
1386
1387 spin_lock_irqsave(&tp->lock, flags);
1388
Michał Mirosław350fb322011-04-08 06:35:56 +00001389 if (features & NETIF_F_RXCSUM)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001390 tp->cp_cmd |= RxChkSum;
1391 else
1392 tp->cp_cmd &= ~RxChkSum;
1393
Michał Mirosław350fb322011-04-08 06:35:56 +00001394 if (dev->features & NETIF_F_HW_VLAN_RX)
1395 tp->cp_cmd |= RxVlan;
1396 else
1397 tp->cp_cmd &= ~RxVlan;
1398
Linus Torvalds1da177e2005-04-16 15:20:36 -07001399 RTL_W16(CPlusCmd, tp->cp_cmd);
1400 RTL_R16(CPlusCmd);
1401
1402 spin_unlock_irqrestore(&tp->lock, flags);
1403
1404 return 0;
1405}
1406
Linus Torvalds1da177e2005-04-16 15:20:36 -07001407static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1408 struct sk_buff *skb)
1409{
Jesse Grosseab6d182010-10-20 13:56:03 +00001410 return (vlan_tx_tag_present(skb)) ?
Linus Torvalds1da177e2005-04-16 15:20:36 -07001411 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1412}
1413
Francois Romieu7a8fc772011-03-01 17:18:33 +01001414static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001415{
1416 u32 opts2 = le32_to_cpu(desc->opts2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001417
Francois Romieu7a8fc772011-03-01 17:18:33 +01001418 if (opts2 & RxVlanTag)
1419 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
Eric Dumazet2edae082010-09-06 18:46:39 +00001420
Linus Torvalds1da177e2005-04-16 15:20:36 -07001421 desc->opts2 = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001422}
1423
Francois Romieuccdffb92008-07-26 14:26:06 +02001424static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001425{
1426 struct rtl8169_private *tp = netdev_priv(dev);
1427 void __iomem *ioaddr = tp->mmio_addr;
1428 u32 status;
1429
1430 cmd->supported =
1431 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1432 cmd->port = PORT_FIBRE;
1433 cmd->transceiver = XCVR_INTERNAL;
1434
1435 status = RTL_R32(TBICSR);
1436 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1437 cmd->autoneg = !!(status & TBINwEnable);
1438
David Decotigny70739492011-04-27 18:32:40 +00001439 ethtool_cmd_speed_set(cmd, SPEED_1000);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001440 cmd->duplex = DUPLEX_FULL; /* Always set */
Francois Romieuccdffb92008-07-26 14:26:06 +02001441
1442 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001443}
1444
Francois Romieuccdffb92008-07-26 14:26:06 +02001445static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001446{
1447 struct rtl8169_private *tp = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001448
Francois Romieuccdffb92008-07-26 14:26:06 +02001449 return mii_ethtool_gset(&tp->mii, cmd);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001450}
1451
1452static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1453{
1454 struct rtl8169_private *tp = netdev_priv(dev);
1455 unsigned long flags;
Francois Romieuccdffb92008-07-26 14:26:06 +02001456 int rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001457
1458 spin_lock_irqsave(&tp->lock, flags);
1459
Francois Romieuccdffb92008-07-26 14:26:06 +02001460 rc = tp->get_settings(dev, cmd);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001461
1462 spin_unlock_irqrestore(&tp->lock, flags);
Francois Romieuccdffb92008-07-26 14:26:06 +02001463 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001464}
1465
1466static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1467 void *p)
1468{
Francois Romieu5b0384f2006-08-16 16:00:01 +02001469 struct rtl8169_private *tp = netdev_priv(dev);
1470 unsigned long flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001471
Francois Romieu5b0384f2006-08-16 16:00:01 +02001472 if (regs->len > R8169_REGS_SIZE)
1473 regs->len = R8169_REGS_SIZE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001474
Francois Romieu5b0384f2006-08-16 16:00:01 +02001475 spin_lock_irqsave(&tp->lock, flags);
1476 memcpy_fromio(p, tp->mmio_addr, regs->len);
1477 spin_unlock_irqrestore(&tp->lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001478}
1479
Stephen Hemmingerb57b7e52005-05-27 21:11:52 +02001480static u32 rtl8169_get_msglevel(struct net_device *dev)
1481{
1482 struct rtl8169_private *tp = netdev_priv(dev);
1483
1484 return tp->msg_enable;
1485}
1486
1487static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1488{
1489 struct rtl8169_private *tp = netdev_priv(dev);
1490
1491 tp->msg_enable = value;
1492}
1493
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +02001494static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1495 "tx_packets",
1496 "rx_packets",
1497 "tx_errors",
1498 "rx_errors",
1499 "rx_missed",
1500 "align_errors",
1501 "tx_single_collisions",
1502 "tx_multi_collisions",
1503 "unicast",
1504 "broadcast",
1505 "multicast",
1506 "tx_aborted",
1507 "tx_underrun",
1508};
1509
Jeff Garzikb9f2c042007-10-03 18:07:32 -07001510static int rtl8169_get_sset_count(struct net_device *dev, int sset)
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +02001511{
Jeff Garzikb9f2c042007-10-03 18:07:32 -07001512 switch (sset) {
1513 case ETH_SS_STATS:
1514 return ARRAY_SIZE(rtl8169_gstrings);
1515 default:
1516 return -EOPNOTSUPP;
1517 }
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +02001518}
1519
Ivan Vecera355423d2009-02-06 21:49:57 -08001520static void rtl8169_update_counters(struct net_device *dev)
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +02001521{
1522 struct rtl8169_private *tp = netdev_priv(dev);
1523 void __iomem *ioaddr = tp->mmio_addr;
Francois Romieucecb5fd2011-04-01 10:21:07 +02001524 struct device *d = &tp->pci_dev->dev;
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +02001525 struct rtl8169_counters *counters;
1526 dma_addr_t paddr;
1527 u32 cmd;
Ivan Vecera355423d2009-02-06 21:49:57 -08001528 int wait = 1000;
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +02001529
Ivan Vecera355423d2009-02-06 21:49:57 -08001530 /*
1531 * Some chips are unable to dump tally counters when the receiver
1532 * is disabled.
1533 */
1534 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1535 return;
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +02001536
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00001537 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +02001538 if (!counters)
1539 return;
1540
1541 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
Yang Hongyang284901a2009-04-06 19:01:15 -07001542 cmd = (u64)paddr & DMA_BIT_MASK(32);
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +02001543 RTL_W32(CounterAddrLow, cmd);
1544 RTL_W32(CounterAddrLow, cmd | CounterDump);
1545
Ivan Vecera355423d2009-02-06 21:49:57 -08001546 while (wait--) {
1547 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
Ivan Vecera355423d2009-02-06 21:49:57 -08001548 memcpy(&tp->counters, counters, sizeof(*counters));
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +02001549 break;
Ivan Vecera355423d2009-02-06 21:49:57 -08001550 }
1551 udelay(10);
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +02001552 }
1553
1554 RTL_W32(CounterAddrLow, 0);
1555 RTL_W32(CounterAddrHigh, 0);
1556
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00001557 dma_free_coherent(d, sizeof(*counters), counters, paddr);
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +02001558}
1559
Ivan Vecera355423d2009-02-06 21:49:57 -08001560static void rtl8169_get_ethtool_stats(struct net_device *dev,
1561 struct ethtool_stats *stats, u64 *data)
1562{
1563 struct rtl8169_private *tp = netdev_priv(dev);
1564
1565 ASSERT_RTNL();
1566
1567 rtl8169_update_counters(dev);
1568
1569 data[0] = le64_to_cpu(tp->counters.tx_packets);
1570 data[1] = le64_to_cpu(tp->counters.rx_packets);
1571 data[2] = le64_to_cpu(tp->counters.tx_errors);
1572 data[3] = le32_to_cpu(tp->counters.rx_errors);
1573 data[4] = le16_to_cpu(tp->counters.rx_missed);
1574 data[5] = le16_to_cpu(tp->counters.align_errors);
1575 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1576 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1577 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1578 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1579 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1580 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1581 data[12] = le16_to_cpu(tp->counters.tx_underun);
1582}
1583
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +02001584static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1585{
1586 switch(stringset) {
1587 case ETH_SS_STATS:
1588 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1589 break;
1590 }
1591}
1592
Jeff Garzik7282d492006-09-13 14:30:00 -04001593static const struct ethtool_ops rtl8169_ethtool_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001594 .get_drvinfo = rtl8169_get_drvinfo,
1595 .get_regs_len = rtl8169_get_regs_len,
1596 .get_link = ethtool_op_get_link,
1597 .get_settings = rtl8169_get_settings,
1598 .set_settings = rtl8169_set_settings,
Stephen Hemmingerb57b7e52005-05-27 21:11:52 +02001599 .get_msglevel = rtl8169_get_msglevel,
1600 .set_msglevel = rtl8169_set_msglevel,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001601 .get_regs = rtl8169_get_regs,
Francois Romieu61a4dcc2006-02-23 00:55:25 +01001602 .get_wol = rtl8169_get_wol,
1603 .set_wol = rtl8169_set_wol,
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +02001604 .get_strings = rtl8169_get_strings,
Jeff Garzikb9f2c042007-10-03 18:07:32 -07001605 .get_sset_count = rtl8169_get_sset_count,
Stephen Hemmingerd4a3a0f2005-05-27 21:11:56 +02001606 .get_ethtool_stats = rtl8169_get_ethtool_stats,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001607};
1608
Francois Romieu07d3f512007-02-21 22:40:46 +01001609static void rtl8169_get_mac_version(struct rtl8169_private *tp,
Francois Romieu5d320a22011-05-08 17:47:36 +02001610 struct net_device *dev, u8 default_version)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001611{
Francois Romieu5d320a22011-05-08 17:47:36 +02001612 void __iomem *ioaddr = tp->mmio_addr;
Francois Romieu0e485152007-02-20 00:00:26 +01001613 /*
1614 * The driver currently handles the 8168Bf and the 8168Be identically
1615 * but they can be identified more specifically through the test below
1616 * if needed:
1617 *
1618 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
Francois Romieu01272152007-02-20 22:58:51 +01001619 *
1620 * Same thing for the 8101Eb and the 8101Ec:
1621 *
1622 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
Francois Romieu0e485152007-02-20 00:00:26 +01001623 */
Alexey Dobriyan350f7592009-11-25 15:54:21 -08001624 static const struct {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001625 u32 mask;
Francois Romieue3cf0cc2007-08-17 14:55:46 +02001626 u32 val;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001627 int mac_version;
1628 } mac_info[] = {
hayeswang01dc7fe2011-03-21 01:50:28 +00001629 /* 8168E family. */
1630 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
1631 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
1632 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
1633
Francois Romieu5b538df2008-07-20 16:22:45 +02001634 /* 8168D family. */
françois romieudaf9df62009-10-07 12:44:20 +00001635 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1636 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
françois romieudaf9df62009-10-07 12:44:20 +00001637 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
Francois Romieu5b538df2008-07-20 16:22:45 +02001638
françois romieue6de30d2011-01-03 15:08:37 +00001639 /* 8168DP family. */
1640 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1641 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
hayeswang4804b3b2011-03-21 01:50:29 +00001642 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
françois romieue6de30d2011-01-03 15:08:37 +00001643
Francois Romieuef808d52008-06-29 13:10:54 +02001644 /* 8168C family. */
Francois Romieu17c99292010-07-11 17:10:09 -07001645 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
Francois Romieuef3386f2008-06-29 12:24:30 +02001646 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
Francois Romieuef808d52008-06-29 13:10:54 +02001647 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
Francois Romieu7f3e3d32008-07-20 18:53:20 +02001648 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
Francois Romieue3cf0cc2007-08-17 14:55:46 +02001649 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1650 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
Francois Romieu197ff762008-06-28 13:16:02 +02001651 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
Francois Romieu6fb07052008-06-29 11:54:28 +02001652 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
Francois Romieuef808d52008-06-29 13:10:54 +02001653 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
Francois Romieue3cf0cc2007-08-17 14:55:46 +02001654
1655 /* 8168B family. */
1656 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1657 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1658 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1659 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1660
1661 /* 8101 family. */
hayeswang36a0e6c2011-03-21 01:50:30 +00001662 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
Hayes Wang5a5e4442011-02-22 17:26:21 +08001663 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
1664 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
1665 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
Francois Romieu2857ffb2008-08-02 21:08:49 +02001666 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1667 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1668 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1669 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1670 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1671 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
Francois Romieue3cf0cc2007-08-17 14:55:46 +02001672 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
Francois Romieu2857ffb2008-08-02 21:08:49 +02001673 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
Francois Romieue3cf0cc2007-08-17 14:55:46 +02001674 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
Francois Romieu2857ffb2008-08-02 21:08:49 +02001675 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1676 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
Francois Romieue3cf0cc2007-08-17 14:55:46 +02001677 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1678 /* FIXME: where did these entries come from ? -- FR */
1679 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1680 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1681
1682 /* 8110 family. */
1683 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1684 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1685 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1686 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1687 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1688 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1689
Jean Delvaref21b75e2009-05-26 20:54:48 -07001690 /* Catch-all */
1691 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001692 }, *p = mac_info;
1693 u32 reg;
1694
Francois Romieue3cf0cc2007-08-17 14:55:46 +02001695 reg = RTL_R32(TxConfig);
1696 while ((reg & p->mask) != p->val)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001697 p++;
1698 tp->mac_version = p->mac_version;
Francois Romieu5d320a22011-05-08 17:47:36 +02001699
1700 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1701 netif_notice(tp, probe, dev,
1702 "unknown MAC, using family default\n");
1703 tp->mac_version = default_version;
1704 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001705}
1706
1707static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1708{
Francois Romieubcf0bf92006-07-26 23:14:13 +02001709 dprintk("mac_version = 0x%02x\n", tp->mac_version);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001710}
1711
Francois Romieu867763c2007-08-17 18:21:58 +02001712struct phy_reg {
1713 u16 reg;
1714 u16 val;
1715};
1716
françois romieu4da19632011-01-03 15:07:55 +00001717static void rtl_writephy_batch(struct rtl8169_private *tp,
1718 const struct phy_reg *regs, int len)
Francois Romieu867763c2007-08-17 18:21:58 +02001719{
1720 while (len-- > 0) {
françois romieu4da19632011-01-03 15:07:55 +00001721 rtl_writephy(tp, regs->reg, regs->val);
Francois Romieu867763c2007-08-17 18:21:58 +02001722 regs++;
1723 }
1724}
1725
françois romieubca03d52011-01-03 15:07:31 +00001726#define PHY_READ 0x00000000
1727#define PHY_DATA_OR 0x10000000
1728#define PHY_DATA_AND 0x20000000
1729#define PHY_BJMPN 0x30000000
1730#define PHY_READ_EFUSE 0x40000000
1731#define PHY_READ_MAC_BYTE 0x50000000
1732#define PHY_WRITE_MAC_BYTE 0x60000000
1733#define PHY_CLEAR_READCOUNT 0x70000000
1734#define PHY_WRITE 0x80000000
1735#define PHY_READCOUNT_EQ_SKIP 0x90000000
1736#define PHY_COMP_EQ_SKIPN 0xa0000000
1737#define PHY_COMP_NEQ_SKIPN 0xb0000000
1738#define PHY_WRITE_PREVIOUS 0xc0000000
1739#define PHY_SKIPN 0xd0000000
1740#define PHY_DELAY_MS 0xe0000000
1741#define PHY_WRITE_ERI_WORD 0xf0000000
1742
1743static void
1744rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1745{
françois romieubca03d52011-01-03 15:07:31 +00001746 __le32 *phytable = (__le32 *)fw->data;
1747 struct net_device *dev = tp->dev;
hayeswang42b82dc2011-01-10 02:07:25 +00001748 size_t index, fw_size = fw->size / sizeof(*phytable);
1749 u32 predata, count;
françois romieubca03d52011-01-03 15:07:31 +00001750
1751 if (fw->size % sizeof(*phytable)) {
1752 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1753 return;
1754 }
1755
hayeswang42b82dc2011-01-10 02:07:25 +00001756 for (index = 0; index < fw_size; index++) {
1757 u32 action = le32_to_cpu(phytable[index]);
1758 u32 regno = (action & 0x0fff0000) >> 16;
françois romieubca03d52011-01-03 15:07:31 +00001759
hayeswang42b82dc2011-01-10 02:07:25 +00001760 switch(action & 0xf0000000) {
1761 case PHY_READ:
1762 case PHY_DATA_OR:
1763 case PHY_DATA_AND:
1764 case PHY_READ_EFUSE:
1765 case PHY_CLEAR_READCOUNT:
1766 case PHY_WRITE:
1767 case PHY_WRITE_PREVIOUS:
1768 case PHY_DELAY_MS:
françois romieubca03d52011-01-03 15:07:31 +00001769 break;
1770
hayeswang42b82dc2011-01-10 02:07:25 +00001771 case PHY_BJMPN:
1772 if (regno > index) {
1773 netif_err(tp, probe, tp->dev,
Francois Romieucecb5fd2011-04-01 10:21:07 +02001774 "Out of range of firmware\n");
hayeswang42b82dc2011-01-10 02:07:25 +00001775 return;
1776 }
1777 break;
1778 case PHY_READCOUNT_EQ_SKIP:
1779 if (index + 2 >= fw_size) {
1780 netif_err(tp, probe, tp->dev,
Francois Romieucecb5fd2011-04-01 10:21:07 +02001781 "Out of range of firmware\n");
hayeswang42b82dc2011-01-10 02:07:25 +00001782 return;
1783 }
1784 break;
1785 case PHY_COMP_EQ_SKIPN:
1786 case PHY_COMP_NEQ_SKIPN:
1787 case PHY_SKIPN:
1788 if (index + 1 + regno >= fw_size) {
1789 netif_err(tp, probe, tp->dev,
Francois Romieucecb5fd2011-04-01 10:21:07 +02001790 "Out of range of firmware\n");
hayeswang42b82dc2011-01-10 02:07:25 +00001791 return;
1792 }
1793 break;
1794
1795 case PHY_READ_MAC_BYTE:
1796 case PHY_WRITE_MAC_BYTE:
1797 case PHY_WRITE_ERI_WORD:
1798 default:
1799 netif_err(tp, probe, tp->dev,
1800 "Invalid action 0x%08x\n", action);
françois romieubca03d52011-01-03 15:07:31 +00001801 return;
1802 }
1803 }
1804
hayeswang42b82dc2011-01-10 02:07:25 +00001805 predata = 0;
1806 count = 0;
1807
1808 for (index = 0; index < fw_size; ) {
1809 u32 action = le32_to_cpu(phytable[index]);
françois romieubca03d52011-01-03 15:07:31 +00001810 u32 data = action & 0x0000ffff;
hayeswang42b82dc2011-01-10 02:07:25 +00001811 u32 regno = (action & 0x0fff0000) >> 16;
1812
1813 if (!action)
1814 break;
françois romieubca03d52011-01-03 15:07:31 +00001815
1816 switch(action & 0xf0000000) {
hayeswang42b82dc2011-01-10 02:07:25 +00001817 case PHY_READ:
1818 predata = rtl_readphy(tp, regno);
1819 count++;
1820 index++;
françois romieubca03d52011-01-03 15:07:31 +00001821 break;
hayeswang42b82dc2011-01-10 02:07:25 +00001822 case PHY_DATA_OR:
1823 predata |= data;
1824 index++;
1825 break;
1826 case PHY_DATA_AND:
1827 predata &= data;
1828 index++;
1829 break;
1830 case PHY_BJMPN:
1831 index -= regno;
1832 break;
1833 case PHY_READ_EFUSE:
1834 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
1835 index++;
1836 break;
1837 case PHY_CLEAR_READCOUNT:
1838 count = 0;
1839 index++;
1840 break;
1841 case PHY_WRITE:
1842 rtl_writephy(tp, regno, data);
1843 index++;
1844 break;
1845 case PHY_READCOUNT_EQ_SKIP:
Francois Romieucecb5fd2011-04-01 10:21:07 +02001846 index += (count == data) ? 2 : 1;
hayeswang42b82dc2011-01-10 02:07:25 +00001847 break;
1848 case PHY_COMP_EQ_SKIPN:
1849 if (predata == data)
1850 index += regno;
1851 index++;
1852 break;
1853 case PHY_COMP_NEQ_SKIPN:
1854 if (predata != data)
1855 index += regno;
1856 index++;
1857 break;
1858 case PHY_WRITE_PREVIOUS:
1859 rtl_writephy(tp, regno, predata);
1860 index++;
1861 break;
1862 case PHY_SKIPN:
1863 index += regno + 1;
1864 break;
1865 case PHY_DELAY_MS:
1866 mdelay(data);
1867 index++;
1868 break;
1869
1870 case PHY_READ_MAC_BYTE:
1871 case PHY_WRITE_MAC_BYTE:
1872 case PHY_WRITE_ERI_WORD:
françois romieubca03d52011-01-03 15:07:31 +00001873 default:
1874 BUG();
1875 }
1876 }
1877}
1878
françois romieuf1e02ed2011-01-13 13:07:53 +00001879static void rtl_release_firmware(struct rtl8169_private *tp)
1880{
François Romieu953a12c2011-04-24 17:38:48 +02001881 if (!IS_ERR_OR_NULL(tp->fw))
1882 release_firmware(tp->fw);
1883 tp->fw = RTL_FIRMWARE_UNKNOWN;
françois romieuf1e02ed2011-01-13 13:07:53 +00001884}
1885
François Romieu953a12c2011-04-24 17:38:48 +02001886static void rtl_apply_firmware(struct rtl8169_private *tp)
françois romieuf1e02ed2011-01-13 13:07:53 +00001887{
François Romieu953a12c2011-04-24 17:38:48 +02001888 const struct firmware *fw = tp->fw;
françois romieuf1e02ed2011-01-13 13:07:53 +00001889
1890 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
François Romieu953a12c2011-04-24 17:38:48 +02001891 if (!IS_ERR_OR_NULL(fw))
1892 rtl_phy_write_fw(tp, fw);
1893}
1894
1895static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
1896{
1897 if (rtl_readphy(tp, reg) != val)
1898 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
1899 else
1900 rtl_apply_firmware(tp);
françois romieuf1e02ed2011-01-13 13:07:53 +00001901}
1902
françois romieu4da19632011-01-03 15:07:55 +00001903static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001904{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08001905 static const struct phy_reg phy_reg_init[] = {
françois romieu0b9b5712009-08-10 19:44:56 +00001906 { 0x1f, 0x0001 },
1907 { 0x06, 0x006e },
1908 { 0x08, 0x0708 },
1909 { 0x15, 0x4000 },
1910 { 0x18, 0x65c7 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001911
françois romieu0b9b5712009-08-10 19:44:56 +00001912 { 0x1f, 0x0001 },
1913 { 0x03, 0x00a1 },
1914 { 0x02, 0x0008 },
1915 { 0x01, 0x0120 },
1916 { 0x00, 0x1000 },
1917 { 0x04, 0x0800 },
1918 { 0x04, 0x0000 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001919
françois romieu0b9b5712009-08-10 19:44:56 +00001920 { 0x03, 0xff41 },
1921 { 0x02, 0xdf60 },
1922 { 0x01, 0x0140 },
1923 { 0x00, 0x0077 },
1924 { 0x04, 0x7800 },
1925 { 0x04, 0x7000 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07001926
françois romieu0b9b5712009-08-10 19:44:56 +00001927 { 0x03, 0x802f },
1928 { 0x02, 0x4f02 },
1929 { 0x01, 0x0409 },
1930 { 0x00, 0xf0f9 },
1931 { 0x04, 0x9800 },
1932 { 0x04, 0x9000 },
1933
1934 { 0x03, 0xdf01 },
1935 { 0x02, 0xdf20 },
1936 { 0x01, 0xff95 },
1937 { 0x00, 0xba00 },
1938 { 0x04, 0xa800 },
1939 { 0x04, 0xa000 },
1940
1941 { 0x03, 0xff41 },
1942 { 0x02, 0xdf20 },
1943 { 0x01, 0x0140 },
1944 { 0x00, 0x00bb },
1945 { 0x04, 0xb800 },
1946 { 0x04, 0xb000 },
1947
1948 { 0x03, 0xdf41 },
1949 { 0x02, 0xdc60 },
1950 { 0x01, 0x6340 },
1951 { 0x00, 0x007d },
1952 { 0x04, 0xd800 },
1953 { 0x04, 0xd000 },
1954
1955 { 0x03, 0xdf01 },
1956 { 0x02, 0xdf20 },
1957 { 0x01, 0x100a },
1958 { 0x00, 0xa0ff },
1959 { 0x04, 0xf800 },
1960 { 0x04, 0xf000 },
1961
1962 { 0x1f, 0x0000 },
1963 { 0x0b, 0x0000 },
1964 { 0x00, 0x9200 }
1965 };
1966
françois romieu4da19632011-01-03 15:07:55 +00001967 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001968}
1969
françois romieu4da19632011-01-03 15:07:55 +00001970static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
Francois Romieu5615d9f2007-08-17 17:50:46 +02001971{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08001972 static const struct phy_reg phy_reg_init[] = {
Francois Romieua441d7b2007-08-17 18:26:35 +02001973 { 0x1f, 0x0002 },
1974 { 0x01, 0x90d0 },
1975 { 0x1f, 0x0000 }
1976 };
1977
françois romieu4da19632011-01-03 15:07:55 +00001978 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
Francois Romieu5615d9f2007-08-17 17:50:46 +02001979}
1980
françois romieu4da19632011-01-03 15:07:55 +00001981static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
françois romieu2e9558562009-08-10 19:44:19 +00001982{
1983 struct pci_dev *pdev = tp->pci_dev;
1984 u16 vendor_id, device_id;
1985
1986 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1987 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1988
1989 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1990 return;
1991
françois romieu4da19632011-01-03 15:07:55 +00001992 rtl_writephy(tp, 0x1f, 0x0001);
1993 rtl_writephy(tp, 0x10, 0xf01b);
1994 rtl_writephy(tp, 0x1f, 0x0000);
françois romieu2e9558562009-08-10 19:44:19 +00001995}
1996
françois romieu4da19632011-01-03 15:07:55 +00001997static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
françois romieu2e9558562009-08-10 19:44:19 +00001998{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08001999 static const struct phy_reg phy_reg_init[] = {
françois romieu2e9558562009-08-10 19:44:19 +00002000 { 0x1f, 0x0001 },
2001 { 0x04, 0x0000 },
2002 { 0x03, 0x00a1 },
2003 { 0x02, 0x0008 },
2004 { 0x01, 0x0120 },
2005 { 0x00, 0x1000 },
2006 { 0x04, 0x0800 },
2007 { 0x04, 0x9000 },
2008 { 0x03, 0x802f },
2009 { 0x02, 0x4f02 },
2010 { 0x01, 0x0409 },
2011 { 0x00, 0xf099 },
2012 { 0x04, 0x9800 },
2013 { 0x04, 0xa000 },
2014 { 0x03, 0xdf01 },
2015 { 0x02, 0xdf20 },
2016 { 0x01, 0xff95 },
2017 { 0x00, 0xba00 },
2018 { 0x04, 0xa800 },
2019 { 0x04, 0xf000 },
2020 { 0x03, 0xdf01 },
2021 { 0x02, 0xdf20 },
2022 { 0x01, 0x101a },
2023 { 0x00, 0xa0ff },
2024 { 0x04, 0xf800 },
2025 { 0x04, 0x0000 },
2026 { 0x1f, 0x0000 },
2027
2028 { 0x1f, 0x0001 },
2029 { 0x10, 0xf41b },
2030 { 0x14, 0xfb54 },
2031 { 0x18, 0xf5c7 },
2032 { 0x1f, 0x0000 },
2033
2034 { 0x1f, 0x0001 },
2035 { 0x17, 0x0cc0 },
2036 { 0x1f, 0x0000 }
2037 };
2038
françois romieu4da19632011-01-03 15:07:55 +00002039 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
françois romieu2e9558562009-08-10 19:44:19 +00002040
françois romieu4da19632011-01-03 15:07:55 +00002041 rtl8169scd_hw_phy_config_quirk(tp);
françois romieu2e9558562009-08-10 19:44:19 +00002042}
2043
françois romieu4da19632011-01-03 15:07:55 +00002044static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
françois romieu8c7006a2009-08-10 19:43:29 +00002045{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002046 static const struct phy_reg phy_reg_init[] = {
françois romieu8c7006a2009-08-10 19:43:29 +00002047 { 0x1f, 0x0001 },
2048 { 0x04, 0x0000 },
2049 { 0x03, 0x00a1 },
2050 { 0x02, 0x0008 },
2051 { 0x01, 0x0120 },
2052 { 0x00, 0x1000 },
2053 { 0x04, 0x0800 },
2054 { 0x04, 0x9000 },
2055 { 0x03, 0x802f },
2056 { 0x02, 0x4f02 },
2057 { 0x01, 0x0409 },
2058 { 0x00, 0xf099 },
2059 { 0x04, 0x9800 },
2060 { 0x04, 0xa000 },
2061 { 0x03, 0xdf01 },
2062 { 0x02, 0xdf20 },
2063 { 0x01, 0xff95 },
2064 { 0x00, 0xba00 },
2065 { 0x04, 0xa800 },
2066 { 0x04, 0xf000 },
2067 { 0x03, 0xdf01 },
2068 { 0x02, 0xdf20 },
2069 { 0x01, 0x101a },
2070 { 0x00, 0xa0ff },
2071 { 0x04, 0xf800 },
2072 { 0x04, 0x0000 },
2073 { 0x1f, 0x0000 },
2074
2075 { 0x1f, 0x0001 },
2076 { 0x0b, 0x8480 },
2077 { 0x1f, 0x0000 },
2078
2079 { 0x1f, 0x0001 },
2080 { 0x18, 0x67c7 },
2081 { 0x04, 0x2000 },
2082 { 0x03, 0x002f },
2083 { 0x02, 0x4360 },
2084 { 0x01, 0x0109 },
2085 { 0x00, 0x3022 },
2086 { 0x04, 0x2800 },
2087 { 0x1f, 0x0000 },
2088
2089 { 0x1f, 0x0001 },
2090 { 0x17, 0x0cc0 },
2091 { 0x1f, 0x0000 }
2092 };
2093
françois romieu4da19632011-01-03 15:07:55 +00002094 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
françois romieu8c7006a2009-08-10 19:43:29 +00002095}
2096
françois romieu4da19632011-01-03 15:07:55 +00002097static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
Francois Romieu236b8082008-05-30 16:11:48 +02002098{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002099 static const struct phy_reg phy_reg_init[] = {
Francois Romieu236b8082008-05-30 16:11:48 +02002100 { 0x10, 0xf41b },
2101 { 0x1f, 0x0000 }
2102 };
2103
françois romieu4da19632011-01-03 15:07:55 +00002104 rtl_writephy(tp, 0x1f, 0x0001);
2105 rtl_patchphy(tp, 0x16, 1 << 0);
Francois Romieu236b8082008-05-30 16:11:48 +02002106
françois romieu4da19632011-01-03 15:07:55 +00002107 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
Francois Romieu236b8082008-05-30 16:11:48 +02002108}
2109
françois romieu4da19632011-01-03 15:07:55 +00002110static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
Francois Romieu236b8082008-05-30 16:11:48 +02002111{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002112 static const struct phy_reg phy_reg_init[] = {
Francois Romieu236b8082008-05-30 16:11:48 +02002113 { 0x1f, 0x0001 },
2114 { 0x10, 0xf41b },
2115 { 0x1f, 0x0000 }
2116 };
2117
françois romieu4da19632011-01-03 15:07:55 +00002118 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
Francois Romieu236b8082008-05-30 16:11:48 +02002119}
2120
françois romieu4da19632011-01-03 15:07:55 +00002121static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
Francois Romieu867763c2007-08-17 18:21:58 +02002122{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002123 static const struct phy_reg phy_reg_init[] = {
Francois Romieu867763c2007-08-17 18:21:58 +02002124 { 0x1f, 0x0000 },
2125 { 0x1d, 0x0f00 },
2126 { 0x1f, 0x0002 },
2127 { 0x0c, 0x1ec8 },
2128 { 0x1f, 0x0000 }
2129 };
2130
françois romieu4da19632011-01-03 15:07:55 +00002131 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
Francois Romieu867763c2007-08-17 18:21:58 +02002132}
2133
françois romieu4da19632011-01-03 15:07:55 +00002134static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
Francois Romieuef3386f2008-06-29 12:24:30 +02002135{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002136 static const struct phy_reg phy_reg_init[] = {
Francois Romieuef3386f2008-06-29 12:24:30 +02002137 { 0x1f, 0x0001 },
2138 { 0x1d, 0x3d98 },
2139 { 0x1f, 0x0000 }
2140 };
2141
françois romieu4da19632011-01-03 15:07:55 +00002142 rtl_writephy(tp, 0x1f, 0x0000);
2143 rtl_patchphy(tp, 0x14, 1 << 5);
2144 rtl_patchphy(tp, 0x0d, 1 << 5);
Francois Romieuef3386f2008-06-29 12:24:30 +02002145
françois romieu4da19632011-01-03 15:07:55 +00002146 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
Francois Romieuef3386f2008-06-29 12:24:30 +02002147}
2148
françois romieu4da19632011-01-03 15:07:55 +00002149static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
Francois Romieu867763c2007-08-17 18:21:58 +02002150{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002151 static const struct phy_reg phy_reg_init[] = {
Francois Romieua3f80672007-10-18 14:35:11 +02002152 { 0x1f, 0x0001 },
2153 { 0x12, 0x2300 },
Francois Romieu867763c2007-08-17 18:21:58 +02002154 { 0x1f, 0x0002 },
2155 { 0x00, 0x88d4 },
2156 { 0x01, 0x82b1 },
2157 { 0x03, 0x7002 },
2158 { 0x08, 0x9e30 },
2159 { 0x09, 0x01f0 },
2160 { 0x0a, 0x5500 },
2161 { 0x0c, 0x00c8 },
2162 { 0x1f, 0x0003 },
2163 { 0x12, 0xc096 },
2164 { 0x16, 0x000a },
Francois Romieuf50d4272008-05-30 16:07:07 +02002165 { 0x1f, 0x0000 },
2166 { 0x1f, 0x0000 },
2167 { 0x09, 0x2000 },
2168 { 0x09, 0x0000 }
Francois Romieu867763c2007-08-17 18:21:58 +02002169 };
2170
françois romieu4da19632011-01-03 15:07:55 +00002171 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
Francois Romieuf50d4272008-05-30 16:07:07 +02002172
françois romieu4da19632011-01-03 15:07:55 +00002173 rtl_patchphy(tp, 0x14, 1 << 5);
2174 rtl_patchphy(tp, 0x0d, 1 << 5);
2175 rtl_writephy(tp, 0x1f, 0x0000);
Francois Romieu867763c2007-08-17 18:21:58 +02002176}
2177
françois romieu4da19632011-01-03 15:07:55 +00002178static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
Francois Romieu7da97ec2007-10-18 15:20:43 +02002179{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002180 static const struct phy_reg phy_reg_init[] = {
Francois Romieuf50d4272008-05-30 16:07:07 +02002181 { 0x1f, 0x0001 },
Francois Romieu7da97ec2007-10-18 15:20:43 +02002182 { 0x12, 0x2300 },
Francois Romieuf50d4272008-05-30 16:07:07 +02002183 { 0x03, 0x802f },
2184 { 0x02, 0x4f02 },
2185 { 0x01, 0x0409 },
2186 { 0x00, 0xf099 },
2187 { 0x04, 0x9800 },
2188 { 0x04, 0x9000 },
2189 { 0x1d, 0x3d98 },
Francois Romieu7da97ec2007-10-18 15:20:43 +02002190 { 0x1f, 0x0002 },
2191 { 0x0c, 0x7eb8 },
Francois Romieuf50d4272008-05-30 16:07:07 +02002192 { 0x06, 0x0761 },
2193 { 0x1f, 0x0003 },
2194 { 0x16, 0x0f0a },
Francois Romieu7da97ec2007-10-18 15:20:43 +02002195 { 0x1f, 0x0000 }
2196 };
2197
françois romieu4da19632011-01-03 15:07:55 +00002198 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
Francois Romieuf50d4272008-05-30 16:07:07 +02002199
françois romieu4da19632011-01-03 15:07:55 +00002200 rtl_patchphy(tp, 0x16, 1 << 0);
2201 rtl_patchphy(tp, 0x14, 1 << 5);
2202 rtl_patchphy(tp, 0x0d, 1 << 5);
2203 rtl_writephy(tp, 0x1f, 0x0000);
Francois Romieu7da97ec2007-10-18 15:20:43 +02002204}
2205
françois romieu4da19632011-01-03 15:07:55 +00002206static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
Francois Romieu197ff762008-06-28 13:16:02 +02002207{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002208 static const struct phy_reg phy_reg_init[] = {
Francois Romieu197ff762008-06-28 13:16:02 +02002209 { 0x1f, 0x0001 },
2210 { 0x12, 0x2300 },
2211 { 0x1d, 0x3d98 },
2212 { 0x1f, 0x0002 },
2213 { 0x0c, 0x7eb8 },
2214 { 0x06, 0x5461 },
2215 { 0x1f, 0x0003 },
2216 { 0x16, 0x0f0a },
2217 { 0x1f, 0x0000 }
2218 };
2219
françois romieu4da19632011-01-03 15:07:55 +00002220 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
Francois Romieu197ff762008-06-28 13:16:02 +02002221
françois romieu4da19632011-01-03 15:07:55 +00002222 rtl_patchphy(tp, 0x16, 1 << 0);
2223 rtl_patchphy(tp, 0x14, 1 << 5);
2224 rtl_patchphy(tp, 0x0d, 1 << 5);
2225 rtl_writephy(tp, 0x1f, 0x0000);
Francois Romieu197ff762008-06-28 13:16:02 +02002226}
2227
françois romieu4da19632011-01-03 15:07:55 +00002228static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
Francois Romieu6fb07052008-06-29 11:54:28 +02002229{
françois romieu4da19632011-01-03 15:07:55 +00002230 rtl8168c_3_hw_phy_config(tp);
Francois Romieu6fb07052008-06-29 11:54:28 +02002231}
2232
françois romieubca03d52011-01-03 15:07:31 +00002233static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
Francois Romieu5b538df2008-07-20 16:22:45 +02002234{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002235 static const struct phy_reg phy_reg_init_0[] = {
françois romieubca03d52011-01-03 15:07:31 +00002236 /* Channel Estimation */
Francois Romieu5b538df2008-07-20 16:22:45 +02002237 { 0x1f, 0x0001 },
françois romieudaf9df62009-10-07 12:44:20 +00002238 { 0x06, 0x4064 },
2239 { 0x07, 0x2863 },
2240 { 0x08, 0x059c },
2241 { 0x09, 0x26b4 },
2242 { 0x0a, 0x6a19 },
2243 { 0x0b, 0xdcc8 },
2244 { 0x10, 0xf06d },
2245 { 0x14, 0x7f68 },
2246 { 0x18, 0x7fd9 },
2247 { 0x1c, 0xf0ff },
2248 { 0x1d, 0x3d9c },
Francois Romieu5b538df2008-07-20 16:22:45 +02002249 { 0x1f, 0x0003 },
françois romieudaf9df62009-10-07 12:44:20 +00002250 { 0x12, 0xf49f },
2251 { 0x13, 0x070b },
2252 { 0x1a, 0x05ad },
françois romieubca03d52011-01-03 15:07:31 +00002253 { 0x14, 0x94c0 },
2254
2255 /*
2256 * Tx Error Issue
Francois Romieucecb5fd2011-04-01 10:21:07 +02002257 * Enhance line driver power
françois romieubca03d52011-01-03 15:07:31 +00002258 */
Francois Romieu5b538df2008-07-20 16:22:45 +02002259 { 0x1f, 0x0002 },
françois romieudaf9df62009-10-07 12:44:20 +00002260 { 0x06, 0x5561 },
Francois Romieu5b538df2008-07-20 16:22:45 +02002261 { 0x1f, 0x0005 },
françois romieudaf9df62009-10-07 12:44:20 +00002262 { 0x05, 0x8332 },
françois romieubca03d52011-01-03 15:07:31 +00002263 { 0x06, 0x5561 },
2264
2265 /*
2266 * Can not link to 1Gbps with bad cable
2267 * Decrease SNR threshold form 21.07dB to 19.04dB
2268 */
2269 { 0x1f, 0x0001 },
2270 { 0x17, 0x0cc0 },
françois romieudaf9df62009-10-07 12:44:20 +00002271
2272 { 0x1f, 0x0000 },
françois romieubca03d52011-01-03 15:07:31 +00002273 { 0x0d, 0xf880 }
Francois Romieu5b538df2008-07-20 16:22:45 +02002274 };
françois romieubca03d52011-01-03 15:07:31 +00002275 void __iomem *ioaddr = tp->mmio_addr;
Francois Romieu5b538df2008-07-20 16:22:45 +02002276
françois romieu4da19632011-01-03 15:07:55 +00002277 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
Francois Romieu5b538df2008-07-20 16:22:45 +02002278
françois romieubca03d52011-01-03 15:07:31 +00002279 /*
2280 * Rx Error Issue
2281 * Fine Tune Switching regulator parameter
2282 */
françois romieu4da19632011-01-03 15:07:55 +00002283 rtl_writephy(tp, 0x1f, 0x0002);
2284 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2285 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
françois romieudaf9df62009-10-07 12:44:20 +00002286
françois romieudaf9df62009-10-07 12:44:20 +00002287 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002288 static const struct phy_reg phy_reg_init[] = {
françois romieudaf9df62009-10-07 12:44:20 +00002289 { 0x1f, 0x0002 },
2290 { 0x05, 0x669a },
Francois Romieu5b538df2008-07-20 16:22:45 +02002291 { 0x1f, 0x0005 },
françois romieudaf9df62009-10-07 12:44:20 +00002292 { 0x05, 0x8330 },
2293 { 0x06, 0x669a },
2294 { 0x1f, 0x0002 }
2295 };
2296 int val;
2297
françois romieu4da19632011-01-03 15:07:55 +00002298 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
françois romieudaf9df62009-10-07 12:44:20 +00002299
françois romieu4da19632011-01-03 15:07:55 +00002300 val = rtl_readphy(tp, 0x0d);
françois romieudaf9df62009-10-07 12:44:20 +00002301
2302 if ((val & 0x00ff) != 0x006c) {
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002303 static const u32 set[] = {
françois romieudaf9df62009-10-07 12:44:20 +00002304 0x0065, 0x0066, 0x0067, 0x0068,
2305 0x0069, 0x006a, 0x006b, 0x006c
2306 };
2307 int i;
2308
françois romieu4da19632011-01-03 15:07:55 +00002309 rtl_writephy(tp, 0x1f, 0x0002);
françois romieudaf9df62009-10-07 12:44:20 +00002310
2311 val &= 0xff00;
2312 for (i = 0; i < ARRAY_SIZE(set); i++)
françois romieu4da19632011-01-03 15:07:55 +00002313 rtl_writephy(tp, 0x0d, val | set[i]);
françois romieudaf9df62009-10-07 12:44:20 +00002314 }
2315 } else {
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002316 static const struct phy_reg phy_reg_init[] = {
françois romieudaf9df62009-10-07 12:44:20 +00002317 { 0x1f, 0x0002 },
2318 { 0x05, 0x6662 },
Francois Romieu5b538df2008-07-20 16:22:45 +02002319 { 0x1f, 0x0005 },
françois romieudaf9df62009-10-07 12:44:20 +00002320 { 0x05, 0x8330 },
2321 { 0x06, 0x6662 }
Francois Romieu5b538df2008-07-20 16:22:45 +02002322 };
2323
françois romieu4da19632011-01-03 15:07:55 +00002324 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
Francois Romieu5b538df2008-07-20 16:22:45 +02002325 }
2326
françois romieubca03d52011-01-03 15:07:31 +00002327 /* RSET couple improve */
françois romieu4da19632011-01-03 15:07:55 +00002328 rtl_writephy(tp, 0x1f, 0x0002);
2329 rtl_patchphy(tp, 0x0d, 0x0300);
2330 rtl_patchphy(tp, 0x0f, 0x0010);
françois romieudaf9df62009-10-07 12:44:20 +00002331
françois romieubca03d52011-01-03 15:07:31 +00002332 /* Fine tune PLL performance */
françois romieu4da19632011-01-03 15:07:55 +00002333 rtl_writephy(tp, 0x1f, 0x0002);
2334 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2335 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
françois romieudaf9df62009-10-07 12:44:20 +00002336
françois romieu4da19632011-01-03 15:07:55 +00002337 rtl_writephy(tp, 0x1f, 0x0005);
2338 rtl_writephy(tp, 0x05, 0x001b);
François Romieu953a12c2011-04-24 17:38:48 +02002339
2340 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
françois romieubca03d52011-01-03 15:07:31 +00002341
françois romieu4da19632011-01-03 15:07:55 +00002342 rtl_writephy(tp, 0x1f, 0x0000);
françois romieudaf9df62009-10-07 12:44:20 +00002343}
2344
françois romieubca03d52011-01-03 15:07:31 +00002345static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
françois romieudaf9df62009-10-07 12:44:20 +00002346{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002347 static const struct phy_reg phy_reg_init_0[] = {
françois romieubca03d52011-01-03 15:07:31 +00002348 /* Channel Estimation */
françois romieudaf9df62009-10-07 12:44:20 +00002349 { 0x1f, 0x0001 },
2350 { 0x06, 0x4064 },
2351 { 0x07, 0x2863 },
2352 { 0x08, 0x059c },
2353 { 0x09, 0x26b4 },
2354 { 0x0a, 0x6a19 },
2355 { 0x0b, 0xdcc8 },
2356 { 0x10, 0xf06d },
2357 { 0x14, 0x7f68 },
2358 { 0x18, 0x7fd9 },
2359 { 0x1c, 0xf0ff },
2360 { 0x1d, 0x3d9c },
2361 { 0x1f, 0x0003 },
2362 { 0x12, 0xf49f },
2363 { 0x13, 0x070b },
2364 { 0x1a, 0x05ad },
2365 { 0x14, 0x94c0 },
2366
françois romieubca03d52011-01-03 15:07:31 +00002367 /*
2368 * Tx Error Issue
Francois Romieucecb5fd2011-04-01 10:21:07 +02002369 * Enhance line driver power
françois romieubca03d52011-01-03 15:07:31 +00002370 */
françois romieudaf9df62009-10-07 12:44:20 +00002371 { 0x1f, 0x0002 },
2372 { 0x06, 0x5561 },
2373 { 0x1f, 0x0005 },
2374 { 0x05, 0x8332 },
françois romieubca03d52011-01-03 15:07:31 +00002375 { 0x06, 0x5561 },
2376
2377 /*
2378 * Can not link to 1Gbps with bad cable
2379 * Decrease SNR threshold form 21.07dB to 19.04dB
2380 */
2381 { 0x1f, 0x0001 },
2382 { 0x17, 0x0cc0 },
françois romieudaf9df62009-10-07 12:44:20 +00002383
2384 { 0x1f, 0x0000 },
françois romieubca03d52011-01-03 15:07:31 +00002385 { 0x0d, 0xf880 }
françois romieudaf9df62009-10-07 12:44:20 +00002386 };
françois romieubca03d52011-01-03 15:07:31 +00002387 void __iomem *ioaddr = tp->mmio_addr;
françois romieudaf9df62009-10-07 12:44:20 +00002388
françois romieu4da19632011-01-03 15:07:55 +00002389 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
françois romieudaf9df62009-10-07 12:44:20 +00002390
2391 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002392 static const struct phy_reg phy_reg_init[] = {
françois romieudaf9df62009-10-07 12:44:20 +00002393 { 0x1f, 0x0002 },
2394 { 0x05, 0x669a },
2395 { 0x1f, 0x0005 },
2396 { 0x05, 0x8330 },
2397 { 0x06, 0x669a },
2398
2399 { 0x1f, 0x0002 }
2400 };
2401 int val;
2402
françois romieu4da19632011-01-03 15:07:55 +00002403 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
françois romieudaf9df62009-10-07 12:44:20 +00002404
françois romieu4da19632011-01-03 15:07:55 +00002405 val = rtl_readphy(tp, 0x0d);
françois romieudaf9df62009-10-07 12:44:20 +00002406 if ((val & 0x00ff) != 0x006c) {
Joe Perchesb6bc7652010-12-21 02:16:08 -08002407 static const u32 set[] = {
françois romieudaf9df62009-10-07 12:44:20 +00002408 0x0065, 0x0066, 0x0067, 0x0068,
2409 0x0069, 0x006a, 0x006b, 0x006c
2410 };
2411 int i;
2412
françois romieu4da19632011-01-03 15:07:55 +00002413 rtl_writephy(tp, 0x1f, 0x0002);
françois romieudaf9df62009-10-07 12:44:20 +00002414
2415 val &= 0xff00;
2416 for (i = 0; i < ARRAY_SIZE(set); i++)
françois romieu4da19632011-01-03 15:07:55 +00002417 rtl_writephy(tp, 0x0d, val | set[i]);
françois romieudaf9df62009-10-07 12:44:20 +00002418 }
2419 } else {
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002420 static const struct phy_reg phy_reg_init[] = {
françois romieudaf9df62009-10-07 12:44:20 +00002421 { 0x1f, 0x0002 },
2422 { 0x05, 0x2642 },
2423 { 0x1f, 0x0005 },
2424 { 0x05, 0x8330 },
2425 { 0x06, 0x2642 }
2426 };
2427
françois romieu4da19632011-01-03 15:07:55 +00002428 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
françois romieudaf9df62009-10-07 12:44:20 +00002429 }
2430
françois romieubca03d52011-01-03 15:07:31 +00002431 /* Fine tune PLL performance */
françois romieu4da19632011-01-03 15:07:55 +00002432 rtl_writephy(tp, 0x1f, 0x0002);
2433 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2434 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
françois romieudaf9df62009-10-07 12:44:20 +00002435
françois romieubca03d52011-01-03 15:07:31 +00002436 /* Switching regulator Slew rate */
françois romieu4da19632011-01-03 15:07:55 +00002437 rtl_writephy(tp, 0x1f, 0x0002);
2438 rtl_patchphy(tp, 0x0f, 0x0017);
françois romieudaf9df62009-10-07 12:44:20 +00002439
françois romieu4da19632011-01-03 15:07:55 +00002440 rtl_writephy(tp, 0x1f, 0x0005);
2441 rtl_writephy(tp, 0x05, 0x001b);
François Romieu953a12c2011-04-24 17:38:48 +02002442
2443 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
françois romieubca03d52011-01-03 15:07:31 +00002444
françois romieu4da19632011-01-03 15:07:55 +00002445 rtl_writephy(tp, 0x1f, 0x0000);
françois romieudaf9df62009-10-07 12:44:20 +00002446}
2447
françois romieu4da19632011-01-03 15:07:55 +00002448static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
françois romieudaf9df62009-10-07 12:44:20 +00002449{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002450 static const struct phy_reg phy_reg_init[] = {
françois romieudaf9df62009-10-07 12:44:20 +00002451 { 0x1f, 0x0002 },
2452 { 0x10, 0x0008 },
2453 { 0x0d, 0x006c },
2454
2455 { 0x1f, 0x0000 },
2456 { 0x0d, 0xf880 },
2457
2458 { 0x1f, 0x0001 },
2459 { 0x17, 0x0cc0 },
2460
2461 { 0x1f, 0x0001 },
2462 { 0x0b, 0xa4d8 },
2463 { 0x09, 0x281c },
2464 { 0x07, 0x2883 },
2465 { 0x0a, 0x6b35 },
2466 { 0x1d, 0x3da4 },
2467 { 0x1c, 0xeffd },
2468 { 0x14, 0x7f52 },
2469 { 0x18, 0x7fc6 },
2470 { 0x08, 0x0601 },
2471 { 0x06, 0x4063 },
2472 { 0x10, 0xf074 },
2473 { 0x1f, 0x0003 },
2474 { 0x13, 0x0789 },
2475 { 0x12, 0xf4bd },
2476 { 0x1a, 0x04fd },
2477 { 0x14, 0x84b0 },
2478 { 0x1f, 0x0000 },
2479 { 0x00, 0x9200 },
2480
2481 { 0x1f, 0x0005 },
2482 { 0x01, 0x0340 },
2483 { 0x1f, 0x0001 },
2484 { 0x04, 0x4000 },
2485 { 0x03, 0x1d21 },
2486 { 0x02, 0x0c32 },
2487 { 0x01, 0x0200 },
2488 { 0x00, 0x5554 },
2489 { 0x04, 0x4800 },
2490 { 0x04, 0x4000 },
2491 { 0x04, 0xf000 },
2492 { 0x03, 0xdf01 },
2493 { 0x02, 0xdf20 },
2494 { 0x01, 0x101a },
2495 { 0x00, 0xa0ff },
2496 { 0x04, 0xf800 },
2497 { 0x04, 0xf000 },
2498 { 0x1f, 0x0000 },
2499
2500 { 0x1f, 0x0007 },
2501 { 0x1e, 0x0023 },
2502 { 0x16, 0x0000 },
2503 { 0x1f, 0x0000 }
2504 };
2505
françois romieu4da19632011-01-03 15:07:55 +00002506 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
Francois Romieu5b538df2008-07-20 16:22:45 +02002507}
2508
françois romieue6de30d2011-01-03 15:08:37 +00002509static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2510{
2511 static const struct phy_reg phy_reg_init[] = {
2512 { 0x1f, 0x0001 },
2513 { 0x17, 0x0cc0 },
2514
2515 { 0x1f, 0x0007 },
2516 { 0x1e, 0x002d },
2517 { 0x18, 0x0040 },
2518 { 0x1f, 0x0000 }
2519 };
2520
2521 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2522 rtl_patchphy(tp, 0x0d, 1 << 5);
2523}
2524
hayeswang01dc7fe2011-03-21 01:50:28 +00002525static void rtl8168e_hw_phy_config(struct rtl8169_private *tp)
2526{
2527 static const struct phy_reg phy_reg_init[] = {
2528 /* Enable Delay cap */
2529 { 0x1f, 0x0005 },
2530 { 0x05, 0x8b80 },
2531 { 0x06, 0xc896 },
2532 { 0x1f, 0x0000 },
2533
2534 /* Channel estimation fine tune */
2535 { 0x1f, 0x0001 },
2536 { 0x0b, 0x6c20 },
2537 { 0x07, 0x2872 },
2538 { 0x1c, 0xefff },
2539 { 0x1f, 0x0003 },
2540 { 0x14, 0x6420 },
2541 { 0x1f, 0x0000 },
2542
2543 /* Update PFM & 10M TX idle timer */
2544 { 0x1f, 0x0007 },
2545 { 0x1e, 0x002f },
2546 { 0x15, 0x1919 },
2547 { 0x1f, 0x0000 },
2548
2549 { 0x1f, 0x0007 },
2550 { 0x1e, 0x00ac },
2551 { 0x18, 0x0006 },
2552 { 0x1f, 0x0000 }
2553 };
2554
Francois Romieu15ecd032011-04-27 13:52:22 -07002555 rtl_apply_firmware(tp);
2556
hayeswang01dc7fe2011-03-21 01:50:28 +00002557 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2558
2559 /* DCO enable for 10M IDLE Power */
2560 rtl_writephy(tp, 0x1f, 0x0007);
2561 rtl_writephy(tp, 0x1e, 0x0023);
2562 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2563 rtl_writephy(tp, 0x1f, 0x0000);
2564
2565 /* For impedance matching */
2566 rtl_writephy(tp, 0x1f, 0x0002);
2567 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
Francois Romieucecb5fd2011-04-01 10:21:07 +02002568 rtl_writephy(tp, 0x1f, 0x0000);
hayeswang01dc7fe2011-03-21 01:50:28 +00002569
2570 /* PHY auto speed down */
2571 rtl_writephy(tp, 0x1f, 0x0007);
2572 rtl_writephy(tp, 0x1e, 0x002d);
2573 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2574 rtl_writephy(tp, 0x1f, 0x0000);
2575 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2576
2577 rtl_writephy(tp, 0x1f, 0x0005);
2578 rtl_writephy(tp, 0x05, 0x8b86);
2579 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2580 rtl_writephy(tp, 0x1f, 0x0000);
2581
2582 rtl_writephy(tp, 0x1f, 0x0005);
2583 rtl_writephy(tp, 0x05, 0x8b85);
2584 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2585 rtl_writephy(tp, 0x1f, 0x0007);
2586 rtl_writephy(tp, 0x1e, 0x0020);
2587 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2588 rtl_writephy(tp, 0x1f, 0x0006);
2589 rtl_writephy(tp, 0x00, 0x5a00);
2590 rtl_writephy(tp, 0x1f, 0x0000);
2591 rtl_writephy(tp, 0x0d, 0x0007);
2592 rtl_writephy(tp, 0x0e, 0x003c);
2593 rtl_writephy(tp, 0x0d, 0x4007);
2594 rtl_writephy(tp, 0x0e, 0x0000);
2595 rtl_writephy(tp, 0x0d, 0x0000);
2596}
2597
françois romieu4da19632011-01-03 15:07:55 +00002598static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
Francois Romieu2857ffb2008-08-02 21:08:49 +02002599{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08002600 static const struct phy_reg phy_reg_init[] = {
Francois Romieu2857ffb2008-08-02 21:08:49 +02002601 { 0x1f, 0x0003 },
2602 { 0x08, 0x441d },
2603 { 0x01, 0x9100 },
2604 { 0x1f, 0x0000 }
2605 };
2606
françois romieu4da19632011-01-03 15:07:55 +00002607 rtl_writephy(tp, 0x1f, 0x0000);
2608 rtl_patchphy(tp, 0x11, 1 << 12);
2609 rtl_patchphy(tp, 0x19, 1 << 13);
2610 rtl_patchphy(tp, 0x10, 1 << 15);
Francois Romieu2857ffb2008-08-02 21:08:49 +02002611
françois romieu4da19632011-01-03 15:07:55 +00002612 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
Francois Romieu2857ffb2008-08-02 21:08:49 +02002613}
2614
Hayes Wang5a5e4442011-02-22 17:26:21 +08002615static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2616{
2617 static const struct phy_reg phy_reg_init[] = {
2618 { 0x1f, 0x0005 },
2619 { 0x1a, 0x0000 },
2620 { 0x1f, 0x0000 },
2621
2622 { 0x1f, 0x0004 },
2623 { 0x1c, 0x0000 },
2624 { 0x1f, 0x0000 },
2625
2626 { 0x1f, 0x0001 },
2627 { 0x15, 0x7701 },
2628 { 0x1f, 0x0000 }
2629 };
2630
2631 /* Disable ALDPS before ram code */
2632 rtl_writephy(tp, 0x1f, 0x0000);
2633 rtl_writephy(tp, 0x18, 0x0310);
2634 msleep(100);
2635
François Romieu953a12c2011-04-24 17:38:48 +02002636 rtl_apply_firmware(tp);
Hayes Wang5a5e4442011-02-22 17:26:21 +08002637
2638 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2639}
2640
Francois Romieu5615d9f2007-08-17 17:50:46 +02002641static void rtl_hw_phy_config(struct net_device *dev)
2642{
2643 struct rtl8169_private *tp = netdev_priv(dev);
Francois Romieu5615d9f2007-08-17 17:50:46 +02002644
2645 rtl8169_print_mac_version(tp);
2646
2647 switch (tp->mac_version) {
2648 case RTL_GIGA_MAC_VER_01:
2649 break;
2650 case RTL_GIGA_MAC_VER_02:
2651 case RTL_GIGA_MAC_VER_03:
françois romieu4da19632011-01-03 15:07:55 +00002652 rtl8169s_hw_phy_config(tp);
Francois Romieu5615d9f2007-08-17 17:50:46 +02002653 break;
2654 case RTL_GIGA_MAC_VER_04:
françois romieu4da19632011-01-03 15:07:55 +00002655 rtl8169sb_hw_phy_config(tp);
Francois Romieu5615d9f2007-08-17 17:50:46 +02002656 break;
françois romieu2e9558562009-08-10 19:44:19 +00002657 case RTL_GIGA_MAC_VER_05:
françois romieu4da19632011-01-03 15:07:55 +00002658 rtl8169scd_hw_phy_config(tp);
françois romieu2e9558562009-08-10 19:44:19 +00002659 break;
françois romieu8c7006a2009-08-10 19:43:29 +00002660 case RTL_GIGA_MAC_VER_06:
françois romieu4da19632011-01-03 15:07:55 +00002661 rtl8169sce_hw_phy_config(tp);
françois romieu8c7006a2009-08-10 19:43:29 +00002662 break;
Francois Romieu2857ffb2008-08-02 21:08:49 +02002663 case RTL_GIGA_MAC_VER_07:
2664 case RTL_GIGA_MAC_VER_08:
2665 case RTL_GIGA_MAC_VER_09:
françois romieu4da19632011-01-03 15:07:55 +00002666 rtl8102e_hw_phy_config(tp);
Francois Romieu2857ffb2008-08-02 21:08:49 +02002667 break;
Francois Romieu236b8082008-05-30 16:11:48 +02002668 case RTL_GIGA_MAC_VER_11:
françois romieu4da19632011-01-03 15:07:55 +00002669 rtl8168bb_hw_phy_config(tp);
Francois Romieu236b8082008-05-30 16:11:48 +02002670 break;
2671 case RTL_GIGA_MAC_VER_12:
françois romieu4da19632011-01-03 15:07:55 +00002672 rtl8168bef_hw_phy_config(tp);
Francois Romieu236b8082008-05-30 16:11:48 +02002673 break;
2674 case RTL_GIGA_MAC_VER_17:
françois romieu4da19632011-01-03 15:07:55 +00002675 rtl8168bef_hw_phy_config(tp);
Francois Romieu236b8082008-05-30 16:11:48 +02002676 break;
Francois Romieu867763c2007-08-17 18:21:58 +02002677 case RTL_GIGA_MAC_VER_18:
françois romieu4da19632011-01-03 15:07:55 +00002678 rtl8168cp_1_hw_phy_config(tp);
Francois Romieu867763c2007-08-17 18:21:58 +02002679 break;
2680 case RTL_GIGA_MAC_VER_19:
françois romieu4da19632011-01-03 15:07:55 +00002681 rtl8168c_1_hw_phy_config(tp);
Francois Romieu867763c2007-08-17 18:21:58 +02002682 break;
Francois Romieu7da97ec2007-10-18 15:20:43 +02002683 case RTL_GIGA_MAC_VER_20:
françois romieu4da19632011-01-03 15:07:55 +00002684 rtl8168c_2_hw_phy_config(tp);
Francois Romieu7da97ec2007-10-18 15:20:43 +02002685 break;
Francois Romieu197ff762008-06-28 13:16:02 +02002686 case RTL_GIGA_MAC_VER_21:
françois romieu4da19632011-01-03 15:07:55 +00002687 rtl8168c_3_hw_phy_config(tp);
Francois Romieu197ff762008-06-28 13:16:02 +02002688 break;
Francois Romieu6fb07052008-06-29 11:54:28 +02002689 case RTL_GIGA_MAC_VER_22:
françois romieu4da19632011-01-03 15:07:55 +00002690 rtl8168c_4_hw_phy_config(tp);
Francois Romieu6fb07052008-06-29 11:54:28 +02002691 break;
Francois Romieuef3386f2008-06-29 12:24:30 +02002692 case RTL_GIGA_MAC_VER_23:
Francois Romieu7f3e3d32008-07-20 18:53:20 +02002693 case RTL_GIGA_MAC_VER_24:
françois romieu4da19632011-01-03 15:07:55 +00002694 rtl8168cp_2_hw_phy_config(tp);
Francois Romieuef3386f2008-06-29 12:24:30 +02002695 break;
Francois Romieu5b538df2008-07-20 16:22:45 +02002696 case RTL_GIGA_MAC_VER_25:
françois romieubca03d52011-01-03 15:07:31 +00002697 rtl8168d_1_hw_phy_config(tp);
françois romieudaf9df62009-10-07 12:44:20 +00002698 break;
2699 case RTL_GIGA_MAC_VER_26:
françois romieubca03d52011-01-03 15:07:31 +00002700 rtl8168d_2_hw_phy_config(tp);
françois romieudaf9df62009-10-07 12:44:20 +00002701 break;
2702 case RTL_GIGA_MAC_VER_27:
françois romieu4da19632011-01-03 15:07:55 +00002703 rtl8168d_3_hw_phy_config(tp);
Francois Romieu5b538df2008-07-20 16:22:45 +02002704 break;
françois romieue6de30d2011-01-03 15:08:37 +00002705 case RTL_GIGA_MAC_VER_28:
2706 rtl8168d_4_hw_phy_config(tp);
2707 break;
Hayes Wang5a5e4442011-02-22 17:26:21 +08002708 case RTL_GIGA_MAC_VER_29:
2709 case RTL_GIGA_MAC_VER_30:
2710 rtl8105e_hw_phy_config(tp);
2711 break;
Francois Romieucecb5fd2011-04-01 10:21:07 +02002712 case RTL_GIGA_MAC_VER_31:
2713 /* None. */
2714 break;
hayeswang01dc7fe2011-03-21 01:50:28 +00002715 case RTL_GIGA_MAC_VER_32:
hayeswang01dc7fe2011-03-21 01:50:28 +00002716 case RTL_GIGA_MAC_VER_33:
Francois Romieu15ecd032011-04-27 13:52:22 -07002717 rtl8168e_hw_phy_config(tp);
hayeswang01dc7fe2011-03-21 01:50:28 +00002718 break;
Francois Romieuef3386f2008-06-29 12:24:30 +02002719
Francois Romieu5615d9f2007-08-17 17:50:46 +02002720 default:
2721 break;
2722 }
2723}
2724
Linus Torvalds1da177e2005-04-16 15:20:36 -07002725static void rtl8169_phy_timer(unsigned long __opaque)
2726{
2727 struct net_device *dev = (struct net_device *)__opaque;
2728 struct rtl8169_private *tp = netdev_priv(dev);
2729 struct timer_list *timer = &tp->timer;
2730 void __iomem *ioaddr = tp->mmio_addr;
2731 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2732
Francois Romieubcf0bf92006-07-26 23:14:13 +02002733 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002734
Linus Torvalds1da177e2005-04-16 15:20:36 -07002735 spin_lock_irq(&tp->lock);
2736
françois romieu4da19632011-01-03 15:07:55 +00002737 if (tp->phy_reset_pending(tp)) {
Francois Romieu5b0384f2006-08-16 16:00:01 +02002738 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002739 * A busy loop could burn quite a few cycles on nowadays CPU.
2740 * Let's delay the execution of the timer for a few ticks.
2741 */
2742 timeout = HZ/10;
2743 goto out_mod_timer;
2744 }
2745
2746 if (tp->link_ok(ioaddr))
2747 goto out_unlock;
2748
Joe Perchesbf82c182010-02-09 11:49:50 +00002749 netif_warn(tp, link, dev, "PHY reset until link up\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002750
françois romieu4da19632011-01-03 15:07:55 +00002751 tp->phy_reset_enable(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002752
2753out_mod_timer:
2754 mod_timer(timer, jiffies + timeout);
2755out_unlock:
2756 spin_unlock_irq(&tp->lock);
2757}
2758
Linus Torvalds1da177e2005-04-16 15:20:36 -07002759#ifdef CONFIG_NET_POLL_CONTROLLER
2760/*
2761 * Polling 'interrupt' - used by things like netconsole to send skbs
2762 * without having to re-enable interrupts. It's not called while
2763 * the interrupt routine is executing.
2764 */
2765static void rtl8169_netpoll(struct net_device *dev)
2766{
2767 struct rtl8169_private *tp = netdev_priv(dev);
2768 struct pci_dev *pdev = tp->pci_dev;
2769
2770 disable_irq(pdev->irq);
David Howells7d12e782006-10-05 14:55:46 +01002771 rtl8169_interrupt(pdev->irq, dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002772 enable_irq(pdev->irq);
2773}
2774#endif
2775
2776static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2777 void __iomem *ioaddr)
2778{
2779 iounmap(ioaddr);
2780 pci_release_regions(pdev);
françois romieu87aeec72010-04-26 11:42:06 +00002781 pci_clear_mwi(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002782 pci_disable_device(pdev);
2783 free_netdev(dev);
2784}
2785
Francois Romieubf793292006-11-01 00:53:05 +01002786static void rtl8169_phy_reset(struct net_device *dev,
2787 struct rtl8169_private *tp)
2788{
Francois Romieu07d3f512007-02-21 22:40:46 +01002789 unsigned int i;
Francois Romieubf793292006-11-01 00:53:05 +01002790
françois romieu4da19632011-01-03 15:07:55 +00002791 tp->phy_reset_enable(tp);
Francois Romieubf793292006-11-01 00:53:05 +01002792 for (i = 0; i < 100; i++) {
françois romieu4da19632011-01-03 15:07:55 +00002793 if (!tp->phy_reset_pending(tp))
Francois Romieubf793292006-11-01 00:53:05 +01002794 return;
2795 msleep(1);
2796 }
Joe Perchesbf82c182010-02-09 11:49:50 +00002797 netif_err(tp, link, dev, "PHY reset failed\n");
Francois Romieubf793292006-11-01 00:53:05 +01002798}
2799
Francois Romieu4ff96fa2006-07-26 22:05:06 +02002800static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002801{
Francois Romieu4ff96fa2006-07-26 22:05:06 +02002802 void __iomem *ioaddr = tp->mmio_addr;
Francois Romieu4ff96fa2006-07-26 22:05:06 +02002803
Francois Romieu5615d9f2007-08-17 17:50:46 +02002804 rtl_hw_phy_config(dev);
Francois Romieu4ff96fa2006-07-26 22:05:06 +02002805
Marcus Sundberg773328942008-07-10 21:28:08 +02002806 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2807 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2808 RTL_W8(0x82, 0x01);
2809 }
Francois Romieu4ff96fa2006-07-26 22:05:06 +02002810
Francois Romieu6dccd162007-02-13 23:38:05 +01002811 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2812
2813 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2814 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
Francois Romieu4ff96fa2006-07-26 22:05:06 +02002815
Francois Romieubcf0bf92006-07-26 23:14:13 +02002816 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
Francois Romieu4ff96fa2006-07-26 22:05:06 +02002817 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2818 RTL_W8(0x82, 0x01);
2819 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
françois romieu4da19632011-01-03 15:07:55 +00002820 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
Francois Romieu4ff96fa2006-07-26 22:05:06 +02002821 }
2822
Francois Romieubf793292006-11-01 00:53:05 +01002823 rtl8169_phy_reset(dev, tp);
2824
Oliver Neukum54405cd2011-01-06 21:55:13 +01002825 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
Francois Romieucecb5fd2011-04-01 10:21:07 +02002826 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2827 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
2828 (tp->mii.supports_gmii ?
2829 ADVERTISED_1000baseT_Half |
2830 ADVERTISED_1000baseT_Full : 0));
Francois Romieu4ff96fa2006-07-26 22:05:06 +02002831
Joe Perchesbf82c182010-02-09 11:49:50 +00002832 if (RTL_R8(PHYstatus) & TBI_Enable)
2833 netif_info(tp, link, dev, "TBI auto-negotiating\n");
Francois Romieu4ff96fa2006-07-26 22:05:06 +02002834}
2835
Francois Romieu773d2022007-01-31 23:47:43 +01002836static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2837{
2838 void __iomem *ioaddr = tp->mmio_addr;
2839 u32 high;
2840 u32 low;
2841
2842 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2843 high = addr[4] | (addr[5] << 8);
2844
2845 spin_lock_irq(&tp->lock);
2846
2847 RTL_W8(Cfg9346, Cfg9346_Unlock);
françois romieu908ba2b2010-04-26 11:42:58 +00002848
Francois Romieu773d2022007-01-31 23:47:43 +01002849 RTL_W32(MAC4, high);
françois romieu908ba2b2010-04-26 11:42:58 +00002850 RTL_R32(MAC4);
2851
Francois Romieu78f1cd02010-03-27 19:35:46 -07002852 RTL_W32(MAC0, low);
françois romieu908ba2b2010-04-26 11:42:58 +00002853 RTL_R32(MAC0);
2854
Francois Romieu773d2022007-01-31 23:47:43 +01002855 RTL_W8(Cfg9346, Cfg9346_Lock);
2856
2857 spin_unlock_irq(&tp->lock);
2858}
2859
2860static int rtl_set_mac_address(struct net_device *dev, void *p)
2861{
2862 struct rtl8169_private *tp = netdev_priv(dev);
2863 struct sockaddr *addr = p;
2864
2865 if (!is_valid_ether_addr(addr->sa_data))
2866 return -EADDRNOTAVAIL;
2867
2868 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2869
2870 rtl_rar_set(tp, dev->dev_addr);
2871
2872 return 0;
2873}
2874
Francois Romieu5f787a12006-08-17 13:02:36 +02002875static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2876{
2877 struct rtl8169_private *tp = netdev_priv(dev);
2878 struct mii_ioctl_data *data = if_mii(ifr);
2879
Francois Romieu8b4ab282008-11-19 22:05:25 -08002880 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2881}
Francois Romieu5f787a12006-08-17 13:02:36 +02002882
Francois Romieucecb5fd2011-04-01 10:21:07 +02002883static int rtl_xmii_ioctl(struct rtl8169_private *tp,
2884 struct mii_ioctl_data *data, int cmd)
Francois Romieu8b4ab282008-11-19 22:05:25 -08002885{
Francois Romieu5f787a12006-08-17 13:02:36 +02002886 switch (cmd) {
2887 case SIOCGMIIPHY:
2888 data->phy_id = 32; /* Internal PHY */
2889 return 0;
2890
2891 case SIOCGMIIREG:
françois romieu4da19632011-01-03 15:07:55 +00002892 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
Francois Romieu5f787a12006-08-17 13:02:36 +02002893 return 0;
2894
2895 case SIOCSMIIREG:
françois romieu4da19632011-01-03 15:07:55 +00002896 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
Francois Romieu5f787a12006-08-17 13:02:36 +02002897 return 0;
2898 }
2899 return -EOPNOTSUPP;
2900}
2901
Francois Romieu8b4ab282008-11-19 22:05:25 -08002902static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2903{
2904 return -EOPNOTSUPP;
2905}
2906
Francois Romieu0e485152007-02-20 00:00:26 +01002907static const struct rtl_cfg_info {
2908 void (*hw_start)(struct net_device *);
2909 unsigned int region;
2910 unsigned int align;
2911 u16 intr_event;
2912 u16 napi_event;
Francois Romieuccdffb92008-07-26 14:26:06 +02002913 unsigned features;
Jean Delvaref21b75e2009-05-26 20:54:48 -07002914 u8 default_ver;
Francois Romieu0e485152007-02-20 00:00:26 +01002915} rtl_cfg_infos [] = {
2916 [RTL_CFG_0] = {
2917 .hw_start = rtl_hw_start_8169,
2918 .region = 1,
Francois Romieue9f63f32007-02-28 23:16:57 +01002919 .align = 0,
Francois Romieu0e485152007-02-20 00:00:26 +01002920 .intr_event = SYSErr | LinkChg | RxOverflow |
2921 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
Francois Romieufbac58f2007-10-04 22:51:38 +02002922 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
Jean Delvaref21b75e2009-05-26 20:54:48 -07002923 .features = RTL_FEATURE_GMII,
2924 .default_ver = RTL_GIGA_MAC_VER_01,
Francois Romieu0e485152007-02-20 00:00:26 +01002925 },
2926 [RTL_CFG_1] = {
2927 .hw_start = rtl_hw_start_8168,
2928 .region = 2,
2929 .align = 8,
françois romieu53f57352010-11-08 13:23:05 +00002930 .intr_event = SYSErr | LinkChg | RxOverflow |
Francois Romieu0e485152007-02-20 00:00:26 +01002931 TxErr | TxOK | RxOK | RxErr,
Francois Romieufbac58f2007-10-04 22:51:38 +02002932 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
Jean Delvaref21b75e2009-05-26 20:54:48 -07002933 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2934 .default_ver = RTL_GIGA_MAC_VER_11,
Francois Romieu0e485152007-02-20 00:00:26 +01002935 },
2936 [RTL_CFG_2] = {
2937 .hw_start = rtl_hw_start_8101,
2938 .region = 2,
2939 .align = 8,
2940 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2941 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
Francois Romieufbac58f2007-10-04 22:51:38 +02002942 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
Jean Delvaref21b75e2009-05-26 20:54:48 -07002943 .features = RTL_FEATURE_MSI,
2944 .default_ver = RTL_GIGA_MAC_VER_13,
Francois Romieu0e485152007-02-20 00:00:26 +01002945 }
2946};
2947
Francois Romieufbac58f2007-10-04 22:51:38 +02002948/* Cfg9346_Unlock assumed. */
2949static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2950 const struct rtl_cfg_info *cfg)
2951{
2952 unsigned msi = 0;
2953 u8 cfg2;
2954
2955 cfg2 = RTL_R8(Config2) & ~MSIEnable;
Francois Romieuccdffb92008-07-26 14:26:06 +02002956 if (cfg->features & RTL_FEATURE_MSI) {
Francois Romieufbac58f2007-10-04 22:51:38 +02002957 if (pci_enable_msi(pdev)) {
2958 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2959 } else {
2960 cfg2 |= MSIEnable;
2961 msi = RTL_FEATURE_MSI;
2962 }
2963 }
2964 RTL_W8(Config2, cfg2);
2965 return msi;
2966}
2967
2968static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2969{
2970 if (tp->features & RTL_FEATURE_MSI) {
2971 pci_disable_msi(pdev);
2972 tp->features &= ~RTL_FEATURE_MSI;
2973 }
2974}
2975
Francois Romieu8b4ab282008-11-19 22:05:25 -08002976static const struct net_device_ops rtl8169_netdev_ops = {
2977 .ndo_open = rtl8169_open,
2978 .ndo_stop = rtl8169_close,
2979 .ndo_get_stats = rtl8169_get_stats,
Stephen Hemminger00829822008-11-20 20:14:53 -08002980 .ndo_start_xmit = rtl8169_start_xmit,
Francois Romieu8b4ab282008-11-19 22:05:25 -08002981 .ndo_tx_timeout = rtl8169_tx_timeout,
2982 .ndo_validate_addr = eth_validate_addr,
2983 .ndo_change_mtu = rtl8169_change_mtu,
Michał Mirosław350fb322011-04-08 06:35:56 +00002984 .ndo_fix_features = rtl8169_fix_features,
2985 .ndo_set_features = rtl8169_set_features,
Francois Romieu8b4ab282008-11-19 22:05:25 -08002986 .ndo_set_mac_address = rtl_set_mac_address,
2987 .ndo_do_ioctl = rtl8169_ioctl,
2988 .ndo_set_multicast_list = rtl_set_rx_mode,
Francois Romieu8b4ab282008-11-19 22:05:25 -08002989#ifdef CONFIG_NET_POLL_CONTROLLER
2990 .ndo_poll_controller = rtl8169_netpoll,
2991#endif
2992
2993};
2994
françois romieuc0e45c12011-01-03 15:08:04 +00002995static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
2996{
2997 struct mdio_ops *ops = &tp->mdio_ops;
2998
2999 switch (tp->mac_version) {
3000 case RTL_GIGA_MAC_VER_27:
3001 ops->write = r8168dp_1_mdio_write;
3002 ops->read = r8168dp_1_mdio_read;
3003 break;
françois romieue6de30d2011-01-03 15:08:37 +00003004 case RTL_GIGA_MAC_VER_28:
hayeswang4804b3b2011-03-21 01:50:29 +00003005 case RTL_GIGA_MAC_VER_31:
françois romieue6de30d2011-01-03 15:08:37 +00003006 ops->write = r8168dp_2_mdio_write;
3007 ops->read = r8168dp_2_mdio_read;
3008 break;
françois romieuc0e45c12011-01-03 15:08:04 +00003009 default:
3010 ops->write = r8169_mdio_write;
3011 ops->read = r8169_mdio_read;
3012 break;
3013 }
3014}
3015
françois romieu065c27c2011-01-03 15:08:12 +00003016static void r810x_phy_power_down(struct rtl8169_private *tp)
3017{
3018 rtl_writephy(tp, 0x1f, 0x0000);
3019 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3020}
3021
3022static void r810x_phy_power_up(struct rtl8169_private *tp)
3023{
3024 rtl_writephy(tp, 0x1f, 0x0000);
3025 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3026}
3027
3028static void r810x_pll_power_down(struct rtl8169_private *tp)
3029{
3030 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3031 rtl_writephy(tp, 0x1f, 0x0000);
3032 rtl_writephy(tp, MII_BMCR, 0x0000);
3033 return;
3034 }
3035
3036 r810x_phy_power_down(tp);
3037}
3038
3039static void r810x_pll_power_up(struct rtl8169_private *tp)
3040{
3041 r810x_phy_power_up(tp);
3042}
3043
3044static void r8168_phy_power_up(struct rtl8169_private *tp)
3045{
3046 rtl_writephy(tp, 0x1f, 0x0000);
hayeswang01dc7fe2011-03-21 01:50:28 +00003047 switch (tp->mac_version) {
3048 case RTL_GIGA_MAC_VER_11:
3049 case RTL_GIGA_MAC_VER_12:
3050 case RTL_GIGA_MAC_VER_17:
3051 case RTL_GIGA_MAC_VER_18:
3052 case RTL_GIGA_MAC_VER_19:
3053 case RTL_GIGA_MAC_VER_20:
3054 case RTL_GIGA_MAC_VER_21:
3055 case RTL_GIGA_MAC_VER_22:
3056 case RTL_GIGA_MAC_VER_23:
3057 case RTL_GIGA_MAC_VER_24:
3058 case RTL_GIGA_MAC_VER_25:
3059 case RTL_GIGA_MAC_VER_26:
3060 case RTL_GIGA_MAC_VER_27:
3061 case RTL_GIGA_MAC_VER_28:
3062 case RTL_GIGA_MAC_VER_31:
3063 rtl_writephy(tp, 0x0e, 0x0000);
3064 break;
3065 default:
3066 break;
3067 }
françois romieu065c27c2011-01-03 15:08:12 +00003068 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3069}
3070
3071static void r8168_phy_power_down(struct rtl8169_private *tp)
3072{
3073 rtl_writephy(tp, 0x1f, 0x0000);
hayeswang01dc7fe2011-03-21 01:50:28 +00003074 switch (tp->mac_version) {
3075 case RTL_GIGA_MAC_VER_32:
3076 case RTL_GIGA_MAC_VER_33:
3077 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3078 break;
3079
3080 case RTL_GIGA_MAC_VER_11:
3081 case RTL_GIGA_MAC_VER_12:
3082 case RTL_GIGA_MAC_VER_17:
3083 case RTL_GIGA_MAC_VER_18:
3084 case RTL_GIGA_MAC_VER_19:
3085 case RTL_GIGA_MAC_VER_20:
3086 case RTL_GIGA_MAC_VER_21:
3087 case RTL_GIGA_MAC_VER_22:
3088 case RTL_GIGA_MAC_VER_23:
3089 case RTL_GIGA_MAC_VER_24:
3090 case RTL_GIGA_MAC_VER_25:
3091 case RTL_GIGA_MAC_VER_26:
3092 case RTL_GIGA_MAC_VER_27:
3093 case RTL_GIGA_MAC_VER_28:
3094 case RTL_GIGA_MAC_VER_31:
3095 rtl_writephy(tp, 0x0e, 0x0200);
3096 default:
3097 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3098 break;
3099 }
françois romieu065c27c2011-01-03 15:08:12 +00003100}
3101
3102static void r8168_pll_power_down(struct rtl8169_private *tp)
3103{
3104 void __iomem *ioaddr = tp->mmio_addr;
3105
Francois Romieucecb5fd2011-04-01 10:21:07 +02003106 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3107 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3108 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
hayeswang4804b3b2011-03-21 01:50:29 +00003109 r8168dp_check_dash(tp)) {
françois romieu065c27c2011-01-03 15:08:12 +00003110 return;
Hayes Wang5d2e1952011-02-22 17:26:22 +08003111 }
françois romieu065c27c2011-01-03 15:08:12 +00003112
Francois Romieucecb5fd2011-04-01 10:21:07 +02003113 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3114 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
françois romieu065c27c2011-01-03 15:08:12 +00003115 (RTL_R16(CPlusCmd) & ASF)) {
3116 return;
3117 }
3118
hayeswang01dc7fe2011-03-21 01:50:28 +00003119 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3120 tp->mac_version == RTL_GIGA_MAC_VER_33)
3121 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3122
françois romieu065c27c2011-01-03 15:08:12 +00003123 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3124 rtl_writephy(tp, 0x1f, 0x0000);
3125 rtl_writephy(tp, MII_BMCR, 0x0000);
3126
3127 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3128 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3129 return;
3130 }
3131
3132 r8168_phy_power_down(tp);
3133
3134 switch (tp->mac_version) {
3135 case RTL_GIGA_MAC_VER_25:
3136 case RTL_GIGA_MAC_VER_26:
Hayes Wang5d2e1952011-02-22 17:26:22 +08003137 case RTL_GIGA_MAC_VER_27:
3138 case RTL_GIGA_MAC_VER_28:
hayeswang4804b3b2011-03-21 01:50:29 +00003139 case RTL_GIGA_MAC_VER_31:
hayeswang01dc7fe2011-03-21 01:50:28 +00003140 case RTL_GIGA_MAC_VER_32:
3141 case RTL_GIGA_MAC_VER_33:
françois romieu065c27c2011-01-03 15:08:12 +00003142 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3143 break;
3144 }
3145}
3146
3147static void r8168_pll_power_up(struct rtl8169_private *tp)
3148{
3149 void __iomem *ioaddr = tp->mmio_addr;
3150
Francois Romieucecb5fd2011-04-01 10:21:07 +02003151 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3152 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3153 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
hayeswang4804b3b2011-03-21 01:50:29 +00003154 r8168dp_check_dash(tp)) {
françois romieu065c27c2011-01-03 15:08:12 +00003155 return;
Hayes Wang5d2e1952011-02-22 17:26:22 +08003156 }
françois romieu065c27c2011-01-03 15:08:12 +00003157
3158 switch (tp->mac_version) {
3159 case RTL_GIGA_MAC_VER_25:
3160 case RTL_GIGA_MAC_VER_26:
Hayes Wang5d2e1952011-02-22 17:26:22 +08003161 case RTL_GIGA_MAC_VER_27:
3162 case RTL_GIGA_MAC_VER_28:
hayeswang4804b3b2011-03-21 01:50:29 +00003163 case RTL_GIGA_MAC_VER_31:
hayeswang01dc7fe2011-03-21 01:50:28 +00003164 case RTL_GIGA_MAC_VER_32:
3165 case RTL_GIGA_MAC_VER_33:
françois romieu065c27c2011-01-03 15:08:12 +00003166 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3167 break;
3168 }
3169
3170 r8168_phy_power_up(tp);
3171}
3172
3173static void rtl_pll_power_op(struct rtl8169_private *tp,
3174 void (*op)(struct rtl8169_private *))
3175{
3176 if (op)
3177 op(tp);
3178}
3179
3180static void rtl_pll_power_down(struct rtl8169_private *tp)
3181{
3182 rtl_pll_power_op(tp, tp->pll_power_ops.down);
3183}
3184
3185static void rtl_pll_power_up(struct rtl8169_private *tp)
3186{
3187 rtl_pll_power_op(tp, tp->pll_power_ops.up);
3188}
3189
3190static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3191{
3192 struct pll_power_ops *ops = &tp->pll_power_ops;
3193
3194 switch (tp->mac_version) {
3195 case RTL_GIGA_MAC_VER_07:
3196 case RTL_GIGA_MAC_VER_08:
3197 case RTL_GIGA_MAC_VER_09:
3198 case RTL_GIGA_MAC_VER_10:
3199 case RTL_GIGA_MAC_VER_16:
Hayes Wang5a5e4442011-02-22 17:26:21 +08003200 case RTL_GIGA_MAC_VER_29:
3201 case RTL_GIGA_MAC_VER_30:
françois romieu065c27c2011-01-03 15:08:12 +00003202 ops->down = r810x_pll_power_down;
3203 ops->up = r810x_pll_power_up;
3204 break;
3205
3206 case RTL_GIGA_MAC_VER_11:
3207 case RTL_GIGA_MAC_VER_12:
3208 case RTL_GIGA_MAC_VER_17:
3209 case RTL_GIGA_MAC_VER_18:
3210 case RTL_GIGA_MAC_VER_19:
3211 case RTL_GIGA_MAC_VER_20:
3212 case RTL_GIGA_MAC_VER_21:
3213 case RTL_GIGA_MAC_VER_22:
3214 case RTL_GIGA_MAC_VER_23:
3215 case RTL_GIGA_MAC_VER_24:
3216 case RTL_GIGA_MAC_VER_25:
3217 case RTL_GIGA_MAC_VER_26:
3218 case RTL_GIGA_MAC_VER_27:
françois romieue6de30d2011-01-03 15:08:37 +00003219 case RTL_GIGA_MAC_VER_28:
hayeswang4804b3b2011-03-21 01:50:29 +00003220 case RTL_GIGA_MAC_VER_31:
hayeswang01dc7fe2011-03-21 01:50:28 +00003221 case RTL_GIGA_MAC_VER_32:
3222 case RTL_GIGA_MAC_VER_33:
françois romieu065c27c2011-01-03 15:08:12 +00003223 ops->down = r8168_pll_power_down;
3224 ops->up = r8168_pll_power_up;
3225 break;
3226
3227 default:
3228 ops->down = NULL;
3229 ops->up = NULL;
3230 break;
3231 }
3232}
3233
Francois Romieu6f43adc2011-04-29 15:05:51 +02003234static void rtl_hw_reset(struct rtl8169_private *tp)
3235{
3236 void __iomem *ioaddr = tp->mmio_addr;
3237 int i;
3238
3239 /* Soft reset the chip. */
3240 RTL_W8(ChipCmd, CmdReset);
3241
3242 /* Check that the chip has finished the reset. */
3243 for (i = 0; i < 100; i++) {
3244 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3245 break;
3246 msleep_interruptible(1);
3247 }
3248}
3249
Francois Romieu4ff96fa2006-07-26 22:05:06 +02003250static int __devinit
3251rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3252{
Francois Romieu0e485152007-02-20 00:00:26 +01003253 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3254 const unsigned int region = cfg->region;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003255 struct rtl8169_private *tp;
Francois Romieuccdffb92008-07-26 14:26:06 +02003256 struct mii_if_info *mii;
Francois Romieu4ff96fa2006-07-26 22:05:06 +02003257 struct net_device *dev;
3258 void __iomem *ioaddr;
Francois Romieu2b7b4312011-04-18 22:53:24 -07003259 int chipset, i;
Francois Romieu07d3f512007-02-21 22:40:46 +01003260 int rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003261
Francois Romieu4ff96fa2006-07-26 22:05:06 +02003262 if (netif_msg_drv(&debug)) {
3263 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3264 MODULENAME, RTL8169_VERSION);
3265 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003266
Linus Torvalds1da177e2005-04-16 15:20:36 -07003267 dev = alloc_etherdev(sizeof (*tp));
Francois Romieu4ff96fa2006-07-26 22:05:06 +02003268 if (!dev) {
Stephen Hemmingerb57b7e52005-05-27 21:11:52 +02003269 if (netif_msg_drv(&debug))
Jeff Garzik9b91cf92006-06-27 11:39:50 -04003270 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
Francois Romieu4ff96fa2006-07-26 22:05:06 +02003271 rc = -ENOMEM;
3272 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003273 }
3274
Linus Torvalds1da177e2005-04-16 15:20:36 -07003275 SET_NETDEV_DEV(dev, &pdev->dev);
Francois Romieu8b4ab282008-11-19 22:05:25 -08003276 dev->netdev_ops = &rtl8169_netdev_ops;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003277 tp = netdev_priv(dev);
David Howellsc4028952006-11-22 14:57:56 +00003278 tp->dev = dev;
Ivan Vecera21e197f2008-04-17 22:48:41 +02003279 tp->pci_dev = pdev;
Stephen Hemmingerb57b7e52005-05-27 21:11:52 +02003280 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003281
Francois Romieuccdffb92008-07-26 14:26:06 +02003282 mii = &tp->mii;
3283 mii->dev = dev;
3284 mii->mdio_read = rtl_mdio_read;
3285 mii->mdio_write = rtl_mdio_write;
3286 mii->phy_id_mask = 0x1f;
3287 mii->reg_num_mask = 0x1f;
3288 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3289
Stanislaw Gruszkaba04c7c2011-02-22 02:00:11 +00003290 /* disable ASPM completely as that cause random device stop working
3291 * problems as well as full system hangs for some PCIe devices users */
3292 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3293 PCIE_LINK_STATE_CLKPM);
3294
Linus Torvalds1da177e2005-04-16 15:20:36 -07003295 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3296 rc = pci_enable_device(pdev);
Stephen Hemmingerb57b7e52005-05-27 21:11:52 +02003297 if (rc < 0) {
Joe Perchesbf82c182010-02-09 11:49:50 +00003298 netif_err(tp, probe, dev, "enable failure\n");
Francois Romieu4ff96fa2006-07-26 22:05:06 +02003299 goto err_out_free_dev_1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003300 }
3301
françois romieu87aeec72010-04-26 11:42:06 +00003302 if (pci_set_mwi(pdev) < 0)
3303 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07003304
Linus Torvalds1da177e2005-04-16 15:20:36 -07003305 /* make sure PCI base addr 1 is MMIO */
Francois Romieubcf0bf92006-07-26 23:14:13 +02003306 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
Joe Perchesbf82c182010-02-09 11:49:50 +00003307 netif_err(tp, probe, dev,
3308 "region #%d not an MMIO resource, aborting\n",
3309 region);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003310 rc = -ENODEV;
françois romieu87aeec72010-04-26 11:42:06 +00003311 goto err_out_mwi_2;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003312 }
Francois Romieu4ff96fa2006-07-26 22:05:06 +02003313
Linus Torvalds1da177e2005-04-16 15:20:36 -07003314 /* check for weird/broken PCI region reporting */
Francois Romieubcf0bf92006-07-26 23:14:13 +02003315 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
Joe Perchesbf82c182010-02-09 11:49:50 +00003316 netif_err(tp, probe, dev,
3317 "Invalid PCI region size(s), aborting\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07003318 rc = -ENODEV;
françois romieu87aeec72010-04-26 11:42:06 +00003319 goto err_out_mwi_2;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003320 }
3321
3322 rc = pci_request_regions(pdev, MODULENAME);
Stephen Hemmingerb57b7e52005-05-27 21:11:52 +02003323 if (rc < 0) {
Joe Perchesbf82c182010-02-09 11:49:50 +00003324 netif_err(tp, probe, dev, "could not request regions\n");
françois romieu87aeec72010-04-26 11:42:06 +00003325 goto err_out_mwi_2;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003326 }
3327
Hayes Wangd24e9aa2011-02-22 17:26:19 +08003328 tp->cp_cmd = RxChkSum;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003329
3330 if ((sizeof(dma_addr_t) > 4) &&
David S. Miller4300e8c2010-03-26 10:23:30 -07003331 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003332 tp->cp_cmd |= PCIDAC;
3333 dev->features |= NETIF_F_HIGHDMA;
3334 } else {
Yang Hongyang284901a2009-04-06 19:01:15 -07003335 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
Linus Torvalds1da177e2005-04-16 15:20:36 -07003336 if (rc < 0) {
Joe Perchesbf82c182010-02-09 11:49:50 +00003337 netif_err(tp, probe, dev, "DMA configuration failed\n");
françois romieu87aeec72010-04-26 11:42:06 +00003338 goto err_out_free_res_3;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003339 }
3340 }
3341
Linus Torvalds1da177e2005-04-16 15:20:36 -07003342 /* ioremap MMIO region */
Francois Romieubcf0bf92006-07-26 23:14:13 +02003343 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
Francois Romieu4ff96fa2006-07-26 22:05:06 +02003344 if (!ioaddr) {
Joe Perchesbf82c182010-02-09 11:49:50 +00003345 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07003346 rc = -EIO;
françois romieu87aeec72010-04-26 11:42:06 +00003347 goto err_out_free_res_3;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003348 }
Francois Romieu6f43adc2011-04-29 15:05:51 +02003349 tp->mmio_addr = ioaddr;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003350
David S. Miller4300e8c2010-03-26 10:23:30 -07003351 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3352 if (!tp->pcie_cap)
3353 netif_info(tp, probe, dev, "no PCI Express capability\n");
3354
Karsten Wiesed78ad8c2009-04-02 01:06:01 -07003355 RTL_W16(IntrMask, 0x0000);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003356
Francois Romieu6f43adc2011-04-29 15:05:51 +02003357 rtl_hw_reset(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003358
Karsten Wiesed78ad8c2009-04-02 01:06:01 -07003359 RTL_W16(IntrStatus, 0xffff);
3360
françois romieuca52efd2009-07-24 12:34:19 +00003361 pci_set_master(pdev);
3362
Linus Torvalds1da177e2005-04-16 15:20:36 -07003363 /* Identify chip attached to board */
Francois Romieu5d320a22011-05-08 17:47:36 +02003364 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003365
Francois Romieu7a8fc772011-03-01 17:18:33 +01003366 /*
3367 * Pretend we are using VLANs; This bypasses a nasty bug where
3368 * Interrupts stop flowing on high load on 8110SCd controllers.
3369 */
3370 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3371 tp->cp_cmd |= RxVlan;
3372
françois romieuc0e45c12011-01-03 15:08:04 +00003373 rtl_init_mdio_ops(tp);
françois romieu065c27c2011-01-03 15:08:12 +00003374 rtl_init_pll_power_ops(tp);
françois romieuc0e45c12011-01-03 15:08:04 +00003375
Linus Torvalds1da177e2005-04-16 15:20:36 -07003376 rtl8169_print_mac_version(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003377
Francois Romieu85bffe62011-04-27 08:22:39 +02003378 chipset = tp->mac_version;
3379 tp->txd_version = rtl_chip_infos[chipset].txd_version;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003380
Francois Romieu5d06a992006-02-23 00:47:58 +01003381 RTL_W8(Cfg9346, Cfg9346_Unlock);
3382 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3383 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
Bruno Prémont20037fa2008-10-08 17:05:03 -07003384 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3385 tp->features |= RTL_FEATURE_WOL;
3386 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3387 tp->features |= RTL_FEATURE_WOL;
Francois Romieufbac58f2007-10-04 22:51:38 +02003388 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
Francois Romieu5d06a992006-02-23 00:47:58 +01003389 RTL_W8(Cfg9346, Cfg9346_Lock);
3390
Francois Romieu66ec5d42007-11-06 22:56:10 +01003391 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3392 (RTL_R8(PHYstatus) & TBI_Enable)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003393 tp->set_speed = rtl8169_set_speed_tbi;
3394 tp->get_settings = rtl8169_gset_tbi;
3395 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3396 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3397 tp->link_ok = rtl8169_tbi_link_ok;
Francois Romieu8b4ab282008-11-19 22:05:25 -08003398 tp->do_ioctl = rtl_tbi_ioctl;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003399 } else {
3400 tp->set_speed = rtl8169_set_speed_xmii;
3401 tp->get_settings = rtl8169_gset_xmii;
3402 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3403 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3404 tp->link_ok = rtl8169_xmii_link_ok;
Francois Romieu8b4ab282008-11-19 22:05:25 -08003405 tp->do_ioctl = rtl_xmii_ioctl;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003406 }
3407
Francois Romieudf58ef512008-10-09 14:35:58 -07003408 spin_lock_init(&tp->lock);
3409
Ivan Vecera7bf6bf42008-09-23 22:46:29 +00003410 /* Get MAC address */
Linus Torvalds1da177e2005-04-16 15:20:36 -07003411 for (i = 0; i < MAC_ADDR_LEN; i++)
3412 dev->dev_addr[i] = RTL_R8(MAC0 + i);
John W. Linville6d6525b2005-09-12 10:48:57 -04003413 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003414
Linus Torvalds1da177e2005-04-16 15:20:36 -07003415 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003416 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3417 dev->irq = pdev->irq;
3418 dev->base_addr = (unsigned long) ioaddr;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003419
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003420 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003421
Michał Mirosław350fb322011-04-08 06:35:56 +00003422 /* don't enable SG, IP_CSUM and TSO by default - it might not work
3423 * properly for all devices */
3424 dev->features |= NETIF_F_RXCSUM |
3425 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3426
3427 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3428 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3429 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3430 NETIF_F_HIGHDMA;
3431
3432 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3433 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3434 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003435
3436 tp->intr_mask = 0xffff;
Francois Romieu0e485152007-02-20 00:00:26 +01003437 tp->hw_start = cfg->hw_start;
3438 tp->intr_event = cfg->intr_event;
3439 tp->napi_event = cfg->napi_event;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003440
Francois Romieu2efa53f2007-03-09 00:00:05 +01003441 init_timer(&tp->timer);
3442 tp->timer.data = (unsigned long) dev;
3443 tp->timer.function = rtl8169_phy_timer;
3444
François Romieu953a12c2011-04-24 17:38:48 +02003445 tp->fw = RTL_FIRMWARE_UNKNOWN;
3446
Linus Torvalds1da177e2005-04-16 15:20:36 -07003447 rc = register_netdev(dev);
Francois Romieu4ff96fa2006-07-26 22:05:06 +02003448 if (rc < 0)
françois romieu87aeec72010-04-26 11:42:06 +00003449 goto err_out_msi_4;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003450
3451 pci_set_drvdata(pdev, dev);
3452
Joe Perchesbf82c182010-02-09 11:49:50 +00003453 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
Francois Romieu85bffe62011-04-27 08:22:39 +02003454 rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
Joe Perchesbf82c182010-02-09 11:49:50 +00003455 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003456
Francois Romieucecb5fd2011-04-01 10:21:07 +02003457 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3458 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3459 tp->mac_version == RTL_GIGA_MAC_VER_31) {
françois romieub646d902011-01-03 15:08:21 +00003460 rtl8168_driver_start(tp);
françois romieue6de30d2011-01-03 15:08:37 +00003461 }
françois romieub646d902011-01-03 15:08:21 +00003462
Bruno Prémont8b76ab32008-10-08 17:06:25 -07003463 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003464
Alan Sternf3ec4f82010-06-08 15:23:51 -04003465 if (pci_dev_run_wake(pdev))
3466 pm_runtime_put_noidle(&pdev->dev);
Rafael J. Wysockie1759442010-03-14 14:33:51 +00003467
Ivan Vecera0d672e92011-02-15 02:08:39 +00003468 netif_carrier_off(dev);
3469
Francois Romieu4ff96fa2006-07-26 22:05:06 +02003470out:
3471 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003472
françois romieu87aeec72010-04-26 11:42:06 +00003473err_out_msi_4:
Francois Romieufbac58f2007-10-04 22:51:38 +02003474 rtl_disable_msi(pdev, tp);
Francois Romieu4ff96fa2006-07-26 22:05:06 +02003475 iounmap(ioaddr);
françois romieu87aeec72010-04-26 11:42:06 +00003476err_out_free_res_3:
Francois Romieu4ff96fa2006-07-26 22:05:06 +02003477 pci_release_regions(pdev);
françois romieu87aeec72010-04-26 11:42:06 +00003478err_out_mwi_2:
Francois Romieu4ff96fa2006-07-26 22:05:06 +02003479 pci_clear_mwi(pdev);
Francois Romieu4ff96fa2006-07-26 22:05:06 +02003480 pci_disable_device(pdev);
3481err_out_free_dev_1:
3482 free_netdev(dev);
3483 goto out;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003484}
3485
Francois Romieu07d3f512007-02-21 22:40:46 +01003486static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003487{
3488 struct net_device *dev = pci_get_drvdata(pdev);
3489 struct rtl8169_private *tp = netdev_priv(dev);
3490
Francois Romieucecb5fd2011-04-01 10:21:07 +02003491 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3492 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3493 tp->mac_version == RTL_GIGA_MAC_VER_31) {
françois romieub646d902011-01-03 15:08:21 +00003494 rtl8168_driver_stop(tp);
françois romieue6de30d2011-01-03 15:08:37 +00003495 }
françois romieub646d902011-01-03 15:08:21 +00003496
Tejun Heo23f333a2010-12-12 16:45:14 +01003497 cancel_delayed_work_sync(&tp->task);
Francois Romieueb2a0212007-02-15 23:37:21 +01003498
Linus Torvalds1da177e2005-04-16 15:20:36 -07003499 unregister_netdev(dev);
Ivan Veceracc098dc2009-11-29 23:12:52 -08003500
François Romieu953a12c2011-04-24 17:38:48 +02003501 rtl_release_firmware(tp);
3502
Alan Sternf3ec4f82010-06-08 15:23:51 -04003503 if (pci_dev_run_wake(pdev))
3504 pm_runtime_get_noresume(&pdev->dev);
Rafael J. Wysockie1759442010-03-14 14:33:51 +00003505
Ivan Veceracc098dc2009-11-29 23:12:52 -08003506 /* restore original MAC address */
3507 rtl_rar_set(tp, dev->perm_addr);
3508
Francois Romieufbac58f2007-10-04 22:51:38 +02003509 rtl_disable_msi(pdev, tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003510 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3511 pci_set_drvdata(pdev, NULL);
3512}
3513
François Romieu953a12c2011-04-24 17:38:48 +02003514static void rtl_request_firmware(struct rtl8169_private *tp)
3515{
François Romieu953a12c2011-04-24 17:38:48 +02003516 /* Return early if the firmware is already loaded / cached. */
Francois Romieu31bd2042011-04-26 18:58:59 +02003517 if (IS_ERR(tp->fw)) {
3518 const char *name;
François Romieu953a12c2011-04-24 17:38:48 +02003519
Francois Romieu31bd2042011-04-26 18:58:59 +02003520 name = rtl_lookup_firmware_name(tp);
3521 if (name) {
François Romieu953a12c2011-04-24 17:38:48 +02003522 int rc;
3523
3524 rc = request_firmware(&tp->fw, name, &tp->pci_dev->dev);
Francois Romieu31bd2042011-04-26 18:58:59 +02003525 if (rc >= 0)
3526 return;
François Romieu953a12c2011-04-24 17:38:48 +02003527
Francois Romieu31bd2042011-04-26 18:58:59 +02003528 netif_warn(tp, ifup, tp->dev, "unable to load "
3529 "firmware patch %s (%d)\n", name, rc);
3530 }
3531 tp->fw = NULL;
3532 }
François Romieu953a12c2011-04-24 17:38:48 +02003533}
3534
Linus Torvalds1da177e2005-04-16 15:20:36 -07003535static int rtl8169_open(struct net_device *dev)
3536{
3537 struct rtl8169_private *tp = netdev_priv(dev);
françois romieueee3a962011-01-08 02:17:26 +00003538 void __iomem *ioaddr = tp->mmio_addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003539 struct pci_dev *pdev = tp->pci_dev;
Francois Romieu99f252b2007-04-02 22:59:59 +02003540 int retval = -ENOMEM;
3541
Rafael J. Wysockie1759442010-03-14 14:33:51 +00003542 pm_runtime_get_sync(&pdev->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003543
Neil Hormanc0cd8842010-03-29 13:16:02 -07003544 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07003545 * Rx and Tx desscriptors needs 256 bytes alignment.
Stanislaw Gruszka82553bb2010-10-08 04:25:01 +00003546 * dma_alloc_coherent provides more.
Linus Torvalds1da177e2005-04-16 15:20:36 -07003547 */
Stanislaw Gruszka82553bb2010-10-08 04:25:01 +00003548 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3549 &tp->TxPhyAddr, GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003550 if (!tp->TxDescArray)
Rafael J. Wysockie1759442010-03-14 14:33:51 +00003551 goto err_pm_runtime_put;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003552
Stanislaw Gruszka82553bb2010-10-08 04:25:01 +00003553 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3554 &tp->RxPhyAddr, GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003555 if (!tp->RxDescArray)
Francois Romieu99f252b2007-04-02 22:59:59 +02003556 goto err_free_tx_0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003557
3558 retval = rtl8169_init_ring(dev);
3559 if (retval < 0)
Francois Romieu99f252b2007-04-02 22:59:59 +02003560 goto err_free_rx_1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003561
David Howellsc4028952006-11-22 14:57:56 +00003562 INIT_DELAYED_WORK(&tp->task, NULL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003563
Francois Romieu99f252b2007-04-02 22:59:59 +02003564 smp_mb();
3565
François Romieu953a12c2011-04-24 17:38:48 +02003566 rtl_request_firmware(tp);
3567
Francois Romieufbac58f2007-10-04 22:51:38 +02003568 retval = request_irq(dev->irq, rtl8169_interrupt,
3569 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
Francois Romieu99f252b2007-04-02 22:59:59 +02003570 dev->name, dev);
3571 if (retval < 0)
François Romieu953a12c2011-04-24 17:38:48 +02003572 goto err_release_fw_2;
Francois Romieu99f252b2007-04-02 22:59:59 +02003573
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003574 napi_enable(&tp->napi);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003575
françois romieueee3a962011-01-08 02:17:26 +00003576 rtl8169_init_phy(dev, tp);
3577
Michał Mirosław350fb322011-04-08 06:35:56 +00003578 rtl8169_set_features(dev, dev->features);
françois romieueee3a962011-01-08 02:17:26 +00003579
françois romieu065c27c2011-01-03 15:08:12 +00003580 rtl_pll_power_up(tp);
3581
Francois Romieu07ce4062007-02-23 23:36:39 +01003582 rtl_hw_start(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003583
Rafael J. Wysockie1759442010-03-14 14:33:51 +00003584 tp->saved_wolopts = 0;
3585 pm_runtime_put_noidle(&pdev->dev);
3586
françois romieueee3a962011-01-08 02:17:26 +00003587 rtl8169_check_link_status(dev, tp, ioaddr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003588out:
3589 return retval;
3590
François Romieu953a12c2011-04-24 17:38:48 +02003591err_release_fw_2:
3592 rtl_release_firmware(tp);
Francois Romieu99f252b2007-04-02 22:59:59 +02003593 rtl8169_rx_clear(tp);
3594err_free_rx_1:
Stanislaw Gruszka82553bb2010-10-08 04:25:01 +00003595 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3596 tp->RxPhyAddr);
Rafael J. Wysockie1759442010-03-14 14:33:51 +00003597 tp->RxDescArray = NULL;
Francois Romieu99f252b2007-04-02 22:59:59 +02003598err_free_tx_0:
Stanislaw Gruszka82553bb2010-10-08 04:25:01 +00003599 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3600 tp->TxPhyAddr);
Rafael J. Wysockie1759442010-03-14 14:33:51 +00003601 tp->TxDescArray = NULL;
3602err_pm_runtime_put:
3603 pm_runtime_put_noidle(&pdev->dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003604 goto out;
3605}
3606
françois romieue6de30d2011-01-03 15:08:37 +00003607static void rtl8169_hw_reset(struct rtl8169_private *tp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003608{
françois romieue6de30d2011-01-03 15:08:37 +00003609 void __iomem *ioaddr = tp->mmio_addr;
3610
Linus Torvalds1da177e2005-04-16 15:20:36 -07003611 /* Disable interrupts */
3612 rtl8169_irq_mask_and_ack(ioaddr);
3613
Hayes Wang5d2e1952011-02-22 17:26:22 +08003614 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
hayeswang4804b3b2011-03-21 01:50:29 +00003615 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3616 tp->mac_version == RTL_GIGA_MAC_VER_31) {
françois romieue6de30d2011-01-03 15:08:37 +00003617 while (RTL_R8(TxPoll) & NPQ)
3618 udelay(20);
3619
3620 }
3621
Linus Torvalds1da177e2005-04-16 15:20:36 -07003622 /* Reset the chipset */
3623 RTL_W8(ChipCmd, CmdReset);
3624
3625 /* PCI commit */
3626 RTL_R8(ChipCmd);
3627}
3628
Francois Romieu7f796d832007-06-11 23:04:41 +02003629static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
Francois Romieu9cb427b2006-11-02 00:10:16 +01003630{
3631 void __iomem *ioaddr = tp->mmio_addr;
3632 u32 cfg = rtl8169_rx_config;
3633
Francois Romieu2b7b4312011-04-18 22:53:24 -07003634 cfg |= (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
Francois Romieu9cb427b2006-11-02 00:10:16 +01003635 RTL_W32(RxConfig, cfg);
3636
3637 /* Set DMA burst size and Interframe Gap Time */
3638 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3639 (InterFrameGap << TxInterFrameGapShift));
3640}
3641
Francois Romieu07ce4062007-02-23 23:36:39 +01003642static void rtl_hw_start(struct net_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003643{
3644 struct rtl8169_private *tp = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003645
Francois Romieu6f43adc2011-04-29 15:05:51 +02003646 rtl_hw_reset(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003647
Francois Romieu07ce4062007-02-23 23:36:39 +01003648 tp->hw_start(dev);
3649
Francois Romieu07ce4062007-02-23 23:36:39 +01003650 netif_start_queue(dev);
3651}
3652
Francois Romieu7f796d832007-06-11 23:04:41 +02003653static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3654 void __iomem *ioaddr)
3655{
3656 /*
3657 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3658 * register to be written before TxDescAddrLow to work.
3659 * Switching from MMIO to I/O access fixes the issue as well.
3660 */
3661 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
Yang Hongyang284901a2009-04-06 19:01:15 -07003662 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
Francois Romieu7f796d832007-06-11 23:04:41 +02003663 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
Yang Hongyang284901a2009-04-06 19:01:15 -07003664 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
Francois Romieu7f796d832007-06-11 23:04:41 +02003665}
3666
3667static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3668{
3669 u16 cmd;
3670
3671 cmd = RTL_R16(CPlusCmd);
3672 RTL_W16(CPlusCmd, cmd);
3673 return cmd;
3674}
3675
Eric Dumazetfdd7b4c2009-06-09 04:01:02 -07003676static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
Francois Romieu7f796d832007-06-11 23:04:41 +02003677{
3678 /* Low hurts. Let's disable the filtering. */
Raimonds Cicans207d6e872009-10-26 10:52:37 +00003679 RTL_W16(RxMaxSize, rx_buf_sz + 1);
Francois Romieu7f796d832007-06-11 23:04:41 +02003680}
3681
Francois Romieu6dccd162007-02-13 23:38:05 +01003682static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3683{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08003684 static const struct {
Francois Romieu6dccd162007-02-13 23:38:05 +01003685 u32 mac_version;
3686 u32 clk;
3687 u32 val;
3688 } cfg2_info [] = {
3689 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3690 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3691 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3692 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3693 }, *p = cfg2_info;
3694 unsigned int i;
3695 u32 clk;
3696
3697 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
Francois Romieucadf1852008-01-03 23:38:38 +01003698 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
Francois Romieu6dccd162007-02-13 23:38:05 +01003699 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3700 RTL_W32(0x7c, p->val);
3701 break;
3702 }
3703 }
3704}
3705
Francois Romieu07ce4062007-02-23 23:36:39 +01003706static void rtl_hw_start_8169(struct net_device *dev)
3707{
3708 struct rtl8169_private *tp = netdev_priv(dev);
3709 void __iomem *ioaddr = tp->mmio_addr;
3710 struct pci_dev *pdev = tp->pci_dev;
Francois Romieu07ce4062007-02-23 23:36:39 +01003711
Francois Romieu9cb427b2006-11-02 00:10:16 +01003712 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3713 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3714 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3715 }
3716
Linus Torvalds1da177e2005-04-16 15:20:36 -07003717 RTL_W8(Cfg9346, Cfg9346_Unlock);
Francois Romieucecb5fd2011-04-01 10:21:07 +02003718 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3719 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3720 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3721 tp->mac_version == RTL_GIGA_MAC_VER_04)
Francois Romieu9cb427b2006-11-02 00:10:16 +01003722 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3723
françois romieuf0298f82011-01-03 15:07:42 +00003724 RTL_W8(EarlyTxThres, NoEarlyTx);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003725
Eric Dumazet6f0333b2010-10-11 11:17:47 +00003726 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003727
Francois Romieucecb5fd2011-04-01 10:21:07 +02003728 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3729 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3730 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3731 tp->mac_version == RTL_GIGA_MAC_VER_04)
Francois Romieuc946b302007-10-04 00:42:50 +02003732 rtl_set_rx_tx_config_registers(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003733
Francois Romieu7f796d832007-06-11 23:04:41 +02003734 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
Francois Romieubcf0bf92006-07-26 23:14:13 +02003735
Francois Romieucecb5fd2011-04-01 10:21:07 +02003736 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3737 tp->mac_version == RTL_GIGA_MAC_VER_03) {
Joe Perches06fa7352007-10-18 21:15:00 +02003738 dprintk("Set MAC Reg C+CR Offset 0xE0. "
Linus Torvalds1da177e2005-04-16 15:20:36 -07003739 "Bit-3 and bit-14 MUST be 1\n");
Francois Romieubcf0bf92006-07-26 23:14:13 +02003740 tp->cp_cmd |= (1 << 14);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003741 }
3742
Francois Romieubcf0bf92006-07-26 23:14:13 +02003743 RTL_W16(CPlusCmd, tp->cp_cmd);
3744
Francois Romieu6dccd162007-02-13 23:38:05 +01003745 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3746
Linus Torvalds1da177e2005-04-16 15:20:36 -07003747 /*
3748 * Undocumented corner. Supposedly:
3749 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3750 */
3751 RTL_W16(IntrMitigate, 0x0000);
3752
Francois Romieu7f796d832007-06-11 23:04:41 +02003753 rtl_set_rx_tx_desc_registers(tp, ioaddr);
Francois Romieu9cb427b2006-11-02 00:10:16 +01003754
Francois Romieucecb5fd2011-04-01 10:21:07 +02003755 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
3756 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
3757 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
3758 tp->mac_version != RTL_GIGA_MAC_VER_04) {
Francois Romieuc946b302007-10-04 00:42:50 +02003759 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3760 rtl_set_rx_tx_config_registers(tp);
3761 }
3762
Linus Torvalds1da177e2005-04-16 15:20:36 -07003763 RTL_W8(Cfg9346, Cfg9346_Lock);
Francois Romieub518fa82006-08-16 15:23:13 +02003764
3765 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3766 RTL_R8(IntrMask);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003767
3768 RTL_W32(RxMissed, 0);
3769
Francois Romieu07ce4062007-02-23 23:36:39 +01003770 rtl_set_rx_mode(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003771
3772 /* no early-rx interrupts */
3773 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
Francois Romieu6dccd162007-02-13 23:38:05 +01003774
3775 /* Enable all known interrupts by setting the interrupt mask. */
Francois Romieu0e485152007-02-20 00:00:26 +01003776 RTL_W16(IntrMask, tp->intr_event);
Francois Romieu07ce4062007-02-23 23:36:39 +01003777}
Linus Torvalds1da177e2005-04-16 15:20:36 -07003778
Francois Romieu9c14cea2008-07-05 00:21:15 +02003779static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
Francois Romieu458a9f62008-08-02 15:50:02 +02003780{
Francois Romieu9c14cea2008-07-05 00:21:15 +02003781 struct net_device *dev = pci_get_drvdata(pdev);
3782 struct rtl8169_private *tp = netdev_priv(dev);
3783 int cap = tp->pcie_cap;
Francois Romieu458a9f62008-08-02 15:50:02 +02003784
Francois Romieu9c14cea2008-07-05 00:21:15 +02003785 if (cap) {
3786 u16 ctl;
3787
3788 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3789 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3790 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3791 }
Francois Romieu458a9f62008-08-02 15:50:02 +02003792}
3793
françois romieu650e8d52011-01-03 15:08:29 +00003794static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
Francois Romieudacf8152008-08-02 20:44:13 +02003795{
3796 u32 csi;
3797
3798 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
françois romieu650e8d52011-01-03 15:08:29 +00003799 rtl_csi_write(ioaddr, 0x070c, csi | bits);
3800}
3801
françois romieue6de30d2011-01-03 15:08:37 +00003802static void rtl_csi_access_enable_1(void __iomem *ioaddr)
3803{
3804 rtl_csi_access_enable(ioaddr, 0x17000000);
3805}
3806
françois romieu650e8d52011-01-03 15:08:29 +00003807static void rtl_csi_access_enable_2(void __iomem *ioaddr)
3808{
3809 rtl_csi_access_enable(ioaddr, 0x27000000);
Francois Romieudacf8152008-08-02 20:44:13 +02003810}
3811
3812struct ephy_info {
3813 unsigned int offset;
3814 u16 mask;
3815 u16 bits;
3816};
3817
Alexey Dobriyan350f7592009-11-25 15:54:21 -08003818static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
Francois Romieudacf8152008-08-02 20:44:13 +02003819{
3820 u16 w;
3821
3822 while (len-- > 0) {
3823 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3824 rtl_ephy_write(ioaddr, e->offset, w);
3825 e++;
3826 }
3827}
3828
Francois Romieub726e492008-06-28 12:22:59 +02003829static void rtl_disable_clock_request(struct pci_dev *pdev)
3830{
3831 struct net_device *dev = pci_get_drvdata(pdev);
3832 struct rtl8169_private *tp = netdev_priv(dev);
3833 int cap = tp->pcie_cap;
3834
3835 if (cap) {
3836 u16 ctl;
3837
3838 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3839 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3840 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3841 }
3842}
3843
françois romieue6de30d2011-01-03 15:08:37 +00003844static void rtl_enable_clock_request(struct pci_dev *pdev)
3845{
3846 struct net_device *dev = pci_get_drvdata(pdev);
3847 struct rtl8169_private *tp = netdev_priv(dev);
3848 int cap = tp->pcie_cap;
3849
3850 if (cap) {
3851 u16 ctl;
3852
3853 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3854 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3855 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3856 }
3857}
3858
Francois Romieub726e492008-06-28 12:22:59 +02003859#define R8168_CPCMD_QUIRK_MASK (\
3860 EnableBist | \
3861 Mac_dbgo_oe | \
3862 Force_half_dup | \
3863 Force_rxflow_en | \
3864 Force_txflow_en | \
3865 Cxpl_dbg_sel | \
3866 ASF | \
3867 PktCntrDisable | \
3868 Mac_dbgo_sel)
3869
Francois Romieu219a1e92008-06-28 11:58:39 +02003870static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3871{
Francois Romieub726e492008-06-28 12:22:59 +02003872 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3873
3874 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3875
Francois Romieu2e68ae42008-06-28 12:00:55 +02003876 rtl_tx_performance_tweak(pdev,
3877 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
Francois Romieu219a1e92008-06-28 11:58:39 +02003878}
3879
3880static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3881{
3882 rtl_hw_start_8168bb(ioaddr, pdev);
Francois Romieub726e492008-06-28 12:22:59 +02003883
françois romieuf0298f82011-01-03 15:07:42 +00003884 RTL_W8(MaxTxPacketSize, TxPacketMax);
Francois Romieub726e492008-06-28 12:22:59 +02003885
3886 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
Francois Romieu219a1e92008-06-28 11:58:39 +02003887}
3888
3889static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3890{
Francois Romieub726e492008-06-28 12:22:59 +02003891 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3892
3893 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3894
Francois Romieu219a1e92008-06-28 11:58:39 +02003895 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
Francois Romieub726e492008-06-28 12:22:59 +02003896
3897 rtl_disable_clock_request(pdev);
3898
3899 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
Francois Romieu219a1e92008-06-28 11:58:39 +02003900}
3901
Francois Romieuef3386f2008-06-29 12:24:30 +02003902static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
Francois Romieu219a1e92008-06-28 11:58:39 +02003903{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08003904 static const struct ephy_info e_info_8168cp[] = {
Francois Romieub726e492008-06-28 12:22:59 +02003905 { 0x01, 0, 0x0001 },
3906 { 0x02, 0x0800, 0x1000 },
3907 { 0x03, 0, 0x0042 },
3908 { 0x06, 0x0080, 0x0000 },
3909 { 0x07, 0, 0x2000 }
3910 };
3911
françois romieu650e8d52011-01-03 15:08:29 +00003912 rtl_csi_access_enable_2(ioaddr);
Francois Romieub726e492008-06-28 12:22:59 +02003913
3914 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3915
Francois Romieu219a1e92008-06-28 11:58:39 +02003916 __rtl_hw_start_8168cp(ioaddr, pdev);
3917}
3918
Francois Romieuef3386f2008-06-29 12:24:30 +02003919static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3920{
françois romieu650e8d52011-01-03 15:08:29 +00003921 rtl_csi_access_enable_2(ioaddr);
Francois Romieuef3386f2008-06-29 12:24:30 +02003922
3923 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3924
3925 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3926
3927 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3928}
3929
Francois Romieu7f3e3d32008-07-20 18:53:20 +02003930static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3931{
françois romieu650e8d52011-01-03 15:08:29 +00003932 rtl_csi_access_enable_2(ioaddr);
Francois Romieu7f3e3d32008-07-20 18:53:20 +02003933
3934 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3935
3936 /* Magic. */
3937 RTL_W8(DBG_REG, 0x20);
3938
françois romieuf0298f82011-01-03 15:07:42 +00003939 RTL_W8(MaxTxPacketSize, TxPacketMax);
Francois Romieu7f3e3d32008-07-20 18:53:20 +02003940
3941 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3942
3943 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3944}
3945
Francois Romieu219a1e92008-06-28 11:58:39 +02003946static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3947{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08003948 static const struct ephy_info e_info_8168c_1[] = {
Francois Romieub726e492008-06-28 12:22:59 +02003949 { 0x02, 0x0800, 0x1000 },
3950 { 0x03, 0, 0x0002 },
3951 { 0x06, 0x0080, 0x0000 }
3952 };
3953
françois romieu650e8d52011-01-03 15:08:29 +00003954 rtl_csi_access_enable_2(ioaddr);
Francois Romieub726e492008-06-28 12:22:59 +02003955
3956 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3957
3958 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3959
Francois Romieu219a1e92008-06-28 11:58:39 +02003960 __rtl_hw_start_8168cp(ioaddr, pdev);
3961}
3962
3963static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3964{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08003965 static const struct ephy_info e_info_8168c_2[] = {
Francois Romieub726e492008-06-28 12:22:59 +02003966 { 0x01, 0, 0x0001 },
3967 { 0x03, 0x0400, 0x0220 }
3968 };
3969
françois romieu650e8d52011-01-03 15:08:29 +00003970 rtl_csi_access_enable_2(ioaddr);
Francois Romieub726e492008-06-28 12:22:59 +02003971
3972 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3973
Francois Romieu219a1e92008-06-28 11:58:39 +02003974 __rtl_hw_start_8168cp(ioaddr, pdev);
3975}
3976
Francois Romieu197ff762008-06-28 13:16:02 +02003977static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3978{
3979 rtl_hw_start_8168c_2(ioaddr, pdev);
3980}
3981
Francois Romieu6fb07052008-06-29 11:54:28 +02003982static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3983{
françois romieu650e8d52011-01-03 15:08:29 +00003984 rtl_csi_access_enable_2(ioaddr);
Francois Romieu6fb07052008-06-29 11:54:28 +02003985
3986 __rtl_hw_start_8168cp(ioaddr, pdev);
3987}
3988
Francois Romieu5b538df2008-07-20 16:22:45 +02003989static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3990{
françois romieu650e8d52011-01-03 15:08:29 +00003991 rtl_csi_access_enable_2(ioaddr);
Francois Romieu5b538df2008-07-20 16:22:45 +02003992
3993 rtl_disable_clock_request(pdev);
3994
françois romieuf0298f82011-01-03 15:07:42 +00003995 RTL_W8(MaxTxPacketSize, TxPacketMax);
Francois Romieu5b538df2008-07-20 16:22:45 +02003996
3997 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3998
3999 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4000}
4001
hayeswang4804b3b2011-03-21 01:50:29 +00004002static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4003{
4004 rtl_csi_access_enable_1(ioaddr);
4005
4006 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4007
4008 RTL_W8(MaxTxPacketSize, TxPacketMax);
4009
4010 rtl_disable_clock_request(pdev);
4011}
4012
françois romieue6de30d2011-01-03 15:08:37 +00004013static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4014{
4015 static const struct ephy_info e_info_8168d_4[] = {
4016 { 0x0b, ~0, 0x48 },
4017 { 0x19, 0x20, 0x50 },
4018 { 0x0c, ~0, 0x20 }
4019 };
4020 int i;
4021
4022 rtl_csi_access_enable_1(ioaddr);
4023
4024 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4025
4026 RTL_W8(MaxTxPacketSize, TxPacketMax);
4027
4028 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4029 const struct ephy_info *e = e_info_8168d_4 + i;
4030 u16 w;
4031
4032 w = rtl_ephy_read(ioaddr, e->offset);
4033 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4034 }
4035
4036 rtl_enable_clock_request(pdev);
4037}
4038
hayeswang01dc7fe2011-03-21 01:50:28 +00004039static void rtl_hw_start_8168e(void __iomem *ioaddr, struct pci_dev *pdev)
4040{
4041 static const struct ephy_info e_info_8168e[] = {
4042 { 0x00, 0x0200, 0x0100 },
4043 { 0x00, 0x0000, 0x0004 },
4044 { 0x06, 0x0002, 0x0001 },
4045 { 0x06, 0x0000, 0x0030 },
4046 { 0x07, 0x0000, 0x2000 },
4047 { 0x00, 0x0000, 0x0020 },
4048 { 0x03, 0x5800, 0x2000 },
4049 { 0x03, 0x0000, 0x0001 },
4050 { 0x01, 0x0800, 0x1000 },
4051 { 0x07, 0x0000, 0x4000 },
4052 { 0x1e, 0x0000, 0x2000 },
4053 { 0x19, 0xffff, 0xfe6c },
4054 { 0x0a, 0x0000, 0x0040 }
4055 };
4056
4057 rtl_csi_access_enable_2(ioaddr);
4058
4059 rtl_ephy_init(ioaddr, e_info_8168e, ARRAY_SIZE(e_info_8168e));
4060
4061 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4062
4063 RTL_W8(MaxTxPacketSize, TxPacketMax);
4064
4065 rtl_disable_clock_request(pdev);
4066
4067 /* Reset tx FIFO pointer */
Francois Romieucecb5fd2011-04-01 10:21:07 +02004068 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4069 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
hayeswang01dc7fe2011-03-21 01:50:28 +00004070
Francois Romieucecb5fd2011-04-01 10:21:07 +02004071 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
hayeswang01dc7fe2011-03-21 01:50:28 +00004072}
4073
Francois Romieu07ce4062007-02-23 23:36:39 +01004074static void rtl_hw_start_8168(struct net_device *dev)
4075{
Francois Romieu2dd99532007-06-11 23:22:52 +02004076 struct rtl8169_private *tp = netdev_priv(dev);
4077 void __iomem *ioaddr = tp->mmio_addr;
Francois Romieu0e485152007-02-20 00:00:26 +01004078 struct pci_dev *pdev = tp->pci_dev;
Francois Romieu2dd99532007-06-11 23:22:52 +02004079
4080 RTL_W8(Cfg9346, Cfg9346_Unlock);
4081
françois romieuf0298f82011-01-03 15:07:42 +00004082 RTL_W8(MaxTxPacketSize, TxPacketMax);
Francois Romieu2dd99532007-06-11 23:22:52 +02004083
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004084 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
Francois Romieu2dd99532007-06-11 23:22:52 +02004085
Francois Romieu0e485152007-02-20 00:00:26 +01004086 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
Francois Romieu2dd99532007-06-11 23:22:52 +02004087
4088 RTL_W16(CPlusCmd, tp->cp_cmd);
4089
Francois Romieu0e485152007-02-20 00:00:26 +01004090 RTL_W16(IntrMitigate, 0x5151);
4091
4092 /* Work around for RxFIFO overflow. */
Ivan Vecerab5ba6d12011-01-27 12:24:11 +01004093 if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
4094 tp->mac_version == RTL_GIGA_MAC_VER_22) {
Francois Romieu0e485152007-02-20 00:00:26 +01004095 tp->intr_event |= RxFIFOOver | PCSTimeout;
4096 tp->intr_event &= ~RxOverflow;
4097 }
Francois Romieu2dd99532007-06-11 23:22:52 +02004098
4099 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4100
Francois Romieub8363902008-06-01 12:31:57 +02004101 rtl_set_rx_mode(dev);
4102
4103 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4104 (InterFrameGap << TxInterFrameGapShift));
Francois Romieu2dd99532007-06-11 23:22:52 +02004105
4106 RTL_R8(IntrMask);
4107
Francois Romieu219a1e92008-06-28 11:58:39 +02004108 switch (tp->mac_version) {
4109 case RTL_GIGA_MAC_VER_11:
4110 rtl_hw_start_8168bb(ioaddr, pdev);
hayeswang4804b3b2011-03-21 01:50:29 +00004111 break;
Francois Romieu219a1e92008-06-28 11:58:39 +02004112
4113 case RTL_GIGA_MAC_VER_12:
4114 case RTL_GIGA_MAC_VER_17:
4115 rtl_hw_start_8168bef(ioaddr, pdev);
hayeswang4804b3b2011-03-21 01:50:29 +00004116 break;
Francois Romieu219a1e92008-06-28 11:58:39 +02004117
4118 case RTL_GIGA_MAC_VER_18:
Francois Romieuef3386f2008-06-29 12:24:30 +02004119 rtl_hw_start_8168cp_1(ioaddr, pdev);
hayeswang4804b3b2011-03-21 01:50:29 +00004120 break;
Francois Romieu219a1e92008-06-28 11:58:39 +02004121
4122 case RTL_GIGA_MAC_VER_19:
4123 rtl_hw_start_8168c_1(ioaddr, pdev);
hayeswang4804b3b2011-03-21 01:50:29 +00004124 break;
Francois Romieu219a1e92008-06-28 11:58:39 +02004125
4126 case RTL_GIGA_MAC_VER_20:
4127 rtl_hw_start_8168c_2(ioaddr, pdev);
hayeswang4804b3b2011-03-21 01:50:29 +00004128 break;
Francois Romieu219a1e92008-06-28 11:58:39 +02004129
Francois Romieu197ff762008-06-28 13:16:02 +02004130 case RTL_GIGA_MAC_VER_21:
4131 rtl_hw_start_8168c_3(ioaddr, pdev);
hayeswang4804b3b2011-03-21 01:50:29 +00004132 break;
Francois Romieu197ff762008-06-28 13:16:02 +02004133
Francois Romieu6fb07052008-06-29 11:54:28 +02004134 case RTL_GIGA_MAC_VER_22:
4135 rtl_hw_start_8168c_4(ioaddr, pdev);
hayeswang4804b3b2011-03-21 01:50:29 +00004136 break;
Francois Romieu6fb07052008-06-29 11:54:28 +02004137
Francois Romieuef3386f2008-06-29 12:24:30 +02004138 case RTL_GIGA_MAC_VER_23:
4139 rtl_hw_start_8168cp_2(ioaddr, pdev);
hayeswang4804b3b2011-03-21 01:50:29 +00004140 break;
Francois Romieuef3386f2008-06-29 12:24:30 +02004141
Francois Romieu7f3e3d32008-07-20 18:53:20 +02004142 case RTL_GIGA_MAC_VER_24:
4143 rtl_hw_start_8168cp_3(ioaddr, pdev);
hayeswang4804b3b2011-03-21 01:50:29 +00004144 break;
Francois Romieu7f3e3d32008-07-20 18:53:20 +02004145
Francois Romieu5b538df2008-07-20 16:22:45 +02004146 case RTL_GIGA_MAC_VER_25:
françois romieudaf9df62009-10-07 12:44:20 +00004147 case RTL_GIGA_MAC_VER_26:
4148 case RTL_GIGA_MAC_VER_27:
Francois Romieu5b538df2008-07-20 16:22:45 +02004149 rtl_hw_start_8168d(ioaddr, pdev);
hayeswang4804b3b2011-03-21 01:50:29 +00004150 break;
Francois Romieu5b538df2008-07-20 16:22:45 +02004151
françois romieue6de30d2011-01-03 15:08:37 +00004152 case RTL_GIGA_MAC_VER_28:
4153 rtl_hw_start_8168d_4(ioaddr, pdev);
hayeswang4804b3b2011-03-21 01:50:29 +00004154 break;
Francois Romieucecb5fd2011-04-01 10:21:07 +02004155
hayeswang4804b3b2011-03-21 01:50:29 +00004156 case RTL_GIGA_MAC_VER_31:
4157 rtl_hw_start_8168dp(ioaddr, pdev);
4158 break;
4159
hayeswang01dc7fe2011-03-21 01:50:28 +00004160 case RTL_GIGA_MAC_VER_32:
4161 case RTL_GIGA_MAC_VER_33:
4162 rtl_hw_start_8168e(ioaddr, pdev);
4163 break;
françois romieue6de30d2011-01-03 15:08:37 +00004164
Francois Romieu219a1e92008-06-28 11:58:39 +02004165 default:
4166 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4167 dev->name, tp->mac_version);
hayeswang4804b3b2011-03-21 01:50:29 +00004168 break;
Francois Romieu219a1e92008-06-28 11:58:39 +02004169 }
Francois Romieu2dd99532007-06-11 23:22:52 +02004170
Francois Romieu0e485152007-02-20 00:00:26 +01004171 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4172
Francois Romieub8363902008-06-01 12:31:57 +02004173 RTL_W8(Cfg9346, Cfg9346_Lock);
4174
Francois Romieu2dd99532007-06-11 23:22:52 +02004175 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
Francois Romieu6dccd162007-02-13 23:38:05 +01004176
Francois Romieu0e485152007-02-20 00:00:26 +01004177 RTL_W16(IntrMask, tp->intr_event);
Francois Romieu07ce4062007-02-23 23:36:39 +01004178}
Linus Torvalds1da177e2005-04-16 15:20:36 -07004179
Francois Romieu2857ffb2008-08-02 21:08:49 +02004180#define R810X_CPCMD_QUIRK_MASK (\
4181 EnableBist | \
4182 Mac_dbgo_oe | \
4183 Force_half_dup | \
françois romieu5edcc532009-08-10 19:41:52 +00004184 Force_rxflow_en | \
Francois Romieu2857ffb2008-08-02 21:08:49 +02004185 Force_txflow_en | \
4186 Cxpl_dbg_sel | \
4187 ASF | \
4188 PktCntrDisable | \
Hayes Wangd24e9aa2011-02-22 17:26:19 +08004189 Mac_dbgo_sel)
Francois Romieu2857ffb2008-08-02 21:08:49 +02004190
4191static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4192{
Alexey Dobriyan350f7592009-11-25 15:54:21 -08004193 static const struct ephy_info e_info_8102e_1[] = {
Francois Romieu2857ffb2008-08-02 21:08:49 +02004194 { 0x01, 0, 0x6e65 },
4195 { 0x02, 0, 0x091f },
4196 { 0x03, 0, 0xc2f9 },
4197 { 0x06, 0, 0xafb5 },
4198 { 0x07, 0, 0x0e00 },
4199 { 0x19, 0, 0xec80 },
4200 { 0x01, 0, 0x2e65 },
4201 { 0x01, 0, 0x6e65 }
4202 };
4203 u8 cfg1;
4204
françois romieu650e8d52011-01-03 15:08:29 +00004205 rtl_csi_access_enable_2(ioaddr);
Francois Romieu2857ffb2008-08-02 21:08:49 +02004206
4207 RTL_W8(DBG_REG, FIX_NAK_1);
4208
4209 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4210
4211 RTL_W8(Config1,
4212 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4213 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4214
4215 cfg1 = RTL_R8(Config1);
4216 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4217 RTL_W8(Config1, cfg1 & ~LEDS0);
4218
Francois Romieu2857ffb2008-08-02 21:08:49 +02004219 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4220}
4221
4222static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4223{
françois romieu650e8d52011-01-03 15:08:29 +00004224 rtl_csi_access_enable_2(ioaddr);
Francois Romieu2857ffb2008-08-02 21:08:49 +02004225
4226 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4227
4228 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4229 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
Francois Romieu2857ffb2008-08-02 21:08:49 +02004230}
4231
4232static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4233{
4234 rtl_hw_start_8102e_2(ioaddr, pdev);
4235
4236 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4237}
4238
Hayes Wang5a5e4442011-02-22 17:26:21 +08004239static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4240{
4241 static const struct ephy_info e_info_8105e_1[] = {
4242 { 0x07, 0, 0x4000 },
4243 { 0x19, 0, 0x0200 },
4244 { 0x19, 0, 0x0020 },
4245 { 0x1e, 0, 0x2000 },
4246 { 0x03, 0, 0x0001 },
4247 { 0x19, 0, 0x0100 },
4248 { 0x19, 0, 0x0004 },
4249 { 0x0a, 0, 0x0020 }
4250 };
4251
Francois Romieucecb5fd2011-04-01 10:21:07 +02004252 /* Force LAN exit from ASPM if Rx/Tx are not idle */
Hayes Wang5a5e4442011-02-22 17:26:21 +08004253 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4254
Francois Romieucecb5fd2011-04-01 10:21:07 +02004255 /* Disable Early Tally Counter */
Hayes Wang5a5e4442011-02-22 17:26:21 +08004256 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4257
4258 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4259 RTL_W8(DLLPR, RTL_R8(DLLPR) | PM_SWITCH);
4260
4261 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4262}
4263
4264static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4265{
4266 rtl_hw_start_8105e_1(ioaddr, pdev);
4267 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4268}
4269
Francois Romieu07ce4062007-02-23 23:36:39 +01004270static void rtl_hw_start_8101(struct net_device *dev)
4271{
Francois Romieucdf1a602007-06-11 23:29:50 +02004272 struct rtl8169_private *tp = netdev_priv(dev);
4273 void __iomem *ioaddr = tp->mmio_addr;
4274 struct pci_dev *pdev = tp->pci_dev;
4275
Francois Romieucecb5fd2011-04-01 10:21:07 +02004276 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4277 tp->mac_version == RTL_GIGA_MAC_VER_16) {
Francois Romieu9c14cea2008-07-05 00:21:15 +02004278 int cap = tp->pcie_cap;
4279
4280 if (cap) {
4281 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4282 PCI_EXP_DEVCTL_NOSNOOP_EN);
4283 }
Francois Romieucdf1a602007-06-11 23:29:50 +02004284 }
4285
Hayes Wangd24e9aa2011-02-22 17:26:19 +08004286 RTL_W8(Cfg9346, Cfg9346_Unlock);
4287
Francois Romieu2857ffb2008-08-02 21:08:49 +02004288 switch (tp->mac_version) {
4289 case RTL_GIGA_MAC_VER_07:
4290 rtl_hw_start_8102e_1(ioaddr, pdev);
4291 break;
4292
4293 case RTL_GIGA_MAC_VER_08:
4294 rtl_hw_start_8102e_3(ioaddr, pdev);
4295 break;
4296
4297 case RTL_GIGA_MAC_VER_09:
4298 rtl_hw_start_8102e_2(ioaddr, pdev);
4299 break;
Hayes Wang5a5e4442011-02-22 17:26:21 +08004300
4301 case RTL_GIGA_MAC_VER_29:
4302 rtl_hw_start_8105e_1(ioaddr, pdev);
4303 break;
4304 case RTL_GIGA_MAC_VER_30:
4305 rtl_hw_start_8105e_2(ioaddr, pdev);
4306 break;
Francois Romieucdf1a602007-06-11 23:29:50 +02004307 }
4308
Hayes Wangd24e9aa2011-02-22 17:26:19 +08004309 RTL_W8(Cfg9346, Cfg9346_Lock);
Francois Romieucdf1a602007-06-11 23:29:50 +02004310
françois romieuf0298f82011-01-03 15:07:42 +00004311 RTL_W8(MaxTxPacketSize, TxPacketMax);
Francois Romieucdf1a602007-06-11 23:29:50 +02004312
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004313 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
Francois Romieucdf1a602007-06-11 23:29:50 +02004314
Hayes Wangd24e9aa2011-02-22 17:26:19 +08004315 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
Francois Romieucdf1a602007-06-11 23:29:50 +02004316 RTL_W16(CPlusCmd, tp->cp_cmd);
4317
4318 RTL_W16(IntrMitigate, 0x0000);
4319
4320 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4321
4322 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4323 rtl_set_rx_tx_config_registers(tp);
4324
Francois Romieucdf1a602007-06-11 23:29:50 +02004325 RTL_R8(IntrMask);
4326
Francois Romieucdf1a602007-06-11 23:29:50 +02004327 rtl_set_rx_mode(dev);
4328
4329 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
Francois Romieu6dccd162007-02-13 23:38:05 +01004330
Francois Romieu0e485152007-02-20 00:00:26 +01004331 RTL_W16(IntrMask, tp->intr_event);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004332}
4333
4334static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4335{
Linus Torvalds1da177e2005-04-16 15:20:36 -07004336 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
4337 return -EINVAL;
4338
4339 dev->mtu = new_mtu;
Michał Mirosław350fb322011-04-08 06:35:56 +00004340 netdev_update_features(dev);
4341
Stanislaw Gruszka323bb682010-10-20 22:25:41 +00004342 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004343}
4344
4345static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4346{
Al Viro95e09182007-12-22 18:55:39 +00004347 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004348 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4349}
4350
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004351static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4352 void **data_buff, struct RxDesc *desc)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004353{
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00004354 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
Stanislaw Gruszka231aee62010-10-20 22:25:38 +00004355 DMA_FROM_DEVICE);
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00004356
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004357 kfree(*data_buff);
4358 *data_buff = NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004359 rtl8169_make_unusable_by_asic(desc);
4360}
4361
4362static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4363{
4364 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4365
4366 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4367}
4368
4369static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4370 u32 rx_buf_sz)
4371{
4372 desc->addr = cpu_to_le64(mapping);
4373 wmb();
4374 rtl8169_mark_to_asic(desc, rx_buf_sz);
4375}
4376
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004377static inline void *rtl8169_align(void *data)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004378{
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004379 return (void *)ALIGN((long)data, 16);
4380}
4381
Stanislaw Gruszka0ecbe1c2010-10-20 22:25:37 +00004382static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4383 struct RxDesc *desc)
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004384{
4385 void *data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004386 dma_addr_t mapping;
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00004387 struct device *d = &tp->pci_dev->dev;
Stanislaw Gruszka0ecbe1c2010-10-20 22:25:37 +00004388 struct net_device *dev = tp->dev;
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004389 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004390
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004391 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4392 if (!data)
4393 return NULL;
Francois Romieue9f63f32007-02-28 23:16:57 +01004394
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004395 if (rtl8169_align(data) != data) {
4396 kfree(data);
4397 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4398 if (!data)
4399 return NULL;
4400 }
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004401
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00004402 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
Stanislaw Gruszka231aee62010-10-20 22:25:38 +00004403 DMA_FROM_DEVICE);
Stanislaw Gruszkad827d862010-10-20 22:25:43 +00004404 if (unlikely(dma_mapping_error(d, mapping))) {
4405 if (net_ratelimit())
4406 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004407 goto err_out;
Stanislaw Gruszkad827d862010-10-20 22:25:43 +00004408 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004409
4410 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004411 return data;
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004412
4413err_out:
4414 kfree(data);
4415 return NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004416}
4417
4418static void rtl8169_rx_clear(struct rtl8169_private *tp)
4419{
Francois Romieu07d3f512007-02-21 22:40:46 +01004420 unsigned int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004421
4422 for (i = 0; i < NUM_RX_DESC; i++) {
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004423 if (tp->Rx_databuff[i]) {
4424 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
Linus Torvalds1da177e2005-04-16 15:20:36 -07004425 tp->RxDescArray + i);
4426 }
4427 }
4428}
4429
Stanislaw Gruszka0ecbe1c2010-10-20 22:25:37 +00004430static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004431{
Stanislaw Gruszka0ecbe1c2010-10-20 22:25:37 +00004432 desc->opts1 |= cpu_to_le32(RingEnd);
4433}
Francois Romieu5b0384f2006-08-16 16:00:01 +02004434
Stanislaw Gruszka0ecbe1c2010-10-20 22:25:37 +00004435static int rtl8169_rx_fill(struct rtl8169_private *tp)
4436{
4437 unsigned int i;
4438
4439 for (i = 0; i < NUM_RX_DESC; i++) {
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004440 void *data;
Francois Romieu4ae47c22007-06-16 23:28:45 +02004441
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004442 if (tp->Rx_databuff[i])
Linus Torvalds1da177e2005-04-16 15:20:36 -07004443 continue;
Francois Romieubcf0bf92006-07-26 23:14:13 +02004444
Stanislaw Gruszka0ecbe1c2010-10-20 22:25:37 +00004445 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004446 if (!data) {
4447 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
Stanislaw Gruszka0ecbe1c2010-10-20 22:25:37 +00004448 goto err_out;
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004449 }
4450 tp->Rx_databuff[i] = data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004451 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004452
Stanislaw Gruszka0ecbe1c2010-10-20 22:25:37 +00004453 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4454 return 0;
4455
4456err_out:
4457 rtl8169_rx_clear(tp);
4458 return -ENOMEM;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004459}
4460
4461static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4462{
4463 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4464}
4465
4466static int rtl8169_init_ring(struct net_device *dev)
4467{
4468 struct rtl8169_private *tp = netdev_priv(dev);
4469
4470 rtl8169_init_ring_indexes(tp);
4471
4472 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004473 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
Linus Torvalds1da177e2005-04-16 15:20:36 -07004474
Stanislaw Gruszka0ecbe1c2010-10-20 22:25:37 +00004475 return rtl8169_rx_fill(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004476}
4477
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00004478static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
Linus Torvalds1da177e2005-04-16 15:20:36 -07004479 struct TxDesc *desc)
4480{
4481 unsigned int len = tx_skb->len;
4482
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00004483 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4484
Linus Torvalds1da177e2005-04-16 15:20:36 -07004485 desc->opts1 = 0x00;
4486 desc->opts2 = 0x00;
4487 desc->addr = 0x00;
4488 tx_skb->len = 0;
4489}
4490
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004491static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4492 unsigned int n)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004493{
4494 unsigned int i;
4495
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004496 for (i = 0; i < n; i++) {
4497 unsigned int entry = (start + i) % NUM_TX_DESC;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004498 struct ring_info *tx_skb = tp->tx_skb + entry;
4499 unsigned int len = tx_skb->len;
4500
4501 if (len) {
4502 struct sk_buff *skb = tx_skb->skb;
4503
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00004504 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
Linus Torvalds1da177e2005-04-16 15:20:36 -07004505 tp->TxDescArray + entry);
4506 if (skb) {
Stanislaw Gruszkacac4b222010-10-20 22:25:40 +00004507 tp->dev->stats.tx_dropped++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004508 dev_kfree_skb(skb);
4509 tx_skb->skb = NULL;
4510 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004511 }
4512 }
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004513}
4514
4515static void rtl8169_tx_clear(struct rtl8169_private *tp)
4516{
4517 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004518 tp->cur_tx = tp->dirty_tx = 0;
4519}
4520
David Howellsc4028952006-11-22 14:57:56 +00004521static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004522{
4523 struct rtl8169_private *tp = netdev_priv(dev);
4524
David Howellsc4028952006-11-22 14:57:56 +00004525 PREPARE_DELAYED_WORK(&tp->task, task);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004526 schedule_delayed_work(&tp->task, 4);
4527}
4528
4529static void rtl8169_wait_for_quiescence(struct net_device *dev)
4530{
4531 struct rtl8169_private *tp = netdev_priv(dev);
4532 void __iomem *ioaddr = tp->mmio_addr;
4533
4534 synchronize_irq(dev->irq);
4535
4536 /* Wait for any pending NAPI task to complete */
Stephen Hemmingerbea33482007-10-03 16:41:36 -07004537 napi_disable(&tp->napi);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004538
4539 rtl8169_irq_mask_and_ack(ioaddr);
4540
David S. Millerd1d08d12008-01-07 20:53:33 -08004541 tp->intr_mask = 0xffff;
4542 RTL_W16(IntrMask, tp->intr_event);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07004543 napi_enable(&tp->napi);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004544}
4545
David Howellsc4028952006-11-22 14:57:56 +00004546static void rtl8169_reinit_task(struct work_struct *work)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004547{
David Howellsc4028952006-11-22 14:57:56 +00004548 struct rtl8169_private *tp =
4549 container_of(work, struct rtl8169_private, task.work);
4550 struct net_device *dev = tp->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004551 int ret;
4552
Francois Romieueb2a0212007-02-15 23:37:21 +01004553 rtnl_lock();
4554
4555 if (!netif_running(dev))
4556 goto out_unlock;
4557
4558 rtl8169_wait_for_quiescence(dev);
4559 rtl8169_close(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004560
4561 ret = rtl8169_open(dev);
4562 if (unlikely(ret < 0)) {
Joe Perchesbf82c182010-02-09 11:49:50 +00004563 if (net_ratelimit())
4564 netif_err(tp, drv, dev,
4565 "reinit failure (status = %d). Rescheduling\n",
4566 ret);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004567 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4568 }
Francois Romieueb2a0212007-02-15 23:37:21 +01004569
4570out_unlock:
4571 rtnl_unlock();
Linus Torvalds1da177e2005-04-16 15:20:36 -07004572}
4573
David Howellsc4028952006-11-22 14:57:56 +00004574static void rtl8169_reset_task(struct work_struct *work)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004575{
David Howellsc4028952006-11-22 14:57:56 +00004576 struct rtl8169_private *tp =
4577 container_of(work, struct rtl8169_private, task.work);
4578 struct net_device *dev = tp->dev;
Francois Romieu56de4142011-03-15 17:29:31 +01004579 int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004580
Francois Romieueb2a0212007-02-15 23:37:21 +01004581 rtnl_lock();
4582
Linus Torvalds1da177e2005-04-16 15:20:36 -07004583 if (!netif_running(dev))
Francois Romieueb2a0212007-02-15 23:37:21 +01004584 goto out_unlock;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004585
4586 rtl8169_wait_for_quiescence(dev);
4587
Francois Romieu56de4142011-03-15 17:29:31 +01004588 for (i = 0; i < NUM_RX_DESC; i++)
4589 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
4590
Linus Torvalds1da177e2005-04-16 15:20:36 -07004591 rtl8169_tx_clear(tp);
4592
Francois Romieu56de4142011-03-15 17:29:31 +01004593 rtl8169_init_ring_indexes(tp);
4594 rtl_hw_start(dev);
4595 netif_wake_queue(dev);
4596 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
Francois Romieueb2a0212007-02-15 23:37:21 +01004597
4598out_unlock:
4599 rtnl_unlock();
Linus Torvalds1da177e2005-04-16 15:20:36 -07004600}
4601
4602static void rtl8169_tx_timeout(struct net_device *dev)
4603{
4604 struct rtl8169_private *tp = netdev_priv(dev);
4605
françois romieue6de30d2011-01-03 15:08:37 +00004606 rtl8169_hw_reset(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004607
4608 /* Let's wait a bit while any (async) irq lands on */
4609 rtl8169_schedule_work(dev, rtl8169_reset_task);
4610}
4611
4612static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
Francois Romieu2b7b4312011-04-18 22:53:24 -07004613 u32 *opts)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004614{
4615 struct skb_shared_info *info = skb_shinfo(skb);
4616 unsigned int cur_frag, entry;
Jeff Garzika6343af2007-07-17 05:39:58 -04004617 struct TxDesc * uninitialized_var(txd);
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00004618 struct device *d = &tp->pci_dev->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004619
4620 entry = tp->cur_tx;
4621 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4622 skb_frag_t *frag = info->frags + cur_frag;
4623 dma_addr_t mapping;
4624 u32 status, len;
4625 void *addr;
4626
4627 entry = (entry + 1) % NUM_TX_DESC;
4628
4629 txd = tp->TxDescArray + entry;
4630 len = frag->size;
4631 addr = ((void *) page_address(frag->page)) + frag->page_offset;
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00004632 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
Stanislaw Gruszkad827d862010-10-20 22:25:43 +00004633 if (unlikely(dma_mapping_error(d, mapping))) {
4634 if (net_ratelimit())
4635 netif_err(tp, drv, tp->dev,
4636 "Failed to map TX fragments DMA!\n");
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004637 goto err_out;
Stanislaw Gruszkad827d862010-10-20 22:25:43 +00004638 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004639
Francois Romieucecb5fd2011-04-01 10:21:07 +02004640 /* Anti gcc 2.95.3 bugware (sic) */
Francois Romieu2b7b4312011-04-18 22:53:24 -07004641 status = opts[0] | len |
4642 (RingEnd * !((entry + 1) % NUM_TX_DESC));
Linus Torvalds1da177e2005-04-16 15:20:36 -07004643
4644 txd->opts1 = cpu_to_le32(status);
Francois Romieu2b7b4312011-04-18 22:53:24 -07004645 txd->opts2 = cpu_to_le32(opts[1]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004646 txd->addr = cpu_to_le64(mapping);
4647
4648 tp->tx_skb[entry].len = len;
4649 }
4650
4651 if (cur_frag) {
4652 tp->tx_skb[entry].skb = skb;
4653 txd->opts1 |= cpu_to_le32(LastFrag);
4654 }
4655
4656 return cur_frag;
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004657
4658err_out:
4659 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4660 return -EIO;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004661}
4662
Francois Romieu2b7b4312011-04-18 22:53:24 -07004663static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
4664 struct sk_buff *skb, u32 *opts)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004665{
Francois Romieu2b7b4312011-04-18 22:53:24 -07004666 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
Michał Mirosław350fb322011-04-08 06:35:56 +00004667 u32 mss = skb_shinfo(skb)->gso_size;
Francois Romieu2b7b4312011-04-18 22:53:24 -07004668 int offset = info->opts_offset;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004669
Francois Romieu2b7b4312011-04-18 22:53:24 -07004670 if (mss) {
4671 opts[0] |= TD_LSO;
4672 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
4673 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
Arnaldo Carvalho de Meloeddc9ec2007-04-20 22:47:35 -07004674 const struct iphdr *ip = ip_hdr(skb);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004675
4676 if (ip->protocol == IPPROTO_TCP)
Francois Romieu2b7b4312011-04-18 22:53:24 -07004677 opts[offset] |= info->checksum.tcp;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004678 else if (ip->protocol == IPPROTO_UDP)
Francois Romieu2b7b4312011-04-18 22:53:24 -07004679 opts[offset] |= info->checksum.udp;
4680 else
4681 WARN_ON_ONCE(1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004682 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004683}
4684
Stephen Hemminger613573252009-08-31 19:50:58 +00004685static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4686 struct net_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004687{
4688 struct rtl8169_private *tp = netdev_priv(dev);
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004689 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004690 struct TxDesc *txd = tp->TxDescArray + entry;
4691 void __iomem *ioaddr = tp->mmio_addr;
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00004692 struct device *d = &tp->pci_dev->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004693 dma_addr_t mapping;
4694 u32 status, len;
Francois Romieu2b7b4312011-04-18 22:53:24 -07004695 u32 opts[2];
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004696 int frags;
Francois Romieu5b0384f2006-08-16 16:00:01 +02004697
Linus Torvalds1da177e2005-04-16 15:20:36 -07004698 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
Joe Perchesbf82c182010-02-09 11:49:50 +00004699 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004700 goto err_stop_0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004701 }
4702
4703 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004704 goto err_stop_0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004705
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004706 len = skb_headlen(skb);
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00004707 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
Stanislaw Gruszkad827d862010-10-20 22:25:43 +00004708 if (unlikely(dma_mapping_error(d, mapping))) {
4709 if (net_ratelimit())
4710 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004711 goto err_dma_0;
Stanislaw Gruszkad827d862010-10-20 22:25:43 +00004712 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004713
4714 tp->tx_skb[entry].len = len;
4715 txd->addr = cpu_to_le64(mapping);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004716
Francois Romieu2b7b4312011-04-18 22:53:24 -07004717 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4718 opts[0] = DescOwn;
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004719
Francois Romieu2b7b4312011-04-18 22:53:24 -07004720 rtl8169_tso_csum(tp, skb, opts);
4721
4722 frags = rtl8169_xmit_frags(tp, skb, opts);
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004723 if (frags < 0)
4724 goto err_dma_1;
4725 else if (frags)
Francois Romieu2b7b4312011-04-18 22:53:24 -07004726 opts[0] |= FirstFrag;
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004727 else {
Francois Romieu2b7b4312011-04-18 22:53:24 -07004728 opts[0] |= FirstFrag | LastFrag;
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004729 tp->tx_skb[entry].skb = skb;
4730 }
4731
Francois Romieu2b7b4312011-04-18 22:53:24 -07004732 txd->opts2 = cpu_to_le32(opts[1]);
4733
Linus Torvalds1da177e2005-04-16 15:20:36 -07004734 wmb();
4735
Francois Romieucecb5fd2011-04-01 10:21:07 +02004736 /* Anti gcc 2.95.3 bugware (sic) */
Francois Romieu2b7b4312011-04-18 22:53:24 -07004737 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
Linus Torvalds1da177e2005-04-16 15:20:36 -07004738 txd->opts1 = cpu_to_le32(status);
4739
Linus Torvalds1da177e2005-04-16 15:20:36 -07004740 tp->cur_tx += frags + 1;
4741
David Dillow4c020a92010-03-03 16:33:10 +00004742 wmb();
Linus Torvalds1da177e2005-04-16 15:20:36 -07004743
Francois Romieucecb5fd2011-04-01 10:21:07 +02004744 RTL_W8(TxPoll, NPQ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004745
4746 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4747 netif_stop_queue(dev);
4748 smp_rmb();
4749 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4750 netif_wake_queue(dev);
4751 }
4752
Stephen Hemminger613573252009-08-31 19:50:58 +00004753 return NETDEV_TX_OK;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004754
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004755err_dma_1:
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00004756 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
Stanislaw Gruszka3eafe502010-10-20 22:25:36 +00004757err_dma_0:
4758 dev_kfree_skb(skb);
4759 dev->stats.tx_dropped++;
4760 return NETDEV_TX_OK;
4761
4762err_stop_0:
Linus Torvalds1da177e2005-04-16 15:20:36 -07004763 netif_stop_queue(dev);
Francois Romieucebf8cc2007-10-18 12:06:54 +02004764 dev->stats.tx_dropped++;
Stephen Hemminger613573252009-08-31 19:50:58 +00004765 return NETDEV_TX_BUSY;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004766}
4767
4768static void rtl8169_pcierr_interrupt(struct net_device *dev)
4769{
4770 struct rtl8169_private *tp = netdev_priv(dev);
4771 struct pci_dev *pdev = tp->pci_dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004772 u16 pci_status, pci_cmd;
4773
4774 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4775 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4776
Joe Perchesbf82c182010-02-09 11:49:50 +00004777 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4778 pci_cmd, pci_status);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004779
4780 /*
4781 * The recovery sequence below admits a very elaborated explanation:
4782 * - it seems to work;
Francois Romieud03902b2006-11-23 00:00:42 +01004783 * - I did not see what else could be done;
4784 * - it makes iop3xx happy.
Linus Torvalds1da177e2005-04-16 15:20:36 -07004785 *
4786 * Feel free to adjust to your needs.
4787 */
Francois Romieua27993f2006-12-18 00:04:19 +01004788 if (pdev->broken_parity_status)
Francois Romieud03902b2006-11-23 00:00:42 +01004789 pci_cmd &= ~PCI_COMMAND_PARITY;
4790 else
4791 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4792
4793 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004794
4795 pci_write_config_word(pdev, PCI_STATUS,
4796 pci_status & (PCI_STATUS_DETECTED_PARITY |
4797 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4798 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4799
4800 /* The infamous DAC f*ckup only happens at boot time */
4801 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
françois romieue6de30d2011-01-03 15:08:37 +00004802 void __iomem *ioaddr = tp->mmio_addr;
4803
Joe Perchesbf82c182010-02-09 11:49:50 +00004804 netif_info(tp, intr, dev, "disabling PCI DAC\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07004805 tp->cp_cmd &= ~PCIDAC;
4806 RTL_W16(CPlusCmd, tp->cp_cmd);
4807 dev->features &= ~NETIF_F_HIGHDMA;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004808 }
4809
françois romieue6de30d2011-01-03 15:08:37 +00004810 rtl8169_hw_reset(tp);
Francois Romieud03902b2006-11-23 00:00:42 +01004811
4812 rtl8169_schedule_work(dev, rtl8169_reinit_task);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004813}
4814
Francois Romieu07d3f512007-02-21 22:40:46 +01004815static void rtl8169_tx_interrupt(struct net_device *dev,
4816 struct rtl8169_private *tp,
4817 void __iomem *ioaddr)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004818{
4819 unsigned int dirty_tx, tx_left;
4820
Linus Torvalds1da177e2005-04-16 15:20:36 -07004821 dirty_tx = tp->dirty_tx;
4822 smp_rmb();
4823 tx_left = tp->cur_tx - dirty_tx;
4824
4825 while (tx_left > 0) {
4826 unsigned int entry = dirty_tx % NUM_TX_DESC;
4827 struct ring_info *tx_skb = tp->tx_skb + entry;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004828 u32 status;
4829
4830 rmb();
4831 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4832 if (status & DescOwn)
4833 break;
4834
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00004835 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4836 tp->TxDescArray + entry);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004837 if (status & LastFrag) {
Stanislaw Gruszkacac4b222010-10-20 22:25:40 +00004838 dev->stats.tx_packets++;
4839 dev->stats.tx_bytes += tx_skb->skb->len;
Eric Dumazet87433bf2009-06-09 22:55:53 +00004840 dev_kfree_skb(tx_skb->skb);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004841 tx_skb->skb = NULL;
4842 }
4843 dirty_tx++;
4844 tx_left--;
4845 }
4846
4847 if (tp->dirty_tx != dirty_tx) {
4848 tp->dirty_tx = dirty_tx;
4849 smp_wmb();
4850 if (netif_queue_stopped(dev) &&
4851 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4852 netif_wake_queue(dev);
4853 }
Francois Romieud78ae2d2007-08-26 20:08:19 +02004854 /*
4855 * 8168 hack: TxPoll requests are lost when the Tx packets are
4856 * too close. Let's kick an extra TxPoll request when a burst
4857 * of start_xmit activity is detected (if it is not detected,
4858 * it is slow enough). -- FR
4859 */
4860 smp_rmb();
4861 if (tp->cur_tx != dirty_tx)
4862 RTL_W8(TxPoll, NPQ);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004863 }
4864}
4865
Francois Romieu126fa4b2005-05-12 20:09:17 -04004866static inline int rtl8169_fragmented_frame(u32 status)
4867{
4868 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4869}
4870
Eric Dumazetadea1ac72010-09-05 20:04:05 -07004871static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004872{
Linus Torvalds1da177e2005-04-16 15:20:36 -07004873 u32 status = opts1 & RxProtoMask;
4874
4875 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
Shan Weid5d3ebe2010-11-12 00:15:25 +00004876 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
Linus Torvalds1da177e2005-04-16 15:20:36 -07004877 skb->ip_summed = CHECKSUM_UNNECESSARY;
4878 else
Eric Dumazetbc8acf22010-09-02 13:07:41 -07004879 skb_checksum_none_assert(skb);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004880}
4881
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004882static struct sk_buff *rtl8169_try_rx_copy(void *data,
4883 struct rtl8169_private *tp,
4884 int pkt_size,
4885 dma_addr_t addr)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004886{
Stephen Hemmingerb4496552007-06-17 01:06:49 +02004887 struct sk_buff *skb;
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00004888 struct device *d = &tp->pci_dev->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004889
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004890 data = rtl8169_align(data);
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00004891 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004892 prefetch(data);
4893 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4894 if (skb)
4895 memcpy(skb->data, data, pkt_size);
Stanislaw Gruszka48addcc2010-10-20 22:25:39 +00004896 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4897
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004898 return skb;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004899}
4900
Francois Romieu07d3f512007-02-21 22:40:46 +01004901static int rtl8169_rx_interrupt(struct net_device *dev,
4902 struct rtl8169_private *tp,
Stephen Hemmingerbea33482007-10-03 16:41:36 -07004903 void __iomem *ioaddr, u32 budget)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004904{
4905 unsigned int cur_rx, rx_left;
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004906 unsigned int count;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004907
Linus Torvalds1da177e2005-04-16 15:20:36 -07004908 cur_rx = tp->cur_rx;
4909 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
Francois Romieu865c6522008-05-11 14:51:00 +02004910 rx_left = min(rx_left, budget);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004911
Richard Dawe4dcb7d32005-05-27 21:12:00 +02004912 for (; rx_left > 0; rx_left--, cur_rx++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07004913 unsigned int entry = cur_rx % NUM_RX_DESC;
Francois Romieu126fa4b2005-05-12 20:09:17 -04004914 struct RxDesc *desc = tp->RxDescArray + entry;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004915 u32 status;
4916
4917 rmb();
Francois Romieu126fa4b2005-05-12 20:09:17 -04004918 status = le32_to_cpu(desc->opts1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004919
4920 if (status & DescOwn)
4921 break;
Richard Dawe4dcb7d32005-05-27 21:12:00 +02004922 if (unlikely(status & RxRES)) {
Joe Perchesbf82c182010-02-09 11:49:50 +00004923 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4924 status);
Francois Romieucebf8cc2007-10-18 12:06:54 +02004925 dev->stats.rx_errors++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004926 if (status & (RxRWT | RxRUNT))
Francois Romieucebf8cc2007-10-18 12:06:54 +02004927 dev->stats.rx_length_errors++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004928 if (status & RxCRC)
Francois Romieucebf8cc2007-10-18 12:06:54 +02004929 dev->stats.rx_crc_errors++;
Francois Romieu9dccf612006-05-14 12:31:17 +02004930 if (status & RxFOVF) {
4931 rtl8169_schedule_work(dev, rtl8169_reset_task);
Francois Romieucebf8cc2007-10-18 12:06:54 +02004932 dev->stats.rx_fifo_errors++;
Francois Romieu9dccf612006-05-14 12:31:17 +02004933 }
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004934 rtl8169_mark_to_asic(desc, rx_buf_sz);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004935 } else {
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004936 struct sk_buff *skb;
Stephen Hemmingerb4496552007-06-17 01:06:49 +02004937 dma_addr_t addr = le64_to_cpu(desc->addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004938 int pkt_size = (status & 0x00001FFF) - 4;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004939
Francois Romieu126fa4b2005-05-12 20:09:17 -04004940 /*
4941 * The driver does not support incoming fragmented
4942 * frames. They are seen as a symptom of over-mtu
4943 * sized frames.
4944 */
4945 if (unlikely(rtl8169_fragmented_frame(status))) {
Francois Romieucebf8cc2007-10-18 12:06:54 +02004946 dev->stats.rx_dropped++;
4947 dev->stats.rx_length_errors++;
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004948 rtl8169_mark_to_asic(desc, rx_buf_sz);
Richard Dawe4dcb7d32005-05-27 21:12:00 +02004949 continue;
Francois Romieu126fa4b2005-05-12 20:09:17 -04004950 }
4951
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004952 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
4953 tp, pkt_size, addr);
4954 rtl8169_mark_to_asic(desc, rx_buf_sz);
4955 if (!skb) {
4956 dev->stats.rx_dropped++;
4957 continue;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004958 }
4959
Eric Dumazetadea1ac72010-09-05 20:04:05 -07004960 rtl8169_rx_csum(skb, status);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004961 skb_put(skb, pkt_size);
4962 skb->protocol = eth_type_trans(skb, dev);
4963
Francois Romieu7a8fc772011-03-01 17:18:33 +01004964 rtl8169_rx_vlan_tag(desc, skb);
4965
Francois Romieu56de4142011-03-15 17:29:31 +01004966 napi_gro_receive(&tp->napi, skb);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004967
Francois Romieucebf8cc2007-10-18 12:06:54 +02004968 dev->stats.rx_bytes += pkt_size;
4969 dev->stats.rx_packets++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004970 }
Francois Romieu6dccd162007-02-13 23:38:05 +01004971
4972 /* Work around for AMD plateform. */
Al Viro95e09182007-12-22 18:55:39 +00004973 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
Francois Romieu6dccd162007-02-13 23:38:05 +01004974 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4975 desc->opts2 = 0;
4976 cur_rx++;
4977 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004978 }
4979
4980 count = cur_rx - tp->cur_rx;
4981 tp->cur_rx = cur_rx;
4982
Eric Dumazet6f0333b2010-10-11 11:17:47 +00004983 tp->dirty_rx += count;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004984
4985 return count;
4986}
4987
Francois Romieu07d3f512007-02-21 22:40:46 +01004988static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004989{
Francois Romieu07d3f512007-02-21 22:40:46 +01004990 struct net_device *dev = dev_instance;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004991 struct rtl8169_private *tp = netdev_priv(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004992 void __iomem *ioaddr = tp->mmio_addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004993 int handled = 0;
Francois Romieu865c6522008-05-11 14:51:00 +02004994 int status;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004995
David Dillowf11a3772009-05-22 15:29:34 +00004996 /* loop handling interrupts until we have no new ones or
4997 * we hit a invalid/hotplug case.
4998 */
Francois Romieu865c6522008-05-11 14:51:00 +02004999 status = RTL_R16(IntrStatus);
David Dillowf11a3772009-05-22 15:29:34 +00005000 while (status && status != 0xffff) {
5001 handled = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005002
David Dillowf11a3772009-05-22 15:29:34 +00005003 /* Handle all of the error cases first. These will reset
5004 * the chip, so just exit the loop.
5005 */
5006 if (unlikely(!netif_running(dev))) {
5007 rtl8169_asic_down(ioaddr);
5008 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005009 }
David Dillowf11a3772009-05-22 15:29:34 +00005010
Francois Romieu1519e572011-02-03 12:02:36 +01005011 if (unlikely(status & RxFIFOOver)) {
5012 switch (tp->mac_version) {
5013 /* Work around for rx fifo overflow */
5014 case RTL_GIGA_MAC_VER_11:
5015 case RTL_GIGA_MAC_VER_22:
5016 case RTL_GIGA_MAC_VER_26:
5017 netif_stop_queue(dev);
5018 rtl8169_tx_timeout(dev);
5019 goto done;
Francois Romieuf60ac8e2011-02-03 17:27:52 +01005020 /* Testers needed. */
5021 case RTL_GIGA_MAC_VER_17:
5022 case RTL_GIGA_MAC_VER_19:
5023 case RTL_GIGA_MAC_VER_20:
5024 case RTL_GIGA_MAC_VER_21:
5025 case RTL_GIGA_MAC_VER_23:
5026 case RTL_GIGA_MAC_VER_24:
5027 case RTL_GIGA_MAC_VER_27:
5028 case RTL_GIGA_MAC_VER_28:
hayeswang4804b3b2011-03-21 01:50:29 +00005029 case RTL_GIGA_MAC_VER_31:
Francois Romieu1519e572011-02-03 12:02:36 +01005030 /* Experimental science. Pktgen proof. */
5031 case RTL_GIGA_MAC_VER_12:
5032 case RTL_GIGA_MAC_VER_25:
5033 if (status == RxFIFOOver)
5034 goto done;
5035 break;
5036 default:
5037 break;
5038 }
David Dillowf11a3772009-05-22 15:29:34 +00005039 }
5040
5041 if (unlikely(status & SYSErr)) {
5042 rtl8169_pcierr_interrupt(dev);
5043 break;
5044 }
5045
5046 if (status & LinkChg)
Rafael J. Wysockie4fbce72010-12-08 15:32:14 +00005047 __rtl8169_check_link_status(dev, tp, ioaddr, true);
David Dillowf11a3772009-05-22 15:29:34 +00005048
5049 /* We need to see the lastest version of tp->intr_mask to
5050 * avoid ignoring an MSI interrupt and having to wait for
5051 * another event which may never come.
5052 */
5053 smp_rmb();
5054 if (status & tp->intr_mask & tp->napi_event) {
5055 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5056 tp->intr_mask = ~tp->napi_event;
5057
5058 if (likely(napi_schedule_prep(&tp->napi)))
5059 __napi_schedule(&tp->napi);
Joe Perchesbf82c182010-02-09 11:49:50 +00005060 else
5061 netif_info(tp, intr, dev,
5062 "interrupt %04x in poll\n", status);
David Dillowf11a3772009-05-22 15:29:34 +00005063 }
5064
5065 /* We only get a new MSI interrupt when all active irq
5066 * sources on the chip have been acknowledged. So, ack
5067 * everything we've seen and check if new sources have become
5068 * active to avoid blocking all interrupts from the chip.
5069 */
5070 RTL_W16(IntrStatus,
5071 (status & RxFIFOOver) ? (status | RxOverflow) : status);
5072 status = RTL_R16(IntrStatus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005073 }
Francois Romieu1519e572011-02-03 12:02:36 +01005074done:
Linus Torvalds1da177e2005-04-16 15:20:36 -07005075 return IRQ_RETVAL(handled);
5076}
5077
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005078static int rtl8169_poll(struct napi_struct *napi, int budget)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005079{
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005080 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5081 struct net_device *dev = tp->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005082 void __iomem *ioaddr = tp->mmio_addr;
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005083 int work_done;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005084
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005085 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005086 rtl8169_tx_interrupt(dev, tp, ioaddr);
5087
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005088 if (work_done < budget) {
Ben Hutchings288379f2009-01-19 16:43:59 -08005089 napi_complete(napi);
David Dillowf11a3772009-05-22 15:29:34 +00005090
5091 /* We need for force the visibility of tp->intr_mask
5092 * for other CPUs, as we can loose an MSI interrupt
5093 * and potentially wait for a retransmit timeout if we don't.
5094 * The posted write to IntrMask is safe, as it will
5095 * eventually make it to the chip and we won't loose anything
5096 * until it does.
Linus Torvalds1da177e2005-04-16 15:20:36 -07005097 */
David Dillowf11a3772009-05-22 15:29:34 +00005098 tp->intr_mask = 0xffff;
David Dillow4c020a92010-03-03 16:33:10 +00005099 wmb();
Francois Romieu0e485152007-02-20 00:00:26 +01005100 RTL_W16(IntrMask, tp->intr_event);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005101 }
5102
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005103 return work_done;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005104}
Linus Torvalds1da177e2005-04-16 15:20:36 -07005105
Francois Romieu523a6092008-09-10 22:28:56 +02005106static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5107{
5108 struct rtl8169_private *tp = netdev_priv(dev);
5109
5110 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5111 return;
5112
5113 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5114 RTL_W32(RxMissed, 0);
5115}
5116
Linus Torvalds1da177e2005-04-16 15:20:36 -07005117static void rtl8169_down(struct net_device *dev)
5118{
5119 struct rtl8169_private *tp = netdev_priv(dev);
5120 void __iomem *ioaddr = tp->mmio_addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005121
Francois Romieu4876cc12011-03-11 21:07:11 +01005122 del_timer_sync(&tp->timer);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005123
5124 netif_stop_queue(dev);
5125
Stephen Hemminger93dd79e2007-10-28 17:14:06 +01005126 napi_disable(&tp->napi);
Stephen Hemminger93dd79e2007-10-28 17:14:06 +01005127
Linus Torvalds1da177e2005-04-16 15:20:36 -07005128 spin_lock_irq(&tp->lock);
5129
5130 rtl8169_asic_down(ioaddr);
Stanislaw Gruszka323bb682010-10-20 22:25:41 +00005131 /*
5132 * At this point device interrupts can not be enabled in any function,
5133 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5134 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5135 */
Francois Romieu523a6092008-09-10 22:28:56 +02005136 rtl8169_rx_missed(dev, ioaddr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005137
5138 spin_unlock_irq(&tp->lock);
5139
5140 synchronize_irq(dev->irq);
5141
Linus Torvalds1da177e2005-04-16 15:20:36 -07005142 /* Give a racing hard_start_xmit a few cycles to complete. */
Paul E. McKenneyfbd568a3e2005-05-01 08:59:04 -07005143 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
Linus Torvalds1da177e2005-04-16 15:20:36 -07005144
Linus Torvalds1da177e2005-04-16 15:20:36 -07005145 rtl8169_tx_clear(tp);
5146
5147 rtl8169_rx_clear(tp);
françois romieu065c27c2011-01-03 15:08:12 +00005148
5149 rtl_pll_power_down(tp);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005150}
5151
5152static int rtl8169_close(struct net_device *dev)
5153{
5154 struct rtl8169_private *tp = netdev_priv(dev);
5155 struct pci_dev *pdev = tp->pci_dev;
5156
Rafael J. Wysockie1759442010-03-14 14:33:51 +00005157 pm_runtime_get_sync(&pdev->dev);
5158
Francois Romieucecb5fd2011-04-01 10:21:07 +02005159 /* Update counters before going down */
Ivan Vecera355423d2009-02-06 21:49:57 -08005160 rtl8169_update_counters(dev);
5161
Linus Torvalds1da177e2005-04-16 15:20:36 -07005162 rtl8169_down(dev);
5163
5164 free_irq(dev->irq, dev);
5165
Stanislaw Gruszka82553bb2010-10-08 04:25:01 +00005166 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5167 tp->RxPhyAddr);
5168 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5169 tp->TxPhyAddr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005170 tp->TxDescArray = NULL;
5171 tp->RxDescArray = NULL;
5172
Rafael J. Wysockie1759442010-03-14 14:33:51 +00005173 pm_runtime_put_sync(&pdev->dev);
5174
Linus Torvalds1da177e2005-04-16 15:20:36 -07005175 return 0;
5176}
5177
Francois Romieu07ce4062007-02-23 23:36:39 +01005178static void rtl_set_rx_mode(struct net_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005179{
5180 struct rtl8169_private *tp = netdev_priv(dev);
5181 void __iomem *ioaddr = tp->mmio_addr;
5182 unsigned long flags;
5183 u32 mc_filter[2]; /* Multicast hash filter */
Francois Romieu07d3f512007-02-21 22:40:46 +01005184 int rx_mode;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005185 u32 tmp = 0;
5186
5187 if (dev->flags & IFF_PROMISC) {
5188 /* Unconditionally log net taps. */
Joe Perchesbf82c182010-02-09 11:49:50 +00005189 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07005190 rx_mode =
5191 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5192 AcceptAllPhys;
5193 mc_filter[1] = mc_filter[0] = 0xffffffff;
Jiri Pirko4cd24ea2010-02-08 04:30:35 +00005194 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
Joe Perches8e95a202009-12-03 07:58:21 +00005195 (dev->flags & IFF_ALLMULTI)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07005196 /* Too many to filter perfectly -- accept all multicasts. */
5197 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5198 mc_filter[1] = mc_filter[0] = 0xffffffff;
5199 } else {
Jiri Pirko22bedad32010-04-01 21:22:57 +00005200 struct netdev_hw_addr *ha;
Francois Romieu07d3f512007-02-21 22:40:46 +01005201
Linus Torvalds1da177e2005-04-16 15:20:36 -07005202 rx_mode = AcceptBroadcast | AcceptMyPhys;
5203 mc_filter[1] = mc_filter[0] = 0;
Jiri Pirko22bedad32010-04-01 21:22:57 +00005204 netdev_for_each_mc_addr(ha, dev) {
5205 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005206 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5207 rx_mode |= AcceptMulticast;
5208 }
5209 }
5210
5211 spin_lock_irqsave(&tp->lock, flags);
5212
5213 tmp = rtl8169_rx_config | rx_mode |
Francois Romieu2b7b4312011-04-18 22:53:24 -07005214 (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005215
Francois Romieuf887cce2008-07-17 22:24:18 +02005216 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
Francois Romieu1087f4f2007-12-26 22:46:05 +01005217 u32 data = mc_filter[0];
5218
5219 mc_filter[0] = swab32(mc_filter[1]);
5220 mc_filter[1] = swab32(data);
Francois Romieubcf0bf92006-07-26 23:14:13 +02005221 }
5222
Linus Torvalds1da177e2005-04-16 15:20:36 -07005223 RTL_W32(MAR0 + 4, mc_filter[1]);
Francois Romieu78f1cd02010-03-27 19:35:46 -07005224 RTL_W32(MAR0 + 0, mc_filter[0]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005225
Francois Romieu57a9f232007-06-04 22:10:15 +02005226 RTL_W32(RxConfig, tmp);
5227
Linus Torvalds1da177e2005-04-16 15:20:36 -07005228 spin_unlock_irqrestore(&tp->lock, flags);
5229}
5230
5231/**
5232 * rtl8169_get_stats - Get rtl8169 read/write statistics
5233 * @dev: The Ethernet Device to get statistics for
5234 *
5235 * Get TX/RX statistics for rtl8169
5236 */
5237static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
5238{
5239 struct rtl8169_private *tp = netdev_priv(dev);
5240 void __iomem *ioaddr = tp->mmio_addr;
5241 unsigned long flags;
5242
5243 if (netif_running(dev)) {
5244 spin_lock_irqsave(&tp->lock, flags);
Francois Romieu523a6092008-09-10 22:28:56 +02005245 rtl8169_rx_missed(dev, ioaddr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005246 spin_unlock_irqrestore(&tp->lock, flags);
5247 }
Francois Romieu5b0384f2006-08-16 16:00:01 +02005248
Francois Romieucebf8cc2007-10-18 12:06:54 +02005249 return &dev->stats;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005250}
5251
Rafael J. Wysocki861ab442009-04-05 08:40:04 +00005252static void rtl8169_net_suspend(struct net_device *dev)
Francois Romieu5d06a992006-02-23 00:47:58 +01005253{
françois romieu065c27c2011-01-03 15:08:12 +00005254 struct rtl8169_private *tp = netdev_priv(dev);
5255
Francois Romieu5d06a992006-02-23 00:47:58 +01005256 if (!netif_running(dev))
Rafael J. Wysocki861ab442009-04-05 08:40:04 +00005257 return;
Francois Romieu5d06a992006-02-23 00:47:58 +01005258
françois romieu065c27c2011-01-03 15:08:12 +00005259 rtl_pll_power_down(tp);
5260
Francois Romieu5d06a992006-02-23 00:47:58 +01005261 netif_device_detach(dev);
5262 netif_stop_queue(dev);
Rafael J. Wysocki861ab442009-04-05 08:40:04 +00005263}
Francois Romieu5d06a992006-02-23 00:47:58 +01005264
Rafael J. Wysocki861ab442009-04-05 08:40:04 +00005265#ifdef CONFIG_PM
5266
5267static int rtl8169_suspend(struct device *device)
5268{
5269 struct pci_dev *pdev = to_pci_dev(device);
5270 struct net_device *dev = pci_get_drvdata(pdev);
5271
5272 rtl8169_net_suspend(dev);
Francois Romieu1371fa62007-04-02 23:01:11 +02005273
Francois Romieu5d06a992006-02-23 00:47:58 +01005274 return 0;
5275}
5276
Rafael J. Wysockie1759442010-03-14 14:33:51 +00005277static void __rtl8169_resume(struct net_device *dev)
5278{
françois romieu065c27c2011-01-03 15:08:12 +00005279 struct rtl8169_private *tp = netdev_priv(dev);
5280
Rafael J. Wysockie1759442010-03-14 14:33:51 +00005281 netif_device_attach(dev);
françois romieu065c27c2011-01-03 15:08:12 +00005282
5283 rtl_pll_power_up(tp);
5284
Rafael J. Wysockie1759442010-03-14 14:33:51 +00005285 rtl8169_schedule_work(dev, rtl8169_reset_task);
5286}
5287
Rafael J. Wysocki861ab442009-04-05 08:40:04 +00005288static int rtl8169_resume(struct device *device)
Francois Romieu5d06a992006-02-23 00:47:58 +01005289{
Rafael J. Wysocki861ab442009-04-05 08:40:04 +00005290 struct pci_dev *pdev = to_pci_dev(device);
Francois Romieu5d06a992006-02-23 00:47:58 +01005291 struct net_device *dev = pci_get_drvdata(pdev);
Stanislaw Gruszkafccec102010-10-20 22:25:42 +00005292 struct rtl8169_private *tp = netdev_priv(dev);
5293
5294 rtl8169_init_phy(dev, tp);
Francois Romieu5d06a992006-02-23 00:47:58 +01005295
Rafael J. Wysockie1759442010-03-14 14:33:51 +00005296 if (netif_running(dev))
5297 __rtl8169_resume(dev);
Francois Romieu5d06a992006-02-23 00:47:58 +01005298
Francois Romieu5d06a992006-02-23 00:47:58 +01005299 return 0;
5300}
5301
Rafael J. Wysockie1759442010-03-14 14:33:51 +00005302static int rtl8169_runtime_suspend(struct device *device)
5303{
5304 struct pci_dev *pdev = to_pci_dev(device);
5305 struct net_device *dev = pci_get_drvdata(pdev);
5306 struct rtl8169_private *tp = netdev_priv(dev);
5307
5308 if (!tp->TxDescArray)
5309 return 0;
5310
5311 spin_lock_irq(&tp->lock);
5312 tp->saved_wolopts = __rtl8169_get_wol(tp);
5313 __rtl8169_set_wol(tp, WAKE_ANY);
5314 spin_unlock_irq(&tp->lock);
5315
5316 rtl8169_net_suspend(dev);
5317
5318 return 0;
5319}
5320
5321static int rtl8169_runtime_resume(struct device *device)
5322{
5323 struct pci_dev *pdev = to_pci_dev(device);
5324 struct net_device *dev = pci_get_drvdata(pdev);
5325 struct rtl8169_private *tp = netdev_priv(dev);
5326
5327 if (!tp->TxDescArray)
5328 return 0;
5329
5330 spin_lock_irq(&tp->lock);
5331 __rtl8169_set_wol(tp, tp->saved_wolopts);
5332 tp->saved_wolopts = 0;
5333 spin_unlock_irq(&tp->lock);
5334
Stanislaw Gruszkafccec102010-10-20 22:25:42 +00005335 rtl8169_init_phy(dev, tp);
5336
Rafael J. Wysockie1759442010-03-14 14:33:51 +00005337 __rtl8169_resume(dev);
5338
5339 return 0;
5340}
5341
5342static int rtl8169_runtime_idle(struct device *device)
5343{
5344 struct pci_dev *pdev = to_pci_dev(device);
5345 struct net_device *dev = pci_get_drvdata(pdev);
5346 struct rtl8169_private *tp = netdev_priv(dev);
5347
Rafael J. Wysockie4fbce72010-12-08 15:32:14 +00005348 return tp->TxDescArray ? -EBUSY : 0;
Rafael J. Wysockie1759442010-03-14 14:33:51 +00005349}
5350
Alexey Dobriyan47145212009-12-14 18:00:08 -08005351static const struct dev_pm_ops rtl8169_pm_ops = {
Francois Romieucecb5fd2011-04-01 10:21:07 +02005352 .suspend = rtl8169_suspend,
5353 .resume = rtl8169_resume,
5354 .freeze = rtl8169_suspend,
5355 .thaw = rtl8169_resume,
5356 .poweroff = rtl8169_suspend,
5357 .restore = rtl8169_resume,
5358 .runtime_suspend = rtl8169_runtime_suspend,
5359 .runtime_resume = rtl8169_runtime_resume,
5360 .runtime_idle = rtl8169_runtime_idle,
Rafael J. Wysocki861ab442009-04-05 08:40:04 +00005361};
5362
5363#define RTL8169_PM_OPS (&rtl8169_pm_ops)
5364
5365#else /* !CONFIG_PM */
5366
5367#define RTL8169_PM_OPS NULL
5368
5369#endif /* !CONFIG_PM */
5370
Francois Romieu1765f952008-09-13 17:21:40 +02005371static void rtl_shutdown(struct pci_dev *pdev)
5372{
Rafael J. Wysocki861ab442009-04-05 08:40:04 +00005373 struct net_device *dev = pci_get_drvdata(pdev);
françois romieu4bb3f522009-06-17 11:41:45 +00005374 struct rtl8169_private *tp = netdev_priv(dev);
5375 void __iomem *ioaddr = tp->mmio_addr;
Francois Romieu1765f952008-09-13 17:21:40 +02005376
Rafael J. Wysocki861ab442009-04-05 08:40:04 +00005377 rtl8169_net_suspend(dev);
5378
Francois Romieucecb5fd2011-04-01 10:21:07 +02005379 /* Restore original MAC address */
Ivan Veceracc098dc2009-11-29 23:12:52 -08005380 rtl_rar_set(tp, dev->perm_addr);
5381
françois romieu4bb3f522009-06-17 11:41:45 +00005382 spin_lock_irq(&tp->lock);
5383
5384 rtl8169_asic_down(ioaddr);
5385
5386 spin_unlock_irq(&tp->lock);
5387
Rafael J. Wysocki861ab442009-04-05 08:40:04 +00005388 if (system_state == SYSTEM_POWER_OFF) {
françois romieuca52efd2009-07-24 12:34:19 +00005389 /* WoL fails with some 8168 when the receiver is disabled. */
5390 if (tp->features & RTL_FEATURE_WOL) {
5391 pci_clear_master(pdev);
5392
5393 RTL_W8(ChipCmd, CmdRxEnb);
5394 /* PCI commit */
5395 RTL_R8(ChipCmd);
5396 }
5397
Rafael J. Wysocki861ab442009-04-05 08:40:04 +00005398 pci_wake_from_d3(pdev, true);
5399 pci_set_power_state(pdev, PCI_D3hot);
5400 }
5401}
Francois Romieu5d06a992006-02-23 00:47:58 +01005402
Linus Torvalds1da177e2005-04-16 15:20:36 -07005403static struct pci_driver rtl8169_pci_driver = {
5404 .name = MODULENAME,
5405 .id_table = rtl8169_pci_tbl,
5406 .probe = rtl8169_init_one,
5407 .remove = __devexit_p(rtl8169_remove_one),
Francois Romieu1765f952008-09-13 17:21:40 +02005408 .shutdown = rtl_shutdown,
Rafael J. Wysocki861ab442009-04-05 08:40:04 +00005409 .driver.pm = RTL8169_PM_OPS,
Linus Torvalds1da177e2005-04-16 15:20:36 -07005410};
5411
Francois Romieu07d3f512007-02-21 22:40:46 +01005412static int __init rtl8169_init_module(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005413{
Jeff Garzik29917622006-08-19 17:48:59 -04005414 return pci_register_driver(&rtl8169_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07005415}
5416
Francois Romieu07d3f512007-02-21 22:40:46 +01005417static void __exit rtl8169_cleanup_module(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005418{
5419 pci_unregister_driver(&rtl8169_pci_driver);
5420}
5421
5422module_init(rtl8169_init_module);
5423module_exit(rtl8169_cleanup_module);