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Tony Lindgren90c62bf2008-12-10 17:37:17 -08001/*
Adrian Hunterd02a900b2010-02-15 10:03:34 -08002 * linux/arch/arm/mach-omap2/hsmmc.c
Tony Lindgren90c62bf2008-12-10 17:37:17 -08003 *
4 * Copyright (C) 2007-2008 Texas Instruments
5 * Copyright (C) 2008 Nokia Corporation
6 * Author: Texas Instruments
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
Adrian Hunterdb0fefc2010-02-15 10:03:34 -080012#include <linux/kernel.h>
13#include <linux/slab.h>
14#include <linux/string.h>
Tony Lindgren90c62bf2008-12-10 17:37:17 -080015#include <linux/delay.h>
Silesh C V5e4698f2011-07-04 04:10:00 -070016#include <linux/gpio.h>
Tony Lindgren90c62bf2008-12-10 17:37:17 -080017#include <mach/hardware.h>
Tony Lindgrence491cf2009-10-20 09:40:47 -070018#include <plat/mmc.h>
Adrian Huntere3df0fb2010-02-15 10:03:34 -080019#include <plat/omap-pm.h>
Kishore Kadiyalad8d0a612011-02-28 20:48:03 +053020#include <plat/mux.h>
Kishore Kadiyala4621d5f2011-02-28 20:48:04 +053021#include <plat/omap_device.h>
Tony Lindgren90c62bf2008-12-10 17:37:17 -080022
Kishore Kadiyalad8d0a612011-02-28 20:48:03 +053023#include "mux.h"
Adrian Hunterd02a900b2010-02-15 10:03:34 -080024#include "hsmmc.h"
Paul Walmsley4814ced2010-10-08 11:40:20 -060025#include "control.h"
Tony Lindgren90c62bf2008-12-10 17:37:17 -080026
Adrian Hunterdb0fefc2010-02-15 10:03:34 -080027#if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
Tony Lindgren90c62bf2008-12-10 17:37:17 -080028
Tony Lindgren90c62bf2008-12-10 17:37:17 -080029static u16 control_pbias_offset;
30static u16 control_devconf1_offset;
kishore kadiyalac83c8e62010-05-15 18:21:25 +000031static u16 control_mmc1;
Tony Lindgren90c62bf2008-12-10 17:37:17 -080032
33#define HSMMC_NAME_LEN 9
34
Denis Karpov1887bde2009-09-22 16:44:40 -070035#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
36
Adrian Hunter68ff0422010-02-15 10:03:34 -080037static int hsmmc_get_context_loss(struct device *dev)
Denis Karpov1887bde2009-09-22 16:44:40 -070038{
Adrian Huntere3df0fb2010-02-15 10:03:34 -080039 return omap_pm_get_dev_context_loss_count(dev);
Denis Karpov1887bde2009-09-22 16:44:40 -070040}
41
42#else
Adrian Hunter68ff0422010-02-15 10:03:34 -080043#define hsmmc_get_context_loss NULL
Denis Karpov1887bde2009-09-22 16:44:40 -070044#endif
45
kishore kadiyalac83c8e62010-05-15 18:21:25 +000046static void omap_hsmmc1_before_set_reg(struct device *dev, int slot,
Adrian Hunterdb0fefc2010-02-15 10:03:34 -080047 int power_on, int vdd)
Tony Lindgren90c62bf2008-12-10 17:37:17 -080048{
Madhu555d5032009-11-22 10:11:08 -080049 u32 reg, prog_io;
Tony Lindgren90c62bf2008-12-10 17:37:17 -080050 struct omap_mmc_platform_data *mmc = dev->platform_data;
51
Adrian Hunterce6f0012010-02-15 10:03:34 -080052 if (mmc->slots[0].remux)
53 mmc->slots[0].remux(dev, slot, power_on);
54
David Brownell0329c372009-03-23 18:23:47 -070055 /*
56 * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
David Brownellb583f262009-05-28 14:04:03 -070057 * card with Vcc regulator (from twl4030 or whatever). OMAP has both
David Brownell0329c372009-03-23 18:23:47 -070058 * 1.8V and 3.0V modes, controlled by the PBIAS register.
59 *
60 * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
61 * is most naturally TWL VSIM; those pins also use PBIAS.
David Brownellb583f262009-05-28 14:04:03 -070062 *
63 * FIXME handle VMMC1A as needed ...
David Brownell0329c372009-03-23 18:23:47 -070064 */
Tony Lindgren90c62bf2008-12-10 17:37:17 -080065 if (power_on) {
66 if (cpu_is_omap2430()) {
67 reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1);
68 if ((1 << vdd) >= MMC_VDD_30_31)
69 reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE;
70 else
71 reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE;
72 omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
73 }
74
75 if (mmc->slots[0].internal_clock) {
76 reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
77 reg |= OMAP2_MMCSDIO1ADPCLKISEL;
78 omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
79 }
80
81 reg = omap_ctrl_readl(control_pbias_offset);
Madhu555d5032009-11-22 10:11:08 -080082 if (cpu_is_omap3630()) {
83 /* Set MMC I/O to 52Mhz */
84 prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
85 prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL;
86 omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1);
87 } else {
88 reg |= OMAP2_PBIASSPEEDCTRL0;
89 }
Tony Lindgren90c62bf2008-12-10 17:37:17 -080090 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
91 omap_ctrl_writel(reg, control_pbias_offset);
Adrian Hunterdb0fefc2010-02-15 10:03:34 -080092 } else {
93 reg = omap_ctrl_readl(control_pbias_offset);
94 reg &= ~OMAP2_PBIASLITEPWRDNZ0;
95 omap_ctrl_writel(reg, control_pbias_offset);
96 }
97}
Tony Lindgren90c62bf2008-12-10 17:37:17 -080098
kishore kadiyalac83c8e62010-05-15 18:21:25 +000099static void omap_hsmmc1_after_set_reg(struct device *dev, int slot,
Adrian Hunterdb0fefc2010-02-15 10:03:34 -0800100 int power_on, int vdd)
101{
102 u32 reg;
Tony Lindgren90c62bf2008-12-10 17:37:17 -0800103
Adrian Hunterdb0fefc2010-02-15 10:03:34 -0800104 /* 100ms delay required for PBIAS configuration */
105 msleep(100);
106
107 if (power_on) {
Tony Lindgren90c62bf2008-12-10 17:37:17 -0800108 reg = omap_ctrl_readl(control_pbias_offset);
109 reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0);
110 if ((1 << vdd) <= MMC_VDD_165_195)
111 reg &= ~OMAP2_PBIASLITEVMODE0;
112 else
113 reg |= OMAP2_PBIASLITEVMODE0;
114 omap_ctrl_writel(reg, control_pbias_offset);
115 } else {
116 reg = omap_ctrl_readl(control_pbias_offset);
Tony Lindgren90c62bf2008-12-10 17:37:17 -0800117 reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 |
118 OMAP2_PBIASLITEVMODE0);
119 omap_ctrl_writel(reg, control_pbias_offset);
120 }
Tony Lindgren90c62bf2008-12-10 17:37:17 -0800121}
122
kishore kadiyalac83c8e62010-05-15 18:21:25 +0000123static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot,
124 int power_on, int vdd)
125{
126 u32 reg;
127
128 /*
129 * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
130 * card with Vcc regulator (from twl4030 or whatever). OMAP has both
131 * 1.8V and 3.0V modes, controlled by the PBIAS register.
kishore kadiyalac83c8e62010-05-15 18:21:25 +0000132 */
Santosh Shilimkardcf5ef32010-09-27 14:02:58 -0600133 reg = omap4_ctrl_pad_readl(control_pbias_offset);
134 reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
Balaji T Kff2beb12011-10-03 17:52:50 +0530135 OMAP4_MMC1_PWRDNZ_MASK |
136 OMAP4_MMC1_PBIASLITE_VMODE_MASK);
Santosh Shilimkardcf5ef32010-09-27 14:02:58 -0600137 omap4_ctrl_pad_writel(reg, control_pbias_offset);
kishore kadiyalac83c8e62010-05-15 18:21:25 +0000138}
139
140static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
141 int power_on, int vdd)
142{
143 u32 reg;
Balaji T K1fcecf22011-06-01 16:45:22 +0530144 unsigned long timeout;
kishore kadiyalac83c8e62010-05-15 18:21:25 +0000145
146 if (power_on) {
Santosh Shilimkardcf5ef32010-09-27 14:02:58 -0600147 reg = omap4_ctrl_pad_readl(control_pbias_offset);
148 reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK;
kishore kadiyalac83c8e62010-05-15 18:21:25 +0000149 if ((1 << vdd) <= MMC_VDD_165_195)
Santosh Shilimkardcf5ef32010-09-27 14:02:58 -0600150 reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK;
kishore kadiyalac83c8e62010-05-15 18:21:25 +0000151 else
Santosh Shilimkardcf5ef32010-09-27 14:02:58 -0600152 reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK;
153 reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
Bryan Buckley3696d302011-09-30 11:05:55 -0700154 OMAP4_MMC1_PWRDNZ_MASK);
Santosh Shilimkardcf5ef32010-09-27 14:02:58 -0600155 omap4_ctrl_pad_writel(reg, control_pbias_offset);
Balaji T K1fcecf22011-06-01 16:45:22 +0530156
157 timeout = jiffies + msecs_to_jiffies(5);
158 do {
159 reg = omap4_ctrl_pad_readl(control_pbias_offset);
160 if (!(reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK))
161 break;
162 usleep_range(100, 200);
163 } while (!time_after(jiffies, timeout));
164
Santosh Shilimkardcf5ef32010-09-27 14:02:58 -0600165 if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) {
kishore kadiyalac83c8e62010-05-15 18:21:25 +0000166 pr_err("Pbias Voltage is not same as LDO\n");
167 /* Caution : On VMODE_ERROR Power Down MMC IO */
Bryan Buckley3696d302011-09-30 11:05:55 -0700168 reg &= ~(OMAP4_MMC1_PWRDNZ_MASK);
Santosh Shilimkardcf5ef32010-09-27 14:02:58 -0600169 omap4_ctrl_pad_writel(reg, control_pbias_offset);
kishore kadiyalac83c8e62010-05-15 18:21:25 +0000170 }
kishore kadiyalac83c8e62010-05-15 18:21:25 +0000171 }
172}
173
Adrian Hunterdb0fefc2010-02-15 10:03:34 -0800174static void hsmmc23_before_set_reg(struct device *dev, int slot,
175 int power_on, int vdd)
Tony Lindgren90c62bf2008-12-10 17:37:17 -0800176{
Tony Lindgren90c62bf2008-12-10 17:37:17 -0800177 struct omap_mmc_platform_data *mmc = dev->platform_data;
Grazvydas Ignotas762ad3a42009-06-23 13:30:22 +0300178
Adrian Hunterce6f0012010-02-15 10:03:34 -0800179 if (mmc->slots[0].remux)
180 mmc->slots[0].remux(dev, slot, power_on);
181
Tony Lindgren90c62bf2008-12-10 17:37:17 -0800182 if (power_on) {
Adrian Hunterdb0fefc2010-02-15 10:03:34 -0800183 /* Only MMC2 supports a CLKIN */
Tony Lindgren90c62bf2008-12-10 17:37:17 -0800184 if (mmc->slots[0].internal_clock) {
185 u32 reg;
186
187 reg = omap_ctrl_readl(control_devconf1_offset);
188 reg |= OMAP2_MMCSDIO2ADPCLKISEL;
189 omap_ctrl_writel(reg, control_devconf1_offset);
190 }
Tony Lindgren90c62bf2008-12-10 17:37:17 -0800191 }
Adrian Hunter9b7c18e2009-09-22 16:44:50 -0700192}
193
stanley.miao03e7e172010-05-13 12:39:31 +0000194static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
195 int vdd)
196{
197 return 0;
198}
199
Kishore Kadiyalad8d0a612011-02-28 20:48:03 +0530200static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
201 int controller_nr)
202{
Silesh C V5e4698f2011-07-04 04:10:00 -0700203 if (gpio_is_valid(mmc_controller->slots[0].switch_pin))
Kishore Kadiyalad8d0a612011-02-28 20:48:03 +0530204 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
205 OMAP_PIN_INPUT_PULLUP);
Silesh C V5e4698f2011-07-04 04:10:00 -0700206 if (gpio_is_valid(mmc_controller->slots[0].gpio_wp))
Kishore Kadiyalad8d0a612011-02-28 20:48:03 +0530207 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
208 OMAP_PIN_INPUT_PULLUP);
209 if (cpu_is_omap34xx()) {
210 if (controller_nr == 0) {
211 omap_mux_init_signal("sdmmc1_clk",
212 OMAP_PIN_INPUT_PULLUP);
213 omap_mux_init_signal("sdmmc1_cmd",
214 OMAP_PIN_INPUT_PULLUP);
215 omap_mux_init_signal("sdmmc1_dat0",
216 OMAP_PIN_INPUT_PULLUP);
217 if (mmc_controller->slots[0].caps &
218 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
219 omap_mux_init_signal("sdmmc1_dat1",
220 OMAP_PIN_INPUT_PULLUP);
221 omap_mux_init_signal("sdmmc1_dat2",
222 OMAP_PIN_INPUT_PULLUP);
223 omap_mux_init_signal("sdmmc1_dat3",
224 OMAP_PIN_INPUT_PULLUP);
225 }
226 if (mmc_controller->slots[0].caps &
227 MMC_CAP_8_BIT_DATA) {
228 omap_mux_init_signal("sdmmc1_dat4",
229 OMAP_PIN_INPUT_PULLUP);
230 omap_mux_init_signal("sdmmc1_dat5",
231 OMAP_PIN_INPUT_PULLUP);
232 omap_mux_init_signal("sdmmc1_dat6",
233 OMAP_PIN_INPUT_PULLUP);
234 omap_mux_init_signal("sdmmc1_dat7",
235 OMAP_PIN_INPUT_PULLUP);
236 }
237 }
238 if (controller_nr == 1) {
239 /* MMC2 */
240 omap_mux_init_signal("sdmmc2_clk",
241 OMAP_PIN_INPUT_PULLUP);
242 omap_mux_init_signal("sdmmc2_cmd",
243 OMAP_PIN_INPUT_PULLUP);
244 omap_mux_init_signal("sdmmc2_dat0",
245 OMAP_PIN_INPUT_PULLUP);
246
247 /*
248 * For 8 wire configurations, Lines DAT4, 5, 6 and 7
249 * need to be muxed in the board-*.c files
250 */
251 if (mmc_controller->slots[0].caps &
252 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
253 omap_mux_init_signal("sdmmc2_dat1",
254 OMAP_PIN_INPUT_PULLUP);
255 omap_mux_init_signal("sdmmc2_dat2",
256 OMAP_PIN_INPUT_PULLUP);
257 omap_mux_init_signal("sdmmc2_dat3",
258 OMAP_PIN_INPUT_PULLUP);
259 }
260 if (mmc_controller->slots[0].caps &
261 MMC_CAP_8_BIT_DATA) {
262 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
263 OMAP_PIN_INPUT_PULLUP);
264 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
265 OMAP_PIN_INPUT_PULLUP);
266 omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
267 OMAP_PIN_INPUT_PULLUP);
268 omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
269 OMAP_PIN_INPUT_PULLUP);
270 }
271 }
272
273 /*
274 * For MMC3 the pins need to be muxed in the board-*.c files
275 */
276 }
277}
278
Kishore Kadiyala4621d5f2011-02-28 20:48:04 +0530279static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
280 struct omap_mmc_platform_data *mmc)
281{
282 char *hc_name;
283
284 hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL);
285 if (!hc_name) {
286 pr_err("Cannot allocate memory for controller slot name\n");
287 kfree(hc_name);
288 return -ENOMEM;
289 }
290
291 if (c->name)
292 strncpy(hc_name, c->name, HSMMC_NAME_LEN);
293 else
294 snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i",
295 c->mmc, 1);
296 mmc->slots[0].name = hc_name;
297 mmc->nr_slots = 1;
298 mmc->slots[0].caps = c->caps;
299 mmc->slots[0].internal_clock = !c->ext_clock;
300 mmc->dma_mask = 0xffffffff;
301 if (cpu_is_omap44xx())
302 mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
303 else
304 mmc->reg_offset = 0;
305
306 mmc->get_context_loss_count = hsmmc_get_context_loss;
307
308 mmc->slots[0].switch_pin = c->gpio_cd;
309 mmc->slots[0].gpio_wp = c->gpio_wp;
310
311 mmc->slots[0].remux = c->remux;
312 mmc->slots[0].init_card = c->init_card;
313
314 if (c->cover_only)
315 mmc->slots[0].cover = 1;
316
317 if (c->nonremovable)
318 mmc->slots[0].nonremovable = 1;
319
320 if (c->power_saving)
321 mmc->slots[0].power_saving = 1;
322
323 if (c->no_off)
324 mmc->slots[0].no_off = 1;
325
Balaji T Kb1c1df72011-05-30 19:55:34 +0530326 if (c->no_off_init)
327 mmc->slots[0].no_regulator_off_init = c->no_off_init;
328
Kishore Kadiyala4621d5f2011-02-28 20:48:04 +0530329 if (c->vcc_aux_disable_is_sleep)
330 mmc->slots[0].vcc_aux_disable_is_sleep = 1;
331
332 /*
333 * NOTE: MMC slots should have a Vcc regulator set up.
334 * This may be from a TWL4030-family chip, another
335 * controllable regulator, or a fixed supply.
336 *
337 * temporary HACK: ocr_mask instead of fixed supply
338 */
339 mmc->slots[0].ocr_mask = c->ocr_mask;
340
341 if (cpu_is_omap3517() || cpu_is_omap3505())
342 mmc->slots[0].set_power = nop_mmc_set_power;
343 else
344 mmc->slots[0].features |= HSMMC_HAS_PBIAS;
345
346 if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
347 mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
348
349 switch (c->mmc) {
350 case 1:
351 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
352 /* on-chip level shifting via PBIAS0/PBIAS1 */
353 if (cpu_is_omap44xx()) {
354 mmc->slots[0].before_set_reg =
355 omap4_hsmmc1_before_set_reg;
356 mmc->slots[0].after_set_reg =
357 omap4_hsmmc1_after_set_reg;
358 } else {
359 mmc->slots[0].before_set_reg =
360 omap_hsmmc1_before_set_reg;
361 mmc->slots[0].after_set_reg =
362 omap_hsmmc1_after_set_reg;
363 }
364 }
365
366 /* OMAP3630 HSMMC1 supports only 4-bit */
367 if (cpu_is_omap3630() &&
368 (c->caps & MMC_CAP_8_BIT_DATA)) {
369 c->caps &= ~MMC_CAP_8_BIT_DATA;
370 c->caps |= MMC_CAP_4_BIT_DATA;
371 mmc->slots[0].caps = c->caps;
372 }
373 break;
374 case 2:
375 if (c->ext_clock)
376 c->transceiver = 1;
377 if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
378 c->caps &= ~MMC_CAP_8_BIT_DATA;
379 c->caps |= MMC_CAP_4_BIT_DATA;
380 }
381 /* FALLTHROUGH */
382 case 3:
383 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
384 /* off-chip level shifting, or none */
385 mmc->slots[0].before_set_reg = hsmmc23_before_set_reg;
386 mmc->slots[0].after_set_reg = NULL;
387 }
388 break;
389 case 4:
390 case 5:
391 mmc->slots[0].before_set_reg = NULL;
392 mmc->slots[0].after_set_reg = NULL;
393 break;
394 default:
395 pr_err("MMC%d configuration not supported!\n", c->mmc);
396 kfree(hc_name);
397 return -ENODEV;
398 }
399 return 0;
400}
401
Kishore Kadiyala4621d5f2011-02-28 20:48:04 +0530402#define MAX_OMAP_MMC_HWMOD_NAME_LEN 16
403
404void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
405{
406 struct omap_hwmod *oh;
Kevin Hilman3528c582011-07-21 13:48:45 -0700407 struct platform_device *pdev;
Kishore Kadiyala4621d5f2011-02-28 20:48:04 +0530408 char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
409 struct omap_mmc_platform_data *mmc_data;
410 struct omap_mmc_dev_attr *mmc_dev_attr;
411 char *name;
412 int l;
Kishore Kadiyala4621d5f2011-02-28 20:48:04 +0530413
414 mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
415 if (!mmc_data) {
416 pr_err("Cannot allocate memory for mmc device!\n");
417 goto done;
418 }
419
420 if (omap_hsmmc_pdata_init(hsmmcinfo, mmc_data) < 0) {
421 pr_err("%s fails!\n", __func__);
422 goto done;
423 }
424 omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
425
Kishore Kadiyala0005ae72011-02-28 20:48:05 +0530426 name = "omap_hsmmc";
Kishore Kadiyala4621d5f2011-02-28 20:48:04 +0530427
428 l = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
429 "mmc%d", ctrl_nr);
430 WARN(l >= MAX_OMAP_MMC_HWMOD_NAME_LEN,
431 "String buffer overflow in MMC%d device setup\n", ctrl_nr);
432 oh = omap_hwmod_lookup(oh_name);
433 if (!oh) {
434 pr_err("Could not look up %s\n", oh_name);
435 kfree(mmc_data->slots[0].name);
436 goto done;
437 }
438
439 if (oh->dev_attr != NULL) {
440 mmc_dev_attr = oh->dev_attr;
441 mmc_data->controller_flags = mmc_dev_attr->flags;
442 }
443
Kevin Hilman3528c582011-07-21 13:48:45 -0700444 pdev = omap_device_build(name, ctrl_nr - 1, oh, mmc_data,
Benoit Coussonf718e2c2011-08-10 15:30:09 +0200445 sizeof(struct omap_mmc_platform_data), NULL, 0, false);
Kevin Hilman3528c582011-07-21 13:48:45 -0700446 if (IS_ERR(pdev)) {
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300447 WARN(1, "Can't build omap_device for %s:%s.\n", name, oh->name);
Kishore Kadiyala4621d5f2011-02-28 20:48:04 +0530448 kfree(mmc_data->slots[0].name);
449 goto done;
450 }
451 /*
452 * return device handle to board setup code
453 * required to populate for regulator framework structure
454 */
Kevin Hilman3528c582011-07-21 13:48:45 -0700455 hsmmcinfo->dev = &pdev->dev;
Kishore Kadiyala4621d5f2011-02-28 20:48:04 +0530456
457done:
458 kfree(mmc_data);
459}
Tony Lindgren90c62bf2008-12-10 17:37:17 -0800460
Adrian Hunter68ff0422010-02-15 10:03:34 -0800461void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
Tony Lindgren90c62bf2008-12-10 17:37:17 -0800462{
kishore kadiyalac83c8e62010-05-15 18:21:25 +0000463 u32 reg;
Tony Lindgren90c62bf2008-12-10 17:37:17 -0800464
kishore kadiyalac83c8e62010-05-15 18:21:25 +0000465 if (!cpu_is_omap44xx()) {
466 if (cpu_is_omap2430()) {
467 control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
468 control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
469 } else {
470 control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
471 control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
472 }
Tony Lindgren90c62bf2008-12-10 17:37:17 -0800473 } else {
Santosh Shilimkardcf5ef32010-09-27 14:02:58 -0600474 control_pbias_offset =
475 OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
476 control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
477 reg = omap4_ctrl_pad_readl(control_mmc1);
478 reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
479 OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
480 reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
481 OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
482 reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK|
483 OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
484 OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
485 omap4_ctrl_pad_writel(reg, control_mmc1);
Tony Lindgren90c62bf2008-12-10 17:37:17 -0800486 }
487
Kishore Kadiyala4621d5f2011-02-28 20:48:04 +0530488 for (; controllers->mmc; controllers++)
489 omap_init_hsmmc(controllers, controllers->mmc);
Tony Lindgren90c62bf2008-12-10 17:37:17 -0800490
Tony Lindgren90c62bf2008-12-10 17:37:17 -0800491}
492
493#endif