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gerrit-public.fairphone.software / kernel / msm-4.9 / 70bef01c0f1c9a55b54b625be3f82ff7ee1e8c05 / . / drivers / clocksource / clksrc_st_lpc.c
blob: f38cf33281a206775c9421d1c959b50a80520ae9 [file] [log] [blame]
Lee Jones70bef012015-05-26 13:39:43 +0100[diff] [blame^]1/*
2 * Clocksource using the Low Power Timer found in the Low Power Controller (LPC)
3 *
4 * Copyright (C) 2015 STMicroelectronics – All Rights Reserved
5 *
6 * Author(s): Francesco Virlinzi <francesco.virlinzi@st.com>
7 * Ajit Pal Singh <ajitpal.singh@st.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#include <linux/clk.h>
16#include <linux/clocksource.h>
17#include <linux/init.h>
18#include <linux/of_address.h>
19#include <linux/slab.h>
20
21#include <dt-bindings/mfd/st-lpc.h>
22
23/* Low Power Timer */
24#define LPC_LPT_LSB_OFF 0x400
25#define LPC_LPT_MSB_OFF 0x404
26#define LPC_LPT_START_OFF 0x408
27
28static struct st_clksrc_ddata {
29 struct clk *clk;
30 void __iomem *base;
31} ddata;
32
33static void __init st_clksrc_reset(void)
34{
35 writel_relaxed(0, ddata.base + LPC_LPT_START_OFF);
36 writel_relaxed(0, ddata.base + LPC_LPT_MSB_OFF);
37 writel_relaxed(0, ddata.base + LPC_LPT_LSB_OFF);
38 writel_relaxed(1, ddata.base + LPC_LPT_START_OFF);
39}
40
41static int __init st_clksrc_init(void)
42{
43 unsigned long rate;
44 int ret;
45
46 st_clksrc_reset();
47
48 rate = clk_get_rate(ddata.clk);
49
50 ret = clocksource_mmio_init(ddata.base + LPC_LPT_LSB_OFF,
51 "clksrc-st-lpc", rate, 300, 32,
52 clocksource_mmio_readl_up);
53 if (ret) {
54 pr_err("clksrc-st-lpc: Failed to register clocksource\n");
55 return ret;
56 }
57
58 return 0;
59}
60
61static int __init st_clksrc_setup_clk(struct device_node *np)
62{
63 struct clk *clk;
64
65 clk = of_clk_get(np, 0);
66 if (IS_ERR(clk)) {
67 pr_err("clksrc-st-lpc: Failed to get LPC clock\n");
68 return PTR_ERR(clk);
69 }
70
71 if (clk_prepare_enable(clk)) {
72 pr_err("clksrc-st-lpc: Failed to enable LPC clock\n");
73 return -EINVAL;
74 }
75
76 if (!clk_get_rate(clk)) {
77 pr_err("clksrc-st-lpc: Failed to get LPC clock rate\n");
78 clk_disable_unprepare(clk);
79 return -EINVAL;
80 }
81
82 ddata.clk = clk;
83
84 return 0;
85}
86
87static void __init st_clksrc_of_register(struct device_node *np)
88{
89 int ret;
90 uint32_t mode;
91
92 ret = of_property_read_u32(np, "st,lpc-mode", &mode);
93 if (ret) {
94 pr_err("clksrc-st-lpc: An LPC mode must be provided\n");
95 return;
96 }
97
98 /* LPC can either run as a Clocksource or in RTC or WDT mode */
99 if (mode != ST_LPC_MODE_CLKSRC)
100 return;
101
102 ddata.base = of_iomap(np, 0);
103 if (!ddata.base) {
104 pr_err("clksrc-st-lpc: Unable to map iomem\n");
105 return;
106 }
107
108 if (st_clksrc_setup_clk(np)) {
109 iounmap(ddata.base);
110 return;
111 }
112
113 if (st_clksrc_init()) {
114 clk_disable_unprepare(ddata.clk);
115 clk_put(ddata.clk);
116 iounmap(ddata.base);
117 return;
118 }
119
120 pr_info("clksrc-st-lpc: clocksource initialised - running @ %luHz\n",
121 clk_get_rate(ddata.clk));
122}
123CLOCKSOURCE_OF_DECLARE(ddata, "st,stih407-lpc", st_clksrc_of_register);