Lakshmi Narayana Kalavala | c0dac06 | 2016-12-01 17:20:09 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
| 14 | &soc { |
| 15 | qcom,cam-req-mgr { |
| 16 | compatible = "qcom,cam-req-mgr"; |
| 17 | status = "ok"; |
| 18 | }; |
Jigarkumar Zala | 86123115 | 2017-02-28 14:05:11 -0800 | [diff] [blame] | 19 | |
| 20 | qcom,csiphy@ac65000 { |
| 21 | cell-index = <0>; |
| 22 | compatible = "qcom,csiphy-v1.0", "qcom,csiphy"; |
| 23 | reg = <0x0ac65000 0x1000>; |
| 24 | reg-names = "csiphy"; |
| 25 | interrupts = <0 477 0>; |
| 26 | interrupt-names = "csiphy"; |
| 27 | gdscr-supply = <&titan_top_gdsc>; |
| 28 | qcom,cam-vreg-name = "gdscr"; |
| 29 | qcom,csi-vdd-voltage = <1200000>; |
| 30 | qcom,mipi-csi-vdd-supply = <&pm8998_l26>; |
| 31 | clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, |
| 32 | <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| 33 | <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, |
| 34 | <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| 35 | <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, |
| 36 | <&clock_camcc CAM_CC_CSIPHY0_CLK>, |
| 37 | <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, |
| 38 | <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>, |
| 39 | <&clock_camcc CAM_CC_IFE_0_CSID_CLK>, |
| 40 | <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>; |
| 41 | clock-names = "camnoc_axi_clk", |
| 42 | "soc_ahb_clk", |
| 43 | "slow_ahb_src_clk", |
| 44 | "cpas_ahb_clk", |
| 45 | "cphy_rx_clk_src", |
| 46 | "csiphy0_clk", |
| 47 | "csi0phytimer_clk_src", |
| 48 | "csi0phytimer_clk", |
| 49 | "ife_0_csid_clk", |
| 50 | "ife_0_csid_clk_src"; |
| 51 | qcom,clock-rates = |
| 52 | <0 0 80000000 0 320000000 0 269333333 0 0 384000000>; |
| 53 | status = "ok"; |
| 54 | }; |
| 55 | |
| 56 | qcom,csiphy@ac66000{ |
| 57 | cell-index = <1>; |
| 58 | compatible = "qcom,csiphy-v1.0", "qcom,csiphy"; |
| 59 | reg = <0xac66000 0x1000>; |
| 60 | reg-names = "csiphy"; |
| 61 | interrupts = <0 478 0>; |
| 62 | interrupt-names = "csiphy"; |
| 63 | gdscr-supply = <&titan_top_gdsc>; |
| 64 | qcom,cam-vreg-name = "gdscr"; |
| 65 | qcom,csi-vdd-voltage = <1200000>; |
| 66 | qcom,mipi-csi-vdd-supply = <&pm8998_l26>; |
| 67 | clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, |
| 68 | <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| 69 | <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, |
| 70 | <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| 71 | <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, |
| 72 | <&clock_camcc CAM_CC_CSIPHY1_CLK>, |
| 73 | <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, |
Viswanadha Raju Thotakura | eed9bb6 | 2017-05-03 12:10:19 -0700 | [diff] [blame] | 74 | <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>, |
Jigarkumar Zala | 86123115 | 2017-02-28 14:05:11 -0800 | [diff] [blame] | 75 | <&clock_camcc CAM_CC_IFE_1_CSID_CLK>, |
| 76 | <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>; |
| 77 | clock-names = "camnoc_axi_clk", |
| 78 | "soc_ahb_clk", |
| 79 | "slow_ahb_src_clk", |
| 80 | "cpas_ahb_clk", |
| 81 | "cphy_rx_clk_src", |
| 82 | "csiphy1_clk", |
| 83 | "csi1phytimer_clk_src", |
| 84 | "csi1phytimer_clk", |
| 85 | "ife_1_csid_clk", |
| 86 | "ife_1_csid_clk_src"; |
| 87 | qcom,clock-rates = |
| 88 | <0 0 80000000 0 320000000 0 269333333 0 0 384000000>; |
| 89 | |
| 90 | status = "ok"; |
| 91 | }; |
| 92 | |
| 93 | qcom,csiphy@ac67000 { |
| 94 | cell-index = <2>; |
| 95 | compatible = "qcom,csiphy-v1.0", "qcom,csiphy"; |
| 96 | reg = <0xac67000 0x1000>; |
| 97 | reg-names = "csiphy"; |
| 98 | interrupts = <0 479 0>; |
| 99 | interrupt-names = "csiphy"; |
| 100 | gdscr-supply = <&titan_top_gdsc>; |
| 101 | qcom,cam-vreg-name = "gdscr"; |
| 102 | qcom,csi-vdd-voltage = <1200000>; |
| 103 | qcom,mipi-csi-vdd-supply = <&pm8998_l26>; |
| 104 | clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, |
| 105 | <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| 106 | <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, |
| 107 | <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| 108 | <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, |
| 109 | <&clock_camcc CAM_CC_CSIPHY2_CLK>, |
| 110 | <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, |
| 111 | <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>, |
| 112 | <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, |
| 113 | <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>; |
| 114 | clock-names = "camnoc_axi_clk", |
| 115 | "soc_ahb_clk", |
| 116 | "slow_ahb_src_clk", |
| 117 | "cpas_ahb_clk", |
| 118 | "cphy_rx_clk_src", |
| 119 | "csiphy2_clk", |
| 120 | "csi2phytimer_clk_src", |
| 121 | "csi2phytimer_clk", |
| 122 | "ife_lite_csid_clk", |
| 123 | "ife_lite_csid_clk_src"; |
| 124 | qcom,clock-rates = |
| 125 | <0 0 80000000 0 320000000 0 269333333 0 0 384000000>; |
| 126 | status = "ok"; |
| 127 | }; |
| 128 | |
| 129 | cci: qcom,cci@ac4a000 { |
| 130 | cell-index = <0>; |
| 131 | compatible = "qcom,cci"; |
| 132 | reg = <0xac4a000 0x4000>; |
| 133 | #address-cells = <1>; |
| 134 | #size-cells = <0>; |
| 135 | reg-names = "cci"; |
| 136 | interrupts = <0 460 0>; |
| 137 | interrupt-names = "cci"; |
| 138 | status = "ok"; |
| 139 | gdscr-supply = <&titan_top_gdsc>; |
| 140 | qcom,cam-vreg-name = "gdscr"; |
| 141 | clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, |
| 142 | <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| 143 | <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, |
| 144 | <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| 145 | <&clock_camcc CAM_CC_CCI_CLK>, |
| 146 | <&clock_camcc CAM_CC_CCI_CLK_SRC>; |
| 147 | clock-names = "camnoc_axi_clk", |
| 148 | "soc_ahb_clk", |
| 149 | "slow_ahb_src_clk", |
| 150 | "cpas_ahb_clk", |
| 151 | "cci_clk", |
| 152 | "cci_clk_src"; |
| 153 | qcom,clock-rates = <0 0 80000000 0 0 37500000>; |
| 154 | pinctrl-names = "cci_default", "cci_suspend"; |
| 155 | pinctrl-0 = <&cci0_active &cci1_active>; |
| 156 | pinctrl-1 = <&cci0_suspend &cci1_suspend>; |
| 157 | gpios = <&tlmm 17 0>, |
| 158 | <&tlmm 18 0>, |
| 159 | <&tlmm 19 0>, |
| 160 | <&tlmm 20 0>; |
| 161 | qcom,gpio-tbl-num = <0 1 2 3>; |
| 162 | qcom,gpio-tbl-flags = <1 1 1 1>; |
| 163 | qcom,gpio-tbl-label = "CCI_I2C_DATA0", |
| 164 | "CCI_I2C_CLK0", |
| 165 | "CCI_I2C_DATA1", |
| 166 | "CCI_I2C_CLK1"; |
| 167 | |
| 168 | i2c_freq_100Khz: qcom,i2c_standard_mode { |
| 169 | qcom,hw-thigh = <201>; |
| 170 | qcom,hw-tlow = <174>; |
| 171 | qcom,hw-tsu-sto = <204>; |
| 172 | qcom,hw-tsu-sta = <231>; |
| 173 | qcom,hw-thd-dat = <22>; |
| 174 | qcom,hw-thd-sta = <162>; |
| 175 | qcom,hw-tbuf = <227>; |
| 176 | qcom,hw-scl-stretch-en = <0>; |
| 177 | qcom,hw-trdhld = <6>; |
| 178 | qcom,hw-tsp = <3>; |
| 179 | qcom,cci-clk-src = <37500000>; |
| 180 | status = "ok"; |
| 181 | }; |
| 182 | |
| 183 | i2c_freq_400Khz: qcom,i2c_fast_mode { |
| 184 | qcom,hw-thigh = <38>; |
| 185 | qcom,hw-tlow = <56>; |
| 186 | qcom,hw-tsu-sto = <40>; |
| 187 | qcom,hw-tsu-sta = <40>; |
| 188 | qcom,hw-thd-dat = <22>; |
| 189 | qcom,hw-thd-sta = <35>; |
| 190 | qcom,hw-tbuf = <62>; |
| 191 | qcom,hw-scl-stretch-en = <0>; |
| 192 | qcom,hw-trdhld = <6>; |
| 193 | qcom,hw-tsp = <3>; |
| 194 | qcom,cci-clk-src = <37500000>; |
| 195 | status = "ok"; |
| 196 | }; |
| 197 | |
| 198 | i2c_freq_custom: qcom,i2c_custom_mode { |
| 199 | qcom,hw-thigh = <38>; |
| 200 | qcom,hw-tlow = <56>; |
| 201 | qcom,hw-tsu-sto = <40>; |
| 202 | qcom,hw-tsu-sta = <40>; |
| 203 | qcom,hw-thd-dat = <22>; |
| 204 | qcom,hw-thd-sta = <35>; |
| 205 | qcom,hw-tbuf = <62>; |
| 206 | qcom,hw-scl-stretch-en = <1>; |
| 207 | qcom,hw-trdhld = <6>; |
| 208 | qcom,hw-tsp = <3>; |
| 209 | qcom,cci-clk-src = <37500000>; |
| 210 | status = "ok"; |
| 211 | }; |
| 212 | |
| 213 | i2c_freq_1Mhz: qcom,i2c_fast_plus_mode { |
| 214 | qcom,hw-thigh = <16>; |
| 215 | qcom,hw-tlow = <22>; |
| 216 | qcom,hw-tsu-sto = <17>; |
| 217 | qcom,hw-tsu-sta = <18>; |
| 218 | qcom,hw-thd-dat = <16>; |
| 219 | qcom,hw-thd-sta = <15>; |
| 220 | qcom,hw-tbuf = <24>; |
| 221 | qcom,hw-scl-stretch-en = <0>; |
| 222 | qcom,hw-trdhld = <3>; |
| 223 | qcom,hw-tsp = <3>; |
| 224 | qcom,cci-clk-src = <37500000>; |
| 225 | status = "ok"; |
| 226 | }; |
| 227 | }; |
Seemanta Dutta | df1dde7 | 2017-04-05 17:33:02 -0700 | [diff] [blame] | 228 | |
| 229 | qcom,cam_smmu { |
| 230 | compatible = "qcom,msm-cam-smmu"; |
| 231 | status = "ok"; |
| 232 | |
| 233 | msm_cam_smmu_ife { |
| 234 | compatible = "qcom,msm-cam-smmu-cb"; |
| 235 | iommus = <&apps_smmu 0x808>, |
| 236 | <&apps_smmu 0x810>, |
| 237 | <&apps_smmu 0x818>, |
| 238 | <&apps_smmu 0xc08>, |
| 239 | <&apps_smmu 0xc10>, |
| 240 | <&apps_smmu 0xc18>; |
| 241 | label = "ife"; |
| 242 | ife_iova_mem_map: iova-mem-map { |
| 243 | /* IO region is approximately 3.4 GB */ |
| 244 | iova-mem-region-io { |
| 245 | iova-region-name = "io"; |
| 246 | iova-region-start = <0x7400000>; |
| 247 | iova-region-len = <0xd8c00000>; |
| 248 | iova-region-id = <0x3>; |
| 249 | status = "ok"; |
| 250 | }; |
| 251 | }; |
| 252 | }; |
| 253 | |
| 254 | msm_cam_icp_fw { |
| 255 | compatible = "qcom,msm-cam-smmu-fw-dev"; |
| 256 | label="icp"; |
| 257 | memory-region = <&pil_camera_mem>; |
| 258 | }; |
| 259 | |
| 260 | msm_cam_smmu_icp { |
| 261 | compatible = "qcom,msm-cam-smmu-cb"; |
| 262 | iommus = <&apps_smmu 0x1078>, |
| 263 | <&apps_smmu 0x1020>, |
| 264 | <&apps_smmu 0x1028>, |
| 265 | <&apps_smmu 0x1040>, |
| 266 | <&apps_smmu 0x1048>, |
| 267 | <&apps_smmu 0x1030>, |
| 268 | <&apps_smmu 0x1050>; |
| 269 | label = "icp"; |
| 270 | icp_iova_mem_map: iova-mem-map { |
| 271 | iova-mem-region-firmware { |
| 272 | /* Firmware region is 5MB */ |
| 273 | iova-region-name = "firmware"; |
| 274 | iova-region-start = <0x0>; |
| 275 | iova-region-len = <0x500000>; |
| 276 | iova-region-id = <0x0>; |
| 277 | status = "ok"; |
| 278 | }; |
| 279 | |
| 280 | iova-mem-region-shared { |
| 281 | /* Shared region is 100MB long */ |
| 282 | iova-region-name = "shared"; |
| 283 | iova-region-start = <0x7400000>; |
| 284 | iova-region-len = <0x6400000>; |
| 285 | iova-region-id = <0x1>; |
| 286 | status = "ok"; |
| 287 | }; |
| 288 | |
| 289 | iova-mem-region-io { |
| 290 | /* IO region is approximately 3.3 GB */ |
| 291 | iova-region-name = "io"; |
| 292 | iova-region-start = <0xd800000>; |
| 293 | iova-region-len = <0xd2800000>; |
| 294 | iova-region-id = <0x3>; |
| 295 | status = "ok"; |
| 296 | }; |
| 297 | }; |
| 298 | }; |
| 299 | |
| 300 | msm_cam_smmu_cpas_cdm { |
| 301 | compatible = "qcom,msm-cam-smmu-cb"; |
| 302 | iommus = <&apps_smmu 0x1000>; |
| 303 | label = "cpas-cdm0"; |
| 304 | cpas_cdm_iova_mem_map: iova-mem-map { |
| 305 | iova-mem-region-io { |
| 306 | /* IO region is approximately 3.4 GB */ |
| 307 | iova-region-name = "io"; |
| 308 | iova-region-start = <0x7400000>; |
| 309 | iova-region-len = <0xd8c00000>; |
| 310 | iova-region-id = <0x3>; |
| 311 | status = "ok"; |
| 312 | }; |
| 313 | }; |
| 314 | }; |
| 315 | |
| 316 | msm_cam_smmu_secure { |
| 317 | compatible = "qcom,msm-cam-smmu-cb"; |
| 318 | iommus = <&apps_smmu 0x1001>; |
| 319 | label = "cam-secure"; |
| 320 | cam_secure_iova_mem_map: iova-mem-map { |
| 321 | /* Secure IO region is approximately 3.4 GB */ |
| 322 | iova-mem-region-io { |
| 323 | iova-region-name = "io"; |
| 324 | iova-region-start = <0x7400000>; |
| 325 | iova-region-len = <0xd8c00000>; |
| 326 | iova-region-id = <0x3>; |
| 327 | status = "ok"; |
| 328 | }; |
| 329 | }; |
| 330 | }; |
| 331 | }; |
Pavan Kumar Chilamkurthi | b6aa86d | 2017-05-01 23:47:11 -0700 | [diff] [blame] | 332 | |
| 333 | qcom,cam-cpas@ac40000 { |
| 334 | cell-index = <0>; |
| 335 | compatible = "qcom,cam-cpas"; |
| 336 | label = "cpas"; |
| 337 | arch-compat = "cpas_top"; |
| 338 | status = "ok"; |
| 339 | reg-names = "cam_cpas_top", "cam_camnoc"; |
| 340 | reg = <0xac40000 0x1000>, |
| 341 | <0xac42000 0x5000>; |
| 342 | reg-cam-base = <0x40000 0x42000>; |
| 343 | interrupt-names = "cpas_camnoc"; |
| 344 | interrupts = <0 459 0>; |
| 345 | regulator-names = "camss-vdd"; |
| 346 | camss-vdd-supply = <&titan_top_gdsc>; |
| 347 | clock-names = "gcc_ahb_clk", |
| 348 | "gcc_axi_clk", |
| 349 | "soc_ahb_clk", |
| 350 | "cpas_ahb_clk", |
| 351 | "slow_ahb_clk_src", |
| 352 | "camnoc_axi_clk"; |
| 353 | clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, |
| 354 | <&clock_gcc GCC_CAMERA_AXI_CLK>, |
| 355 | <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| 356 | <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| 357 | <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, |
| 358 | <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>; |
| 359 | src-clock-name = "slow_ahb_clk_src"; |
| 360 | clock-rates = <0 0 0 0 80000000 0>; |
| 361 | qcom,msm-bus,name = "cam_ahb"; |
| 362 | qcom,msm-bus,num-cases = <4>; |
| 363 | qcom,msm-bus,num-paths = <1>; |
| 364 | qcom,msm-bus,vectors-KBps = |
| 365 | <MSM_BUS_MASTER_AMPSS_M0 |
| 366 | MSM_BUS_SLAVE_CAMERA_CFG 0 0>, |
| 367 | <MSM_BUS_MASTER_AMPSS_M0 |
| 368 | MSM_BUS_SLAVE_CAMERA_CFG 0 300000>, |
| 369 | <MSM_BUS_MASTER_AMPSS_M0 |
| 370 | MSM_BUS_SLAVE_CAMERA_CFG 0 640000>, |
| 371 | <MSM_BUS_MASTER_AMPSS_M0 |
| 372 | MSM_BUS_SLAVE_CAMERA_CFG 0 640000>; |
| 373 | client-id-based; |
| 374 | client-names = |
| 375 | "csiphy0", "csiphy1", "csiphy2", "cci0", |
Pavan Kumar Chilamkurthi | 4e070ba | 2017-05-12 14:47:04 -0700 | [diff] [blame] | 376 | "csid0", "csid1", "csid2", |
Pavan Kumar Chilamkurthi | b6aa86d | 2017-05-01 23:47:11 -0700 | [diff] [blame] | 377 | "ife0", "ife1", "ife2", "ipe0", |
| 378 | "ipe1", "cam-cdm-intf0", "cpas-cdm0", "bps0", |
| 379 | "icp0", "jpeg-dma0", "jpeg0", "fd0"; |
| 380 | client-axi-port-names = |
| 381 | "cam_hf_1", "cam_hf_2", "cam_hf_2", "cam_sf_1", |
Pavan Kumar Chilamkurthi | 4e070ba | 2017-05-12 14:47:04 -0700 | [diff] [blame] | 382 | "cam_hf_1", "cam_hf_2", "cam_hf_2", |
Pavan Kumar Chilamkurthi | b6aa86d | 2017-05-01 23:47:11 -0700 | [diff] [blame] | 383 | "cam_hf_1", "cam_hf_2", "cam_hf_2", "cam_sf_1", |
| 384 | "cam_sf_1", "cam_sf_1", "cam_sf_1", "cam_sf_1", |
| 385 | "cam_sf_1", "cam_sf_1", "cam_sf_1", "cam_sf_1"; |
| 386 | client-bus-camnoc-based; |
| 387 | qcom,axi-port-list { |
| 388 | qcom,axi-port1 { |
| 389 | qcom,axi-port-name = "cam_hf_1"; |
| 390 | qcom,axi-port-mnoc { |
| 391 | qcom,msm-bus,name = "cam_hf_1_mnoc"; |
| 392 | qcom,msm-bus-vector-dyn-vote; |
| 393 | qcom,msm-bus,num-cases = <2>; |
| 394 | qcom,msm-bus,num-paths = <1>; |
| 395 | qcom,msm-bus,vectors-KBps = |
| 396 | <MSM_BUS_MASTER_CAMNOC_HF |
| 397 | MSM_BUS_SLAVE_EBI_CH0 0 0>, |
| 398 | <MSM_BUS_MASTER_CAMNOC_HF |
| 399 | MSM_BUS_SLAVE_EBI_CH0 0 0>; |
| 400 | }; |
| 401 | qcom,axi-port-camnoc { |
| 402 | qcom,msm-bus,name = "cam_hf_1_camnoc"; |
| 403 | qcom,msm-bus-vector-dyn-vote; |
| 404 | qcom,msm-bus,num-cases = <2>; |
| 405 | qcom,msm-bus,num-paths = <1>; |
| 406 | qcom,msm-bus,vectors-KBps = |
| 407 | <MSM_BUS_MASTER_CAMNOC_HF |
| 408 | MSM_BUS_SLAVE_EBI_CH0 0 0>, |
| 409 | <MSM_BUS_MASTER_CAMNOC_HF |
| 410 | MSM_BUS_SLAVE_EBI_CH0 0 0>; |
| 411 | }; |
| 412 | }; |
| 413 | qcom,axi-port2 { |
| 414 | qcom,axi-port-name = "cam_hf_2"; |
| 415 | qcom,axi-port-mnoc { |
| 416 | qcom,msm-bus,name = "cam_hf_2_mnoc"; |
| 417 | qcom,msm-bus-vector-dyn-vote; |
| 418 | qcom,msm-bus,num-cases = <2>; |
| 419 | qcom,msm-bus,num-paths = <1>; |
| 420 | qcom,msm-bus,vectors-KBps = |
| 421 | <MSM_BUS_MASTER_CAMNOC_HF |
| 422 | MSM_BUS_SLAVE_EBI_CH0 0 0>, |
| 423 | <MSM_BUS_MASTER_CAMNOC_HF |
| 424 | MSM_BUS_SLAVE_EBI_CH0 0 0>; |
| 425 | }; |
| 426 | qcom,axi-port-camnoc { |
| 427 | qcom,msm-bus,name = "cam_hf_1_camnoc"; |
| 428 | qcom,msm-bus-vector-dyn-vote; |
| 429 | qcom,msm-bus,num-cases = <2>; |
| 430 | qcom,msm-bus,num-paths = <1>; |
| 431 | qcom,msm-bus,vectors-KBps = |
| 432 | <MSM_BUS_MASTER_CAMNOC_HF |
| 433 | MSM_BUS_SLAVE_EBI_CH0 0 0>, |
| 434 | <MSM_BUS_MASTER_CAMNOC_HF |
| 435 | MSM_BUS_SLAVE_EBI_CH0 0 0>; |
| 436 | }; |
| 437 | }; |
| 438 | qcom,axi-port3 { |
| 439 | qcom,axi-port-name = "cam_sf_1"; |
| 440 | qcom,axi-port-mnoc { |
| 441 | qcom,msm-bus,name = "cam_sf_1_mnoc"; |
| 442 | qcom,msm-bus-vector-dyn-vote; |
| 443 | qcom,msm-bus,num-cases = <2>; |
| 444 | qcom,msm-bus,num-paths = <1>; |
| 445 | qcom,msm-bus,vectors-KBps = |
| 446 | <MSM_BUS_MASTER_CAMNOC_SF |
| 447 | MSM_BUS_SLAVE_EBI_CH0 0 0>, |
| 448 | <MSM_BUS_MASTER_CAMNOC_SF |
| 449 | MSM_BUS_SLAVE_EBI_CH0 0 0>; |
| 450 | }; |
| 451 | qcom,axi-port-camnoc { |
| 452 | qcom,msm-bus,name = "cam_sf_1_camnoc"; |
| 453 | qcom,msm-bus-vector-dyn-vote; |
| 454 | qcom,msm-bus,num-cases = <2>; |
| 455 | qcom,msm-bus,num-paths = <1>; |
| 456 | qcom,msm-bus,vectors-KBps = |
| 457 | <MSM_BUS_MASTER_CAMNOC_SF |
| 458 | MSM_BUS_SLAVE_EBI_CH0 0 0>, |
| 459 | <MSM_BUS_MASTER_CAMNOC_SF |
| 460 | MSM_BUS_SLAVE_EBI_CH0 0 0>; |
| 461 | }; |
| 462 | }; |
| 463 | }; |
| 464 | }; |
Hariram Purushothaman | e87b44e0 | 2017-03-29 13:53:01 -0700 | [diff] [blame] | 465 | |
| 466 | qcom,cam-cdm-intf { |
| 467 | compatible = "qcom,cam-cdm-intf"; |
| 468 | cell-index = <0>; |
| 469 | label = "cam-cdm-intf"; |
| 470 | num-hw-cdm = <1>; |
| 471 | cdm-client-names = "ife", |
| 472 | "jpeg-dma", |
| 473 | "jpeg", |
| 474 | "fd"; |
| 475 | status = "ok"; |
| 476 | }; |
| 477 | |
| 478 | qcom,cpas-cdm0@ac48000 { |
| 479 | cell-index = <0>; |
| 480 | compatible = "qcom,cam170-cpas-cdm0"; |
| 481 | label = "cpas-cdm"; |
| 482 | reg = <0xac48000 0x1000>; |
| 483 | reg-names = "cpas-cdm"; |
| 484 | reg-cam-base = <0x48000>; |
| 485 | interrupts = <0 461 0>; |
| 486 | interrupt-names = "cpas-cdm"; |
| 487 | regulator-names = "camss"; |
| 488 | camss-supply = <&titan_top_gdsc>; |
| 489 | clock-names = "gcc_camera_ahb", |
| 490 | "gcc_camera_axi", |
| 491 | "cam_cc_soc_ahb_clk", |
| 492 | "cam_cc_cpas_ahb_clk", |
| 493 | "cam_cc_camnoc_axi_clk"; |
| 494 | clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, |
| 495 | <&clock_gcc GCC_CAMERA_AXI_CLK>, |
| 496 | <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| 497 | <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| 498 | <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>; |
| 499 | clock-rates = <0 0 0 0 0>; |
| 500 | cdm-client-names = "vfe"; |
| 501 | status = "ok"; |
| 502 | }; |
Jing Zhou | d402069 | 2017-02-09 15:16:49 -0800 | [diff] [blame] | 503 | |
| 504 | qcom,cam-isp { |
| 505 | compatible = "qcom,cam-isp"; |
| 506 | arch-compat = "ife"; |
| 507 | status = "ok"; |
| 508 | }; |
| 509 | |
| 510 | qcom,csid0@acb3000 { |
| 511 | cell-index = <0>; |
| 512 | compatible = "qcom,csid170"; |
| 513 | reg-names = "csid"; |
| 514 | reg = <0xacb3000 0x1000>; |
| 515 | reg-cam-base = <0xb3000>; |
| 516 | interrupt-names = "csid"; |
| 517 | interrupts = <0 464 0>; |
| 518 | regulator-names = "camss", "ife0"; |
| 519 | camss-supply = <&titan_top_gdsc>; |
| 520 | ife0-supply = <&ife_0_gdsc>; |
| 521 | clock-names = "camera_ahb", |
| 522 | "camera_axi", |
| 523 | "soc_ahb_clk", |
| 524 | "cpas_ahb_clk", |
| 525 | "slow_ahb_clk_src", |
| 526 | "ife_csid_clk", |
| 527 | "ife_csid_clk_src", |
| 528 | "ife_cphy_rx_clk", |
| 529 | "cphy_rx_clk_src", |
| 530 | "ife_clk", |
| 531 | "ife_clk_src", |
| 532 | "camnoc_axi_clk", |
| 533 | "ife_axi_clk"; |
| 534 | clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, |
| 535 | <&clock_gcc GCC_CAMERA_AXI_CLK>, |
| 536 | <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| 537 | <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| 538 | <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, |
| 539 | <&clock_camcc CAM_CC_IFE_0_CSID_CLK>, |
| 540 | <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>, |
| 541 | <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>, |
| 542 | <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, |
| 543 | <&clock_camcc CAM_CC_IFE_0_CLK>, |
| 544 | <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, |
| 545 | <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, |
| 546 | <&clock_camcc CAM_CC_IFE_0_AXI_CLK>; |
| 547 | clock-rates = <0 0 0 0 0 0 384000000 0 0 0 40400000 0 0>; |
| 548 | src-clock-name = "ife_csid_clk_src"; |
| 549 | status = "ok"; |
| 550 | }; |
| 551 | |
| 552 | qcom,vfe0@acaf000 { |
| 553 | cell-index = <0>; |
| 554 | compatible = "qcom,vfe170"; |
| 555 | reg-names = "ife"; |
| 556 | reg = <0xacaf000 0x4000>; |
| 557 | reg-cam-base = <0xaf000>; |
| 558 | interrupt-names = "ife"; |
| 559 | interrupts = <0 465 0>; |
| 560 | regulator-names = "camss", "ife0"; |
| 561 | camss-supply = <&titan_top_gdsc>; |
| 562 | ife0-supply = <&ife_0_gdsc>; |
| 563 | clock-names = "camera_ahb", |
| 564 | "camera_axi", |
| 565 | "soc_ahb_clk", |
| 566 | "cpas_ahb_clk", |
| 567 | "slow_ahb_clk_src", |
| 568 | "ife_clk", |
| 569 | "ife_clk_src", |
| 570 | "camnoc_axi_clk", |
| 571 | "ife_axi_clk"; |
| 572 | clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, |
| 573 | <&clock_gcc GCC_CAMERA_AXI_CLK>, |
| 574 | <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| 575 | <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| 576 | <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, |
| 577 | <&clock_camcc CAM_CC_IFE_0_CLK>, |
| 578 | <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, |
| 579 | <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, |
| 580 | <&clock_camcc CAM_CC_IFE_0_AXI_CLK>; |
| 581 | clock-rates = <0 0 0 0 0 0 404000000 0 0>; |
| 582 | src-clock-name = "ife_clk_src"; |
| 583 | clock-names-option = "ife_dsp_clk"; |
| 584 | clocks-option = <&clock_camcc CAM_CC_IFE_0_DSP_CLK>; |
| 585 | clock-rates-option = <404000000>; |
| 586 | status = "ok"; |
| 587 | }; |
| 588 | |
| 589 | qcom,csid1@acba000 { |
| 590 | cell-index = <1>; |
| 591 | compatible = "qcom,csid170"; |
| 592 | reg-names = "csid"; |
| 593 | reg = <0xacba000 0x1000>; |
| 594 | reg-cam-base = <0xba000>; |
| 595 | interrupt-names = "csid"; |
| 596 | interrupts = <0 466 0>; |
| 597 | regulator-names = "camss", "ife1"; |
| 598 | camss-supply = <&titan_top_gdsc>; |
| 599 | ife1-supply = <&ife_1_gdsc>; |
| 600 | clock-names = "camera_ahb", |
| 601 | "camera_axi", |
| 602 | "soc_ahb_clk", |
| 603 | "cpas_ahb_clk", |
| 604 | "slow_ahb_clk_src", |
| 605 | "ife_csid_clk", |
| 606 | "ife_csid_clk_src", |
| 607 | "ife_cphy_rx_clk", |
| 608 | "cphy_rx_clk_src", |
| 609 | "ife_clk", |
| 610 | "ife_clk_src", |
| 611 | "camnoc_axi_clk", |
| 612 | "ife_axi_clk"; |
| 613 | clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, |
| 614 | <&clock_gcc GCC_CAMERA_AXI_CLK>, |
| 615 | <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| 616 | <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| 617 | <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, |
| 618 | <&clock_camcc CAM_CC_IFE_1_CSID_CLK>, |
| 619 | <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>, |
| 620 | <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>, |
| 621 | <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, |
| 622 | <&clock_camcc CAM_CC_IFE_1_CLK>, |
| 623 | <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, |
| 624 | <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, |
| 625 | <&clock_camcc CAM_CC_IFE_1_AXI_CLK>; |
| 626 | clock-rates = <0 0 0 0 0 0 384000000 0 0 0 40400000 0 0>; |
| 627 | src-clock-name = "ife_csid_clk_src"; |
| 628 | status = "ok"; |
| 629 | }; |
| 630 | |
| 631 | qcom,vfe1@acb6000 { |
| 632 | cell-index = <1>; |
| 633 | compatible = "qcom,vfe170"; |
| 634 | reg-names = "ife"; |
| 635 | reg = <0xacb6000 0x4000>; |
| 636 | reg-cam-base = <0xb6000>; |
| 637 | interrupt-names = "ife"; |
| 638 | interrupts = <0 467 0>; |
| 639 | regulator-names = "camss", "ife1"; |
| 640 | camss-supply = <&titan_top_gdsc>; |
| 641 | ife1-supply = <&ife_1_gdsc>; |
| 642 | clock-names = "camera_ahb", |
| 643 | "camera_axi", |
| 644 | "soc_ahb_clk", |
| 645 | "cpas_ahb_clk", |
| 646 | "slow_ahb_clk_src", |
| 647 | "ife_clk", |
| 648 | "ife_clk_src", |
| 649 | "camnoc_axi_clk", |
| 650 | "ife_axi_clk"; |
| 651 | clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, |
| 652 | <&clock_gcc GCC_CAMERA_AXI_CLK>, |
| 653 | <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| 654 | <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| 655 | <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, |
| 656 | <&clock_camcc CAM_CC_IFE_1_CLK>, |
| 657 | <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, |
| 658 | <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, |
| 659 | <&clock_camcc CAM_CC_IFE_1_AXI_CLK>; |
| 660 | clock-rates = <0 0 0 0 0 0 404000000 0 0>; |
| 661 | src-clock-name = "ife_clk_src"; |
| 662 | clock-names-option = "ife_dsp_clk"; |
| 663 | clocks-option = <&clock_camcc CAM_CC_IFE_1_DSP_CLK>; |
| 664 | clock-rates-option = <404000000>; |
| 665 | status = "ok"; |
| 666 | }; |
| 667 | |
| 668 | qcom,csid-lite@acc8000 { |
| 669 | cell-index = <2>; |
| 670 | compatible = "qcom,csid-lite170"; |
| 671 | reg-names = "csid-lite"; |
| 672 | reg = <0xacc8000 0x1000>; |
| 673 | reg-cam-base = <0xc8000>; |
| 674 | interrupt-names = "csid-lite"; |
| 675 | interrupts = <0 468 0>; |
| 676 | regulator-names = "camss"; |
| 677 | camss-supply = <&titan_top_gdsc>; |
| 678 | clock-names = "camera_ahb", |
| 679 | "camera_axi", |
| 680 | "soc_ahb_clk", |
| 681 | "cpas_ahb_clk", |
| 682 | "slow_ahb_clk_src", |
| 683 | "ife_csid_clk", |
| 684 | "ife_csid_clk_src", |
| 685 | "ife_cphy_rx_clk", |
| 686 | "cphy_rx_clk_src", |
| 687 | "ife_clk", |
| 688 | "ife_clk_src", |
| 689 | "camnoc_axi_clk"; |
| 690 | clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, |
| 691 | <&clock_gcc GCC_CAMERA_AXI_CLK>, |
| 692 | <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| 693 | <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| 694 | <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, |
| 695 | <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, |
| 696 | <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, |
| 697 | <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, |
| 698 | <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, |
| 699 | <&clock_camcc CAM_CC_IFE_LITE_CLK>, |
| 700 | <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>, |
| 701 | <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>; |
| 702 | clock-rates = <0 0 0 0 0 0 384000000 0 0 0 40400000 0>; |
| 703 | src-clock-name = "ife_csid_clk_src"; |
| 704 | status = "ok"; |
| 705 | }; |
| 706 | |
| 707 | qcom,vfe-lite@acc4000 { |
| 708 | cell-index = <2>; |
| 709 | compatible = "qcom,vfe-lite170"; |
| 710 | reg-names = "ife-lite"; |
| 711 | reg = <0xacc4000 0x4000>; |
| 712 | reg-cam-base = <0xc4000>; |
| 713 | interrupt-names = "ife-lite"; |
| 714 | interrupts = <0 469 0>; |
| 715 | regulator-names = "camss"; |
| 716 | camss-supply = <&titan_top_gdsc>; |
| 717 | clock-names = "camera_ahb", |
| 718 | "camera_axi", |
| 719 | "soc_ahb_clk", |
| 720 | "cpas_ahb_clk", |
| 721 | "slow_ahb_clk_src", |
| 722 | "ife_clk", |
| 723 | "ife_clk_src", |
| 724 | "camnoc_axi_clk"; |
| 725 | clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, |
| 726 | <&clock_gcc GCC_CAMERA_AXI_CLK>, |
| 727 | <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| 728 | <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| 729 | <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, |
| 730 | <&clock_camcc CAM_CC_IFE_LITE_CLK>, |
| 731 | <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>, |
| 732 | <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>; |
| 733 | qcom,clock-rates = <0 0 0 0 0 0 404000000 0>; |
| 734 | src-clock-name = "ife_clk_src"; |
| 735 | status = "ok"; |
| 736 | }; |
Hariram Purushothaman | 71b8d63 | 2017-05-15 14:49:59 -0700 | [diff] [blame] | 737 | |
| 738 | qcom,cam-icp { |
| 739 | compatible = "qcom,cam-icp"; |
| 740 | compat-hw-name = "qcom,a5", |
| 741 | "qcom,ipe0", |
| 742 | "qcom,ipe1", |
| 743 | "qcom,bps"; |
| 744 | num-a5 = <1>; |
| 745 | num-ipe = <2>; |
| 746 | num-bps = <1>; |
| 747 | status = "ok"; |
| 748 | }; |
| 749 | |
| 750 | qcom,a5@ac00000 { |
| 751 | cell-index = <0>; |
| 752 | compatible = "qcom,cam_a5"; |
| 753 | reg = <0xac00000 0x6000>, |
| 754 | <0xac10000 0x8000>, |
| 755 | <0xac18000 0x3000>; |
| 756 | reg-names = "a5_qgic", "a5_sierra", "a5_csr"; |
| 757 | reg-cam-base = <0x00000 0x10000 0x18000>; |
| 758 | interrupts = <0 463 0>; |
| 759 | interrupt-names = "a5"; |
| 760 | regulator-names = "camss-vdd"; |
| 761 | camss-vdd-supply = <&titan_top_gdsc>; |
| 762 | clock-names = "gcc_cam_ahb_clk", |
| 763 | "gcc_cam_axi_clk", |
| 764 | "soc_ahb_clk", |
| 765 | "cpas_ahb_clk", |
| 766 | "camnoc_axi_clk", |
| 767 | "icp_apb_clk", |
| 768 | "icp_atb_clk", |
| 769 | "icp_clk", |
| 770 | "icp_clk_src", |
| 771 | "icp_cti_clk", |
| 772 | "icp_ts_clk"; |
| 773 | clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>, |
| 774 | <&clock_gcc GCC_CAMERA_AXI_CLK>, |
| 775 | <&clock_camcc CAM_CC_SOC_AHB_CLK>, |
| 776 | <&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
| 777 | <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, |
| 778 | <&clock_camcc CAM_CC_ICP_APB_CLK>, |
| 779 | <&clock_camcc CAM_CC_ICP_ATB_CLK>, |
| 780 | <&clock_camcc CAM_CC_ICP_CLK>, |
| 781 | <&clock_camcc CAM_CC_ICP_CLK_SRC>, |
| 782 | <&clock_camcc CAM_CC_ICP_CTI_CLK>, |
| 783 | <&clock_camcc CAM_CC_ICP_TS_CLK>; |
| 784 | |
| 785 | clock-rates = <0 0 0 80000000 0 0 0 0 600000000 0 0>; |
| 786 | fw_name = "CAMERA_ICP.elf"; |
| 787 | status = "ok"; |
| 788 | }; |
| 789 | |
| 790 | qcom,ipe0 { |
| 791 | cell-index = <0>; |
| 792 | compatible = "qcom,cam_ipe"; |
| 793 | regulator-names = "ipe0-vdd"; |
| 794 | ipe0-vdd-supply = <&ipe_0_gdsc>; |
| 795 | clock-names = "ipe_0_ahb_clk", |
| 796 | "ipe_0_areg_clk", |
| 797 | "ipe_0_axi_clk", |
| 798 | "ipe_0_clk", |
| 799 | "ipe_0_clk_src"; |
| 800 | clocks = <&clock_camcc CAM_CC_IPE_0_AHB_CLK>, |
| 801 | <&clock_camcc CAM_CC_IPE_0_AREG_CLK>, |
| 802 | <&clock_camcc CAM_CC_IPE_0_AXI_CLK>, |
| 803 | <&clock_camcc CAM_CC_IPE_0_CLK>, |
| 804 | <&clock_camcc CAM_CC_IPE_0_CLK_SRC>; |
| 805 | |
| 806 | clock-rates = <80000000 400000000 0 0 600000000>; |
| 807 | status = "ok"; |
| 808 | }; |
| 809 | |
| 810 | qcom,ipe1 { |
| 811 | cell-index = <1>; |
| 812 | compatible = "qcom,cam_ipe"; |
| 813 | regulator-names = "ipe1-vdd"; |
| 814 | ipe1-vdd-supply = <&ipe_1_gdsc>; |
| 815 | clock-names = "ipe_1_ahb_clk", |
| 816 | "ipe_1_areg_clk", |
| 817 | "ipe_1_axi_clk", |
| 818 | "ipe_1_clk", |
| 819 | "ipe_1_clk_src"; |
| 820 | clocks = <&clock_camcc CAM_CC_IPE_1_AHB_CLK>, |
| 821 | <&clock_camcc CAM_CC_IPE_1_AREG_CLK>, |
| 822 | <&clock_camcc CAM_CC_IPE_1_AXI_CLK>, |
| 823 | <&clock_camcc CAM_CC_IPE_1_CLK>, |
| 824 | <&clock_camcc CAM_CC_IPE_1_CLK_SRC>; |
| 825 | |
| 826 | clock-rates = <80000000 400000000 0 0 600000000>; |
| 827 | status = "ok"; |
| 828 | }; |
| 829 | |
| 830 | qcom,bps { |
| 831 | cell-index = <0>; |
| 832 | compatible = "qcom,cam_bps"; |
| 833 | regulator-names = "bps-vdd"; |
| 834 | bps-vdd-supply = <&bps_gdsc>; |
| 835 | clock-names = "bps_ahb_clk", |
| 836 | "bps_areg_clk", |
| 837 | "bps_axi_clk", |
| 838 | "bps_clk", |
| 839 | "bps_clk_src"; |
| 840 | clocks = <&clock_camcc CAM_CC_BPS_AHB_CLK>, |
| 841 | <&clock_camcc CAM_CC_BPS_AREG_CLK>, |
| 842 | <&clock_camcc CAM_CC_BPS_AXI_CLK>, |
| 843 | <&clock_camcc CAM_CC_BPS_CLK>, |
| 844 | <&clock_camcc CAM_CC_BPS_CLK_SRC>; |
| 845 | |
| 846 | clock-rates = <80000000 400000000 0 0 600000000>; |
| 847 | status = "ok"; |
| 848 | }; |
Lakshmi Narayana Kalavala | c0dac06 | 2016-12-01 17:20:09 -0800 | [diff] [blame] | 849 | }; |