Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 1 | /* |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 2 | * Copyright (C) 2002 ARM Limited, All Rights Reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | * |
| 8 | * Interrupt architecture for the GIC: |
| 9 | * |
| 10 | * o There is one Interrupt Distributor, which receives interrupts |
| 11 | * from system devices and sends them to the Interrupt Controllers. |
| 12 | * |
| 13 | * o There is one CPU Interface per CPU, which sends interrupts sent |
| 14 | * by the Distributor, and interrupts generated locally, to the |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 15 | * associated CPU. The base address of the CPU interface is usually |
| 16 | * aliased so that the same address points to different chips depending |
| 17 | * on the CPU it is accessed from. |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 18 | * |
| 19 | * Note that IRQs 0-31 are special - they are local to each CPU. |
| 20 | * As such, the enable set/clear, pending set/clear and active bit |
| 21 | * registers are banked per-cpu for these sources. |
| 22 | */ |
| 23 | #include <linux/init.h> |
| 24 | #include <linux/kernel.h> |
Rob Herring | f37a53c | 2011-10-21 17:14:27 -0500 | [diff] [blame] | 25 | #include <linux/err.h> |
Arnd Bergmann | 7e1efcf | 2011-11-01 00:28:37 +0100 | [diff] [blame] | 26 | #include <linux/module.h> |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 27 | #include <linux/list.h> |
| 28 | #include <linux/smp.h> |
Catalin Marinas | c011470 | 2013-01-14 18:05:37 +0000 | [diff] [blame] | 29 | #include <linux/cpu.h> |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 30 | #include <linux/cpu_pm.h> |
Catalin Marinas | dcb86e8 | 2005-08-31 21:45:14 +0100 | [diff] [blame] | 31 | #include <linux/cpumask.h> |
Russell King | fced80c | 2008-09-06 12:10:45 +0100 | [diff] [blame] | 32 | #include <linux/io.h> |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 33 | #include <linux/of.h> |
| 34 | #include <linux/of_address.h> |
| 35 | #include <linux/of_irq.h> |
Tomasz Nowicki | d60fc38 | 2015-03-24 14:02:49 +0000 | [diff] [blame] | 36 | #include <linux/acpi.h> |
Rob Herring | 4294f8ba | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 37 | #include <linux/irqdomain.h> |
Marc Zyngier | 292b293 | 2011-07-20 16:24:14 +0100 | [diff] [blame] | 38 | #include <linux/interrupt.h> |
| 39 | #include <linux/percpu.h> |
| 40 | #include <linux/slab.h> |
Joel Porquet | 41a83e0 | 2015-07-07 17:11:46 -0400 | [diff] [blame] | 41 | #include <linux/irqchip.h> |
Catalin Marinas | de88cbb | 2013-01-18 15:31:37 +0000 | [diff] [blame] | 42 | #include <linux/irqchip/chained_irq.h> |
Rob Herring | 520f7bd | 2012-12-27 13:10:24 -0600 | [diff] [blame] | 43 | #include <linux/irqchip/arm-gic.h> |
Subbaraman Narayanamurthy | 6d16998 | 2014-04-29 12:30:42 -0700 | [diff] [blame] | 44 | #include <linux/msm_rtb.h> |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 45 | |
Tomasz Figa | 29e697b | 2014-07-17 17:23:44 +0200 | [diff] [blame] | 46 | #include <asm/cputype.h> |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 47 | #include <asm/irq.h> |
Marc Zyngier | 562e002 | 2011-09-06 09:56:17 +0100 | [diff] [blame] | 48 | #include <asm/exception.h> |
Will Deacon | eb50439 | 2012-01-20 12:01:12 +0100 | [diff] [blame] | 49 | #include <asm/smp_plat.h> |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame] | 50 | #include <asm/virt.h> |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 51 | |
Teng Fei Fan | 1e3e9f6 | 2018-04-11 18:02:28 +0800 | [diff] [blame] | 52 | #include <linux/syscore_ops.h> |
Marc Zyngier | d51d0af | 2014-06-30 16:01:30 +0100 | [diff] [blame] | 53 | #include "irq-gic-common.h" |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 54 | |
Marc Zyngier | 76e52dd | 2015-09-30 12:01:16 +0100 | [diff] [blame] | 55 | #ifdef CONFIG_ARM64 |
| 56 | #include <asm/cpufeature.h> |
| 57 | |
| 58 | static void gic_check_cpu_features(void) |
| 59 | { |
Marc Zyngier | 25fc11a | 2016-04-22 12:25:33 +0100 | [diff] [blame] | 60 | WARN_TAINT_ONCE(this_cpu_has_cap(ARM64_HAS_SYSREG_GIC_CPUIF), |
Marc Zyngier | 76e52dd | 2015-09-30 12:01:16 +0100 | [diff] [blame] | 61 | TAINT_CPU_OUT_OF_SPEC, |
| 62 | "GICv3 system registers enabled, broken firmware!\n"); |
| 63 | } |
| 64 | #else |
| 65 | #define gic_check_cpu_features() do { } while(0) |
| 66 | #endif |
| 67 | |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 68 | union gic_base { |
| 69 | void __iomem *common_base; |
Stephen Boyd | 6859358 | 2014-03-04 17:02:01 -0800 | [diff] [blame] | 70 | void __percpu * __iomem *percpu_base; |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 71 | }; |
| 72 | |
| 73 | struct gic_chip_data { |
Linus Walleij | 58b8964 | 2015-10-24 00:15:53 +0200 | [diff] [blame] | 74 | struct irq_chip chip; |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 75 | union gic_base dist_base; |
| 76 | union gic_base cpu_base; |
Jon Hunter | f673b9b | 2016-05-10 16:14:44 +0100 | [diff] [blame] | 77 | void __iomem *raw_dist_base; |
| 78 | void __iomem *raw_cpu_base; |
| 79 | u32 percpu_offset; |
Jon Hunter | 9c8eddd | 2016-06-07 16:12:34 +0100 | [diff] [blame] | 80 | #if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM) |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 81 | u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)]; |
Marc Zyngier | 1c7d4dd | 2015-11-16 19:13:28 +0000 | [diff] [blame] | 82 | u32 saved_spi_active[DIV_ROUND_UP(1020, 32)]; |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 83 | u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)]; |
| 84 | u32 saved_spi_target[DIV_ROUND_UP(1020, 4)]; |
| 85 | u32 __percpu *saved_ppi_enable; |
Marc Zyngier | 1c7d4dd | 2015-11-16 19:13:28 +0000 | [diff] [blame] | 86 | u32 __percpu *saved_ppi_active; |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 87 | u32 __percpu *saved_ppi_conf; |
| 88 | #endif |
Grant Likely | 7529495 | 2012-02-14 14:06:57 -0700 | [diff] [blame] | 89 | struct irq_domain *domain; |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 90 | unsigned int gic_irqs; |
| 91 | #ifdef CONFIG_GIC_NON_BANKED |
| 92 | void __iomem *(*get_base)(union gic_base *); |
| 93 | #endif |
| 94 | }; |
| 95 | |
Marc Zyngier | 04c8b0f | 2016-06-27 18:11:43 +0100 | [diff] [blame] | 96 | #ifdef CONFIG_BL_SWITCHER |
| 97 | |
| 98 | static DEFINE_RAW_SPINLOCK(cpu_map_lock); |
| 99 | |
| 100 | #define gic_lock_irqsave(f) \ |
| 101 | raw_spin_lock_irqsave(&cpu_map_lock, (f)) |
| 102 | #define gic_unlock_irqrestore(f) \ |
| 103 | raw_spin_unlock_irqrestore(&cpu_map_lock, (f)) |
| 104 | |
| 105 | #define gic_lock() raw_spin_lock(&cpu_map_lock) |
| 106 | #define gic_unlock() raw_spin_unlock(&cpu_map_lock) |
| 107 | |
| 108 | #else |
| 109 | |
| 110 | #define gic_lock_irqsave(f) do { (void)(f); } while(0) |
| 111 | #define gic_unlock_irqrestore(f) do { (void)(f); } while(0) |
| 112 | |
| 113 | #define gic_lock() do { } while(0) |
| 114 | #define gic_unlock() do { } while(0) |
| 115 | |
| 116 | #endif |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 117 | |
Santosh Shilimkar | d7ed36a | 2011-03-02 08:03:22 +0100 | [diff] [blame] | 118 | /* |
Nicolas Pitre | 384a290 | 2012-04-11 18:55:48 -0400 | [diff] [blame] | 119 | * The GIC mapping of CPU interfaces does not necessarily match |
| 120 | * the logical CPU numbering. Let's use a mapping as returned |
| 121 | * by the GIC itself. |
| 122 | */ |
| 123 | #define NR_GIC_CPU_IF 8 |
| 124 | static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly; |
| 125 | |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame] | 126 | static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE; |
| 127 | |
Linus Walleij | a27d21e | 2015-12-18 10:44:53 +0100 | [diff] [blame] | 128 | static struct gic_chip_data gic_data[CONFIG_ARM_GIC_MAX_NR] __read_mostly; |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 129 | |
Julien Grall | 502d6df | 2016-04-11 16:32:54 +0100 | [diff] [blame] | 130 | static struct gic_kvm_info gic_v2_kvm_info; |
| 131 | |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 132 | #ifdef CONFIG_GIC_NON_BANKED |
| 133 | static void __iomem *gic_get_percpu_base(union gic_base *base) |
| 134 | { |
Christoph Lameter | 513d1a2 | 2014-09-02 10:00:07 -0500 | [diff] [blame] | 135 | return raw_cpu_read(*base->percpu_base); |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 136 | } |
| 137 | |
| 138 | static void __iomem *gic_get_common_base(union gic_base *base) |
| 139 | { |
| 140 | return base->common_base; |
| 141 | } |
| 142 | |
| 143 | static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data) |
| 144 | { |
| 145 | return data->get_base(&data->dist_base); |
| 146 | } |
| 147 | |
| 148 | static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data) |
| 149 | { |
| 150 | return data->get_base(&data->cpu_base); |
| 151 | } |
| 152 | |
| 153 | static inline void gic_set_base_accessor(struct gic_chip_data *data, |
| 154 | void __iomem *(*f)(union gic_base *)) |
| 155 | { |
| 156 | data->get_base = f; |
| 157 | } |
| 158 | #else |
| 159 | #define gic_data_dist_base(d) ((d)->dist_base.common_base) |
| 160 | #define gic_data_cpu_base(d) ((d)->cpu_base.common_base) |
Sachin Kamat | 46f101d | 2013-03-13 15:05:15 +0530 | [diff] [blame] | 161 | #define gic_set_base_accessor(d, f) |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 162 | #endif |
| 163 | |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 164 | static inline void __iomem *gic_dist_base(struct irq_data *d) |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 165 | { |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 166 | struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 167 | return gic_data_dist_base(gic_data); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 168 | } |
| 169 | |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 170 | static inline void __iomem *gic_cpu_base(struct irq_data *d) |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 171 | { |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 172 | struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 173 | return gic_data_cpu_base(gic_data); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 174 | } |
| 175 | |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 176 | static inline unsigned int gic_irq(struct irq_data *d) |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 177 | { |
Rob Herring | 4294f8ba | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 178 | return d->hwirq; |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 179 | } |
| 180 | |
Marc Zyngier | 01f779f | 2015-08-26 17:00:45 +0100 | [diff] [blame] | 181 | static inline bool cascading_gic_irq(struct irq_data *d) |
| 182 | { |
| 183 | void *data = irq_data_get_irq_handler_data(d); |
| 184 | |
| 185 | /* |
Thomas Gleixner | 71466535 | 2015-09-15 12:37:36 +0200 | [diff] [blame] | 186 | * If handler_data is set, this is a cascading interrupt, and |
| 187 | * it cannot possibly be forwarded. |
Marc Zyngier | 01f779f | 2015-08-26 17:00:45 +0100 | [diff] [blame] | 188 | */ |
Thomas Gleixner | 71466535 | 2015-09-15 12:37:36 +0200 | [diff] [blame] | 189 | return data != NULL; |
Marc Zyngier | 01f779f | 2015-08-26 17:00:45 +0100 | [diff] [blame] | 190 | } |
| 191 | |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 192 | /* |
| 193 | * Routines to acknowledge, disable and enable interrupts |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 194 | */ |
Marc Zyngier | 5671780 | 2015-03-18 11:01:23 +0000 | [diff] [blame] | 195 | static void gic_poke_irq(struct irq_data *d, u32 offset) |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 196 | { |
Rob Herring | 4294f8ba | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 197 | u32 mask = 1 << (gic_irq(d) % 32); |
Marc Zyngier | 5671780 | 2015-03-18 11:01:23 +0000 | [diff] [blame] | 198 | writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4); |
| 199 | } |
| 200 | |
| 201 | static int gic_peek_irq(struct irq_data *d, u32 offset) |
| 202 | { |
| 203 | u32 mask = 1 << (gic_irq(d) % 32); |
| 204 | return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask); |
| 205 | } |
| 206 | |
| 207 | static void gic_mask_irq(struct irq_data *d) |
| 208 | { |
Marc Zyngier | 5671780 | 2015-03-18 11:01:23 +0000 | [diff] [blame] | 209 | gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 210 | } |
| 211 | |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame] | 212 | static void gic_eoimode1_mask_irq(struct irq_data *d) |
| 213 | { |
| 214 | gic_mask_irq(d); |
Marc Zyngier | 01f779f | 2015-08-26 17:00:45 +0100 | [diff] [blame] | 215 | /* |
| 216 | * When masking a forwarded interrupt, make sure it is |
| 217 | * deactivated as well. |
| 218 | * |
| 219 | * This ensures that an interrupt that is getting |
| 220 | * disabled/masked will not get "stuck", because there is |
| 221 | * noone to deactivate it (guest is being terminated). |
| 222 | */ |
Thomas Gleixner | 71466535 | 2015-09-15 12:37:36 +0200 | [diff] [blame] | 223 | if (irqd_is_forwarded_to_vcpu(d)) |
Marc Zyngier | 01f779f | 2015-08-26 17:00:45 +0100 | [diff] [blame] | 224 | gic_poke_irq(d, GIC_DIST_ACTIVE_CLEAR); |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame] | 225 | } |
| 226 | |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 227 | static void gic_unmask_irq(struct irq_data *d) |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 228 | { |
Marc Zyngier | 5671780 | 2015-03-18 11:01:23 +0000 | [diff] [blame] | 229 | gic_poke_irq(d, GIC_DIST_ENABLE_SET); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 230 | } |
| 231 | |
Will Deacon | 1a01753 | 2011-02-09 12:01:12 +0000 | [diff] [blame] | 232 | static void gic_eoi_irq(struct irq_data *d) |
| 233 | { |
Subbaraman Narayanamurthy | c63401e | 2018-02-23 21:26:28 +0530 | [diff] [blame] | 234 | writel_relaxed_no_log(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); |
Will Deacon | 1a01753 | 2011-02-09 12:01:12 +0000 | [diff] [blame] | 235 | } |
| 236 | |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame] | 237 | static void gic_eoimode1_eoi_irq(struct irq_data *d) |
| 238 | { |
Marc Zyngier | 01f779f | 2015-08-26 17:00:45 +0100 | [diff] [blame] | 239 | /* Do not deactivate an IRQ forwarded to a vcpu. */ |
Thomas Gleixner | 71466535 | 2015-09-15 12:37:36 +0200 | [diff] [blame] | 240 | if (irqd_is_forwarded_to_vcpu(d)) |
Marc Zyngier | 01f779f | 2015-08-26 17:00:45 +0100 | [diff] [blame] | 241 | return; |
| 242 | |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame] | 243 | writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_DEACTIVATE); |
| 244 | } |
| 245 | |
Marc Zyngier | 5671780 | 2015-03-18 11:01:23 +0000 | [diff] [blame] | 246 | static int gic_irq_set_irqchip_state(struct irq_data *d, |
| 247 | enum irqchip_irq_state which, bool val) |
| 248 | { |
| 249 | u32 reg; |
| 250 | |
| 251 | switch (which) { |
| 252 | case IRQCHIP_STATE_PENDING: |
| 253 | reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR; |
| 254 | break; |
| 255 | |
| 256 | case IRQCHIP_STATE_ACTIVE: |
| 257 | reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR; |
| 258 | break; |
| 259 | |
| 260 | case IRQCHIP_STATE_MASKED: |
| 261 | reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET; |
| 262 | break; |
| 263 | |
| 264 | default: |
| 265 | return -EINVAL; |
| 266 | } |
| 267 | |
| 268 | gic_poke_irq(d, reg); |
| 269 | return 0; |
| 270 | } |
| 271 | |
| 272 | static int gic_irq_get_irqchip_state(struct irq_data *d, |
| 273 | enum irqchip_irq_state which, bool *val) |
| 274 | { |
| 275 | switch (which) { |
| 276 | case IRQCHIP_STATE_PENDING: |
| 277 | *val = gic_peek_irq(d, GIC_DIST_PENDING_SET); |
| 278 | break; |
| 279 | |
| 280 | case IRQCHIP_STATE_ACTIVE: |
| 281 | *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET); |
| 282 | break; |
| 283 | |
| 284 | case IRQCHIP_STATE_MASKED: |
| 285 | *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET); |
| 286 | break; |
| 287 | |
| 288 | default: |
| 289 | return -EINVAL; |
| 290 | } |
| 291 | |
| 292 | return 0; |
| 293 | } |
| 294 | |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 295 | static int gic_set_type(struct irq_data *d, unsigned int type) |
Rabin Vincent | 5c0c1f0 | 2010-05-28 04:37:38 +0100 | [diff] [blame] | 296 | { |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 297 | void __iomem *base = gic_dist_base(d); |
| 298 | unsigned int gicirq = gic_irq(d); |
Rabin Vincent | 5c0c1f0 | 2010-05-28 04:37:38 +0100 | [diff] [blame] | 299 | |
| 300 | /* Interrupt configuration for SGIs can't be changed */ |
| 301 | if (gicirq < 16) |
| 302 | return -EINVAL; |
| 303 | |
Liviu Dudau | fb7e7de | 2015-01-20 16:52:59 +0000 | [diff] [blame] | 304 | /* SPIs have restrictions on the supported types */ |
| 305 | if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && |
| 306 | type != IRQ_TYPE_EDGE_RISING) |
Rabin Vincent | 5c0c1f0 | 2010-05-28 04:37:38 +0100 | [diff] [blame] | 307 | return -EINVAL; |
| 308 | |
Marc Zyngier | 1dcc73d | 2015-04-22 18:20:04 +0100 | [diff] [blame] | 309 | return gic_configure_irq(gicirq, type, base, NULL); |
Santosh Shilimkar | d7ed36a | 2011-03-02 08:03:22 +0100 | [diff] [blame] | 310 | } |
| 311 | |
Marc Zyngier | 01f779f | 2015-08-26 17:00:45 +0100 | [diff] [blame] | 312 | static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) |
| 313 | { |
| 314 | /* Only interrupts on the primary GIC can be forwarded to a vcpu. */ |
| 315 | if (cascading_gic_irq(d)) |
| 316 | return -EINVAL; |
| 317 | |
Thomas Gleixner | 71466535 | 2015-09-15 12:37:36 +0200 | [diff] [blame] | 318 | if (vcpu) |
| 319 | irqd_set_forwarded_to_vcpu(d); |
| 320 | else |
| 321 | irqd_clr_forwarded_to_vcpu(d); |
Marc Zyngier | 01f779f | 2015-08-26 17:00:45 +0100 | [diff] [blame] | 322 | return 0; |
| 323 | } |
| 324 | |
Catalin Marinas | a06f546 | 2005-09-30 16:07:05 +0100 | [diff] [blame] | 325 | #ifdef CONFIG_SMP |
Russell King | c191789 | 2011-01-23 12:12:01 +0000 | [diff] [blame] | 326 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, |
| 327 | bool force) |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 328 | { |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 329 | void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3); |
Thomas Gleixner | ffde1de | 2014-04-16 14:36:44 +0000 | [diff] [blame] | 330 | unsigned int cpu, shift = (gic_irq(d) % 4) * 8; |
Russell King | c191789 | 2011-01-23 12:12:01 +0000 | [diff] [blame] | 331 | u32 val, mask, bit; |
Marc Zyngier | cf61387 | 2015-03-06 16:37:44 +0000 | [diff] [blame] | 332 | unsigned long flags; |
Russell King | c191789 | 2011-01-23 12:12:01 +0000 | [diff] [blame] | 333 | |
Thomas Gleixner | ffde1de | 2014-04-16 14:36:44 +0000 | [diff] [blame] | 334 | if (!force) |
| 335 | cpu = cpumask_any_and(mask_val, cpu_online_mask); |
| 336 | else |
| 337 | cpu = cpumask_first(mask_val); |
| 338 | |
Nicolas Pitre | 384a290 | 2012-04-11 18:55:48 -0400 | [diff] [blame] | 339 | if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids) |
Russell King | c191789 | 2011-01-23 12:12:01 +0000 | [diff] [blame] | 340 | return -EINVAL; |
| 341 | |
Marc Zyngier | 04c8b0f | 2016-06-27 18:11:43 +0100 | [diff] [blame] | 342 | gic_lock_irqsave(flags); |
Russell King | c191789 | 2011-01-23 12:12:01 +0000 | [diff] [blame] | 343 | mask = 0xff << shift; |
Nicolas Pitre | 384a290 | 2012-04-11 18:55:48 -0400 | [diff] [blame] | 344 | bit = gic_cpu_map[cpu] << shift; |
Subbaraman Narayanamurthy | c63401e | 2018-02-23 21:26:28 +0530 | [diff] [blame] | 345 | val = readl_relaxed_no_log(reg) & ~mask; |
| 346 | writel_relaxed_no_log(val | bit, reg); |
Marc Zyngier | 04c8b0f | 2016-06-27 18:11:43 +0100 | [diff] [blame] | 347 | gic_unlock_irqrestore(flags); |
Yinghai Lu | d5dedd4 | 2009-04-27 17:59:21 -0700 | [diff] [blame] | 348 | |
Marc Zyngier | 0407dac | 2016-02-19 15:00:29 +0000 | [diff] [blame] | 349 | return IRQ_SET_MASK_OK_DONE; |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 350 | } |
Catalin Marinas | a06f546 | 2005-09-30 16:07:05 +0100 | [diff] [blame] | 351 | #endif |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 352 | |
Stephen Boyd | 8783dd3 | 2014-03-04 16:40:30 -0800 | [diff] [blame] | 353 | static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) |
Marc Zyngier | 562e002 | 2011-09-06 09:56:17 +0100 | [diff] [blame] | 354 | { |
| 355 | u32 irqstat, irqnr; |
| 356 | struct gic_chip_data *gic = &gic_data[0]; |
| 357 | void __iomem *cpu_base = gic_data_cpu_base(gic); |
| 358 | |
| 359 | do { |
Subbaraman Narayanamurthy | c63401e | 2018-02-23 21:26:28 +0530 | [diff] [blame] | 360 | irqstat = readl_relaxed_no_log(cpu_base + GIC_CPU_INTACK); |
Haojian Zhuang | b8802f7 | 2014-05-11 16:05:58 +0800 | [diff] [blame] | 361 | irqnr = irqstat & GICC_IAR_INT_ID_MASK; |
Marc Zyngier | 562e002 | 2011-09-06 09:56:17 +0100 | [diff] [blame] | 362 | |
Marc Zyngier | 327ebe1 | 2015-12-16 14:11:22 +0000 | [diff] [blame] | 363 | if (likely(irqnr > 15 && irqnr < 1020)) { |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame] | 364 | if (static_key_true(&supports_deactivate)) |
Subbaraman Narayanamurthy | c63401e | 2018-02-23 21:26:28 +0530 | [diff] [blame] | 365 | writel_relaxed_no_log(irqstat, |
| 366 | cpu_base + GIC_CPU_EOI); |
Marc Zyngier | 60031b4 | 2014-08-26 11:03:20 +0100 | [diff] [blame] | 367 | handle_domain_irq(gic->domain, irqnr, regs); |
Subbaraman Narayanamurthy | 6d16998 | 2014-04-29 12:30:42 -0700 | [diff] [blame] | 368 | uncached_logk(LOGK_IRQ, (void *)(uintptr_t)irqnr); |
Marc Zyngier | 562e002 | 2011-09-06 09:56:17 +0100 | [diff] [blame] | 369 | continue; |
| 370 | } |
| 371 | if (irqnr < 16) { |
Subbaraman Narayanamurthy | c63401e | 2018-02-23 21:26:28 +0530 | [diff] [blame] | 372 | writel_relaxed_no_log(irqstat, cpu_base + GIC_CPU_EOI); |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame] | 373 | if (static_key_true(&supports_deactivate)) |
Subbaraman Narayanamurthy | c63401e | 2018-02-23 21:26:28 +0530 | [diff] [blame] | 374 | writel_relaxed_no_log(irqstat, |
| 375 | cpu_base + GIC_CPU_DEACTIVATE); |
Marc Zyngier | 562e002 | 2011-09-06 09:56:17 +0100 | [diff] [blame] | 376 | #ifdef CONFIG_SMP |
Will Deacon | f86c4fb | 2016-04-26 12:00:00 +0100 | [diff] [blame] | 377 | /* |
| 378 | * Ensure any shared data written by the CPU sending |
| 379 | * the IPI is read after we've read the ACK register |
| 380 | * on the GIC. |
| 381 | * |
| 382 | * Pairs with the write barrier in gic_raise_softirq |
| 383 | */ |
| 384 | smp_rmb(); |
Marc Zyngier | 562e002 | 2011-09-06 09:56:17 +0100 | [diff] [blame] | 385 | handle_IPI(irqnr, regs); |
| 386 | #endif |
Subbaraman Narayanamurthy | 6d16998 | 2014-04-29 12:30:42 -0700 | [diff] [blame] | 387 | uncached_logk(LOGK_IRQ, (void *)(uintptr_t)irqnr); |
Marc Zyngier | 562e002 | 2011-09-06 09:56:17 +0100 | [diff] [blame] | 388 | continue; |
| 389 | } |
| 390 | break; |
| 391 | } while (1); |
| 392 | } |
| 393 | |
Thomas Gleixner | bd0b9ac | 2015-09-14 10:42:37 +0200 | [diff] [blame] | 394 | static void gic_handle_cascade_irq(struct irq_desc *desc) |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 395 | { |
Jiang Liu | 5b29264 | 2015-06-04 12:13:20 +0800 | [diff] [blame] | 396 | struct gic_chip_data *chip_data = irq_desc_get_handler_data(desc); |
| 397 | struct irq_chip *chip = irq_desc_get_chip(desc); |
Russell King | 0f347bb | 2007-05-17 10:11:34 +0100 | [diff] [blame] | 398 | unsigned int cascade_irq, gic_irq; |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 399 | unsigned long status; |
| 400 | |
Will Deacon | 1a01753 | 2011-02-09 12:01:12 +0000 | [diff] [blame] | 401 | chained_irq_enter(chip, desc); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 402 | |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 403 | status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 404 | |
Feng Kan | e5f8153 | 2014-07-30 14:56:58 -0700 | [diff] [blame] | 405 | gic_irq = (status & GICC_IAR_INT_ID_MASK); |
| 406 | if (gic_irq == GICC_INT_SPURIOUS) |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 407 | goto out; |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 408 | |
Grant Likely | 7529495 | 2012-02-14 14:06:57 -0700 | [diff] [blame] | 409 | cascade_irq = irq_find_mapping(chip_data->domain, gic_irq); |
| 410 | if (unlikely(gic_irq < 32 || gic_irq > 1020)) |
Thomas Gleixner | bd0b9ac | 2015-09-14 10:42:37 +0200 | [diff] [blame] | 411 | handle_bad_irq(desc); |
Russell King | 0f347bb | 2007-05-17 10:11:34 +0100 | [diff] [blame] | 412 | else |
| 413 | generic_handle_irq(cascade_irq); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 414 | |
| 415 | out: |
Will Deacon | 1a01753 | 2011-02-09 12:01:12 +0000 | [diff] [blame] | 416 | chained_irq_exit(chip, desc); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 417 | } |
| 418 | |
David Brownell | 38c677c | 2006-08-01 22:26:25 +0100 | [diff] [blame] | 419 | static struct irq_chip gic_chip = { |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 420 | .irq_mask = gic_mask_irq, |
| 421 | .irq_unmask = gic_unmask_irq, |
Will Deacon | 1a01753 | 2011-02-09 12:01:12 +0000 | [diff] [blame] | 422 | .irq_eoi = gic_eoi_irq, |
Lennert Buytenhek | 7d1f428 | 2010-11-29 10:18:20 +0100 | [diff] [blame] | 423 | .irq_set_type = gic_set_type, |
Marc Zyngier | 5671780 | 2015-03-18 11:01:23 +0000 | [diff] [blame] | 424 | .irq_get_irqchip_state = gic_irq_get_irqchip_state, |
| 425 | .irq_set_irqchip_state = gic_irq_set_irqchip_state, |
Sudeep Holla | aec89ef | 2015-07-15 15:38:28 +0100 | [diff] [blame] | 426 | .flags = IRQCHIP_SET_TYPE_MASKED | |
| 427 | IRQCHIP_SKIP_SET_WAKE | |
| 428 | IRQCHIP_MASK_ON_SUSPEND, |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 429 | }; |
| 430 | |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 431 | void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) |
| 432 | { |
Linus Walleij | a27d21e | 2015-12-18 10:44:53 +0100 | [diff] [blame] | 433 | BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR); |
Thomas Gleixner | 4d83fcf | 2015-06-21 21:10:53 +0200 | [diff] [blame] | 434 | irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, |
| 435 | &gic_data[gic_nr]); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 436 | } |
| 437 | |
Russell King | 2bb3135 | 2013-01-30 23:49:57 +0000 | [diff] [blame] | 438 | static u8 gic_get_cpumask(struct gic_chip_data *gic) |
| 439 | { |
| 440 | void __iomem *base = gic_data_dist_base(gic); |
| 441 | u32 mask, i; |
| 442 | |
| 443 | for (i = mask = 0; i < 32; i += 4) { |
| 444 | mask = readl_relaxed(base + GIC_DIST_TARGET + i); |
| 445 | mask |= mask >> 16; |
| 446 | mask |= mask >> 8; |
| 447 | if (mask) |
| 448 | break; |
| 449 | } |
| 450 | |
Stephen Boyd | 6e3aca4 | 2015-03-11 23:21:31 -0700 | [diff] [blame] | 451 | if (!mask && num_possible_cpus() > 1) |
Russell King | 2bb3135 | 2013-01-30 23:49:57 +0000 | [diff] [blame] | 452 | pr_crit("GIC CPU mask not found - kernel will fail to boot.\n"); |
| 453 | |
| 454 | return mask; |
| 455 | } |
| 456 | |
Jon Hunter | 4c2880b | 2015-07-31 09:44:12 +0100 | [diff] [blame] | 457 | static void gic_cpu_if_up(struct gic_chip_data *gic) |
Feng Kan | 3228950 | 2014-07-30 14:56:59 -0700 | [diff] [blame] | 458 | { |
Jon Hunter | 4c2880b | 2015-07-31 09:44:12 +0100 | [diff] [blame] | 459 | void __iomem *cpu_base = gic_data_cpu_base(gic); |
Feng Kan | 3228950 | 2014-07-30 14:56:59 -0700 | [diff] [blame] | 460 | u32 bypass = 0; |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame] | 461 | u32 mode = 0; |
| 462 | |
Jon Hunter | 389a00d | 2016-02-09 15:24:57 +0000 | [diff] [blame] | 463 | if (gic == &gic_data[0] && static_key_true(&supports_deactivate)) |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame] | 464 | mode = GIC_CPU_CTRL_EOImodeNS; |
Feng Kan | 3228950 | 2014-07-30 14:56:59 -0700 | [diff] [blame] | 465 | |
| 466 | /* |
| 467 | * Preserve bypass disable bits to be written back later |
| 468 | */ |
| 469 | bypass = readl(cpu_base + GIC_CPU_CTRL); |
| 470 | bypass &= GICC_DIS_BYPASS_MASK; |
| 471 | |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame] | 472 | writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL); |
Feng Kan | 3228950 | 2014-07-30 14:56:59 -0700 | [diff] [blame] | 473 | } |
| 474 | |
| 475 | |
Jon Hunter | cdbb813 | 2016-06-07 16:12:32 +0100 | [diff] [blame] | 476 | static void gic_dist_init(struct gic_chip_data *gic) |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 477 | { |
Grant Likely | 7529495 | 2012-02-14 14:06:57 -0700 | [diff] [blame] | 478 | unsigned int i; |
Will Deacon | 267840f | 2011-08-23 22:20:03 +0100 | [diff] [blame] | 479 | u32 cpumask; |
Rob Herring | 4294f8ba | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 480 | unsigned int gic_irqs = gic->gic_irqs; |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 481 | void __iomem *base = gic_data_dist_base(gic); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 482 | |
Feng Kan | e5f8153 | 2014-07-30 14:56:58 -0700 | [diff] [blame] | 483 | writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 484 | |
| 485 | /* |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 486 | * Set all global interrupts to this CPU only. |
| 487 | */ |
Russell King | 2bb3135 | 2013-01-30 23:49:57 +0000 | [diff] [blame] | 488 | cpumask = gic_get_cpumask(gic); |
| 489 | cpumask |= cpumask << 8; |
| 490 | cpumask |= cpumask << 16; |
Pawel Moll | e6afec9 | 2010-11-26 13:45:43 +0100 | [diff] [blame] | 491 | for (i = 32; i < gic_irqs; i += 4) |
Santosh Shilimkar | 6ac77e4 | 2011-03-28 19:27:46 +0530 | [diff] [blame] | 492 | writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 493 | |
Marc Zyngier | d51d0af | 2014-06-30 16:01:30 +0100 | [diff] [blame] | 494 | gic_dist_config(base, gic_irqs, NULL); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 495 | |
Feng Kan | e5f8153 | 2014-07-30 14:56:58 -0700 | [diff] [blame] | 496 | writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL); |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 497 | } |
| 498 | |
Jon Hunter | dc9722c | 2016-05-10 16:14:42 +0100 | [diff] [blame] | 499 | static int gic_cpu_init(struct gic_chip_data *gic) |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 500 | { |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 501 | void __iomem *dist_base = gic_data_dist_base(gic); |
| 502 | void __iomem *base = gic_data_cpu_base(gic); |
Nicolas Pitre | 384a290 | 2012-04-11 18:55:48 -0400 | [diff] [blame] | 503 | unsigned int cpu_mask, cpu = smp_processor_id(); |
Russell King | 9395f6e | 2010-11-11 23:10:30 +0000 | [diff] [blame] | 504 | int i; |
| 505 | |
Russell King | 9395f6e | 2010-11-11 23:10:30 +0000 | [diff] [blame] | 506 | /* |
Jon Hunter | 567e5a0 | 2015-07-31 09:44:11 +0100 | [diff] [blame] | 507 | * Setting up the CPU map is only relevant for the primary GIC |
| 508 | * because any nested/secondary GICs do not directly interface |
| 509 | * with the CPU(s). |
Nicolas Pitre | 384a290 | 2012-04-11 18:55:48 -0400 | [diff] [blame] | 510 | */ |
Jon Hunter | 567e5a0 | 2015-07-31 09:44:11 +0100 | [diff] [blame] | 511 | if (gic == &gic_data[0]) { |
| 512 | /* |
| 513 | * Get what the GIC says our CPU mask is. |
| 514 | */ |
Jon Hunter | dc9722c | 2016-05-10 16:14:42 +0100 | [diff] [blame] | 515 | if (WARN_ON(cpu >= NR_GIC_CPU_IF)) |
| 516 | return -EINVAL; |
| 517 | |
Marc Zyngier | 25fc11a | 2016-04-22 12:25:33 +0100 | [diff] [blame] | 518 | gic_check_cpu_features(); |
Jon Hunter | 567e5a0 | 2015-07-31 09:44:11 +0100 | [diff] [blame] | 519 | cpu_mask = gic_get_cpumask(gic); |
| 520 | gic_cpu_map[cpu] = cpu_mask; |
Nicolas Pitre | 384a290 | 2012-04-11 18:55:48 -0400 | [diff] [blame] | 521 | |
Jon Hunter | 567e5a0 | 2015-07-31 09:44:11 +0100 | [diff] [blame] | 522 | /* |
| 523 | * Clear our mask from the other map entries in case they're |
| 524 | * still undefined. |
| 525 | */ |
| 526 | for (i = 0; i < NR_GIC_CPU_IF; i++) |
| 527 | if (i != cpu) |
| 528 | gic_cpu_map[i] &= ~cpu_mask; |
| 529 | } |
Nicolas Pitre | 384a290 | 2012-04-11 18:55:48 -0400 | [diff] [blame] | 530 | |
Marc Zyngier | d51d0af | 2014-06-30 16:01:30 +0100 | [diff] [blame] | 531 | gic_cpu_config(dist_base, NULL); |
Russell King | 9395f6e | 2010-11-11 23:10:30 +0000 | [diff] [blame] | 532 | |
Feng Kan | e5f8153 | 2014-07-30 14:56:58 -0700 | [diff] [blame] | 533 | writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK); |
Jon Hunter | 4c2880b | 2015-07-31 09:44:12 +0100 | [diff] [blame] | 534 | gic_cpu_if_up(gic); |
Jon Hunter | dc9722c | 2016-05-10 16:14:42 +0100 | [diff] [blame] | 535 | |
| 536 | return 0; |
Russell King | f27ecac | 2005-08-18 21:31:00 +0100 | [diff] [blame] | 537 | } |
| 538 | |
Jon Hunter | 4c2880b | 2015-07-31 09:44:12 +0100 | [diff] [blame] | 539 | int gic_cpu_if_down(unsigned int gic_nr) |
Nicolas Pitre | 10d9eb8 | 2013-03-19 23:59:04 -0400 | [diff] [blame] | 540 | { |
Jon Hunter | 4c2880b | 2015-07-31 09:44:12 +0100 | [diff] [blame] | 541 | void __iomem *cpu_base; |
Feng Kan | 3228950 | 2014-07-30 14:56:59 -0700 | [diff] [blame] | 542 | u32 val = 0; |
| 543 | |
Linus Walleij | a27d21e | 2015-12-18 10:44:53 +0100 | [diff] [blame] | 544 | if (gic_nr >= CONFIG_ARM_GIC_MAX_NR) |
Jon Hunter | 4c2880b | 2015-07-31 09:44:12 +0100 | [diff] [blame] | 545 | return -EINVAL; |
| 546 | |
| 547 | cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); |
Feng Kan | 3228950 | 2014-07-30 14:56:59 -0700 | [diff] [blame] | 548 | val = readl(cpu_base + GIC_CPU_CTRL); |
| 549 | val &= ~GICC_ENABLE; |
| 550 | writel_relaxed(val, cpu_base + GIC_CPU_CTRL); |
Jon Hunter | 4c2880b | 2015-07-31 09:44:12 +0100 | [diff] [blame] | 551 | |
| 552 | return 0; |
Nicolas Pitre | 10d9eb8 | 2013-03-19 23:59:04 -0400 | [diff] [blame] | 553 | } |
| 554 | |
Jon Hunter | 9c8eddd | 2016-06-07 16:12:34 +0100 | [diff] [blame] | 555 | #if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM) |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 556 | /* |
| 557 | * Saves the GIC distributor registers during suspend or idle. Must be called |
| 558 | * with interrupts disabled but before powering down the GIC. After calling |
| 559 | * this function, no interrupts will be delivered by the GIC, and another |
| 560 | * platform-specific wakeup source must be enabled. |
| 561 | */ |
Jon Hunter | cdbb813 | 2016-06-07 16:12:32 +0100 | [diff] [blame] | 562 | void gic_dist_save(struct gic_chip_data *gic) |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 563 | { |
| 564 | unsigned int gic_irqs; |
| 565 | void __iomem *dist_base; |
| 566 | int i; |
| 567 | |
Jon Hunter | 6e5b592 | 2016-05-10 16:14:43 +0100 | [diff] [blame] | 568 | if (WARN_ON(!gic)) |
| 569 | return; |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 570 | |
Jon Hunter | 6e5b592 | 2016-05-10 16:14:43 +0100 | [diff] [blame] | 571 | gic_irqs = gic->gic_irqs; |
| 572 | dist_base = gic_data_dist_base(gic); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 573 | |
| 574 | if (!dist_base) |
| 575 | return; |
| 576 | |
| 577 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) |
Jon Hunter | 6e5b592 | 2016-05-10 16:14:43 +0100 | [diff] [blame] | 578 | gic->saved_spi_conf[i] = |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 579 | readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); |
| 580 | |
| 581 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) |
Jon Hunter | 6e5b592 | 2016-05-10 16:14:43 +0100 | [diff] [blame] | 582 | gic->saved_spi_target[i] = |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 583 | readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); |
| 584 | |
| 585 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) |
Jon Hunter | 6e5b592 | 2016-05-10 16:14:43 +0100 | [diff] [blame] | 586 | gic->saved_spi_enable[i] = |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 587 | readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); |
Marc Zyngier | 1c7d4dd | 2015-11-16 19:13:28 +0000 | [diff] [blame] | 588 | |
| 589 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) |
Jon Hunter | 6e5b592 | 2016-05-10 16:14:43 +0100 | [diff] [blame] | 590 | gic->saved_spi_active[i] = |
Marc Zyngier | 1c7d4dd | 2015-11-16 19:13:28 +0000 | [diff] [blame] | 591 | readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 592 | } |
| 593 | |
| 594 | /* |
| 595 | * Restores the GIC distributor registers during resume or when coming out of |
| 596 | * idle. Must be called before enabling interrupts. If a level interrupt |
| 597 | * that occured while the GIC was suspended is still present, it will be |
| 598 | * handled normally, but any edge interrupts that occured will not be seen by |
| 599 | * the GIC and need to be handled by the platform-specific wakeup source. |
| 600 | */ |
Jon Hunter | cdbb813 | 2016-06-07 16:12:32 +0100 | [diff] [blame] | 601 | void gic_dist_restore(struct gic_chip_data *gic) |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 602 | { |
| 603 | unsigned int gic_irqs; |
| 604 | unsigned int i; |
| 605 | void __iomem *dist_base; |
| 606 | |
Jon Hunter | 6e5b592 | 2016-05-10 16:14:43 +0100 | [diff] [blame] | 607 | if (WARN_ON(!gic)) |
| 608 | return; |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 609 | |
Jon Hunter | 6e5b592 | 2016-05-10 16:14:43 +0100 | [diff] [blame] | 610 | gic_irqs = gic->gic_irqs; |
| 611 | dist_base = gic_data_dist_base(gic); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 612 | |
| 613 | if (!dist_base) |
| 614 | return; |
| 615 | |
Feng Kan | e5f8153 | 2014-07-30 14:56:58 -0700 | [diff] [blame] | 616 | writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 617 | |
| 618 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) |
Jon Hunter | 6e5b592 | 2016-05-10 16:14:43 +0100 | [diff] [blame] | 619 | writel_relaxed(gic->saved_spi_conf[i], |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 620 | dist_base + GIC_DIST_CONFIG + i * 4); |
| 621 | |
| 622 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) |
Feng Kan | e5f8153 | 2014-07-30 14:56:58 -0700 | [diff] [blame] | 623 | writel_relaxed(GICD_INT_DEF_PRI_X4, |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 624 | dist_base + GIC_DIST_PRI + i * 4); |
| 625 | |
| 626 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) |
Jon Hunter | 6e5b592 | 2016-05-10 16:14:43 +0100 | [diff] [blame] | 627 | writel_relaxed(gic->saved_spi_target[i], |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 628 | dist_base + GIC_DIST_TARGET + i * 4); |
| 629 | |
Marc Zyngier | 92eda4a | 2015-11-16 19:13:27 +0000 | [diff] [blame] | 630 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) { |
| 631 | writel_relaxed(GICD_INT_EN_CLR_X32, |
| 632 | dist_base + GIC_DIST_ENABLE_CLEAR + i * 4); |
Jon Hunter | 6e5b592 | 2016-05-10 16:14:43 +0100 | [diff] [blame] | 633 | writel_relaxed(gic->saved_spi_enable[i], |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 634 | dist_base + GIC_DIST_ENABLE_SET + i * 4); |
Marc Zyngier | 92eda4a | 2015-11-16 19:13:27 +0000 | [diff] [blame] | 635 | } |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 636 | |
Marc Zyngier | 1c7d4dd | 2015-11-16 19:13:28 +0000 | [diff] [blame] | 637 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) { |
| 638 | writel_relaxed(GICD_INT_EN_CLR_X32, |
| 639 | dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4); |
Jon Hunter | 6e5b592 | 2016-05-10 16:14:43 +0100 | [diff] [blame] | 640 | writel_relaxed(gic->saved_spi_active[i], |
Marc Zyngier | 1c7d4dd | 2015-11-16 19:13:28 +0000 | [diff] [blame] | 641 | dist_base + GIC_DIST_ACTIVE_SET + i * 4); |
| 642 | } |
| 643 | |
Feng Kan | e5f8153 | 2014-07-30 14:56:58 -0700 | [diff] [blame] | 644 | writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 645 | } |
| 646 | |
Jon Hunter | cdbb813 | 2016-06-07 16:12:32 +0100 | [diff] [blame] | 647 | void gic_cpu_save(struct gic_chip_data *gic) |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 648 | { |
| 649 | int i; |
| 650 | u32 *ptr; |
| 651 | void __iomem *dist_base; |
| 652 | void __iomem *cpu_base; |
| 653 | |
Jon Hunter | 6e5b592 | 2016-05-10 16:14:43 +0100 | [diff] [blame] | 654 | if (WARN_ON(!gic)) |
| 655 | return; |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 656 | |
Jon Hunter | 6e5b592 | 2016-05-10 16:14:43 +0100 | [diff] [blame] | 657 | dist_base = gic_data_dist_base(gic); |
| 658 | cpu_base = gic_data_cpu_base(gic); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 659 | |
| 660 | if (!dist_base || !cpu_base) |
| 661 | return; |
| 662 | |
Jon Hunter | 6e5b592 | 2016-05-10 16:14:43 +0100 | [diff] [blame] | 663 | ptr = raw_cpu_ptr(gic->saved_ppi_enable); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 664 | for (i = 0; i < DIV_ROUND_UP(32, 32); i++) |
Subbaraman Narayanamurthy | c63401e | 2018-02-23 21:26:28 +0530 | [diff] [blame] | 665 | ptr[i] = readl_relaxed_no_log(dist_base + |
| 666 | GIC_DIST_ENABLE_SET + i * 4); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 667 | |
Jon Hunter | 6e5b592 | 2016-05-10 16:14:43 +0100 | [diff] [blame] | 668 | ptr = raw_cpu_ptr(gic->saved_ppi_active); |
Marc Zyngier | 1c7d4dd | 2015-11-16 19:13:28 +0000 | [diff] [blame] | 669 | for (i = 0; i < DIV_ROUND_UP(32, 32); i++) |
Subbaraman Narayanamurthy | c63401e | 2018-02-23 21:26:28 +0530 | [diff] [blame] | 670 | ptr[i] = readl_relaxed_no_log(dist_base + |
| 671 | GIC_DIST_ACTIVE_SET + i * 4); |
Marc Zyngier | 1c7d4dd | 2015-11-16 19:13:28 +0000 | [diff] [blame] | 672 | |
Jon Hunter | 6e5b592 | 2016-05-10 16:14:43 +0100 | [diff] [blame] | 673 | ptr = raw_cpu_ptr(gic->saved_ppi_conf); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 674 | for (i = 0; i < DIV_ROUND_UP(32, 16); i++) |
Subbaraman Narayanamurthy | c63401e | 2018-02-23 21:26:28 +0530 | [diff] [blame] | 675 | ptr[i] = readl_relaxed_no_log(dist_base + |
| 676 | GIC_DIST_CONFIG + i * 4); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 677 | } |
| 678 | |
Jon Hunter | cdbb813 | 2016-06-07 16:12:32 +0100 | [diff] [blame] | 679 | void gic_cpu_restore(struct gic_chip_data *gic) |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 680 | { |
| 681 | int i; |
| 682 | u32 *ptr; |
| 683 | void __iomem *dist_base; |
| 684 | void __iomem *cpu_base; |
| 685 | |
Jon Hunter | 6e5b592 | 2016-05-10 16:14:43 +0100 | [diff] [blame] | 686 | if (WARN_ON(!gic)) |
| 687 | return; |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 688 | |
Jon Hunter | 6e5b592 | 2016-05-10 16:14:43 +0100 | [diff] [blame] | 689 | dist_base = gic_data_dist_base(gic); |
| 690 | cpu_base = gic_data_cpu_base(gic); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 691 | |
| 692 | if (!dist_base || !cpu_base) |
| 693 | return; |
| 694 | |
Jon Hunter | 6e5b592 | 2016-05-10 16:14:43 +0100 | [diff] [blame] | 695 | ptr = raw_cpu_ptr(gic->saved_ppi_enable); |
Marc Zyngier | 92eda4a | 2015-11-16 19:13:27 +0000 | [diff] [blame] | 696 | for (i = 0; i < DIV_ROUND_UP(32, 32); i++) { |
Subbaraman Narayanamurthy | c63401e | 2018-02-23 21:26:28 +0530 | [diff] [blame] | 697 | writel_relaxed_no_log(GICD_INT_EN_CLR_X32, |
Marc Zyngier | 92eda4a | 2015-11-16 19:13:27 +0000 | [diff] [blame] | 698 | dist_base + GIC_DIST_ENABLE_CLEAR + i * 4); |
Subbaraman Narayanamurthy | c63401e | 2018-02-23 21:26:28 +0530 | [diff] [blame] | 699 | writel_relaxed_no_log(ptr[i], dist_base + |
| 700 | GIC_DIST_ENABLE_SET + i * 4); |
Marc Zyngier | 92eda4a | 2015-11-16 19:13:27 +0000 | [diff] [blame] | 701 | } |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 702 | |
Jon Hunter | 6e5b592 | 2016-05-10 16:14:43 +0100 | [diff] [blame] | 703 | ptr = raw_cpu_ptr(gic->saved_ppi_active); |
Marc Zyngier | 1c7d4dd | 2015-11-16 19:13:28 +0000 | [diff] [blame] | 704 | for (i = 0; i < DIV_ROUND_UP(32, 32); i++) { |
Subbaraman Narayanamurthy | c63401e | 2018-02-23 21:26:28 +0530 | [diff] [blame] | 705 | writel_relaxed_no_log(GICD_INT_EN_CLR_X32, |
Marc Zyngier | 1c7d4dd | 2015-11-16 19:13:28 +0000 | [diff] [blame] | 706 | dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4); |
Subbaraman Narayanamurthy | c63401e | 2018-02-23 21:26:28 +0530 | [diff] [blame] | 707 | writel_relaxed_no_log(ptr[i], dist_base + |
| 708 | GIC_DIST_ACTIVE_SET + i * 4); |
Marc Zyngier | 1c7d4dd | 2015-11-16 19:13:28 +0000 | [diff] [blame] | 709 | } |
| 710 | |
Jon Hunter | 6e5b592 | 2016-05-10 16:14:43 +0100 | [diff] [blame] | 711 | ptr = raw_cpu_ptr(gic->saved_ppi_conf); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 712 | for (i = 0; i < DIV_ROUND_UP(32, 16); i++) |
Subbaraman Narayanamurthy | c63401e | 2018-02-23 21:26:28 +0530 | [diff] [blame] | 713 | writel_relaxed_no_log(ptr[i], dist_base + |
| 714 | GIC_DIST_CONFIG + i * 4); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 715 | |
| 716 | for (i = 0; i < DIV_ROUND_UP(32, 4); i++) |
Subbaraman Narayanamurthy | c63401e | 2018-02-23 21:26:28 +0530 | [diff] [blame] | 717 | writel_relaxed_no_log(GICD_INT_DEF_PRI_X4, |
Feng Kan | e5f8153 | 2014-07-30 14:56:58 -0700 | [diff] [blame] | 718 | dist_base + GIC_DIST_PRI + i * 4); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 719 | |
Subbaraman Narayanamurthy | c63401e | 2018-02-23 21:26:28 +0530 | [diff] [blame] | 720 | writel_relaxed_no_log(GICC_INT_PRI_THRESHOLD, |
| 721 | cpu_base + GIC_CPU_PRIMASK); |
Jon Hunter | 6e5b592 | 2016-05-10 16:14:43 +0100 | [diff] [blame] | 722 | gic_cpu_if_up(gic); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 723 | } |
| 724 | |
Murali Nalajala | de7c75e | 2015-01-07 19:36:57 -0800 | [diff] [blame] | 725 | static int gic_notifier(struct notifier_block *self, unsigned long cmd, |
| 726 | void *aff_level) |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 727 | { |
| 728 | int i; |
| 729 | |
Linus Walleij | a27d21e | 2015-12-18 10:44:53 +0100 | [diff] [blame] | 730 | for (i = 0; i < CONFIG_ARM_GIC_MAX_NR; i++) { |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 731 | #ifdef CONFIG_GIC_NON_BANKED |
| 732 | /* Skip over unused GICs */ |
| 733 | if (!gic_data[i].get_base) |
| 734 | continue; |
| 735 | #endif |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 736 | switch (cmd) { |
| 737 | case CPU_PM_ENTER: |
Jon Hunter | 6e5b592 | 2016-05-10 16:14:43 +0100 | [diff] [blame] | 738 | gic_cpu_save(&gic_data[i]); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 739 | break; |
| 740 | case CPU_PM_ENTER_FAILED: |
| 741 | case CPU_PM_EXIT: |
Jon Hunter | 6e5b592 | 2016-05-10 16:14:43 +0100 | [diff] [blame] | 742 | gic_cpu_restore(&gic_data[i]); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 743 | break; |
| 744 | case CPU_CLUSTER_PM_ENTER: |
Murali Nalajala | de7c75e | 2015-01-07 19:36:57 -0800 | [diff] [blame] | 745 | /* |
| 746 | * Affinity level of the node |
| 747 | * eg: |
| 748 | * cpu level = 0 |
| 749 | * l2 level = 1 |
| 750 | * cci level = 2 |
| 751 | */ |
| 752 | if (!(unsigned long)aff_level) |
| 753 | gic_dist_save(&gic_data[i]); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 754 | break; |
| 755 | case CPU_CLUSTER_PM_ENTER_FAILED: |
| 756 | case CPU_CLUSTER_PM_EXIT: |
Murali Nalajala | de7c75e | 2015-01-07 19:36:57 -0800 | [diff] [blame] | 757 | if (!(unsigned long)aff_level) |
| 758 | gic_dist_restore(&gic_data[i]); |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 759 | break; |
| 760 | } |
| 761 | } |
| 762 | |
| 763 | return NOTIFY_OK; |
| 764 | } |
| 765 | |
| 766 | static struct notifier_block gic_notifier_block = { |
| 767 | .notifier_call = gic_notifier, |
| 768 | }; |
| 769 | |
Jon Hunter | cdbb813 | 2016-06-07 16:12:32 +0100 | [diff] [blame] | 770 | static int gic_pm_init(struct gic_chip_data *gic) |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 771 | { |
| 772 | gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, |
| 773 | sizeof(u32)); |
Jon Hunter | dc9722c | 2016-05-10 16:14:42 +0100 | [diff] [blame] | 774 | if (WARN_ON(!gic->saved_ppi_enable)) |
| 775 | return -ENOMEM; |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 776 | |
Marc Zyngier | 1c7d4dd | 2015-11-16 19:13:28 +0000 | [diff] [blame] | 777 | gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, |
| 778 | sizeof(u32)); |
Jon Hunter | dc9722c | 2016-05-10 16:14:42 +0100 | [diff] [blame] | 779 | if (WARN_ON(!gic->saved_ppi_active)) |
| 780 | goto free_ppi_enable; |
Marc Zyngier | 1c7d4dd | 2015-11-16 19:13:28 +0000 | [diff] [blame] | 781 | |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 782 | gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4, |
| 783 | sizeof(u32)); |
Jon Hunter | dc9722c | 2016-05-10 16:14:42 +0100 | [diff] [blame] | 784 | if (WARN_ON(!gic->saved_ppi_conf)) |
| 785 | goto free_ppi_active; |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 786 | |
Marc Zyngier | abdd7b9 | 2011-11-25 17:58:19 +0100 | [diff] [blame] | 787 | if (gic == &gic_data[0]) |
| 788 | cpu_pm_register_notifier(&gic_notifier_block); |
Jon Hunter | dc9722c | 2016-05-10 16:14:42 +0100 | [diff] [blame] | 789 | |
| 790 | return 0; |
| 791 | |
| 792 | free_ppi_active: |
| 793 | free_percpu(gic->saved_ppi_active); |
| 794 | free_ppi_enable: |
| 795 | free_percpu(gic->saved_ppi_enable); |
| 796 | |
| 797 | return -ENOMEM; |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 798 | } |
| 799 | #else |
Jon Hunter | cdbb813 | 2016-06-07 16:12:32 +0100 | [diff] [blame] | 800 | static int gic_pm_init(struct gic_chip_data *gic) |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 801 | { |
Jon Hunter | dc9722c | 2016-05-10 16:14:42 +0100 | [diff] [blame] | 802 | return 0; |
Colin Cross | 254056f | 2011-02-10 12:54:10 -0800 | [diff] [blame] | 803 | } |
| 804 | #endif |
| 805 | |
Rob Herring | b1cffeb | 2012-11-26 15:05:48 -0600 | [diff] [blame] | 806 | #ifdef CONFIG_SMP |
Stephen Boyd | 6859358 | 2014-03-04 17:02:01 -0800 | [diff] [blame] | 807 | static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) |
Rob Herring | b1cffeb | 2012-11-26 15:05:48 -0600 | [diff] [blame] | 808 | { |
| 809 | int cpu; |
Nicolas Pitre | 1a6b69b | 2012-04-12 01:40:31 -0400 | [diff] [blame] | 810 | unsigned long flags, map = 0; |
| 811 | |
Marc Zyngier | 059e232 | 2016-08-09 07:50:44 +0100 | [diff] [blame] | 812 | if (unlikely(nr_cpu_ids == 1)) { |
| 813 | /* Only one CPU? let's do a self-IPI... */ |
Subbaraman Narayanamurthy | c63401e | 2018-02-23 21:26:28 +0530 | [diff] [blame] | 814 | writel_relaxed_no_log(2 << 24 | irq, |
Marc Zyngier | 059e232 | 2016-08-09 07:50:44 +0100 | [diff] [blame] | 815 | gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); |
| 816 | return; |
| 817 | } |
| 818 | |
Marc Zyngier | 04c8b0f | 2016-06-27 18:11:43 +0100 | [diff] [blame] | 819 | gic_lock_irqsave(flags); |
Rob Herring | b1cffeb | 2012-11-26 15:05:48 -0600 | [diff] [blame] | 820 | |
| 821 | /* Convert our logical CPU mask into a physical one. */ |
| 822 | for_each_cpu(cpu, mask) |
Javi Merino | 91bdf0d | 2013-02-19 13:52:22 +0000 | [diff] [blame] | 823 | map |= gic_cpu_map[cpu]; |
Rob Herring | b1cffeb | 2012-11-26 15:05:48 -0600 | [diff] [blame] | 824 | |
| 825 | /* |
| 826 | * Ensure that stores to Normal memory are visible to the |
Will Deacon | 8adbf57 | 2014-02-20 17:42:07 +0000 | [diff] [blame] | 827 | * other CPUs before they observe us issuing the IPI. |
Rob Herring | b1cffeb | 2012-11-26 15:05:48 -0600 | [diff] [blame] | 828 | */ |
Will Deacon | 8adbf57 | 2014-02-20 17:42:07 +0000 | [diff] [blame] | 829 | dmb(ishst); |
Rob Herring | b1cffeb | 2012-11-26 15:05:48 -0600 | [diff] [blame] | 830 | |
| 831 | /* this always happens on GIC0 */ |
Subbaraman Narayanamurthy | c63401e | 2018-02-23 21:26:28 +0530 | [diff] [blame] | 832 | writel_relaxed_no_log(map << 16 | irq, |
| 833 | gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); |
Nicolas Pitre | 1a6b69b | 2012-04-12 01:40:31 -0400 | [diff] [blame] | 834 | |
Marc Zyngier | 04c8b0f | 2016-06-27 18:11:43 +0100 | [diff] [blame] | 835 | gic_unlock_irqrestore(flags); |
Nicolas Pitre | 1a6b69b | 2012-04-12 01:40:31 -0400 | [diff] [blame] | 836 | } |
| 837 | #endif |
| 838 | |
| 839 | #ifdef CONFIG_BL_SWITCHER |
| 840 | /* |
Nicolas Pitre | 14d2ca6 | 2012-11-28 18:48:19 -0500 | [diff] [blame] | 841 | * gic_send_sgi - send a SGI directly to given CPU interface number |
| 842 | * |
| 843 | * cpu_id: the ID for the destination CPU interface |
| 844 | * irq: the IPI number to send a SGI for |
| 845 | */ |
| 846 | void gic_send_sgi(unsigned int cpu_id, unsigned int irq) |
| 847 | { |
| 848 | BUG_ON(cpu_id >= NR_GIC_CPU_IF); |
| 849 | cpu_id = 1 << cpu_id; |
| 850 | /* this always happens on GIC0 */ |
| 851 | writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); |
| 852 | } |
| 853 | |
| 854 | /* |
Nicolas Pitre | ed96762 | 2012-07-05 21:33:26 -0400 | [diff] [blame] | 855 | * gic_get_cpu_id - get the CPU interface ID for the specified CPU |
| 856 | * |
| 857 | * @cpu: the logical CPU number to get the GIC ID for. |
| 858 | * |
| 859 | * Return the CPU interface ID for the given logical CPU number, |
| 860 | * or -1 if the CPU number is too large or the interface ID is |
| 861 | * unknown (more than one bit set). |
| 862 | */ |
| 863 | int gic_get_cpu_id(unsigned int cpu) |
| 864 | { |
| 865 | unsigned int cpu_bit; |
| 866 | |
| 867 | if (cpu >= NR_GIC_CPU_IF) |
| 868 | return -1; |
| 869 | cpu_bit = gic_cpu_map[cpu]; |
| 870 | if (cpu_bit & (cpu_bit - 1)) |
| 871 | return -1; |
| 872 | return __ffs(cpu_bit); |
| 873 | } |
| 874 | |
| 875 | /* |
Nicolas Pitre | 1a6b69b | 2012-04-12 01:40:31 -0400 | [diff] [blame] | 876 | * gic_migrate_target - migrate IRQs to another CPU interface |
| 877 | * |
| 878 | * @new_cpu_id: the CPU target ID to migrate IRQs to |
| 879 | * |
| 880 | * Migrate all peripheral interrupts with a target matching the current CPU |
| 881 | * to the interface corresponding to @new_cpu_id. The CPU interface mapping |
| 882 | * is also updated. Targets to other CPU interfaces are unchanged. |
| 883 | * This must be called with IRQs locally disabled. |
| 884 | */ |
| 885 | void gic_migrate_target(unsigned int new_cpu_id) |
| 886 | { |
| 887 | unsigned int cur_cpu_id, gic_irqs, gic_nr = 0; |
| 888 | void __iomem *dist_base; |
| 889 | int i, ror_val, cpu = smp_processor_id(); |
| 890 | u32 val, cur_target_mask, active_mask; |
| 891 | |
Linus Walleij | a27d21e | 2015-12-18 10:44:53 +0100 | [diff] [blame] | 892 | BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR); |
Nicolas Pitre | 1a6b69b | 2012-04-12 01:40:31 -0400 | [diff] [blame] | 893 | |
| 894 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
| 895 | if (!dist_base) |
| 896 | return; |
| 897 | gic_irqs = gic_data[gic_nr].gic_irqs; |
| 898 | |
| 899 | cur_cpu_id = __ffs(gic_cpu_map[cpu]); |
| 900 | cur_target_mask = 0x01010101 << cur_cpu_id; |
| 901 | ror_val = (cur_cpu_id - new_cpu_id) & 31; |
| 902 | |
Marc Zyngier | 04c8b0f | 2016-06-27 18:11:43 +0100 | [diff] [blame] | 903 | gic_lock(); |
Nicolas Pitre | 1a6b69b | 2012-04-12 01:40:31 -0400 | [diff] [blame] | 904 | |
| 905 | /* Update the target interface for this logical CPU */ |
| 906 | gic_cpu_map[cpu] = 1 << new_cpu_id; |
| 907 | |
| 908 | /* |
| 909 | * Find all the peripheral interrupts targetting the current |
| 910 | * CPU interface and migrate them to the new CPU interface. |
| 911 | * We skip DIST_TARGET 0 to 7 as they are read-only. |
| 912 | */ |
| 913 | for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) { |
| 914 | val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); |
| 915 | active_mask = val & cur_target_mask; |
| 916 | if (active_mask) { |
| 917 | val &= ~active_mask; |
| 918 | val |= ror32(active_mask, ror_val); |
| 919 | writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4); |
| 920 | } |
| 921 | } |
| 922 | |
Marc Zyngier | 04c8b0f | 2016-06-27 18:11:43 +0100 | [diff] [blame] | 923 | gic_unlock(); |
Nicolas Pitre | 1a6b69b | 2012-04-12 01:40:31 -0400 | [diff] [blame] | 924 | |
| 925 | /* |
| 926 | * Now let's migrate and clear any potential SGIs that might be |
| 927 | * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET |
| 928 | * is a banked register, we can only forward the SGI using |
| 929 | * GIC_DIST_SOFTINT. The original SGI source is lost but Linux |
| 930 | * doesn't use that information anyway. |
| 931 | * |
| 932 | * For the same reason we do not adjust SGI source information |
| 933 | * for previously sent SGIs by us to other CPUs either. |
| 934 | */ |
| 935 | for (i = 0; i < 16; i += 4) { |
| 936 | int j; |
| 937 | val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i); |
| 938 | if (!val) |
| 939 | continue; |
| 940 | writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i); |
| 941 | for (j = i; j < i + 4; j++) { |
| 942 | if (val & 0xff) |
| 943 | writel_relaxed((1 << (new_cpu_id + 16)) | j, |
| 944 | dist_base + GIC_DIST_SOFTINT); |
| 945 | val >>= 8; |
| 946 | } |
| 947 | } |
Rob Herring | b1cffeb | 2012-11-26 15:05:48 -0600 | [diff] [blame] | 948 | } |
Nicolas Pitre | eeb4465 | 2012-11-28 18:17:25 -0500 | [diff] [blame] | 949 | |
| 950 | /* |
| 951 | * gic_get_sgir_physaddr - get the physical address for the SGI register |
| 952 | * |
| 953 | * REturn the physical address of the SGI register to be used |
| 954 | * by some early assembly code when the kernel is not yet available. |
| 955 | */ |
| 956 | static unsigned long gic_dist_physaddr; |
| 957 | |
| 958 | unsigned long gic_get_sgir_physaddr(void) |
| 959 | { |
| 960 | if (!gic_dist_physaddr) |
| 961 | return 0; |
| 962 | return gic_dist_physaddr + GIC_DIST_SOFTINT; |
| 963 | } |
| 964 | |
Baoyou Xie | 89c59cc | 2016-09-07 19:26:45 +0800 | [diff] [blame] | 965 | static void __init gic_init_physaddr(struct device_node *node) |
Nicolas Pitre | eeb4465 | 2012-11-28 18:17:25 -0500 | [diff] [blame] | 966 | { |
| 967 | struct resource res; |
| 968 | if (of_address_to_resource(node, 0, &res) == 0) { |
| 969 | gic_dist_physaddr = res.start; |
| 970 | pr_info("GIC physical location is %#lx\n", gic_dist_physaddr); |
| 971 | } |
| 972 | } |
| 973 | |
| 974 | #else |
| 975 | #define gic_init_physaddr(node) do { } while (0) |
Rob Herring | b1cffeb | 2012-11-26 15:05:48 -0600 | [diff] [blame] | 976 | #endif |
| 977 | |
Grant Likely | 7529495 | 2012-02-14 14:06:57 -0700 | [diff] [blame] | 978 | static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, |
| 979 | irq_hw_number_t hw) |
| 980 | { |
Linus Walleij | 58b8964 | 2015-10-24 00:15:53 +0200 | [diff] [blame] | 981 | struct gic_chip_data *gic = d->host_data; |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame] | 982 | |
Grant Likely | 7529495 | 2012-02-14 14:06:57 -0700 | [diff] [blame] | 983 | if (hw < 32) { |
| 984 | irq_set_percpu_devid(irq); |
Linus Walleij | 58b8964 | 2015-10-24 00:15:53 +0200 | [diff] [blame] | 985 | irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data, |
Yingjoe Chen | 9a1091e | 2014-11-25 16:04:19 +0800 | [diff] [blame] | 986 | handle_percpu_devid_irq, NULL, NULL); |
Rob Herring | d17cab4 | 2015-08-29 18:01:22 -0500 | [diff] [blame] | 987 | irq_set_status_flags(irq, IRQ_NOAUTOEN); |
Grant Likely | 7529495 | 2012-02-14 14:06:57 -0700 | [diff] [blame] | 988 | } else { |
Linus Walleij | 58b8964 | 2015-10-24 00:15:53 +0200 | [diff] [blame] | 989 | irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data, |
Yingjoe Chen | 9a1091e | 2014-11-25 16:04:19 +0800 | [diff] [blame] | 990 | handle_fasteoi_irq, NULL, NULL); |
Rob Herring | d17cab4 | 2015-08-29 18:01:22 -0500 | [diff] [blame] | 991 | irq_set_probe(irq); |
Grant Likely | 7529495 | 2012-02-14 14:06:57 -0700 | [diff] [blame] | 992 | } |
Grant Likely | 7529495 | 2012-02-14 14:06:57 -0700 | [diff] [blame] | 993 | return 0; |
| 994 | } |
| 995 | |
Sricharan R | 006e983 | 2013-12-03 15:57:22 +0530 | [diff] [blame] | 996 | static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq) |
| 997 | { |
Sricharan R | 006e983 | 2013-12-03 15:57:22 +0530 | [diff] [blame] | 998 | } |
| 999 | |
Marc Zyngier | f833f57 | 2015-10-13 12:51:33 +0100 | [diff] [blame] | 1000 | static int gic_irq_domain_translate(struct irq_domain *d, |
| 1001 | struct irq_fwspec *fwspec, |
| 1002 | unsigned long *hwirq, |
| 1003 | unsigned int *type) |
| 1004 | { |
| 1005 | if (is_of_node(fwspec->fwnode)) { |
| 1006 | if (fwspec->param_count < 3) |
| 1007 | return -EINVAL; |
| 1008 | |
| 1009 | /* Get the interrupt number and add 16 to skip over SGIs */ |
| 1010 | *hwirq = fwspec->param[1] + 16; |
| 1011 | |
| 1012 | /* |
| 1013 | * For SPIs, we need to add 16 more to get the GIC irq |
| 1014 | * ID number |
| 1015 | */ |
| 1016 | if (!fwspec->param[0]) |
| 1017 | *hwirq += 16; |
| 1018 | |
| 1019 | *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; |
| 1020 | return 0; |
| 1021 | } |
| 1022 | |
Suravee Suthikulpanit | 75aba7b | 2015-12-10 08:55:28 -0800 | [diff] [blame] | 1023 | if (is_fwnode_irqchip(fwspec->fwnode)) { |
Marc Zyngier | 891ae76 | 2015-10-13 12:51:40 +0100 | [diff] [blame] | 1024 | if(fwspec->param_count != 2) |
| 1025 | return -EINVAL; |
| 1026 | |
| 1027 | *hwirq = fwspec->param[0]; |
| 1028 | *type = fwspec->param[1]; |
| 1029 | return 0; |
| 1030 | } |
| 1031 | |
Marc Zyngier | f833f57 | 2015-10-13 12:51:33 +0100 | [diff] [blame] | 1032 | return -EINVAL; |
| 1033 | } |
| 1034 | |
Richard Cochran | 93131f7 | 2016-07-13 17:16:04 +0000 | [diff] [blame] | 1035 | static int gic_starting_cpu(unsigned int cpu) |
Catalin Marinas | c011470 | 2013-01-14 18:05:37 +0000 | [diff] [blame] | 1036 | { |
Richard Cochran | 93131f7 | 2016-07-13 17:16:04 +0000 | [diff] [blame] | 1037 | gic_cpu_init(&gic_data[0]); |
| 1038 | return 0; |
Catalin Marinas | c011470 | 2013-01-14 18:05:37 +0000 | [diff] [blame] | 1039 | } |
| 1040 | |
Yingjoe Chen | 9a1091e | 2014-11-25 16:04:19 +0800 | [diff] [blame] | 1041 | static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, |
| 1042 | unsigned int nr_irqs, void *arg) |
| 1043 | { |
| 1044 | int i, ret; |
| 1045 | irq_hw_number_t hwirq; |
| 1046 | unsigned int type = IRQ_TYPE_NONE; |
Marc Zyngier | f833f57 | 2015-10-13 12:51:33 +0100 | [diff] [blame] | 1047 | struct irq_fwspec *fwspec = arg; |
Yingjoe Chen | 9a1091e | 2014-11-25 16:04:19 +0800 | [diff] [blame] | 1048 | |
Marc Zyngier | f833f57 | 2015-10-13 12:51:33 +0100 | [diff] [blame] | 1049 | ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); |
Yingjoe Chen | 9a1091e | 2014-11-25 16:04:19 +0800 | [diff] [blame] | 1050 | if (ret) |
| 1051 | return ret; |
| 1052 | |
| 1053 | for (i = 0; i < nr_irqs; i++) |
| 1054 | gic_irq_domain_map(domain, virq + i, hwirq + i); |
| 1055 | |
| 1056 | return 0; |
| 1057 | } |
| 1058 | |
| 1059 | static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = { |
Marc Zyngier | f833f57 | 2015-10-13 12:51:33 +0100 | [diff] [blame] | 1060 | .translate = gic_irq_domain_translate, |
Yingjoe Chen | 9a1091e | 2014-11-25 16:04:19 +0800 | [diff] [blame] | 1061 | .alloc = gic_irq_domain_alloc, |
| 1062 | .free = irq_domain_free_irqs_top, |
| 1063 | }; |
| 1064 | |
Stephen Boyd | 6859358 | 2014-03-04 17:02:01 -0800 | [diff] [blame] | 1065 | static const struct irq_domain_ops gic_irq_domain_ops = { |
Grant Likely | 7529495 | 2012-02-14 14:06:57 -0700 | [diff] [blame] | 1066 | .map = gic_irq_domain_map, |
Sricharan R | 006e983 | 2013-12-03 15:57:22 +0530 | [diff] [blame] | 1067 | .unmap = gic_irq_domain_unmap, |
Rob Herring | 4294f8ba | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 1068 | }; |
| 1069 | |
Jon Hunter | faea645 | 2016-06-07 16:12:31 +0100 | [diff] [blame] | 1070 | static void gic_init_chip(struct gic_chip_data *gic, struct device *dev, |
| 1071 | const char *name, bool use_eoimode1) |
Russell King | b580b89 | 2010-12-04 15:55:14 +0000 | [diff] [blame] | 1072 | { |
Linus Walleij | 58b8964 | 2015-10-24 00:15:53 +0200 | [diff] [blame] | 1073 | /* Initialize irq_chip */ |
Jon Hunter | c2baa2f | 2016-05-10 16:14:41 +0100 | [diff] [blame] | 1074 | gic->chip = gic_chip; |
Jon Hunter | faea645 | 2016-06-07 16:12:31 +0100 | [diff] [blame] | 1075 | gic->chip.name = name; |
| 1076 | gic->chip.parent_device = dev; |
Jon Hunter | c2baa2f | 2016-05-10 16:14:41 +0100 | [diff] [blame] | 1077 | |
Jon Hunter | faea645 | 2016-06-07 16:12:31 +0100 | [diff] [blame] | 1078 | if (use_eoimode1) { |
Jon Hunter | c2baa2f | 2016-05-10 16:14:41 +0100 | [diff] [blame] | 1079 | gic->chip.irq_mask = gic_eoimode1_mask_irq; |
| 1080 | gic->chip.irq_eoi = gic_eoimode1_eoi_irq; |
| 1081 | gic->chip.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity; |
Linus Walleij | 58b8964 | 2015-10-24 00:15:53 +0200 | [diff] [blame] | 1082 | } |
| 1083 | |
Jon Hunter | 7bf29d3 | 2016-02-09 15:24:56 +0000 | [diff] [blame] | 1084 | #ifdef CONFIG_SMP |
Jon Hunter | f673b9b | 2016-05-10 16:14:44 +0100 | [diff] [blame] | 1085 | if (gic == &gic_data[0]) |
Jon Hunter | 7bf29d3 | 2016-02-09 15:24:56 +0000 | [diff] [blame] | 1086 | gic->chip.irq_set_affinity = gic_set_affinity; |
| 1087 | #endif |
Jon Hunter | faea645 | 2016-06-07 16:12:31 +0100 | [diff] [blame] | 1088 | } |
| 1089 | |
| 1090 | static int gic_init_bases(struct gic_chip_data *gic, int irq_start, |
| 1091 | struct fwnode_handle *handle) |
| 1092 | { |
| 1093 | irq_hw_number_t hwirq_base; |
| 1094 | int gic_irqs, irq_base, ret; |
Jon Hunter | 7bf29d3 | 2016-02-09 15:24:56 +0000 | [diff] [blame] | 1095 | |
Jon Hunter | f673b9b | 2016-05-10 16:14:44 +0100 | [diff] [blame] | 1096 | if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) { |
Jon Hunter | dc9722c | 2016-05-10 16:14:42 +0100 | [diff] [blame] | 1097 | /* Frankein-GIC without banked registers... */ |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 1098 | unsigned int cpu; |
| 1099 | |
| 1100 | gic->dist_base.percpu_base = alloc_percpu(void __iomem *); |
| 1101 | gic->cpu_base.percpu_base = alloc_percpu(void __iomem *); |
| 1102 | if (WARN_ON(!gic->dist_base.percpu_base || |
| 1103 | !gic->cpu_base.percpu_base)) { |
Jon Hunter | dc9722c | 2016-05-10 16:14:42 +0100 | [diff] [blame] | 1104 | ret = -ENOMEM; |
| 1105 | goto error; |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 1106 | } |
| 1107 | |
| 1108 | for_each_possible_cpu(cpu) { |
Tomasz Figa | 29e697b | 2014-07-17 17:23:44 +0200 | [diff] [blame] | 1109 | u32 mpidr = cpu_logical_map(cpu); |
| 1110 | u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); |
Jon Hunter | f673b9b | 2016-05-10 16:14:44 +0100 | [diff] [blame] | 1111 | unsigned long offset = gic->percpu_offset * core_id; |
| 1112 | *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = |
| 1113 | gic->raw_dist_base + offset; |
| 1114 | *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = |
| 1115 | gic->raw_cpu_base + offset; |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 1116 | } |
| 1117 | |
| 1118 | gic_set_base_accessor(gic, gic_get_percpu_base); |
Jon Hunter | dc9722c | 2016-05-10 16:14:42 +0100 | [diff] [blame] | 1119 | } else { |
| 1120 | /* Normal, sane GIC... */ |
Jon Hunter | f673b9b | 2016-05-10 16:14:44 +0100 | [diff] [blame] | 1121 | WARN(gic->percpu_offset, |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 1122 | "GIC_NON_BANKED not enabled, ignoring %08x offset!", |
Jon Hunter | f673b9b | 2016-05-10 16:14:44 +0100 | [diff] [blame] | 1123 | gic->percpu_offset); |
| 1124 | gic->dist_base.common_base = gic->raw_dist_base; |
| 1125 | gic->cpu_base.common_base = gic->raw_cpu_base; |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 1126 | gic_set_base_accessor(gic, gic_get_common_base); |
| 1127 | } |
Russell King | bef8f9e | 2010-12-04 16:50:58 +0000 | [diff] [blame] | 1128 | |
Rob Herring | 4294f8ba | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 1129 | /* |
Rob Herring | 4294f8ba | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 1130 | * Find out how many interrupts are supported. |
| 1131 | * The GIC only supports up to 1020 interrupt sources. |
| 1132 | */ |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 1133 | gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f; |
Rob Herring | 4294f8ba | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 1134 | gic_irqs = (gic_irqs + 1) * 32; |
| 1135 | if (gic_irqs > 1020) |
| 1136 | gic_irqs = 1020; |
| 1137 | gic->gic_irqs = gic_irqs; |
| 1138 | |
Marc Zyngier | 891ae76 | 2015-10-13 12:51:40 +0100 | [diff] [blame] | 1139 | if (handle) { /* DT/ACPI */ |
| 1140 | gic->domain = irq_domain_create_linear(handle, gic_irqs, |
| 1141 | &gic_irq_domain_hierarchy_ops, |
| 1142 | gic); |
| 1143 | } else { /* Legacy support */ |
Yingjoe Chen | 9a1091e | 2014-11-25 16:04:19 +0800 | [diff] [blame] | 1144 | /* |
| 1145 | * For primary GICs, skip over SGIs. |
| 1146 | * For secondary GICs, skip over PPIs, too. |
| 1147 | */ |
Jon Hunter | f673b9b | 2016-05-10 16:14:44 +0100 | [diff] [blame] | 1148 | if (gic == &gic_data[0] && (irq_start & 31) > 0) { |
Yingjoe Chen | 9a1091e | 2014-11-25 16:04:19 +0800 | [diff] [blame] | 1149 | hwirq_base = 16; |
| 1150 | if (irq_start != -1) |
| 1151 | irq_start = (irq_start & ~31) + 16; |
| 1152 | } else { |
| 1153 | hwirq_base = 32; |
| 1154 | } |
| 1155 | |
| 1156 | gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */ |
| 1157 | |
Sricharan R | 006e983 | 2013-12-03 15:57:22 +0530 | [diff] [blame] | 1158 | irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, |
| 1159 | numa_node_id()); |
Arnd Bergmann | 287980e | 2016-05-27 23:23:25 +0200 | [diff] [blame] | 1160 | if (irq_base < 0) { |
Sricharan R | 006e983 | 2013-12-03 15:57:22 +0530 | [diff] [blame] | 1161 | WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n", |
| 1162 | irq_start); |
| 1163 | irq_base = irq_start; |
| 1164 | } |
| 1165 | |
Marc Zyngier | 891ae76 | 2015-10-13 12:51:40 +0100 | [diff] [blame] | 1166 | gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base, |
Sricharan R | 006e983 | 2013-12-03 15:57:22 +0530 | [diff] [blame] | 1167 | hwirq_base, &gic_irq_domain_ops, gic); |
Rob Herring | f37a53c | 2011-10-21 17:14:27 -0500 | [diff] [blame] | 1168 | } |
Sricharan R | 006e983 | 2013-12-03 15:57:22 +0530 | [diff] [blame] | 1169 | |
Jon Hunter | dc9722c | 2016-05-10 16:14:42 +0100 | [diff] [blame] | 1170 | if (WARN_ON(!gic->domain)) { |
| 1171 | ret = -ENODEV; |
| 1172 | goto error; |
| 1173 | } |
Russell King | bef8f9e | 2010-12-04 16:50:58 +0000 | [diff] [blame] | 1174 | |
Rob Herring | 4294f8ba | 2011-09-28 21:25:31 -0500 | [diff] [blame] | 1175 | gic_dist_init(gic); |
Jon Hunter | dc9722c | 2016-05-10 16:14:42 +0100 | [diff] [blame] | 1176 | ret = gic_cpu_init(gic); |
| 1177 | if (ret) |
| 1178 | goto error; |
| 1179 | |
| 1180 | ret = gic_pm_init(gic); |
| 1181 | if (ret) |
| 1182 | goto error; |
| 1183 | |
| 1184 | return 0; |
| 1185 | |
| 1186 | error: |
Jon Hunter | f673b9b | 2016-05-10 16:14:44 +0100 | [diff] [blame] | 1187 | if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) { |
Jon Hunter | dc9722c | 2016-05-10 16:14:42 +0100 | [diff] [blame] | 1188 | free_percpu(gic->dist_base.percpu_base); |
| 1189 | free_percpu(gic->cpu_base.percpu_base); |
| 1190 | } |
| 1191 | |
Jon Hunter | dc9722c | 2016-05-10 16:14:42 +0100 | [diff] [blame] | 1192 | return ret; |
Russell King | b580b89 | 2010-12-04 15:55:14 +0000 | [diff] [blame] | 1193 | } |
| 1194 | |
Jon Hunter | d6ce564 | 2016-06-07 16:12:30 +0100 | [diff] [blame] | 1195 | static int __init __gic_init_bases(struct gic_chip_data *gic, |
| 1196 | int irq_start, |
| 1197 | struct fwnode_handle *handle) |
| 1198 | { |
Jon Hunter | faea645 | 2016-06-07 16:12:31 +0100 | [diff] [blame] | 1199 | char *name; |
| 1200 | int i, ret; |
Jon Hunter | d6ce564 | 2016-06-07 16:12:30 +0100 | [diff] [blame] | 1201 | |
| 1202 | if (WARN_ON(!gic || gic->domain)) |
| 1203 | return -EINVAL; |
| 1204 | |
| 1205 | if (gic == &gic_data[0]) { |
| 1206 | /* |
| 1207 | * Initialize the CPU interface map to all CPUs. |
| 1208 | * It will be refined as each CPU probes its ID. |
| 1209 | * This is only necessary for the primary GIC. |
| 1210 | */ |
| 1211 | for (i = 0; i < NR_GIC_CPU_IF; i++) |
| 1212 | gic_cpu_map[i] = 0xff; |
| 1213 | #ifdef CONFIG_SMP |
| 1214 | set_smp_cross_call(gic_raise_softirq); |
Jon Hunter | d6ce564 | 2016-06-07 16:12:30 +0100 | [diff] [blame] | 1215 | #endif |
Richard Cochran | 93131f7 | 2016-07-13 17:16:04 +0000 | [diff] [blame] | 1216 | cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING, |
| 1217 | "AP_IRQ_GIC_STARTING", |
| 1218 | gic_starting_cpu, NULL); |
Jon Hunter | d6ce564 | 2016-06-07 16:12:30 +0100 | [diff] [blame] | 1219 | set_handle_irq(gic_handle_irq); |
| 1220 | if (static_key_true(&supports_deactivate)) |
| 1221 | pr_info("GIC: Using split EOI/Deactivate mode\n"); |
| 1222 | } |
| 1223 | |
Jon Hunter | faea645 | 2016-06-07 16:12:31 +0100 | [diff] [blame] | 1224 | if (static_key_true(&supports_deactivate) && gic == &gic_data[0]) { |
| 1225 | name = kasprintf(GFP_KERNEL, "GICv2"); |
| 1226 | gic_init_chip(gic, NULL, name, true); |
| 1227 | } else { |
| 1228 | name = kasprintf(GFP_KERNEL, "GIC-%d", (int)(gic-&gic_data[0])); |
| 1229 | gic_init_chip(gic, NULL, name, false); |
| 1230 | } |
| 1231 | |
| 1232 | ret = gic_init_bases(gic, irq_start, handle); |
| 1233 | if (ret) |
| 1234 | kfree(name); |
| 1235 | |
| 1236 | return ret; |
Jon Hunter | d6ce564 | 2016-06-07 16:12:30 +0100 | [diff] [blame] | 1237 | } |
| 1238 | |
Teng Fei Fan | 1e3e9f6 | 2018-04-11 18:02:28 +0800 | [diff] [blame] | 1239 | #ifdef CONFIG_PM |
| 1240 | static int gic_suspend(void) |
| 1241 | { |
| 1242 | return 0; |
| 1243 | } |
| 1244 | |
| 1245 | static void gic_show_resume_irq(struct gic_chip_data *gic) |
| 1246 | { |
| 1247 | unsigned int i; |
| 1248 | u32 enabled; |
| 1249 | u32 pending[32]; |
| 1250 | void __iomem *base = gic_data_dist_base(gic); |
| 1251 | |
| 1252 | if (!msm_show_resume_irq_mask) |
| 1253 | return; |
| 1254 | |
| 1255 | for (i = 0; i * 32 < gic->gic_irqs; i++) { |
| 1256 | enabled = readl_relaxed(base + GIC_DIST_ENABLE_CLEAR + i * 4); |
| 1257 | pending[i] = readl_relaxed(base + GIC_DIST_PENDING_SET + i * 4); |
| 1258 | pending[i] &= enabled; |
| 1259 | } |
| 1260 | |
| 1261 | for (i = find_first_bit((unsigned long *)pending, gic->gic_irqs); |
| 1262 | i < gic->gic_irqs; |
| 1263 | i = find_next_bit((unsigned long *)pending, gic->gic_irqs, i+1)) { |
| 1264 | unsigned int irq = irq_find_mapping(gic->domain, i); |
| 1265 | struct irq_desc *desc = irq_to_desc(irq); |
| 1266 | const char *name = "null"; |
| 1267 | |
| 1268 | if (desc == NULL) |
| 1269 | name = "stray irq"; |
| 1270 | else if (desc->action && desc->action->name) |
| 1271 | name = desc->action->name; |
| 1272 | |
| 1273 | pr_warn("%s: %d triggered %s\n", __func__, i, name); |
| 1274 | } |
| 1275 | } |
| 1276 | |
| 1277 | static void gic_resume_one(struct gic_chip_data *gic) |
| 1278 | { |
| 1279 | gic_show_resume_irq(gic); |
| 1280 | } |
| 1281 | |
| 1282 | static void gic_resume(void) |
| 1283 | { |
| 1284 | int i; |
| 1285 | |
| 1286 | for (i = 0; i < CONFIG_ARM_GIC_MAX_NR; i++) |
| 1287 | gic_resume_one(&gic_data[i]); |
| 1288 | } |
| 1289 | |
| 1290 | static struct syscore_ops gic_syscore_ops = { |
| 1291 | .suspend = gic_suspend, |
| 1292 | .resume = gic_resume, |
| 1293 | }; |
| 1294 | |
| 1295 | static int __init gic_init_sys(void) |
| 1296 | { |
| 1297 | register_syscore_ops(&gic_syscore_ops); |
| 1298 | return 0; |
| 1299 | } |
| 1300 | arch_initcall(gic_init_sys); |
| 1301 | #endif |
| 1302 | |
Marc Zyngier | e81a7cd | 2015-10-13 12:51:39 +0100 | [diff] [blame] | 1303 | void __init gic_init(unsigned int gic_nr, int irq_start, |
| 1304 | void __iomem *dist_base, void __iomem *cpu_base) |
Marc Zyngier | 4a6ac30 | 2015-09-01 10:08:53 +0100 | [diff] [blame] | 1305 | { |
Jon Hunter | f673b9b | 2016-05-10 16:14:44 +0100 | [diff] [blame] | 1306 | struct gic_chip_data *gic; |
| 1307 | |
| 1308 | if (WARN_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR)) |
| 1309 | return; |
| 1310 | |
Marc Zyngier | 4a6ac30 | 2015-09-01 10:08:53 +0100 | [diff] [blame] | 1311 | /* |
| 1312 | * Non-DT/ACPI systems won't run a hypervisor, so let's not |
| 1313 | * bother with these... |
| 1314 | */ |
| 1315 | static_key_slow_dec(&supports_deactivate); |
Jon Hunter | f673b9b | 2016-05-10 16:14:44 +0100 | [diff] [blame] | 1316 | |
| 1317 | gic = &gic_data[gic_nr]; |
| 1318 | gic->raw_dist_base = dist_base; |
| 1319 | gic->raw_cpu_base = cpu_base; |
| 1320 | |
| 1321 | __gic_init_bases(gic, irq_start, NULL); |
Marc Zyngier | 4a6ac30 | 2015-09-01 10:08:53 +0100 | [diff] [blame] | 1322 | } |
| 1323 | |
Jon Hunter | d649046 | 2016-05-10 16:14:45 +0100 | [diff] [blame] | 1324 | static void gic_teardown(struct gic_chip_data *gic) |
| 1325 | { |
| 1326 | if (WARN_ON(!gic)) |
| 1327 | return; |
| 1328 | |
| 1329 | if (gic->raw_dist_base) |
| 1330 | iounmap(gic->raw_dist_base); |
| 1331 | if (gic->raw_cpu_base) |
| 1332 | iounmap(gic->raw_cpu_base); |
Catalin Marinas | b3a1bde | 2007-02-14 19:14:56 +0100 | [diff] [blame] | 1333 | } |
| 1334 | |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 1335 | #ifdef CONFIG_OF |
Sachin Kamat | 46f101d | 2013-03-13 15:05:15 +0530 | [diff] [blame] | 1336 | static int gic_cnt __initdata; |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 1337 | |
Marc Zyngier | 12e1406 | 2015-09-13 12:14:31 +0100 | [diff] [blame] | 1338 | static bool gic_check_eoimode(struct device_node *node, void __iomem **base) |
| 1339 | { |
| 1340 | struct resource cpuif_res; |
| 1341 | |
| 1342 | of_address_to_resource(node, 1, &cpuif_res); |
| 1343 | |
| 1344 | if (!is_hyp_mode_available()) |
| 1345 | return false; |
| 1346 | if (resource_size(&cpuif_res) < SZ_8K) |
| 1347 | return false; |
| 1348 | if (resource_size(&cpuif_res) == SZ_128K) { |
| 1349 | u32 val_low, val_high; |
| 1350 | |
| 1351 | /* |
| 1352 | * Verify that we have the first 4kB of a GIC400 |
| 1353 | * aliased over the first 64kB by checking the |
| 1354 | * GICC_IIDR register on both ends. |
| 1355 | */ |
| 1356 | val_low = readl_relaxed(*base + GIC_CPU_IDENT); |
| 1357 | val_high = readl_relaxed(*base + GIC_CPU_IDENT + 0xf000); |
| 1358 | if ((val_low & 0xffff0fff) != 0x0202043B || |
| 1359 | val_low != val_high) |
| 1360 | return false; |
| 1361 | |
| 1362 | /* |
| 1363 | * Move the base up by 60kB, so that we have a 8kB |
| 1364 | * contiguous region, which allows us to use GICC_DIR |
| 1365 | * at its normal offset. Please pass me that bucket. |
| 1366 | */ |
| 1367 | *base += 0xf000; |
| 1368 | cpuif_res.start += 0xf000; |
Marc Zyngier | fd5bed4 | 2016-10-20 11:21:01 +0100 | [diff] [blame] | 1369 | pr_warn("GIC: Adjusting CPU interface base to %pa\n", |
Marc Zyngier | 12e1406 | 2015-09-13 12:14:31 +0100 | [diff] [blame] | 1370 | &cpuif_res.start); |
| 1371 | } |
| 1372 | |
| 1373 | return true; |
| 1374 | } |
| 1375 | |
Jon Hunter | 9c8eddd | 2016-06-07 16:12:34 +0100 | [diff] [blame] | 1376 | static int gic_of_setup(struct gic_chip_data *gic, struct device_node *node) |
Jon Hunter | d649046 | 2016-05-10 16:14:45 +0100 | [diff] [blame] | 1377 | { |
| 1378 | if (!gic || !node) |
| 1379 | return -EINVAL; |
| 1380 | |
| 1381 | gic->raw_dist_base = of_iomap(node, 0); |
| 1382 | if (WARN(!gic->raw_dist_base, "unable to map gic dist registers\n")) |
| 1383 | goto error; |
| 1384 | |
| 1385 | gic->raw_cpu_base = of_iomap(node, 1); |
| 1386 | if (WARN(!gic->raw_cpu_base, "unable to map gic cpu registers\n")) |
| 1387 | goto error; |
| 1388 | |
| 1389 | if (of_property_read_u32(node, "cpu-offset", &gic->percpu_offset)) |
| 1390 | gic->percpu_offset = 0; |
| 1391 | |
| 1392 | return 0; |
| 1393 | |
| 1394 | error: |
| 1395 | gic_teardown(gic); |
| 1396 | |
| 1397 | return -ENOMEM; |
| 1398 | } |
| 1399 | |
Jon Hunter | 9c8eddd | 2016-06-07 16:12:34 +0100 | [diff] [blame] | 1400 | int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq) |
| 1401 | { |
| 1402 | int ret; |
| 1403 | |
| 1404 | if (!dev || !dev->of_node || !gic || !irq) |
| 1405 | return -EINVAL; |
| 1406 | |
| 1407 | *gic = devm_kzalloc(dev, sizeof(**gic), GFP_KERNEL); |
| 1408 | if (!*gic) |
| 1409 | return -ENOMEM; |
| 1410 | |
| 1411 | gic_init_chip(*gic, dev, dev->of_node->name, false); |
| 1412 | |
| 1413 | ret = gic_of_setup(*gic, dev->of_node); |
| 1414 | if (ret) |
| 1415 | return ret; |
| 1416 | |
| 1417 | ret = gic_init_bases(*gic, -1, &dev->of_node->fwnode); |
| 1418 | if (ret) { |
| 1419 | gic_teardown(*gic); |
| 1420 | return ret; |
| 1421 | } |
| 1422 | |
| 1423 | irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, *gic); |
| 1424 | |
| 1425 | return 0; |
| 1426 | } |
| 1427 | |
Julien Grall | 502d6df | 2016-04-11 16:32:54 +0100 | [diff] [blame] | 1428 | static void __init gic_of_setup_kvm_info(struct device_node *node) |
| 1429 | { |
| 1430 | int ret; |
| 1431 | struct resource *vctrl_res = &gic_v2_kvm_info.vctrl; |
| 1432 | struct resource *vcpu_res = &gic_v2_kvm_info.vcpu; |
| 1433 | |
| 1434 | gic_v2_kvm_info.type = GIC_V2; |
| 1435 | |
| 1436 | gic_v2_kvm_info.maint_irq = irq_of_parse_and_map(node, 0); |
| 1437 | if (!gic_v2_kvm_info.maint_irq) |
| 1438 | return; |
| 1439 | |
| 1440 | ret = of_address_to_resource(node, 2, vctrl_res); |
| 1441 | if (ret) |
| 1442 | return; |
| 1443 | |
| 1444 | ret = of_address_to_resource(node, 3, vcpu_res); |
| 1445 | if (ret) |
| 1446 | return; |
| 1447 | |
| 1448 | gic_set_kvm_info(&gic_v2_kvm_info); |
| 1449 | } |
| 1450 | |
Linus Walleij | 8673c1d | 2015-10-24 00:15:52 +0200 | [diff] [blame] | 1451 | int __init |
Stephen Boyd | 6859358 | 2014-03-04 17:02:01 -0800 | [diff] [blame] | 1452 | gic_of_init(struct device_node *node, struct device_node *parent) |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 1453 | { |
Jon Hunter | f673b9b | 2016-05-10 16:14:44 +0100 | [diff] [blame] | 1454 | struct gic_chip_data *gic; |
Jon Hunter | dc9722c | 2016-05-10 16:14:42 +0100 | [diff] [blame] | 1455 | int irq, ret; |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 1456 | |
| 1457 | if (WARN_ON(!node)) |
| 1458 | return -ENODEV; |
| 1459 | |
Jon Hunter | f673b9b | 2016-05-10 16:14:44 +0100 | [diff] [blame] | 1460 | if (WARN_ON(gic_cnt >= CONFIG_ARM_GIC_MAX_NR)) |
| 1461 | return -EINVAL; |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 1462 | |
Jon Hunter | f673b9b | 2016-05-10 16:14:44 +0100 | [diff] [blame] | 1463 | gic = &gic_data[gic_cnt]; |
| 1464 | |
Jon Hunter | d649046 | 2016-05-10 16:14:45 +0100 | [diff] [blame] | 1465 | ret = gic_of_setup(gic, node); |
| 1466 | if (ret) |
| 1467 | return ret; |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 1468 | |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame] | 1469 | /* |
| 1470 | * Disable split EOI/Deactivate if either HYP is not available |
| 1471 | * or the CPU interface is too small. |
| 1472 | */ |
Jon Hunter | f673b9b | 2016-05-10 16:14:44 +0100 | [diff] [blame] | 1473 | if (gic_cnt == 0 && !gic_check_eoimode(node, &gic->raw_cpu_base)) |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame] | 1474 | static_key_slow_dec(&supports_deactivate); |
| 1475 | |
Jon Hunter | f673b9b | 2016-05-10 16:14:44 +0100 | [diff] [blame] | 1476 | ret = __gic_init_bases(gic, -1, &node->fwnode); |
Jon Hunter | dc9722c | 2016-05-10 16:14:42 +0100 | [diff] [blame] | 1477 | if (ret) { |
Jon Hunter | d649046 | 2016-05-10 16:14:45 +0100 | [diff] [blame] | 1478 | gic_teardown(gic); |
Jon Hunter | dc9722c | 2016-05-10 16:14:42 +0100 | [diff] [blame] | 1479 | return ret; |
| 1480 | } |
Marc Zyngier | db0d4db | 2011-11-12 16:09:49 +0000 | [diff] [blame] | 1481 | |
Julien Grall | 502d6df | 2016-04-11 16:32:54 +0100 | [diff] [blame] | 1482 | if (!gic_cnt) { |
Nicolas Pitre | eeb4465 | 2012-11-28 18:17:25 -0500 | [diff] [blame] | 1483 | gic_init_physaddr(node); |
Julien Grall | 502d6df | 2016-04-11 16:32:54 +0100 | [diff] [blame] | 1484 | gic_of_setup_kvm_info(node); |
| 1485 | } |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 1486 | |
| 1487 | if (parent) { |
| 1488 | irq = irq_of_parse_and_map(node, 0); |
| 1489 | gic_cascade_irq(gic_cnt, irq); |
| 1490 | } |
Suravee Suthikulpanit | 853a33c | 2014-11-25 18:47:22 +0000 | [diff] [blame] | 1491 | |
| 1492 | if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) |
Suravee Suthikulpanit | 0644b3d | 2015-12-10 08:55:30 -0800 | [diff] [blame] | 1493 | gicv2m_init(&node->fwnode, gic_data[gic_cnt].domain); |
Suravee Suthikulpanit | 853a33c | 2014-11-25 18:47:22 +0000 | [diff] [blame] | 1494 | |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 1495 | gic_cnt++; |
| 1496 | return 0; |
| 1497 | } |
Suravee Suthikulpanit | 144cb08 | 2014-07-15 00:03:03 +0200 | [diff] [blame] | 1498 | IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init); |
Linus Walleij | fa6e2ee | 2014-10-01 09:29:22 +0200 | [diff] [blame] | 1499 | IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init); |
| 1500 | IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init); |
Rob Herring | 81243e4 | 2012-11-20 21:21:40 -0600 | [diff] [blame] | 1501 | IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); |
| 1502 | IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); |
Matthias Brugger | a97e8027 | 2014-07-03 13:58:52 +0200 | [diff] [blame] | 1503 | IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init); |
Rob Herring | 81243e4 | 2012-11-20 21:21:40 -0600 | [diff] [blame] | 1504 | IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); |
| 1505 | IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); |
Geert Uytterhoeven | 8709b9e | 2015-09-14 22:06:43 +0200 | [diff] [blame] | 1506 | IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init); |
Jon Hunter | 9c8eddd | 2016-06-07 16:12:34 +0100 | [diff] [blame] | 1507 | #else |
| 1508 | int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq) |
| 1509 | { |
| 1510 | return -ENOTSUPP; |
| 1511 | } |
Rob Herring | b3f7ed0 | 2011-09-28 21:27:52 -0500 | [diff] [blame] | 1512 | #endif |
Tomasz Nowicki | d60fc38 | 2015-03-24 14:02:49 +0000 | [diff] [blame] | 1513 | |
| 1514 | #ifdef CONFIG_ACPI |
Julien Grall | bafa919 | 2016-04-11 16:32:53 +0100 | [diff] [blame] | 1515 | static struct |
| 1516 | { |
| 1517 | phys_addr_t cpu_phys_base; |
Julien Grall | 502d6df | 2016-04-11 16:32:54 +0100 | [diff] [blame] | 1518 | u32 maint_irq; |
| 1519 | int maint_irq_mode; |
| 1520 | phys_addr_t vctrl_base; |
| 1521 | phys_addr_t vcpu_base; |
Julien Grall | bafa919 | 2016-04-11 16:32:53 +0100 | [diff] [blame] | 1522 | } acpi_data __initdata; |
Tomasz Nowicki | d60fc38 | 2015-03-24 14:02:49 +0000 | [diff] [blame] | 1523 | |
| 1524 | static int __init |
| 1525 | gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header, |
| 1526 | const unsigned long end) |
| 1527 | { |
| 1528 | struct acpi_madt_generic_interrupt *processor; |
| 1529 | phys_addr_t gic_cpu_base; |
| 1530 | static int cpu_base_assigned; |
| 1531 | |
| 1532 | processor = (struct acpi_madt_generic_interrupt *)header; |
| 1533 | |
Al Stone | 99e3e3a | 2015-07-06 17:16:48 -0600 | [diff] [blame] | 1534 | if (BAD_MADT_GICC_ENTRY(processor, end)) |
Tomasz Nowicki | d60fc38 | 2015-03-24 14:02:49 +0000 | [diff] [blame] | 1535 | return -EINVAL; |
| 1536 | |
| 1537 | /* |
| 1538 | * There is no support for non-banked GICv1/2 register in ACPI spec. |
| 1539 | * All CPU interface addresses have to be the same. |
| 1540 | */ |
| 1541 | gic_cpu_base = processor->base_address; |
Julien Grall | bafa919 | 2016-04-11 16:32:53 +0100 | [diff] [blame] | 1542 | if (cpu_base_assigned && gic_cpu_base != acpi_data.cpu_phys_base) |
Tomasz Nowicki | d60fc38 | 2015-03-24 14:02:49 +0000 | [diff] [blame] | 1543 | return -EINVAL; |
| 1544 | |
Julien Grall | bafa919 | 2016-04-11 16:32:53 +0100 | [diff] [blame] | 1545 | acpi_data.cpu_phys_base = gic_cpu_base; |
Julien Grall | 502d6df | 2016-04-11 16:32:54 +0100 | [diff] [blame] | 1546 | acpi_data.maint_irq = processor->vgic_interrupt; |
| 1547 | acpi_data.maint_irq_mode = (processor->flags & ACPI_MADT_VGIC_IRQ_MODE) ? |
| 1548 | ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; |
| 1549 | acpi_data.vctrl_base = processor->gich_base_address; |
| 1550 | acpi_data.vcpu_base = processor->gicv_base_address; |
| 1551 | |
Tomasz Nowicki | d60fc38 | 2015-03-24 14:02:49 +0000 | [diff] [blame] | 1552 | cpu_base_assigned = 1; |
| 1553 | return 0; |
| 1554 | } |
| 1555 | |
Marc Zyngier | f26527b | 2015-09-28 15:49:14 +0100 | [diff] [blame] | 1556 | /* The things you have to do to just *count* something... */ |
| 1557 | static int __init acpi_dummy_func(struct acpi_subtable_header *header, |
| 1558 | const unsigned long end) |
Tomasz Nowicki | d60fc38 | 2015-03-24 14:02:49 +0000 | [diff] [blame] | 1559 | { |
Tomasz Nowicki | d60fc38 | 2015-03-24 14:02:49 +0000 | [diff] [blame] | 1560 | return 0; |
| 1561 | } |
| 1562 | |
Marc Zyngier | f26527b | 2015-09-28 15:49:14 +0100 | [diff] [blame] | 1563 | static bool __init acpi_gic_redist_is_present(void) |
Tomasz Nowicki | d60fc38 | 2015-03-24 14:02:49 +0000 | [diff] [blame] | 1564 | { |
Marc Zyngier | f26527b | 2015-09-28 15:49:14 +0100 | [diff] [blame] | 1565 | return acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, |
| 1566 | acpi_dummy_func, 0) > 0; |
| 1567 | } |
| 1568 | |
| 1569 | static bool __init gic_validate_dist(struct acpi_subtable_header *header, |
| 1570 | struct acpi_probe_entry *ape) |
| 1571 | { |
| 1572 | struct acpi_madt_generic_distributor *dist; |
| 1573 | dist = (struct acpi_madt_generic_distributor *)header; |
| 1574 | |
| 1575 | return (dist->version == ape->driver_data && |
| 1576 | (dist->version != ACPI_MADT_GIC_VERSION_NONE || |
| 1577 | !acpi_gic_redist_is_present())); |
| 1578 | } |
| 1579 | |
| 1580 | #define ACPI_GICV2_DIST_MEM_SIZE (SZ_4K) |
| 1581 | #define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K) |
Julien Grall | 502d6df | 2016-04-11 16:32:54 +0100 | [diff] [blame] | 1582 | #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K) |
| 1583 | #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K) |
| 1584 | |
| 1585 | static void __init gic_acpi_setup_kvm_info(void) |
| 1586 | { |
| 1587 | int irq; |
| 1588 | struct resource *vctrl_res = &gic_v2_kvm_info.vctrl; |
| 1589 | struct resource *vcpu_res = &gic_v2_kvm_info.vcpu; |
| 1590 | |
| 1591 | gic_v2_kvm_info.type = GIC_V2; |
| 1592 | |
| 1593 | if (!acpi_data.vctrl_base) |
| 1594 | return; |
| 1595 | |
| 1596 | vctrl_res->flags = IORESOURCE_MEM; |
| 1597 | vctrl_res->start = acpi_data.vctrl_base; |
| 1598 | vctrl_res->end = vctrl_res->start + ACPI_GICV2_VCTRL_MEM_SIZE - 1; |
| 1599 | |
| 1600 | if (!acpi_data.vcpu_base) |
| 1601 | return; |
| 1602 | |
| 1603 | vcpu_res->flags = IORESOURCE_MEM; |
| 1604 | vcpu_res->start = acpi_data.vcpu_base; |
| 1605 | vcpu_res->end = vcpu_res->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; |
| 1606 | |
| 1607 | irq = acpi_register_gsi(NULL, acpi_data.maint_irq, |
| 1608 | acpi_data.maint_irq_mode, |
| 1609 | ACPI_ACTIVE_HIGH); |
| 1610 | if (irq <= 0) |
| 1611 | return; |
| 1612 | |
| 1613 | gic_v2_kvm_info.maint_irq = irq; |
| 1614 | |
| 1615 | gic_set_kvm_info(&gic_v2_kvm_info); |
| 1616 | } |
Marc Zyngier | f26527b | 2015-09-28 15:49:14 +0100 | [diff] [blame] | 1617 | |
| 1618 | static int __init gic_v2_acpi_init(struct acpi_subtable_header *header, |
| 1619 | const unsigned long end) |
| 1620 | { |
| 1621 | struct acpi_madt_generic_distributor *dist; |
Marc Zyngier | 891ae76 | 2015-10-13 12:51:40 +0100 | [diff] [blame] | 1622 | struct fwnode_handle *domain_handle; |
Jon Hunter | f673b9b | 2016-05-10 16:14:44 +0100 | [diff] [blame] | 1623 | struct gic_chip_data *gic = &gic_data[0]; |
Jon Hunter | dc9722c | 2016-05-10 16:14:42 +0100 | [diff] [blame] | 1624 | int count, ret; |
Tomasz Nowicki | d60fc38 | 2015-03-24 14:02:49 +0000 | [diff] [blame] | 1625 | |
| 1626 | /* Collect CPU base addresses */ |
Marc Zyngier | f26527b | 2015-09-28 15:49:14 +0100 | [diff] [blame] | 1627 | count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, |
| 1628 | gic_acpi_parse_madt_cpu, 0); |
Tomasz Nowicki | d60fc38 | 2015-03-24 14:02:49 +0000 | [diff] [blame] | 1629 | if (count <= 0) { |
| 1630 | pr_err("No valid GICC entries exist\n"); |
| 1631 | return -EINVAL; |
| 1632 | } |
| 1633 | |
Linus Torvalds | 7beaa24 | 2016-05-19 11:27:09 -0700 | [diff] [blame] | 1634 | gic->raw_cpu_base = ioremap(acpi_data.cpu_phys_base, ACPI_GIC_CPU_IF_MEM_SIZE); |
Jon Hunter | f673b9b | 2016-05-10 16:14:44 +0100 | [diff] [blame] | 1635 | if (!gic->raw_cpu_base) { |
Tomasz Nowicki | d60fc38 | 2015-03-24 14:02:49 +0000 | [diff] [blame] | 1636 | pr_err("Unable to map GICC registers\n"); |
| 1637 | return -ENOMEM; |
| 1638 | } |
| 1639 | |
Marc Zyngier | f26527b | 2015-09-28 15:49:14 +0100 | [diff] [blame] | 1640 | dist = (struct acpi_madt_generic_distributor *)header; |
Jon Hunter | f673b9b | 2016-05-10 16:14:44 +0100 | [diff] [blame] | 1641 | gic->raw_dist_base = ioremap(dist->base_address, |
| 1642 | ACPI_GICV2_DIST_MEM_SIZE); |
| 1643 | if (!gic->raw_dist_base) { |
Tomasz Nowicki | d60fc38 | 2015-03-24 14:02:49 +0000 | [diff] [blame] | 1644 | pr_err("Unable to map GICD registers\n"); |
Jon Hunter | d649046 | 2016-05-10 16:14:45 +0100 | [diff] [blame] | 1645 | gic_teardown(gic); |
Tomasz Nowicki | d60fc38 | 2015-03-24 14:02:49 +0000 | [diff] [blame] | 1646 | return -ENOMEM; |
| 1647 | } |
| 1648 | |
| 1649 | /* |
Marc Zyngier | 0b996fd | 2015-08-26 17:00:44 +0100 | [diff] [blame] | 1650 | * Disable split EOI/Deactivate if HYP is not available. ACPI |
| 1651 | * guarantees that we'll always have a GICv2, so the CPU |
| 1652 | * interface will always be the right size. |
| 1653 | */ |
| 1654 | if (!is_hyp_mode_available()) |
| 1655 | static_key_slow_dec(&supports_deactivate); |
| 1656 | |
| 1657 | /* |
Marc Zyngier | 891ae76 | 2015-10-13 12:51:40 +0100 | [diff] [blame] | 1658 | * Initialize GIC instance zero (no multi-GIC support). |
Tomasz Nowicki | d60fc38 | 2015-03-24 14:02:49 +0000 | [diff] [blame] | 1659 | */ |
Jon Hunter | f673b9b | 2016-05-10 16:14:44 +0100 | [diff] [blame] | 1660 | domain_handle = irq_domain_alloc_fwnode(gic->raw_dist_base); |
Marc Zyngier | 891ae76 | 2015-10-13 12:51:40 +0100 | [diff] [blame] | 1661 | if (!domain_handle) { |
| 1662 | pr_err("Unable to allocate domain handle\n"); |
Jon Hunter | d649046 | 2016-05-10 16:14:45 +0100 | [diff] [blame] | 1663 | gic_teardown(gic); |
Marc Zyngier | 891ae76 | 2015-10-13 12:51:40 +0100 | [diff] [blame] | 1664 | return -ENOMEM; |
| 1665 | } |
Lorenzo Pieralisi | d8f4f16 | 2015-03-24 17:58:51 +0000 | [diff] [blame] | 1666 | |
Jon Hunter | f673b9b | 2016-05-10 16:14:44 +0100 | [diff] [blame] | 1667 | ret = __gic_init_bases(gic, -1, domain_handle); |
Jon Hunter | dc9722c | 2016-05-10 16:14:42 +0100 | [diff] [blame] | 1668 | if (ret) { |
| 1669 | pr_err("Failed to initialise GIC\n"); |
| 1670 | irq_domain_free_fwnode(domain_handle); |
Jon Hunter | d649046 | 2016-05-10 16:14:45 +0100 | [diff] [blame] | 1671 | gic_teardown(gic); |
Jon Hunter | dc9722c | 2016-05-10 16:14:42 +0100 | [diff] [blame] | 1672 | return ret; |
| 1673 | } |
Marc Zyngier | 891ae76 | 2015-10-13 12:51:40 +0100 | [diff] [blame] | 1674 | |
| 1675 | acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); |
Suravee Suthikulpanit | 0644b3d | 2015-12-10 08:55:30 -0800 | [diff] [blame] | 1676 | |
| 1677 | if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) |
| 1678 | gicv2m_init(NULL, gic_data[0].domain); |
| 1679 | |
Julien Grall | 502d6df | 2016-04-11 16:32:54 +0100 | [diff] [blame] | 1680 | gic_acpi_setup_kvm_info(); |
| 1681 | |
Tomasz Nowicki | d60fc38 | 2015-03-24 14:02:49 +0000 | [diff] [blame] | 1682 | return 0; |
| 1683 | } |
Marc Zyngier | f26527b | 2015-09-28 15:49:14 +0100 | [diff] [blame] | 1684 | IRQCHIP_ACPI_DECLARE(gic_v2, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, |
| 1685 | gic_validate_dist, ACPI_MADT_GIC_VERSION_V2, |
| 1686 | gic_v2_acpi_init); |
| 1687 | IRQCHIP_ACPI_DECLARE(gic_v2_maybe, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, |
| 1688 | gic_validate_dist, ACPI_MADT_GIC_VERSION_NONE, |
| 1689 | gic_v2_acpi_init); |
Tomasz Nowicki | d60fc38 | 2015-03-24 14:02:49 +0000 | [diff] [blame] | 1690 | #endif |