Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 1 | /* |
Anoop Thomas Mathew | b6b2485 | 2013-09-18 12:02:00 -0700 | [diff] [blame] | 2 | * OMAP4 SMP source file. It contains platform specific functions |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 3 | * needed for the linux smp kernel. |
| 4 | * |
| 5 | * Copyright (C) 2009 Texas Instruments, Inc. |
| 6 | * |
| 7 | * Author: |
| 8 | * Santosh Shilimkar <santosh.shilimkar@ti.com> |
| 9 | * |
| 10 | * Platform file needed for the OMAP4 SMP. This file is based on arm |
| 11 | * realview smp platform. |
| 12 | * * Copyright (c) 2002 ARM Limited. |
| 13 | * |
| 14 | * This program is free software; you can redistribute it and/or modify |
| 15 | * it under the terms of the GNU General Public License version 2 as |
| 16 | * published by the Free Software Foundation. |
| 17 | */ |
| 18 | #include <linux/init.h> |
| 19 | #include <linux/device.h> |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 20 | #include <linux/smp.h> |
| 21 | #include <linux/io.h> |
Rob Herring | 520f7bd | 2012-12-27 13:10:24 -0600 | [diff] [blame] | 22 | #include <linux/irqchip/arm-gic.h> |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 23 | |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 24 | #include <asm/smp_scu.h> |
Lennart Sorensen | 999f934 | 2015-01-05 15:45:45 -0800 | [diff] [blame] | 25 | #include <asm/virt.h> |
Tony Lindgren | ee0839c | 2012-02-24 10:34:35 -0800 | [diff] [blame] | 26 | |
Tony Lindgren | c1db9d7 | 2012-09-20 11:41:14 -0700 | [diff] [blame] | 27 | #include "omap-secure.h" |
Tony Lindgren | 732231a | 2012-09-20 11:41:16 -0700 | [diff] [blame] | 28 | #include "omap-wakeupgen.h" |
Santosh Shilimkar | 247c445 | 2012-05-09 20:38:35 +0530 | [diff] [blame] | 29 | #include <asm/cputype.h> |
Tony Lindgren | 4e65331 | 2011-11-10 22:45:17 +0100 | [diff] [blame] | 30 | |
Tony Lindgren | dbc0416 | 2012-08-31 10:59:07 -0700 | [diff] [blame] | 31 | #include "soc.h" |
Tony Lindgren | ee0839c | 2012-02-24 10:34:35 -0800 | [diff] [blame] | 32 | #include "iomap.h" |
Tony Lindgren | 4e65331 | 2011-11-10 22:45:17 +0100 | [diff] [blame] | 33 | #include "common.h" |
Santosh Shilimkar | e97ca47 | 2010-06-16 22:19:49 +0530 | [diff] [blame] | 34 | #include "clockdomain.h" |
Santosh Shilimkar | ff999b8 | 2012-10-18 12:20:05 +0300 | [diff] [blame] | 35 | #include "pm.h" |
Santosh Shilimkar | e97ca47 | 2010-06-16 22:19:49 +0530 | [diff] [blame] | 36 | |
Santosh Shilimkar | 283f708 | 2012-03-19 19:29:41 +0530 | [diff] [blame] | 37 | #define CPU_MASK 0xff0ffff0 |
| 38 | #define CPU_CORTEX_A9 0x410FC090 |
| 39 | #define CPU_CORTEX_A15 0x410FC0F0 |
| 40 | |
| 41 | #define OMAP5_CORE_COUNT 0x2 |
| 42 | |
Tony Lindgren | 3251885 | 2016-06-22 01:59:40 -0700 | [diff] [blame] | 43 | struct omap_smp_config { |
| 44 | unsigned long cpu1_rstctrl_pa; |
| 45 | void __iomem *cpu1_rstctrl_va; |
| 46 | void __iomem *scu_base; |
| 47 | void *startup_addr; |
| 48 | }; |
| 49 | |
| 50 | static struct omap_smp_config cfg; |
| 51 | |
| 52 | static const struct omap_smp_config omap443x_cfg __initconst = { |
| 53 | .cpu1_rstctrl_pa = 0x4824380c, |
| 54 | .startup_addr = omap4_secondary_startup, |
| 55 | }; |
| 56 | |
| 57 | static const struct omap_smp_config omap446x_cfg __initconst = { |
| 58 | .cpu1_rstctrl_pa = 0x4824380c, |
| 59 | .startup_addr = omap4460_secondary_startup, |
| 60 | }; |
| 61 | |
| 62 | static const struct omap_smp_config omap5_cfg __initconst = { |
| 63 | .cpu1_rstctrl_pa = 0x48243810, |
| 64 | .startup_addr = omap5_secondary_startup, |
| 65 | }; |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 66 | |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 67 | static DEFINE_SPINLOCK(boot_lock); |
| 68 | |
Santosh Shilimkar | 02afe8a | 2011-03-03 18:03:25 +0530 | [diff] [blame] | 69 | void __iomem *omap4_get_scu_base(void) |
| 70 | { |
Tony Lindgren | 3251885 | 2016-06-22 01:59:40 -0700 | [diff] [blame] | 71 | return cfg.scu_base; |
Santosh Shilimkar | 02afe8a | 2011-03-03 18:03:25 +0530 | [diff] [blame] | 72 | } |
| 73 | |
Nishanth Menon | c0053bd | 2015-08-06 10:54:24 -0500 | [diff] [blame] | 74 | #ifdef CONFIG_OMAP5_ERRATA_801819 |
| 75 | void omap5_erratum_workaround_801819(void) |
| 76 | { |
| 77 | u32 acr, revidr; |
| 78 | u32 acr_mask; |
| 79 | |
| 80 | /* REVIDR[3] indicates erratum fix available on silicon */ |
| 81 | asm volatile ("mrc p15, 0, %0, c0, c0, 6" : "=r" (revidr)); |
| 82 | if (revidr & (0x1 << 3)) |
| 83 | return; |
| 84 | |
| 85 | asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); |
| 86 | /* |
| 87 | * BIT(27) - Disables streaming. All write-allocate lines allocate in |
| 88 | * the L1 or L2 cache. |
| 89 | * BIT(25) - Disables streaming. All write-allocate lines allocate in |
| 90 | * the L1 cache. |
| 91 | */ |
| 92 | acr_mask = (0x3 << 25) | (0x3 << 27); |
| 93 | /* do we already have it done.. if yes, skip expensive smc */ |
| 94 | if ((acr & acr_mask) == acr_mask) |
| 95 | return; |
| 96 | |
| 97 | acr |= acr_mask; |
| 98 | omap_smc1(OMAP5_DRA7_MON_SET_ACR_INDEX, acr); |
| 99 | |
| 100 | pr_debug("%s: ARM erratum workaround 801819 applied on CPU%d\n", |
| 101 | __func__, smp_processor_id()); |
| 102 | } |
| 103 | #else |
| 104 | static inline void omap5_erratum_workaround_801819(void) { } |
| 105 | #endif |
| 106 | |
Nishanth Menon | 66b29e2 | 2018-07-10 14:47:25 -0500 | [diff] [blame] | 107 | #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR |
| 108 | /* |
| 109 | * Configure ACR and enable ACTLR[0] (Enable invalidates of BTB with |
| 110 | * ICIALLU) to activate the workaround for secondary Core. |
| 111 | * NOTE: it is assumed that the primary core's configuration is done |
| 112 | * by the boot loader (kernel will detect a misconfiguration and complain |
| 113 | * if this is not done). |
| 114 | * |
| 115 | * In General Purpose(GP) devices, ACR bit settings can only be done |
| 116 | * by ROM code in "secure world" using the smc call and there is no |
| 117 | * option to update the "firmware" on such devices. This also works for |
| 118 | * High security(HS) devices, as a backup option in case the |
| 119 | * "update" is not done in the "security firmware". |
| 120 | */ |
| 121 | static void omap5_secondary_harden_predictor(void) |
| 122 | { |
| 123 | u32 acr, acr_mask; |
| 124 | |
| 125 | asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); |
| 126 | |
| 127 | /* |
| 128 | * ACTLR[0] (Enable invalidates of BTB with ICIALLU) |
| 129 | */ |
| 130 | acr_mask = BIT(0); |
| 131 | |
| 132 | /* Do we already have it done.. if yes, skip expensive smc */ |
| 133 | if ((acr & acr_mask) == acr_mask) |
| 134 | return; |
| 135 | |
| 136 | acr |= acr_mask; |
| 137 | omap_smc1(OMAP5_DRA7_MON_SET_ACR_INDEX, acr); |
| 138 | |
| 139 | pr_debug("%s: ARM ACR setup for CVE_2017_5715 applied on CPU%d\n", |
| 140 | __func__, smp_processor_id()); |
| 141 | } |
| 142 | #else |
| 143 | static inline void omap5_secondary_harden_predictor(void) { } |
| 144 | #endif |
| 145 | |
Paul Gortmaker | 8bd26e3 | 2013-06-17 15:43:14 -0400 | [diff] [blame] | 146 | static void omap4_secondary_init(unsigned int cpu) |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 147 | { |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 148 | /* |
Santosh Shilimkar | b2b9762 | 2010-06-16 22:19:48 +0530 | [diff] [blame] | 149 | * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device. |
| 150 | * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA |
| 151 | * init and for CPU1, a secure PPA API provided. CPU0 must be ON |
| 152 | * while executing NS_SMP API on CPU1 and PPA version must be 1.4.0+. |
| 153 | * OMAP443X GP devices- SMP bit isn't accessible. |
| 154 | * OMAP446X GP devices - SMP bit access is enabled on both CPUs. |
| 155 | */ |
Tony Lindgren | 3251885 | 2016-06-22 01:59:40 -0700 | [diff] [blame] | 156 | if (soc_is_omap443x() && (omap_type() != OMAP2_DEVICE_TYPE_GP)) |
Santosh Shilimkar | b2b9762 | 2010-06-16 22:19:48 +0530 | [diff] [blame] | 157 | omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX, |
| 158 | 4, 0, 0, 0, 0, 0); |
| 159 | |
Nishanth Menon | c0053bd | 2015-08-06 10:54:24 -0500 | [diff] [blame] | 160 | if (soc_is_omap54xx() || soc_is_dra7xx()) { |
| 161 | /* |
| 162 | * Configure the CNTFRQ register for the secondary cpu's which |
| 163 | * indicates the frequency of the cpu local timers. |
| 164 | */ |
R Sricharan | 5523e40 | 2013-10-10 13:13:48 +0530 | [diff] [blame] | 165 | set_cntfreq(); |
Nishanth Menon | c0053bd | 2015-08-06 10:54:24 -0500 | [diff] [blame] | 166 | /* Configure ACR to disable streaming WA for 801819 */ |
| 167 | omap5_erratum_workaround_801819(); |
Nishanth Menon | 66b29e2 | 2018-07-10 14:47:25 -0500 | [diff] [blame] | 168 | /* Enable ACR to allow for ICUALLU workaround */ |
| 169 | omap5_secondary_harden_predictor(); |
Nishanth Menon | c0053bd | 2015-08-06 10:54:24 -0500 | [diff] [blame] | 170 | } |
R Sricharan | 5523e40 | 2013-10-10 13:13:48 +0530 | [diff] [blame] | 171 | |
| 172 | /* |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 173 | * Synchronise with the boot thread. |
| 174 | */ |
| 175 | spin_lock(&boot_lock); |
| 176 | spin_unlock(&boot_lock); |
| 177 | } |
| 178 | |
Paul Gortmaker | 8bd26e3 | 2013-06-17 15:43:14 -0400 | [diff] [blame] | 179 | static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle) |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 180 | { |
Santosh Shilimkar | e97ca47 | 2010-06-16 22:19:49 +0530 | [diff] [blame] | 181 | static struct clockdomain *cpu1_clkdm; |
| 182 | static bool booted; |
Santosh Shilimkar | b7806dc | 2013-02-08 22:50:58 +0530 | [diff] [blame] | 183 | static struct powerdomain *cpu1_pwrdm; |
Santosh Shilimkar | 247c445 | 2012-05-09 20:38:35 +0530 | [diff] [blame] | 184 | void __iomem *base = omap_get_wakeupgen_base(); |
| 185 | |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 186 | /* |
| 187 | * Set synchronisation state between this boot processor |
| 188 | * and the secondary one |
| 189 | */ |
| 190 | spin_lock(&boot_lock); |
| 191 | |
| 192 | /* |
Santosh Shilimkar | 942e2c9 | 2009-12-11 16:16:35 -0800 | [diff] [blame] | 193 | * Update the AuxCoreBoot0 with boot state for secondary core. |
Santosh Shilimkar | baf4b7d | 2013-04-05 18:29:02 +0530 | [diff] [blame] | 194 | * omap4_secondary_startup() routine will hold the secondary core till |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 195 | * the AuxCoreBoot1 register is updated with cpu state |
| 196 | * A barrier is added to ensure that write buffer is drained |
| 197 | */ |
Santosh Shilimkar | 247c445 | 2012-05-09 20:38:35 +0530 | [diff] [blame] | 198 | if (omap_secure_apis_support()) |
| 199 | omap_modify_auxcoreboot0(0x200, 0xfffffdff); |
| 200 | else |
Victor Kamensky | edfaf05 | 2014-04-15 20:37:46 +0300 | [diff] [blame] | 201 | writel_relaxed(0x20, base + OMAP_AUX_CORE_BOOT_0); |
Santosh Shilimkar | 247c445 | 2012-05-09 20:38:35 +0530 | [diff] [blame] | 202 | |
Santosh Shilimkar | b7806dc | 2013-02-08 22:50:58 +0530 | [diff] [blame] | 203 | if (!cpu1_clkdm && !cpu1_pwrdm) { |
Santosh Shilimkar | e97ca47 | 2010-06-16 22:19:49 +0530 | [diff] [blame] | 204 | cpu1_clkdm = clkdm_lookup("mpu1_clkdm"); |
Santosh Shilimkar | b7806dc | 2013-02-08 22:50:58 +0530 | [diff] [blame] | 205 | cpu1_pwrdm = pwrdm_lookup("cpu1_pwrdm"); |
| 206 | } |
Santosh Shilimkar | e97ca47 | 2010-06-16 22:19:49 +0530 | [diff] [blame] | 207 | |
| 208 | /* |
| 209 | * The SGI(Software Generated Interrupts) are not wakeup capable |
| 210 | * from low power states. This is known limitation on OMAP4 and |
| 211 | * needs to be worked around by using software forced clockdomain |
| 212 | * wake-up. To wakeup CPU1, CPU0 forces the CPU1 clockdomain to |
| 213 | * software force wakeup. The clockdomain is then put back to |
| 214 | * hardware supervised mode. |
| 215 | * More details can be found in OMAP4430 TRM - Version J |
| 216 | * Section : |
| 217 | * 4.3.4.2 Power States of CPU0 and CPU1 |
| 218 | */ |
Santosh Shilimkar | b7806dc | 2013-02-08 22:50:58 +0530 | [diff] [blame] | 219 | if (booted && cpu1_pwrdm && cpu1_clkdm) { |
Santosh Shilimkar | ff999b8 | 2012-10-18 12:20:05 +0300 | [diff] [blame] | 220 | /* |
| 221 | * GIC distributor control register has changed between |
| 222 | * CortexA9 r1pX and r2pX. The Control Register secure |
| 223 | * banked version is now composed of 2 bits: |
| 224 | * bit 0 == Secure Enable |
| 225 | * bit 1 == Non-Secure Enable |
| 226 | * The Non-Secure banked register has not changed |
| 227 | * Because the ROM Code is based on the r1pX GIC, the CPU1 |
| 228 | * GIC restoration will cause a problem to CPU0 Non-Secure SW. |
| 229 | * The workaround must be: |
| 230 | * 1) Before doing the CPU1 wakeup, CPU0 must disable |
| 231 | * the GIC distributor |
| 232 | * 2) CPU1 must re-enable the GIC distributor on |
| 233 | * it's wakeup path. |
| 234 | */ |
Colin Cross | cd8ce15 | 2012-10-18 12:20:08 +0300 | [diff] [blame] | 235 | if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) { |
| 236 | local_irq_disable(); |
Santosh Shilimkar | ff999b8 | 2012-10-18 12:20:05 +0300 | [diff] [blame] | 237 | gic_dist_disable(); |
Colin Cross | cd8ce15 | 2012-10-18 12:20:08 +0300 | [diff] [blame] | 238 | } |
Santosh Shilimkar | ff999b8 | 2012-10-18 12:20:05 +0300 | [diff] [blame] | 239 | |
Santosh Shilimkar | b7806dc | 2013-02-08 22:50:58 +0530 | [diff] [blame] | 240 | /* |
| 241 | * Ensure that CPU power state is set to ON to avoid CPU |
| 242 | * powerdomain transition on wfi |
| 243 | */ |
Tero Kristo | 1d9a542 | 2016-06-30 16:15:02 +0300 | [diff] [blame] | 244 | clkdm_deny_idle_nolock(cpu1_clkdm); |
Grygorii Strashko | 918af9f | 2015-11-16 19:38:53 +0200 | [diff] [blame] | 245 | pwrdm_set_next_pwrst(cpu1_pwrdm, PWRDM_POWER_ON); |
| 246 | clkdm_allow_idle_nolock(cpu1_clkdm); |
Colin Cross | cd8ce15 | 2012-10-18 12:20:08 +0300 | [diff] [blame] | 247 | |
| 248 | if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) { |
| 249 | while (gic_dist_disabled()) { |
| 250 | udelay(1); |
| 251 | cpu_relax(); |
| 252 | } |
| 253 | gic_timer_retrigger(); |
| 254 | local_irq_enable(); |
| 255 | } |
Santosh Shilimkar | e97ca47 | 2010-06-16 22:19:49 +0530 | [diff] [blame] | 256 | } else { |
| 257 | dsb_sev(); |
| 258 | booted = true; |
| 259 | } |
| 260 | |
Rob Herring | b1cffeb | 2012-11-26 15:05:48 -0600 | [diff] [blame] | 261 | arch_send_wakeup_ipi_mask(cpumask_of(cpu)); |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 262 | |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 263 | /* |
| 264 | * Now the secondary core is starting up let it run its |
| 265 | * calibrations, then wait for it to finish |
| 266 | */ |
| 267 | spin_unlock(&boot_lock); |
| 268 | |
| 269 | return 0; |
| 270 | } |
| 271 | |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 272 | /* |
| 273 | * Initialise the CPU possible map early - this describes the CPUs |
| 274 | * which may be present or become present in the system. |
| 275 | */ |
Marc Zyngier | 0691532 | 2011-09-08 13:15:22 +0100 | [diff] [blame] | 276 | static void __init omap4_smp_init_cpus(void) |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 277 | { |
Santosh Shilimkar | 283f708 | 2012-03-19 19:29:41 +0530 | [diff] [blame] | 278 | unsigned int i = 0, ncores = 1, cpu_id; |
Tony Lindgren | e4e7a13 | 2009-10-19 15:25:26 -0700 | [diff] [blame] | 279 | |
Santosh Shilimkar | 283f708 | 2012-03-19 19:29:41 +0530 | [diff] [blame] | 280 | /* Use ARM cpuid check here, as SoC detection will not work so early */ |
Uwe Kleine-König | ac52e83 | 2013-01-30 17:38:21 +0100 | [diff] [blame] | 281 | cpu_id = read_cpuid_id() & CPU_MASK; |
Santosh Shilimkar | 283f708 | 2012-03-19 19:29:41 +0530 | [diff] [blame] | 282 | if (cpu_id == CPU_CORTEX_A9) { |
| 283 | /* |
| 284 | * Currently we can't call ioremap here because |
| 285 | * SoC detection won't work until after init_early. |
| 286 | */ |
Tony Lindgren | 3251885 | 2016-06-22 01:59:40 -0700 | [diff] [blame] | 287 | cfg.scu_base = OMAP2_L4_IO_ADDRESS(scu_a9_get_base()); |
| 288 | BUG_ON(!cfg.scu_base); |
| 289 | ncores = scu_get_core_count(cfg.scu_base); |
Santosh Shilimkar | 283f708 | 2012-03-19 19:29:41 +0530 | [diff] [blame] | 290 | } else if (cpu_id == CPU_CORTEX_A15) { |
| 291 | ncores = OMAP5_CORE_COUNT; |
| 292 | } |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 293 | |
| 294 | /* sanity check */ |
Russell King | a06f916 | 2011-10-20 22:04:18 +0100 | [diff] [blame] | 295 | if (ncores > nr_cpu_ids) { |
| 296 | pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", |
| 297 | ncores, nr_cpu_ids); |
| 298 | ncores = nr_cpu_ids; |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 299 | } |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 300 | |
Russell King | bbc3d14e9 | 2010-12-03 10:42:58 +0000 | [diff] [blame] | 301 | for (i = 0; i < ncores; i++) |
| 302 | set_cpu_possible(i, true); |
| 303 | } |
| 304 | |
Marc Zyngier | 0691532 | 2011-09-08 13:15:22 +0100 | [diff] [blame] | 305 | static void __init omap4_smp_prepare_cpus(unsigned int max_cpus) |
Russell King | bbc3d14e9 | 2010-12-03 10:42:58 +0000 | [diff] [blame] | 306 | { |
Santosh Shilimkar | b699ddd | 2013-02-10 13:54:00 +0530 | [diff] [blame] | 307 | void __iomem *base = omap_get_wakeupgen_base(); |
Tony Lindgren | 3251885 | 2016-06-22 01:59:40 -0700 | [diff] [blame] | 308 | const struct omap_smp_config *c = NULL; |
| 309 | |
| 310 | if (soc_is_omap443x()) |
| 311 | c = &omap443x_cfg; |
| 312 | else if (soc_is_omap446x()) |
| 313 | c = &omap446x_cfg; |
| 314 | else if (soc_is_dra74x() || soc_is_omap54xx()) |
| 315 | c = &omap5_cfg; |
| 316 | |
| 317 | if (!c) { |
| 318 | pr_err("%s Unknown SMP SoC?\n", __func__); |
| 319 | return; |
| 320 | } |
| 321 | |
| 322 | /* Must preserve cfg.scu_base set earlier */ |
| 323 | cfg.cpu1_rstctrl_pa = c->cpu1_rstctrl_pa; |
| 324 | cfg.startup_addr = c->startup_addr; |
| 325 | |
| 326 | if (soc_is_dra74x() || soc_is_omap54xx()) { |
| 327 | if ((__boot_cpu_mode & MODE_MASK) == HYP_MODE) |
| 328 | cfg.startup_addr = omap5_secondary_hyp_startup; |
| 329 | omap5_erratum_workaround_801819(); |
| 330 | } |
| 331 | |
| 332 | cfg.cpu1_rstctrl_va = ioremap(cfg.cpu1_rstctrl_pa, 4); |
| 333 | if (!cfg.cpu1_rstctrl_va) |
| 334 | return; |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 335 | |
Russell King | 05c74a6 | 2010-12-03 11:09:48 +0000 | [diff] [blame] | 336 | /* |
| 337 | * Initialise the SCU and wake up the secondary core using |
| 338 | * wakeup_secondary(). |
| 339 | */ |
Tony Lindgren | 3251885 | 2016-06-22 01:59:40 -0700 | [diff] [blame] | 340 | if (cfg.scu_base) |
| 341 | scu_enable(cfg.scu_base); |
Santosh Shilimkar | b699ddd | 2013-02-10 13:54:00 +0530 | [diff] [blame] | 342 | |
Tony Lindgren | 3251885 | 2016-06-22 01:59:40 -0700 | [diff] [blame] | 343 | /* |
| 344 | * Reset CPU1 before configuring, otherwise kexec will |
| 345 | * end up trying to use old kernel startup address. |
| 346 | */ |
| 347 | if (cfg.cpu1_rstctrl_va) { |
| 348 | writel_relaxed(1, cfg.cpu1_rstctrl_va); |
| 349 | readl_relaxed(cfg.cpu1_rstctrl_va); |
| 350 | writel_relaxed(0, cfg.cpu1_rstctrl_va); |
| 351 | } |
Santosh Shilimkar | b699ddd | 2013-02-10 13:54:00 +0530 | [diff] [blame] | 352 | |
| 353 | /* |
| 354 | * Write the address of secondary startup routine into the |
| 355 | * AuxCoreBoot1 where ROM code will jump and start executing |
| 356 | * on secondary core once out of WFE |
| 357 | * A barrier is added to ensure that write buffer is drained |
| 358 | */ |
| 359 | if (omap_secure_apis_support()) |
Tony Lindgren | 3251885 | 2016-06-22 01:59:40 -0700 | [diff] [blame] | 360 | omap_auxcoreboot_addr(virt_to_phys(cfg.startup_addr)); |
Santosh Shilimkar | b699ddd | 2013-02-10 13:54:00 +0530 | [diff] [blame] | 361 | else |
Tony Lindgren | 3251885 | 2016-06-22 01:59:40 -0700 | [diff] [blame] | 362 | writel_relaxed(virt_to_phys(cfg.startup_addr), |
| 363 | base + OMAP_AUX_CORE_BOOT_1); |
Santosh Shilimkar | 367cd31 | 2009-04-28 20:51:52 +0530 | [diff] [blame] | 364 | } |
Marc Zyngier | 0691532 | 2011-09-08 13:15:22 +0100 | [diff] [blame] | 365 | |
Masahiro Yamada | 7530527 | 2015-11-15 10:39:53 +0900 | [diff] [blame] | 366 | const struct smp_operations omap4_smp_ops __initconst = { |
Marc Zyngier | 0691532 | 2011-09-08 13:15:22 +0100 | [diff] [blame] | 367 | .smp_init_cpus = omap4_smp_init_cpus, |
| 368 | .smp_prepare_cpus = omap4_smp_prepare_cpus, |
| 369 | .smp_secondary_init = omap4_secondary_init, |
| 370 | .smp_boot_secondary = omap4_boot_secondary, |
| 371 | #ifdef CONFIG_HOTPLUG_CPU |
| 372 | .cpu_die = omap4_cpu_die, |
Tony Lindgren | 3251885 | 2016-06-22 01:59:40 -0700 | [diff] [blame] | 373 | .cpu_kill = omap4_cpu_kill, |
Marc Zyngier | 0691532 | 2011-09-08 13:15:22 +0100 | [diff] [blame] | 374 | #endif |
| 375 | }; |