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gerrit-public.fairphone.software / kernel / msm-4.9 / refs/tags/rel/11/fp3/8901.4.A.0016.6 / . / include / linux / regulator / qpnp-regulator.h
blob: 36288c068ac3aa6581c151bfead52bb958371770 [file] [log] [blame]
David Collins7370f1a2017-01-18 16:21:53 -0800[diff] [blame]1/*
2 * Copyright (c) 2012-2013, 2017, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef __REGULATOR_QPNP_REGULATOR_H__
15#define __REGULATOR_QPNP_REGULATOR_H__
16
17#include <linux/regulator/machine.h>
18
19#define QPNP_REGULATOR_DRIVER_NAME "qcom,qpnp-regulator"
20
21/* Pin control enable input pins. */
22#define QPNP_REGULATOR_PIN_CTRL_ENABLE_NONE 0x00
23#define QPNP_REGULATOR_PIN_CTRL_ENABLE_EN0 0x01
24#define QPNP_REGULATOR_PIN_CTRL_ENABLE_EN1 0x02
25#define QPNP_REGULATOR_PIN_CTRL_ENABLE_EN2 0x04
26#define QPNP_REGULATOR_PIN_CTRL_ENABLE_EN3 0x08
27#define QPNP_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT 0x10
28
29/* Pin control high power mode input pins. */
30#define QPNP_REGULATOR_PIN_CTRL_HPM_NONE 0x00
31#define QPNP_REGULATOR_PIN_CTRL_HPM_EN0 0x01
32#define QPNP_REGULATOR_PIN_CTRL_HPM_EN1 0x02
33#define QPNP_REGULATOR_PIN_CTRL_HPM_EN2 0x04
34#define QPNP_REGULATOR_PIN_CTRL_HPM_EN3 0x08
35#define QPNP_REGULATOR_PIN_CTRL_HPM_SLEEP_B 0x10
36#define QPNP_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT 0x20
37
38/*
39 * Used with enable parameters to specify that hardware default register values
40 * should be left unaltered.
41 */
42#define QPNP_REGULATOR_DISABLE 0
43#define QPNP_REGULATOR_ENABLE 1
44#define QPNP_REGULATOR_USE_HW_DEFAULT 2
45
46/* Soft start strength of a voltage switch type regulator */
47enum qpnp_vs_soft_start_str {
48 QPNP_VS_SOFT_START_STR_0P05_UA,
49 QPNP_VS_SOFT_START_STR_0P25_UA,
50 QPNP_VS_SOFT_START_STR_0P55_UA,
51 QPNP_VS_SOFT_START_STR_0P75_UA,
52 QPNP_VS_SOFT_START_STR_HW_DEFAULT,
53};
54
55/* Current limit of a boost type regulator */
56enum qpnp_boost_current_limit {
57 QPNP_BOOST_CURRENT_LIMIT_300_MA,
58 QPNP_BOOST_CURRENT_LIMIT_600_MA,
59 QPNP_BOOST_CURRENT_LIMIT_900_MA,
60 QPNP_BOOST_CURRENT_LIMIT_1200_MA,
61 QPNP_BOOST_CURRENT_LIMIT_1500_MA,
62 QPNP_BOOST_CURRENT_LIMIT_1800_MA,
63 QPNP_BOOST_CURRENT_LIMIT_2100_MA,
64 QPNP_BOOST_CURRENT_LIMIT_2400_MA,
65 QPNP_BOOST_CURRENT_LIMIT_HW_DEFAULT,
66};
67
68/**
69 * struct qpnp_regulator_platform_data - qpnp-regulator initialization data
70 * @init_data: regulator constraints
71 * @pull_down_enable: 1 = Enable output pull down resistor when the
72 * regulator is disabled
73 * 0 = Disable pull down resistor
74 * QPNP_REGULATOR_USE_HW_DEFAULT = do not modify
75 * pull down state
76 * @pin_ctrl_enable: Bit mask specifying which hardware pins should be
77 * used to enable the regulator, if any
78 * Value should be an ORing of
79 * QPNP_REGULATOR_PIN_CTRL_ENABLE_* constants. If
80 * the bit specified by
81 * QPNP_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT is
82 * set, then pin control enable hardware registers
83 * will not be modified.
84 * @pin_ctrl_hpm: Bit mask specifying which hardware pins should be
85 * used to force the regulator into high power
86 * mode, if any
87 * Value should be an ORing of
88 * QPNP_REGULATOR_PIN_CTRL_HPM_* constants. If
89 * the bit specified by
90 * QPNP_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT is
91 * set, then pin control mode hardware registers
92 * will not be modified.
93 * @system_load: Load in uA present on regulator that is not captured
94 * by any consumer request
95 * @enable_time: Time in us to delay after enabling the regulator
96 * @ocp_enable: 1 = Allow over current protection (OCP) to be
97 * enabled for voltage switch type regulators so
98 * that they latch off automatically when over
99 * current is detected. OCP is enabled when in HPM
100 * or auto mode.
101 * 0 = Disable OCP
102 * QPNP_REGULATOR_USE_HW_DEFAULT = do not modify
103 * OCP state
104 * @ocp_irq: IRQ number of the voltage switch OCP IRQ. If
105 * specified the voltage switch will be toggled off
106 * and back on when OCP triggers in order to handle
107 * high in-rush current.
108 * @ocp_max_retries: Maximum number of times to try toggling a voltage
109 * switch off and back on as a result of
110 * consecutive over current events.
111 * @ocp_retry_delay_ms: Time to delay in milliseconds between each
112 * voltage switch toggle after an over current
113 * event takes place.
114 * @boost_current_limit: This parameter sets the current limit of boost type
115 * regulators. Its value should be one of
116 * QPNP_BOOST_CURRENT_LIMIT_*. If its value is
117 * QPNP_BOOST_CURRENT_LIMIT_HW_DEFAULT, then the
118 * boost current limit will be left at its default
119 * hardware value.
120 * @soft_start_enable: 1 = Enable soft start for LDO and voltage switch
121 * type regulators so that output voltage slowly
122 * ramps up when the regulator is enabled
123 * 0 = Disable soft start
124 * QPNP_REGULATOR_USE_HW_DEFAULT = do not modify
125 * soft start state
126 * @vs_soft_start_strength: This parameter sets the soft start strength for
127 * voltage switch type regulators. Its value
128 * should be one of QPNP_VS_SOFT_START_STR_*. If
129 * its value is QPNP_VS_SOFT_START_STR_HW_DEFAULT,
130 * then the soft start strength will be left at its
131 * default hardware value.
132 * @auto_mode_enable: 1 = Enable automatic hardware selection of regulator
133 * mode (HPM vs LPM). Auto mode is not available
134 * on boost type regulators
135 * 0 = Disable auto mode selection
136 * QPNP_REGULATOR_USE_HW_DEFAULT = do not modify
137 * auto mode state
138 * @bypass_mode_enable: 1 = Enable bypass mode for an LDO type regulator so
139 * that it acts like a switch and simply outputs
140 * its input voltage
141 * 0 = Do not enable bypass mode
142 * QPNP_REGULATOR_USE_HW_DEFAULT = do not modify
143 * bypass mode state
144 * @hpm_enable: 1 = Enable high power mode (HPM), also referred to
145 * as NPM. HPM consumes more ground current than
146 * LPM, but it can source significantly higher load
147 * current. HPM is not available on boost type
148 * regulators. For voltage switch type regulators,
149 * HPM implies that over current protection and
150 * soft start are active all the time. This
151 * configuration can be overwritten by changing the
152 * regulator's mode dynamically.
153 * 0 = Do not enable HPM
154 * QPNP_REGULATOR_USE_HW_DEFAULT = do not modify
155 * HPM state
156 * @base_addr: SMPI base address for the regulator peripheral
157 */
158struct qpnp_regulator_platform_data {
159 struct regulator_init_data init_data;
160 int pull_down_enable;
161 unsigned int pin_ctrl_enable;
162 unsigned int pin_ctrl_hpm;
163 int system_load;
164 int enable_time;
165 int ocp_enable;
166 int ocp_irq;
167 int ocp_max_retries;
168 int ocp_retry_delay_ms;
169 enum qpnp_boost_current_limit boost_current_limit;
170 int soft_start_enable;
171 enum qpnp_vs_soft_start_str vs_soft_start_strength;
172 int auto_mode_enable;
173 int bypass_mode_enable;
174 int hpm_enable;
175 u16 base_addr;
176};
177
178#ifdef CONFIG_REGULATOR_QPNP
179
180/**
181 * qpnp_regulator_init() - register spmi driver for qpnp-regulator
182 *
183 * This initialization function should be called in systems in which driver
184 * registration ordering must be controlled precisely.
185 */
186int __init qpnp_regulator_init(void);
187
188#else
189
190static inline int __init qpnp_regulator_init(void)
191{
192 return -ENODEV;
193}
194
195#endif /* CONFIG_REGULATOR_QPNP */
196
197#endif