1. d05ca30 drm/i915: Zap the GTT mapping when transitioning from untiled to tiled. by Eric Anholt · 15 years ago
  2. b99e228 drm/i915: check for CONFIG_PNP before using pnp function by Keith Packard · 15 years ago
  3. 52dc7d3 drm/i915: Clear fence register on tiling stride change. by Chris Wilson · 15 years ago
  4. d765898 drm/i915: enable MCHBAR if needed by Jesse Barnes · 15 years ago
  5. 2cce0d8 drm/i915: Disable tiling on IGDNG for now by Zhenyu Wang · 15 years ago
  6. e76a16d drm/i915: Fix tiling pitch handling on 8xx. by Eric Anholt · 15 years ago
  7. 5b0bdd6 drm/i915: fix transition to I915_TILING_NONE by Keith Packard · 15 years ago
  8. 280b713 drm/i915: Allow tiling of objects with bit 17 swizzling by the CPU. by Eric Anholt · 15 years ago
  9. 8d7773a drm/i915: fix up tiling/fence reg setup on i8xx class hw by Daniel Vetter · 15 years ago
  10. 568d9a8 drm/i915: Change DCC tiling detection case to cover only mobile parts. by Eric Anholt · 15 years ago
  11. d687310 drm/i915: hold mutex for unreference() in i915_gem_tiling.c by Chris Wilson · 15 years ago
  12. 72daad4 drm/i915: Unref the object after failing to set tiling mode. by Chris Wilson · 15 years ago
  13. 0f973f2 drm/i915: add fence register management to execbuf by Jesse Barnes · 15 years ago
  14. de151cf drm/i915: add GEM GTT mapping support by Jesse Barnes · 16 years ago
  15. a7f014f drm/i915: Respect GM965/GM45 bit-17-instead-of-bit-11 option for swizzling. by Eric Anholt · 16 years ago
  16. b612eda i915: GM45 has GM965-style MCH setup. by Eric Anholt · 16 years ago
  17. 28af0a2 drm: G33-class hardware has a newer 965-style MCH (no DCC register). by Eric Anholt · 16 years ago
  18. 673a394 drm: Add GEM ("graphics execution manager") to i915 driver. by Eric Anholt · 16 years ago