Log - 30e664afb5cb597dd6f7651e6d116e10b9741084 - kernel/msm-4.9

a3fed9b omap3: Prevent SDRC deadlock when L3 is changing frequency by Jon Hunter · 14 years ago
18862cb OMAP3: SDRC: Place SDRC AC timing and MR changes in CORE DVFS SRAM code behind Kconfig by Paul Walmsley · 15 years ago
df56556 OMAP3 SDRC: Move the clk stabilization delay to the right place by Rajendra Nayak · 15 years ago
8ff120e OMAP3 SDRC: Fix freeze when scaling CORE dpll to < 83Mhz by Rajendra Nayak · 15 years ago
75f251e OMAP2/3 SDRC: don't set SDRC_POWER.PWDENA on boot by Paul Walmsley · 15 years ago
58cda88 OMAP3 SDRC: add support for 2 SDRAM chip selects by Jean Pihet · 15 years ago
7b7bcef OMAP3 SDRC: set FIXEDDELAY when disabling SDRC DLL by Paul Walmsley · 15 years ago
3afec633 OMAP3: Add support for DPLL3 divisor values higher than 2 by Tero Kristo · 15 years ago
df14e47 OMAP3 SRAM: convert SRAM code to use macros rather than magic numbers by Paul Walmsley · 15 years ago
4267b5d OMAP3 SRAM: add more comments on the SRAM code by Paul Walmsley · 15 years ago
d0ba392 OMAP3 clock/SDRC: program SDRC_MR register during SDRC clock change by Paul Walmsley · 15 years ago
c9812d0 OMAP3 clock: add a short delay when lowering CORE clk rate by Paul Walmsley · 15 years ago
6adb8f3 OMAP3 clock: remove wait for DPLL3 M2 clock to stabilize by Paul Walmsley · 15 years ago
4519c2b OMAP3 clock: only unlock SDRC DLL if SDRC clk < 83MHz by Paul Walmsley · 16 years ago
b2abb27 OMAP3 SRAM: renumber registers to make space for argument passing by Paul Walmsley · 16 years ago
fa0406a OMAP3 SRAM: clear the SDRC PWRENA bit during SDRC frequency change by Paul Walmsley · 16 years ago
d75d9e7 OMAP3 clock: add interconnect barriers to CORE DPLL M2 change by Paul Walmsley · 16 years ago
69d4255 OMAP3 SRAM: add ARM barriers to omap3_sram_configure_core_dpll by Paul Walmsley · 16 years ago
cc26b3b ARM: OMAP3: Add minimal omap3430 support by Syed Mohammed, Khasim · 16 years ago