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gerrit-public.fairphone.software
/
kernel
/
msm-4.9
/
3600836585e3fdef0a1410d63fe5ce4015007aac
/
drivers
/
gpu
/
drm
/
i915
/
i915_reg.h
73c352a
drm/i915: wire up SDVO hpd support on cpt/ppt
by Daniel Vetter
· 11 years ago
e5868a3
DRM/i915: Convert HPD interrupts to make use of HPD pin assignment in encoders (v2)
by Egbert Eich
· 11 years ago
92bd1bf
drm/i915: HSW PM Frequency bits fix
by Rodrigo Vivi
· 11 years ago
e3dff58
drm/i915: Implement WaSwitchSolVfFArbitrationPriority
by Ben Widawsky
· 11 years ago
12569ad
drm/i915: DSPFW and BLC regs are in the display offset range
by Jesse Barnes
· 11 years ago
ed5de39
drm/i915: add media well to VLV force wake routines v2
by Jesse Barnes
· 11 years ago
0d4a42f
Merge tag 'v3.9-rc3' into drm-intel-next-queued
by Daniel Vetter
· 11 years ago
d62b489
drm/i915: allow force wake at init time on VLV v2
by Jesse Barnes
· 11 years ago
60222c0
drm/i915: Fix incorrect definition of ADPA HSYNC and VSYNC bits
by Patrik Jakobsson
· 11 years ago
4f3a8bc
drm/i915: rename some HDMI bit definitions
by Paulo Zanoni
· 11 years ago
dc0fa71
drm/i915: remove duplicated SDVO/HDMI bit definitions
by Paulo Zanoni
· 11 years ago
c20cd31
drm/i915: unify the definitions of the HDMI/SDVO register
by Paulo Zanoni
· 11 years ago
e2debe9
drm/i915: clarify confusion between SDVO and HDMI registers
by Paulo Zanoni
· 11 years ago
7d9bceb
drm/i915: Use cpu_transcoder for HSW_TVIDEO_DIP_* instead of pipe
by Rodrigo Vivi
· 11 years ago
90a72f8
drm/i915: Refactor gen2 to gen4 vblank interrupt handling
by Ville Syrjälä
· 11 years ago
3f1e109
drm/i915: use FPGA_DBG for the "unclaimed register" checks
by Paulo Zanoni
· 11 years ago
86d3efc
drm/i915: Implement pipe CSC based limited range RGB output
by Ville Syrjälä
· 12 years ago
b9e1faa
drm/i915: Fix PIPE_CONTROL DW/QW write through global GTT on IVB+
by Ville Syrjälä
· 12 years ago
876a8cd
drm/i915: Preserve the DDI link reversal configuration
by Damien Lespiau
· 12 years ago
3e68320
drm/i915: Preserve the FDI line reversal override bit on CPT
by Damien Lespiau
· 12 years ago
1d7aaa0
drm/i915: detect wrong MCH watermark values
by Daniel Vetter
· 12 years ago
26739f1
drm/i915: unify HDMI/DP hpd definitions
by Daniel Vetter
· 12 years ago
7083e05
drm/i915: Fix RC6VIDS encode/decode
by Ben Widawsky
· 12 years ago
6dc1c49
Merge branch 'fbcon-locking-fixes' of ssh://people.freedesktop.org/~airlied/linux into drm-next
by Dave Airlie
· 12 years ago
766aa1c
drm/i915: Introduce i915_vgacntrl_reg()
by Ville Syrjälä
· 12 years ago
f82855d
drm/i915: Fix CAGF for HSW
by Ben Widawsky
· 12 years ago
41c0b3a
drm/i915: Implement WaVSRefCountFullforceMissDisable
by Ben Widawsky
· 12 years ago
fa42e23
drm/i915: fix intel_init_power_wells
by Paulo Zanoni
· 12 years ago
80a75f7
drm/i915: SWF screatch registers need an offset on VLV
by Ville Syrjälä
· 12 years ago
56a12a5
drm/i915: Include display_mmio_offset in sequencer index/data registers
by Ville Syrjälä
· 12 years ago
fc2de40
drm/i915: PLL registers need an offset on VLV
by Ville Syrjälä
· 12 years ago
54d9d49
drm/i915: DPIO registers are VLV only and need an offset
by Ville Syrjälä
· 12 years ago
ff76301
drm/i915: Spell out VLV_DISPLAY_BASE for interrupt registers
by Ville Syrjälä
· 12 years ago
07ec7ec
drm/i915: Make VLV_GUNIT_CLOCK_GATE register value more readable
by Ville Syrjälä
· 12 years ago
d88b227
drm/i915: FB_BLC_SELF_VLV is VLV only and needs an offset
by Ville Syrjälä
· 12 years ago
4b05998
drm/i915: Pipe palette registers need an offset on VLV
by Ville Syrjälä
· 12 years ago
4e8e7eb
drm/i915: Pipe timing registers need an offset on VLV
by Ville Syrjälä
· 12 years ago
67d62c5
drm/i915: PORT_HOTPLUG registers need an offset on VLV
by Ville Syrjälä
· 12 years ago
7e470ab
drm/i915: Panel fitter registers need an offset on VLV
by Ville Syrjälä
· 12 years ago
b41fbda
drm/i915: DPFLIPSTAT and DPINVGTT registers are VLV only and need an offset
by Ville Syrjälä
· 12 years ago
90f7da3
drm/i915: DSPFW registers need an offset on VLV
by Ville Syrjälä
· 12 years ago
8f6d8ee
drm/i915: VLV_DDL is VLV only and needs an offset
by Ville Syrjälä
· 12 years ago
9dc33f3
drm/i915: Cursor registers need an offset on VLV
by Ville Syrjälä
· 12 years ago
0c3870e
drm/i915: Pipe registers need an offset on VLV
by Ville Syrjälä
· 12 years ago
895abf0
drm/i915: Primary plane registers need an offset on VLV
by Ville Syrjälä
· 12 years ago
aab1713
drm/i915: PIPE M/N registers need an offset on VLV
by Ville Syrjälä
· 12 years ago
b906487
drm/i915: VLV_VIDEO_DIP_CTL is for VLV only
by Ville Syrjälä
· 12 years ago
f12c47b
drm/i915: Per-pipe PP registers are for VLV only
by Ville Syrjälä
· 12 years ago
f4ba9f8
drm/i915: AUD_VID_DID needs an offset on VLV
by Ville Syrjälä
· 12 years ago
1c8c38c
drm/i915: Disable AsyncFlip performance optimisations
by Chris Wilson
· 12 years ago
3685a8f
drm/i915: Fix RGB color range property for PCH platforms
by Ville Syrjälä
· 12 years ago
c70af1e
drm/i915: Fix SPRITE0_FLIP_DONE_INT_EN_VLV and SPRITE0_FLIPDONE_INT_STATUS_VLV
by Ville Syrjälä
· 12 years ago
b5cc6c0
Merge tag 'drm-intel-next-2012-12-21' of git://people.freedesktop.org/~danvet/drm-intel into drm-next
by Dave Airlie
· 12 years ago
0f3b684
drm/i915: Record DERRMR, FORCEWAKE and RING_CTL in error-state
by Chris Wilson
· 12 years ago
6547fbd
drm/i915: Implement WaSetupGtModeTdRowDispatch
by Daniel Vetter
· 12 years ago
4283908
drm/i915: Implement WaDisableHiZPlanesWhenMSAAEnabled
by Daniel Vetter
· 12 years ago
dfd07d7
drm/i915: clean up PIPECONF bpc #defines
by Daniel Vetter
· 12 years ago
b696519
drm/i915: Cleanup SHOTPLUG_CTL status bits definitions
by Damien Lespiau
· 12 years ago
68d18ad
drm/i915: set the LPT FDI RX polarity reversal bit when needed
by Paulo Zanoni
· 12 years ago
dde86e2
drm/i915: add lpt_init_pch_refclk
by Paulo Zanoni
· 12 years ago
988d6ee
drm/i915: add support for mPHY destination on intel_sbi_{read, write}
by Paulo Zanoni
· 12 years ago
6ef6a45
drm/i915: Remove duplicate and unused register #defines in i915_reg.h
by Dexuan Cui
· 12 years ago
f930ddd
drm/i915: remove duplicate register #defines
by Daniel Vetter
· 12 years ago
13888d7
drm/i915: make the panel fitter work on pipes B and C on IVB
by Paulo Zanoni
· 12 years ago
79935fc
drm/i915: don't intel_crt_init if DDI A has 4 lanes
by Paulo Zanoni
· 12 years ago
17a303e
drm/i915: make DP work on LPT-LP machines
by Paulo Zanoni
· 12 years ago
26b1ff3
drm/i915: Move the remaining gtt code
by Ben Widawsky
· 12 years ago
0f9b91c
drm/i915: flush system agent TLBs on SNB
by Ben Widawsky
· 12 years ago
03752f5
drm/i915: Calculate correct stolen size for GEN7+
by Ben Widawsky
· 12 years ago
e76e9ae
drm/i915: Stop using AGP layer for GEN6+
by Ben Widawsky
· 12 years ago
9a28977
drm/i915: TLB invalidation with MI_FLUSH_DW requires a post-sync op v3
by Jesse Barnes
· 12 years ago
12f3382
drm/i915: implement WaDisablePSDDualDispatchEnable on IVB & VLV
by Jesse Barnes
· 12 years ago
2d80957
drm/i915: implement WaDisableVLVClockGating_VBIIssue on VLV
by Jesse Barnes
· 12 years ago
8ab4397
drm/i915: implement WaDisableDopClockGatingisable on VLV and IVB
by Jesse Barnes
· 12 years ago
d0cf5ea
drm/i915: implement WaDisableL3CacheAging on VLV
by Jesse Barnes
· 12 years ago
0494564
drm/i915: fix Haswell FDI link training code
by Paulo Zanoni
· 12 years ago
ce40141
drm/i915: implement WADP0ClockGatingDisable
by Daniel Vetter
· 12 years ago
23670b32
drm/i915: CPT+ pch transcoder workaround
by Daniel Vetter
· 12 years ago
32ae46bf
drm/i915: Add SURFLIVE register definitions
by Ville Syrjälä
· 12 years ago
57779d0
drm/i915: Fix display pixel format handling
by Ville Syrjälä
· 12 years ago
4358a37
drm/i915: implement WaDisableRenderCachePipelinedFlush
by Daniel Vetter
· 12 years ago
c54173a
drm/i915: Fix sprite offset on HSW
by Damien Lespiau
· 12 years ago
bc1c91e
drm/i915: Fix primary plane offset on HSW
by Damien Lespiau
· 12 years ago
01a415f
drm/i915: check fdi B/C lane sharing constraint
by Daniel Vetter
· 12 years ago
fe2b8f9
drm/i915: convert pipe timing definitions to transcoder
by Paulo Zanoni
· 12 years ago
afe2fcf
drm/i915: convert CPU M/N timings to transcoder
by Paulo Zanoni
· 12 years ago
c980979
drm/i915: convert PIPE_MSA_MISC to transcoder
by Paulo Zanoni
· 12 years ago
702e7a5
drm/i915: convert PIPECONF to use transcoder instead of pipe
by Paulo Zanoni
· 12 years ago
ad80a81
drm/i915: convert DDI_FUNC_CTL to transcoder
by Paulo Zanoni
· 12 years ago
bb523fc
drm/i915: convert PIPE_CLK_SEL to transcoder
by Paulo Zanoni
· 12 years ago
a5c961d
drm/i915: add TRANSCODER_EDP
by Paulo Zanoni
· 12 years ago
82ed61f
drm/i915: make edp panel power sequence setup more robust
by Daniel Vetter
· 12 years ago
c2fb791
Merge tag 'v3.7-rc2' into drm-intel-next-queued
by Daniel Vetter
· 12 years ago
231e54f
drm/i915: Consolidate ILK_DSPCLK_GATE and PCH_DSPCLK_GATE
by Damien Lespiau
· 12 years ago
d6c0d72
drm/i915: add basic Haswell DP link train bits
by Paulo Zanoni
· 12 years ago
dae8479
drm/i915: add intel_ddi_set_pipe_settings
by Paulo Zanoni
· 12 years ago
c5836c2
drm/i915: Document the multi-threaded FORCEWAKE bits
by Chris Wilson
· 12 years ago
d7d4eed
drm/i915: Allow DRM_ROOT_ONLY|DRM_MASTER to submit privileged batchbuffers
by Chris Wilson
· 12 years ago
31643d5
drm/i915: Workaround to bump rc6 voltage to 450
by Ben Widawsky
· 12 years ago
26b6e44
drm/i915: Set guardband clipping workaround bit in the right register.
by Kenneth Graunke
· 12 years ago
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