Log - 427486843488f67acd9d1b8f574a0482631ba2fc - kernel/msm-4.9

0e051f1 clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset by Chen-Yu Tsai · 7 years ago
35ef543 clk: sunxi-ng: mp: Adjust parent rate for pre-dividers by Chen-Yu Tsai · 7 years ago
867f780 clk: sunxi-ng: sun6i: Fix enable bit offset for hdmi-ddc module clock by Chen-Yu Tsai · 7 years ago
6c9f628 clk: sunxi-ng: sun8i-h3: Set CLK_SET_RATE_PARENT for audio module clocks by Chen-Yu Tsai · 8 years ago
36a6f70 clk: sunxi-ng: sun8i-a23: Set CLK_SET_RATE_PARENT for audio module clocks by Chen-Yu Tsai · 8 years ago
98fb2b9 clk: sunxi-ng: enable so-said LDOs for A33 SoC's pll-mipi clock by Icenowy Zheng · 8 years ago
95881a5 clk: sunxi-ng: sun6i-a31: Enable PLL-MIPI LDOs when ungating it by Chen-Yu Tsai · 8 years ago
a17b9e4 clk: sunxi-ng: sun6i-a31: Force AHB1 clock to use PLL6 as parent by Chen-Yu Tsai · 8 years ago
5519cf2 clk: sunxi-ng: Fix reset offset for the A23 and A33 by Maxime Ripard · 8 years ago
5254223 clk: sunxi-ng: sun6i-a31: Fix register offset for mipi-csi clk by Chen-Yu Tsai · 8 years ago
d613782 clk: sunxi-ng: sun6i-a31: set CLK_SET_RATE_UNGATE for all PLLs by Chen-Yu Tsai · 8 years ago
d832fdd clk: sunxi-ng: sun6i-a31: Set CLK_SET_RATE_PARENT for display output clocks by Chen-Yu Tsai · 8 years ago
de64f5c Merge tag 'sunxi-clk-for-4.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next by Stephen Boyd · 8 years ago
d63a5e7 clk: sunxi-ng: Add hardware dependency by Jean Delvare · 8 years ago
5690879 clk: sunxi-ng: Add A23 CCU by Maxime Ripard · 8 years ago
d05c748 clk: sunxi-ng: Add A33 CCU support by Maxime Ripard · 8 years ago
aa15233 clk: sunxi-ng: Add N-class clocks support by Maxime Ripard · 8 years ago
13e91e4 clk: sunxi-ng: mux: Add mux table macro by Maxime Ripard · 8 years ago
87ba9e5 clk: sunxi-ng: div: Allow to set a maximum by Maxime Ripard · 8 years ago
e9c959a clk: sunxi-ng: div: Add kerneldoc for the _ccu_div structure by Maxime Ripard · 8 years ago
6f91c60 clk: sunxi-ng: div: Add mux table macros by Maxime Ripard · 8 years ago
6654674 clk: sunxi-ng: Fix wrong reset register offsets by Jorik Jonker · 8 years ago
c6e6c96 clk: sunxi-ng: Add A31/A31s clocks by Chen-Yu Tsai · 8 years ago
8adfb08 clk: sunxi-ng: mux: Add clk notifier functions by Chen-Yu Tsai · 8 years ago
ff5294d clk: sunxi-ng: mux: support fixed pre-dividers on multiple parents by Chen-Yu Tsai · 8 years ago
2b9c875 clk: sunxi-ng: mux: Add support for mux tables by Chen-Yu Tsai · 8 years ago
89af852 clk: sunxi-ng: mux: Rename mux macro to be consistent by Maxime Ripard · 8 years ago
a365835 clk: sunxi-ng: nkm: Add mux to support multiple parents by Chen-Yu Tsai · 8 years ago
178ca53 clk: sunxi-ng: mux: Increase fixed pre-divider div size by Chen-Yu Tsai · 8 years ago
06421a7 clk: sunxi-ng: nk: Make ccu_nk_find_best static by Chen-Yu Tsai · 8 years ago
156ad0d clk: sunxi-ng: Fix inverted test condition in ccu_helper_wait_for_lock by Chen-Yu Tsai · 8 years ago
5dc3916 clk: sunxi-ng: h3: Fix Kconfig symbol typo by Maxime Ripard · 8 years ago
0bd8fa2 clk: sunxi-ng: h3: Fix audio clock divider offset by Maxime Ripard · 8 years ago
0577e48 clk: sunxi-ng: Add H3 clocks by Maxime Ripard · 8 years ago
4f728b5 clk: sunxi-ng: Add N-K-M-P factor clock by Maxime Ripard · 8 years ago
df6561e clk: sunxi-ng: Add N-K-M Factor clock by Maxime Ripard · 8 years ago
6174a1e clk: sunxi-ng: Add N-M-factor clock support by Maxime Ripard · 8 years ago
adbfb00 clk: sunxi-ng: Add N-K-factor clock support by Maxime Ripard · 8 years ago
2ab836d clk: sunxi-ng: Add M-P factor clock support by Maxime Ripard · 8 years ago
e9b9321 clk: sunxi-ng: Add divider by Maxime Ripard · 8 years ago
6f9f7f8 clk: sunxi-ng: Add phase clock support by Maxime Ripard · 8 years ago
2a65ed4 clk: sunxi-ng: Add mux clock support by Maxime Ripard · 8 years ago
1a7e7c3 clk: sunxi-ng: Add gate clock support by Maxime Ripard · 8 years ago
89a3dfb clk: sunxi-ng: Add fractional lib by Maxime Ripard · 8 years ago
1d80c14 clk: sunxi-ng: Add common infrastructure by Maxime Ripard · 8 years ago